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Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
FEATURES
* * * * * * * * * 750kHz to 400MHz output range. Low phase noise output (@ 10kHz frequency offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for 106.25MHz, -125dBc/Hz for 155.52MHz). Selectable CMOS, PECL and LVDS output. 12 to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (+/-190 ppm) 3.3V operation. Available in DIE (65 mil x 62 mil).
Y
DIE CONFIGURATION
65 mil (1550,1475)
19 18 17 16 25 26 24 23 22 21 20
27
15
28
14
62 mil
13 29 12
11 30 10 31 1 2 3 4 5 6 7 8 9
(0,0)
DESCRIPTIONS
The PLL502-10 is a monolithic low jitter and low phase noise (-140dBc/Hz @ 10kHz offset) VCXO IC Die, with CMOS, LVDS and PECL output, covering the 750kHz to 400MHz output range. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The same die can be used as a VCXO with output frequencies ranging from F XIN / 16 to F XIN x 16 thanks to frequency selector pads. This makes the PLL502-10 ideal as a universal die for applications ranging from ADSL to SONET.
X
DIE SPECIFICATIONS
Name Size Reverse side Pad dimensions Thickness Value 62 x 65 mil GND 80 micron x 80 micron 10 mil
OUTPUT SELECTION AND ENABLE
Pad #18 OUTSEL1 0 0 1 1 OE_SELECT (Pad #9) 0 1 (Default) Pad #25 OUTSEL0 0 1 0 1 OE_CTRL (Pad #30) 0 (Default) 1 0 1 (Default) Selected Output High Drive CMOS Standard CMOS PECL LVDS State Output enabled Tri-state Tri-state Output enabled
BLOCK DIAGRAM
VCO Divider Charge Pump
SEL
Reference Divider
Phase Detector
+ Loop Filter
VCO
CLKBAR CLK
XIN XOUT
XTAL OSC VARICAP
OE
VCON
Pad #9: Bond to GND to set to "0", bond to VDD to set to "1" Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9) is "0" Logical states defined by CMOS levels if OE_SELECT is "1"
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 1
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
FREQUENCY SELECTION TABLE
Pad #28 SEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 Pad #29 SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Pad #19 SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pad #20 SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Selected Multiplier Reserved Reserved Reserved Reserved Reserved Reserved Fin / 8 Fin x 2 Reserved Fin / 2 Fin / 16 Fin x 4 Fin / 4 Fin x 8 Fin x 16 No multiplication
1
1 1
All pads have internal pull-ups (default value is 1). Bond to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 2
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection
SYMBOL
VDD VI VO TS TA TJ
MIN.
VSS-0.5 VSS-0.5 -65 -40
MAX.
7 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR
SYMBOL
FXIN CL (xtal) C0/C1 (xtal) RE
CONDITIONS
Parallel Fundamental Mode at VCON = 1.65V AT cut AT cut
MIN.
12
TYP.
MAX.
25
UNITS
MHz pF
9.5 250 30
Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range.
3. Voltage Control Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW 0V VCON 3.3V, -3dB 2000 25
SYMBOL
TVCXOSTB
CONDITIONS
From power valid FXIN = 12 - 25MHz; XTAL C0/C1 < 250 0V VCON 3.3V
MIN.
380 190
TYP.
10
MAX.
UNITS
ms ppm ppm
5 115
10
% ppm/V k kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 3
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
4. General Electrical Specifications PARAMETERS
Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD
CONDITIONS
Fout < 24MHz PECL/LVDS/CMOS 24MHz < Fout < 96MHz 96MHz < Fout < 400MHz
MIN.
TYP.
MAX.
25/25/15 65/45/30 100/80/40
UNITS
mA
VDD @ 1.4V (CMOS) @ 1.25V (LVDS) @ Vdd - 1.3V (PECL)
3.13 45 45 45 50 50 50 50
3.47 55 55 55
V % mA
5. Jitter specifications PARAMETERS
Period jitter RMS
CONDITIONS
With capacitive decoupling between VDD and GND. With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz
FREQUENCY
19.44MHz 77.76MHz 155.52MHz
MIN.
TYP.
5 8 9 TBM 3
MAX.
UNITS
ps
Accumulated jitter RMS Integrated jitter RMS
155.52MHz 155.52MHz
ps 4 ps
6. Phase noise specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
19.44MHz 106.25MHz 155.52MHz
@10Hz
-60 -60 -60
@100Hz
-90 -90 -90
@1kHz
-112 -112 -112
@10kHz
-140 -127 -125
@100kHz
-150 -125 -123
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 4
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
7. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current 8. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL V OD V OD V OH V OL V OS V OS I OXD I OSD
CONDITIONS
MIN. 247 -50
TYP. 355 1.4
MAX. 454 50 1.6 1.375 25 10 -8
UNITS mV mV V V V mV uA mA
R L = 100 (see figure)
0.9 1.125 0
1.1 1.2 3 1 -5.7
V out = V DD or GND V DD = 0V
SYMBOL
tr tf
CONDITIONS R L = 100 C L = 10 pF (see figure)
MIN. 0.2 0.2
TYP. 0.7 0.7
MAX. 1.0 1.0
UNITS ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% V DIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 5
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
9. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL V OH V OL CONDITIONS R L = 50 to (V DD - 2V) (see figure) MIN. V DD - 1.025 V DD - 1.620 MAX. UNITS V V
10. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL
tr tf
CONDITIONS @20/80% - PECL @80/20% - PECL
MIN.
TYP. 0.6 0.5
MAX. 1.5 1.5
UNITS ns ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 6
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
PAD ASSIGNMENT
Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Name GND GND GND GND GND N/C GND GNDBUF OE_SELECT LVDS PECL VDDBUF VDDBUF PECLB LVDSB CMOS GNDBUF OUTSEL1 SEL1 SEL0 VDD VDD VDD VDD OUTSEL0 XIN XOUT SEL3 SEL2 OE_CTRL VCON X ( m) 248 361 473 587 702 874 1042 1171 1400 1400 1400 1400 1400 1400 1400 1400 1389 1232 1042 854 659 559 459 358 194 109 109 109 109 109 109 Y ( m) 109 109 109 109 109 109 109 109 125 259 476 616 716 871 1089 1227 1365 1365 1365 1365 1365 1365 1365 1365 1365 1223 1017 858 646 397 181
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 7
Preliminary
PLL502-10
750kHz - 400MHz Low Phase Noise VCXO (for 12 - 25MHz Crystals)
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PART NUMBER
PLL502-10 D C
PART NUMBER TEMPERATURATRE
C=COMMERCIAL M=MILITARY
I=INDUSTRAL
D=DIE
PACKAGE TYPE
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 11/06/02 Page 8

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