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Arria II GX Device Handbook Volume 3
101 Innovation Drive San Jose, CA 95134 www.altera.com AIIGX5V3-2.3
Copyright (c) 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Section I. Arria II GX Device Data Sheet and Addendum
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
Chapter 1. Arria II GX Devices Data Sheet
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Maximum Allowed I/O Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 Schmitt Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 Power Consumption for Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Transceiver Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Core Performance Specifications for Arria II GX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 Clock Tree Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25 DSP Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Embedded Memory Block Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Periphery Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 High-Speed I/O Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31 Duty Cycle Distortion (DCD) Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32 IOE Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-37
Chapter 2. Addendum to the Arria II GX Device Handbook
Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 High-Speed LVDS I/O with DPA and Soft CDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Auto-Calibrating External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Guidelines for Connecting Serial Configuration Device to Arria II GX Device Family on AS Interface 2-2 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Additional Information
About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1
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Contents
Arria II GX Device Handbook Volume 3
(c) March 2010 Altera Corporation
Chapter Revision Dates
The chapters in this book, Arria II GX Device Handbook Volume 3, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1 Arria II GX Devices Data Sheet Revised: March 2010 Part Number: AIIGX53001-2.3 Addendum to the Arria II GX Device Handbook Revised: March 2010 Part Number: AIIGX53002-1.1
Chapter 2
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Chapter Revision Dates
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Section I. Arria II GX Device Data Sheet and Addendum
This section provides information about the Arria (R) II GX device data sheet and addendum. This section includes the following chapters:

Chapter 1, Arria II GX Devices Data Sheet Chapter 2, Addendum to the Arria II GX Device Handbook
Revision History
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in this volume.
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Section I. Arria II GX Device Data Sheet and Addendum
Arria II GX Device Handbook Volume 3
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1. Arria II GX Devices Data Sheet
AIIGX53001-2.3
This chapter describes the electrical and switching characteristics of the Arria(R) II GX device family. This chapter contains the following sections:

"Electrical Characteristics" on page 1-1 "Switching Characteristics" on page 1-13 "Glossary" on page 1-34
Electrical Characteristics
The following sections describe the electrical characteristics.
Operating Conditions
When Arria II GX devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Arria II GX devices, system designers must consider the operating requirements in this chapter. Arria II GX devices are offered in both commercial and industrial grades. Commercial devices are offered in -4 (fastest), -5, and -6 (slowest) speed grades. Industrial device is only offered in -5 speed grade. 1 In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with the "C" prefix, and industrial with the "I" prefix. Commercial devices are therefore indicated as C4, C5, and C6 speed grade respectively, while the industrial device is indicated as I5.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Arria II GX devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied under these conditions. Table 1-1 lists the absolute maximum ratings for Arria II GX devices. 1 Conditions beyond those listed in Table 1-1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 1-1. Arria II GX Device Absolute Maximum Ratings (Part 1 of 2) Symbol VC C VC CC B Description Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS Supplies power to the configuration RAM bits Minimum -0.5 -0.5 Maximum 1.35 1.8 Unit V V
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Chapter 1: Arria II GX Devices Data Sheet Electrical Characteristics
Table 1-1. Arria II GX Device Absolute Maximum Ratings (Part 2 of 2) Symbol VC CB AT VC CP D VC CIO VC CD_P LL VC CA _PLL VI IOUT VC CA VC CL_GXB VC CH_GX B TJ TS TG Description Battery back-up power supply for design security volatile key register Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry Supplies power to the I/O banks Supplies power to the digital portions of the PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry DC input voltage DC output current, per pin Supplies power to the transceiver PMA regulator Supplies power to the transceiver PMA TX, PMA RX, and clocking Supplies power to the transceiver PMA output (TX) buffer Operating junction temperature Storage temperature (no bias) Minimum -0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -25 -- -- -- -55 -65 Maximum 3.75 3.75 3.9 1.35 3.75 4.0 40 2.625 1.21 1.8 125 150 Unit V V V V V V mA V V V C C
Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1-2 and undershoot to -2.0 V for magnitude of currents less than 100 mA and periods shorter than 20 ns. Table 1-2 lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the device lifetime. The maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the device: for a device lifetime of 10 years, this amounts to 5.41/10ths of a year.
Table 1-2. Maximum Allowed Overshoot During Transitions Symbol Description Condition 4.0 V 4.05 V 4.1 V 4.15 V 4.2 V 4.25 V VI (AC) AC Input Voltage 4.3 V 4.35 V 4.4 V 4.45 V 4.5 V 4.55 V 4.6 V Overshoot Duration as % of High Time 100.000 79.330 46.270 27.030 15.800 9.240 5.410 3.160 1.850 1.080 0.630 0.370 0.220 Unit % % % % % % % % % % % % %
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Maximum Allowed I/O Operating Frequency
Table 1-3 lists the maximum allowed I/O operating frequency for I/Os using the specified I/O standards to ensure device reliability.
Table 1-3. Maximum Allowed I/O Operating Frequency I/O Standard HSTL-18, HSTL-15 SSTL -15 SSTL-18 2.5-V LVCMOS 3.3-V and 3.0-V LVTTL 3.3-V, 3.0-V, 1.8-V, 1.5-V LVCMOS PCI and PCI-X SSTL-2 1.2-V LVCMOS HSTL-12 200 250 I/O Frequency (MHz) 333 400 333 260
Recommended Operating Conditions
This section lists the functional operation limits for AC and DC parameters for Arria II GX devices. The steady-state voltage and current values expected from Arria II GX devices are listed in Table 1-4. All supplies are required to monotonically reach their full-rail values without plateaus within tRAMP .
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Chapter 1: Arria II GX Devices Data Sheet Electrical Characteristics
Table 1-4 lists the recommended operating conditions for Arria II GX device.
Table 1-4. Arria II GX Device Recommended Operating Conditions Symbol VC C VC CC B VCCBAT (2) Description Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS Supplies power to the configuration RAM bits Battery back-up power supply for design security volatile key registers (Note 1) Minimum 0.87 1.425 1.2 3.135 2.85 2.375 3.135 2.85 2.375 1.71 1.425 1.14 0.87 Typical 0.90 1.50 -- 3.3 3.0 2.5 3.3 3.0 2.5 1.8 1.5 1.2 0.90 Maximum 0.93 1.575 3.3 3.465 3.15 2.625 3.465 3.15 2.625 1.89 1.575 1.26 0.93 Unit V V V V V V V V V V V V V
Condition -- -- -- -- -- -- -- -- -- -- -- --
Supplies power to the I/O pre-drivers, VCCPD (3) differential input buffers, and MSEL circuitry
VCCIO
Supplies power to the I/O banks (4)
VC CD_P LL VC CA _PLL VI VO VC CA VC CL_GXB VC CH_GX B TJ tRAM P
Supplies power to the digital portions of the PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry DC Input voltage Output voltage Supplies power to the transceiver PMA regulator Supplies power to the transceiver PMA TX, PMA RX, and clocking Supplies power to the transceiver PMA output (TX) buffer Operating junction temperature Power Supply Ramp time
--
-- -- -- -- -- -- Commercial Industrial Normal POR Fast POR
2.375 -0.5 0 2.375 1.045 1.425 0 -40 0.05 0.05
2.5 -- -- 2.5 1.1 1.5 -- -- -- --
2.625 3.6 VC CIO 2.625 1.155 1.575 85 100 100 4
V V V V V V C C ms ms
Notes to Table 1-4:
(1) For more information about supply pin connection details, refer to the Arria II GX Device Family Pin Connection Guidelines. (2) Altera recommends a 3.0-V nominal battery voltage when connecting VCC BAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCC BAT to either GND or a 3.0-V power supply. (3) VCC PD must be 2.5-V for I/O banks with 2.5-V and lower VC CIO, 3.0-V for 3.0-V VC CIO , and 3.3-V for 3.3-V VCC IO . (4) VCCIO for 3C and 8C I/O banks where the configuration pins reside only supports 3.3-, 3.0-, 2.5-, or 1.8-V voltage levels.
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DC Characteristics
This section lists the supply current, I/O pin leakage current, on-chip termination (OCT) accuracy and variation, input pin capacitance, internal weak pull-up and pull-down resistance, hot socketing, and Schmitt trigger input specifications. Supply Current Standby current is the current the device draws after the device is configured with no inputs or outputs toggling and no activity in the device. Since these currents vary largely with resources used, use the Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. f For more information about power estimation tools, refer to the Arria II GX EPE User Guide and the PowerPlay Power Analysis chapter. I/O Pin Leakage Current Table 1-5 lists the Arria II GX I/O pin leakage current specifications.
Table 1-5. Arria II GX I/O Pin Leakage Current Symbol II IOZ Description Input pin Tri-stated I/O pin Conditions VI = 0 V to VCCIOM AX VO = 0 V to VC CIOMA X Min -10 -10 Typ -- -- Max 10 10 Unit A A
Bus Hold Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Table 1-6 lists bus hold specifications for Arria II GX devices.
Table 1-6. Arria II GX Devices Bus Hold Parameter (Part 1 of 2) (Note 1) VCC IO (V) Parameter Condition Min Bus-hold low, sustaining current Bus-hold high, sustaining current Bus-hold low, overdrive current VIN > VIL (maximum) 1.2 Max Min 1.5 Max Min 1.8 Max Min 2.5 Max 3.0 Min Max Min 3.3 Max Unit
8
--
12
--
30
--
50
--
70
--
70
--
A
VIN < VIL (minimum)
-8
--
-12
--
-30
--
-50
--
-70
--
-70
--
A
0 V < VIN --
125
--
175
--
200
--
300
--
500
--
500
A
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Chapter 1: Arria II GX Devices Data Sheet Electrical Characteristics
Table 1-6. Arria II GX Devices Bus Hold Parameter (Part 2 of 2) (Note 1) VCC IO (V) Parameter Condition Min Bus-hold high, overdrive current Bus-hold trip point
Note to Table 1-6:
(1) The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
1.2 Max Min
1.5 Max Min
1.8 Max Min
2.5 Max
3.0 Min Max Min
3.3 Max
Unit
0 V < VIN --
-125
--
-175
--
-200
--
-300
--
-500
--
-500
A
--
0.3
0.9
0.375 1.125
0.68
1.07
0.7
1.7
0.8
2
0.8
2
V
OCT Specifications Table 1-7 lists the Arria II GX series and differential OCT with and without calibration accuracy.
Table 1-7. OCT With and Without Calibration Specification for I/Os (Note 1) Calibration Accuracy Symbol 25- RS 3.0/2.5 50- RS 3.0/2.5 25- RS 1.8 50- RS 1.8 25- RS 1.5/1.2 50- RS 1.5/1.2 25- RS 3.0/2.5/1.8/ 1.5/1.2 50- RS 3.0/2.5/1.8/ 1.5/1.2 100- RD 2.5
Note to Table 1-7:
(1) OCT with calibration accuracy is valid at the time of calibration only.
Description 25- series OCT without calibration 50- series COT without calibration 25- series OCT without calibration 50- series OCT without calibration 25- series OCT without calibration 50- series OCT without calibration 25- series OCT with calibration 50- series OCT with calibration 100- differential OCT without calibration
Conditions Commercial VC CIO = 3.0/2.5 V VC CIO = 3.0/2.5 V VCC IO = 1.8 V VCC IO = 1.8 V VC CIO = 1.5/1.2 V VC CIO = 1.5/1.2 V VC CIO = 3.0/2.5/1.8/ 1.5/1.2 V VC CIO = 3.0/2.5/1.8/ 1.5/1.2 V 30 30 40 40 50 50 Industrial 40 40 50 50 50 50
Unit % % % % % %
10
10
%
10
10
%
VCC IO = 2.5 V
30
30
%
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OCT calibration is automatically performed at power up for OCT-enabled I/Os. When voltage and temperature conditions change after calibration, the resistance may change. Use Equation 1-1 and Table 1-8 to determine the OCT variation when voltage and temperature vary after power-up calibration.
Equation 1-1. OCT Variation (Note 1)
dR dR R OCT = R SCAL 1 + ------ T ------ V dT dV
Notes to Equation 1-1:
(1) ROCT value calculated from Equation 1-1shows the range of OCT resistance with the variation of temperature and VCCIO. (2) RSCAL is the OCT resistance value at power up. (3) T is the variation of temperature with respect to the temperature at power up. (4) V is the variation of voltage with respect to the VCCIO at power up. (5) dR/dT is the percentage change of RSCAL with temperature. (6) dR/dV is the percentage change of RSCAL with voltage.
Table 1-8 lists OCT variation with temperature and voltage after power-up calibration.
Table 1-8. OCT Variation after Power-up Calibration Nominal Voltage 3.0 2.5 1.8 1.5 1.2 dR/dT (%/C) 0.262 0.234 0.219 0.199 0.161 dR/dV(%/mV) 0.035 0.039 0.086 0.136 0.288
Pin Capacitance Table 1-9 lists the Arria II GX devices pin capacitance.
Table 1-9. Arria II GX Device Capacitance Symbol CIO Description Input capacitance on I/O pins, dual-purpose pins (differential I/O, clock, Rup, Rdn), and dedicated clock input pins Typical 7 Unit pF
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Chapter 1: Arria II GX Devices Data Sheet Electrical Characteristics
Internal Weak Pull-Up and Weak Pull-Down Resistors Table 1-10 lists the Arria II GX devices weak pull-up and pull-down resistor values.
Table 1-10. Arria II GX Internal Weak Pull-up and Weak Pull-Down Resistors (Note 1) Symbol Description Conditions VCC IO = 3.3 V 5% (2) VCC IO = 3.0 V 5% (2) Value of I/O pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. VCC IO = 2.5 V 5% (2) VCC IO = 1.8 V 5% (2) VCC IO = 1.5 V 5% (2) VCC IO = 1.2 V 5% (2) VCC IO = 3.3 V 5% VCC IO = 3.0 V 5% RPD Value of TCK pin pull-down resistor VCC IO = 2.5 V 5% VCC IO = 1.8 V 5% VCC IO = 1.5 V 5%
Notes to Table 1-10:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
Min. 7 7 8 10 13 19 6 6 6 7 8
Typ. 25 28 35 57 82 143 19 22 25 35 50
Max. 41 47 61 108 163 351 29 32 42 70 112
Unit k k k k k k k k k k k
RPU
Hot Socketing Table 1-11 lists the hot-socketing specification for Arria II GX devices.
Table 1-11. Arria II GX Hot Socketing Specifications Symbol IIIOPIN(DC) IIOPIN(AC) IXCVRTX(DC) IXCVRRX(DC)
Note to Table 1-11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which "C" is I/O pin capacitance and "dv/dt" is slew rate.
Description DC current per I/O pin AC current per I/O pin DC current per transceiver TX pin DC current per transceiver RX pin
Maximum 300 A 8 mA (1) 100 mA 50 mA
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Schmitt Trigger Input
The Arria II GX device supports Schmitt trigger input on TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rates. Table 1-12 lists the hysteresis specifications across the supported VCCIO range for Schmitt trigger inputs in Arria II GX devices.
Table 1-12. Arria II GX Schmitt Trigger Input Hysteresis Specifications Symbol Description Condition VCCIO = 3.3 V VSchmitt Hysteresis for Schmitt trigger input VCCIO = 2.5 V VCCIO = 1.8 V VCCIO = 1.5 V Minimum 220 180 110 70 Unit mV mV mV mV
I/O Standard Specifications
Table 1-13 through Table 1-18 list input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by Arria II GX devices. They also show the Arria II GX device family I/O standard specifications. VOL and VOH values are valid at the corresponding IOH and IOL, respectively. 1 For an explanation of terms used in Table 1-13 through Table 1-18, refer to "Glossary" on page 1-34. Table 1-13 lists the Arria II GX single-ended I/O standards.
Table 1-13. Single-Ended I/O Standards (Part 1 of 2) VCCIO (V) I/O Standard Min 3.3 V LVTTL 3.3 V LVCMOS 3.0 V LVTTL 3.0 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.135 3.135 2.85 2.85 2.375 1.71 1.425 1.14 Typ 3.3 3.3 3 3 2.5 1.8 1.5 1.2 Max 3.465 3.465 3.15 3.15 2.625 1.89 1.575 1.26 Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max 0.8 0.8 0.8 0.8 0.7 0.35 x VCC IO 0.35 x VCC IO 0.35 x VCC IO Min 1.7 1.7 1.7 1.7 1.7 0.65 x VCC IO 0.65 x VCC IO 0.65 x VCC IO Max 3.6 3.6 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 Max 0.45 0.2 0.45 0.2 0.4 0.45 0.25 * VCC IO 0.25 * VCC IO Min 2.4 VCCIO -0.2 2.4 VCCIO - 0.2 2 VCC IO - 0.45 0.75 x VC CIO 0.75 x VC CIO VIL (V) VIH (V) VO L (V) VOH (V) IOL (mA) 4 2 4 0.1 1 2 2 2 IOH (mA) -4 -2 -4 -0.1 -1 -2 -2 -2
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Table 1-13. Single-Ended I/O Standards (Part 2 of 2) VCCIO (V) I/O Standard Min 3.0-V PCI 3.0-V PCI-X 2.85 2.85 Typ 3 3 Max 3.15 3.15 Min -- -- Max 0.3 x VCC IO 0.35 x VCC IO Min 0.5 x VCC IO 0.5 x VCC IO Max VCCIO + 0.3 VCCIO + 0.3 Max 0.1 x VCC IO 0.1 x VCC IO Min 0.9 x VCC IO 0.9 x VCC IO VIL (V) VIH (V) VO L (V) VOH (V) IOL (mA) 1.5 1.5 IOH (mA) -0.5 -0.5
Table 1-14 lists the Arria II GX single-ended SSTL and HSTL I/O reference voltage specifications.
Table 1-14. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications VCC IO (V) I/O Standard Min SSTL-2 Class I, II SSTL-18 Class I, II SSTL-15 Class I, II HSTL-18 Class I, II HSTL-15 Class I, II HSTL-12 Class I, II 2.375 1.71 1.425 1.71 1.425 1.14 Typ 2.5 1.8 1.5 1.8 1.5 1.2 Max 2.625 1.89 1.575 1.89 1.575 1.26 Min 0.49 x VC CIO 0.833 0.47 x VC CIO 0.85 0.71 0.48 x VC CIO Typ 0.5 x VC CIO 0.9 0.5 x VC CIO 0.9 0.75 0.5 x VC CIO Max 0.51 x VCC IO 0.969 0.53 x VCC IO 0.95 0.79 0.52 x VCC IO Min VREF 0.04 VREF 0.04 0.47 x VCC IO 0.85 0.71 -- Typ VREF VREF 0.5 x VCCIO 0.9 0.75 VC CIO/2 Max VREF + 0.04 VREF + 0.04 0.53 x VC CIO 0.95 0.79 -- VREF (V) VTT (V)
Table 1-15 lists the Arria II GX single-ended SSTL and HSTL I/O standard signal specifications.
Table 1-15. Single-Ended SSTL and HSTL I/O Standard Signal Specifications (Part 1 of 2) VIL(DC ) (V) I/O Standard Min SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II SSTL-15 Class I SSTL-15 Class II HSTL-18 Class I -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 Max VREF 0.18 VREF 0.18 VREF 0.125 VREF 0.125 VREF 0.1 VREF 0.1 VREF 0.1 Min VREF + 0.18 VREF + 0.18 VREF + 0.125 VREF + 0.125 VREF + 0.1 VREF + 0.1 VREF + 0.1 Max VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 Max VREF - 0.35 VREF - 0.35 VREF - 0.25 VREF - 0.25 VREF - 0.175 VREF - 0.175 VREF - 0.2 Min VREF + 0.35 VREF + 0.35 VREF + 0.25 VREF + 0.25 VREF + 0.175 VREF + 0.175 VREF + 0.2 Max VTT 0.57 VTT 0.76 VTT 0.475 0.28 0.2 x VCCIO 0.2 x VCCIO 0.4 Min VTT + 0.57 VTT + 0.76 VTT + 0.475 VC CIO 0.28 0.8 x VCC IO 0.8 x VCC IO VC CIO 0.4 VIH (D C) (V) VIL(A C) (V) VIH(AC ) (V) VOL (V) VO H (V) IO L (mA) 8.1 16.4 6.7 13.4 8 16 8 IOH (mA) -8.1 -16.4 -6.7 -13.4 -8 -16 -8
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Table 1-15. Single-Ended SSTL and HSTL I/O Standard Signal Specifications (Part 2 of 2) VIL(DC ) (V) I/O Standard Min HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II HSTL-12 Class I HSTL-12 Class II -0.3 -0.3 -0.3 -0.15 -0.15 Max VREF 0.1 VREF 0.1 VREF 0.1 VREF 0.08 VREF 0.08 Min VREF + 0.1 VREF + 0.1 VREF + 0.1 VREF + 0.08 VREF + 0.08 Max VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.3 VCC IO + 0.15 VCC IO + 0.15 Max VREF - 0.2 VREF - 0.2 VREF - 0.2 VREF - 0.15 VREF - 0.15 Min VREF + 0.2 VREF + 0.2 VREF + 0.2 VREF + 0.15 VREF + 0.15 Max 0.4 0.4 0.4 0.25 x VCCIO 0.25 x VCCIO Min VC CIO 0.4 VC CIO 0.4 VC CIO 0.4 0.75 x VCC IO 0.75 x VCC IO VIH (D C) (V) VIL(A C) (V) VIH(AC ) (V) VOL (V) VO H (V) IO L (mA) 16 8 16 8 14 IOH (mA) -16 -8 -16 -8 -14
Table 1-16 lists the Arria II GX differential SSTL I/O standards.
Table 1-16. Differential SSTL I/O Standards VCC IO (V) I/O Standard Min SSTL-2 Class I, II 2.375 Typ 2.5 Max Min Max VC CIO VC CIO -- Min VCC IO/2 - 0.2 VCC IO/2 0.175 -- Typ -- Max VCCIO/2 + 0.2 VCCIO/2 + 0.175 -- Min 0.7 Max VCC IO VCC IO -- Min VC CIO/2 - 0.15 VC CIO/2 0.125 -- Typ -- Max VC CIO/2 + 0.15 VC CIO/2 + 0.125 -- 2.625 0.36 (Note 1) VSWIN G(DC ) (V) VX(A C) (V) VSWIN G(AC ) (V) VO X(AC ) (V)
SSTL-18 Class I, II SSTL-15 Class I, II
Note to Table 1-16:
1.71 1.425
1.8 1.5
1.89 1.575
0.25 0.2
-- VCC IO /2
0.5 0.35
-- VCC IO /2
(1) Pending silicon characterization.
Table 1-17 lists the Arria II GX HSTL I/O standards.
Table 1-17. Differential HSTL I/O Standards VCC IO (V) I/O Standard Min HSTL-18 Class I HSTL-15 Class I, II HSTL-12 Class I, II 1.71 1.425 1.14 Typ 1.8 1.5 1.2 Max 1.89 1.575 1.26 Min 0.2 0.2 0.16 Max -- -- -- Min 0.85 0.71 -- Typ -- -- 0.5 x VC CIO Max 0.95 0.79 -- Min 0.88 0.71 0.48 x VCC IO Typ -- -- 0.5 x VCC IO Max 0.95 0.79 0.52 x VCC IO Min 0.4 0.4 0.3 Max -- -- -- VDIF(DC) (V) VX (A C) (V) VC M(DC ) (V) VDIF(A C) (V)
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Table 1-18 lists the Arria II GX differential I/O standard specifications.
Table 1-18. Differential I/O Standard Specifications (Note 1) I/O Standard VCCIO (V) Min Typ Max Min VTH (mV) Cond. VC M = 1.25 V -- -- Max -- -- -- -- Min 0.05 1.05 -- -- 0.6 2.375 2.5 2.625 300 -- -- 1.0 VICM (V) (2) Cond. Dm ax <= 700 Mbps Dm ax > 700 Mbps -- -- Dm ax <= 700 Mbps Dm ax > 700 Mbps Max 1.80 0.247 1.55 -- -- 1.8 -- 1.6 -- -- -- -- -- 0.1 0.25 0.2 -- 0.6 0.6 0.5 1 1.2 1.2 1.4 1.4 -- 0.6 1.125 1.25 1.375 Min VOD (V) (3) Typ Max Min VOS (V) Typ Max
2.5V LVDS RSDS (4) MiniLVDS (4) LVPECL (5)
2.375
2.5
2.625
100
2.375 2.375
2.5 2.5
2.625 2.625
-- --
Notes to Table 1-18:
(1) (2) (3) (4) (5) 1.5 V PCML transceiver I/O standard specifications are described in "Transceiver Performance Specifications" on page 1-13. VIN range: 0 <= VIN <= 1.85 V. RL range: 90 <= RL <= 110 . RSDS and mini-LVDS I/O standards are only supported for differential outputs. LVPECL input standard is supported at the dedicated clock input pins (GCLK) only.
Power Consumption for Arria II GX Devices
Altera offers two ways to estimate power for a design:

the Excel-based Early Power Estimator. the Quartus(R) II PowerPlay Power Analyzer feature.
The interactive Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimates. f For more information about power estimation tools, refer to the Arria II GX EPE User Guide and the PowerPlay Power Analysis chapter.
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Switching Characteristics
This section provides performance characteristics of the Arria II GX core and periphery blocks for commercial grade devices. These characteristics can be designated as Preliminary or Final. Preliminary characteristics are created using simulation results, process data, and other known parameters. Final characteristics are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. 1 The table title shows the designations as "Preliminary" for each table with preliminary characteristics.
Transceiver Performance Specifications
Table 1-19 lists the Arria II GX transceiver specifications.
Table 1-19. Arria II GX Transceiver Specification (Part 1 of 4)--Preliminary (Note 1) Symbol/ Description Reference Clock Input frequency from REFCLK input pins Input frequency from PLD input Absolute VMAX for a REFCLK pin Absolute VMIN for a REFCLK pin Rise/fall time (9) Duty cycle Peak-to-peak differential input voltage Spread-spectrum modulating clock frequency Spread-spectrum downspread On-chip termination resistors VICM (AC coupled) VICM (DC coupled) -- -- -- -- -- -- -- 50 50 -- -0.3 -- 45 200 -- -- -- -- -- -- -- 622.08 200 2.2 -- 0.2 55 2000 50 50 -- -0.3 -- 45 200 -- -- -- -- -- -- -- 622.08 200 2.2 -- 0.2 55 2000 50 50 -- -0.3 -- 45 200 -- -- -- -- -- -- -- 622.08 200 2.2 -- 0.2 55 2000 MHz MHz V V UI % mV C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
PCI Express
30
-- 0 to -0.5% 100 1100 5%
33
30
-- 0 to -0.5% 100 1100 5%
33
30
-- 0 to -0.5 % 100 1100 5%
33
kHz
PCI Express -- -- HCSL I/O standard for PCI Express reference clock
-- --
-- --
-- --
-- --
-- --
-- --
-- mV
250
--
550
250
--
550
250
--
550
mV
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Table 1-19. Arria II GX Transceiver Specification (Part 2 of 4)--Preliminary (Note 1) Symbol/ Description Rref Transceiver Clocks Calibration block clock frequency fixedclk clock frequency reconfig_clk clock frequency Delta time between reconfig_clks (11) Transceiver block minimum power-down pulse width Receiver Data rate Absolute VM AX for a receiver pin (2) Absolute VM IN for a receiver pin Maximum peak-to-peak differential input voltage VID (diff p-p) Minimum peak-to-peak differential input voltage VID (diff p-p) -- -- -- VICM = 0.82 V setting VICM =1.1 V setting (3) Data Rate = 600 Mbps to 3.75 Gbps. VICM = 0.82 V setting VICM =1.1 V setting (3) 100 setting PCI Express XAUI PCI Express XAUI -- 600 -- -0.4 -- -- -- -- -- -- -- 3750 1.5 -- 2.7 1.6 600 -- -0.4 -- -- -- -- -- -- -- 3750 1.5 -- 2.7 1.6 600 -- -0.4 -- -- -- -- -- -- -- 3125 1.5 -- 2.7 1.6 Mbps V V V V -- PCI Express Receiver Detect Dynamic reconfiguration clock frequency -- 10 -- 2.5/ 37.5 (10) -- -- 125 125 -- 10 -- 2.5/ 37.5 (10) -- -- 125 125 -- 10 -- 2.5/ 37.5 (10) -- -- 125 125 -- MHz MHz C4 Conditions Min -- -- -- Typ 2000 1% Max -- Min -- Typ 2000 1% Max -- Min -- Typ 2000 1% Max -- C5, I5 C6 Unit
--
50
--
50
--
50
--
--
2
--
2
--
2
ms
--
--
1
--
--
1
--
--
1
--
s
100
--
--
100
--
--
100
--
--
mV
-- -- --
820 1100 100
-- -- --
-- -- --
820 1100 100
-- -- --
-- -- --
820 1100 100
-- -- --
mV mV
VICM
Differential on-chip termination resistors Return loss differential mode Return loss common mode Programmable PPM detector (4)
50 MHz to 1.25 GHz: -10dB 100 MHz to 2.5 GHz: -10dB 50 MHz to 1.25 GHz: -6dB 100 MHz to 2.5 GHz: -6dB 62.5, 100, 125, 200, 250, 300, 500, 1000 ppm
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Table 1-19. Arria II GX Transceiver Specification (Part 3 of 4)--Preliminary (Note 1) Symbol/ Description Run length Programmable equalization Signal detect/loss threshold CDR LTR time (5) CDR minimum T1b (6) LTD lock time (7) Data lock time from rx_freqlocked (8) C4 Conditions Min -- -- PCI Express (PIPE) Mode -- -- -- -- DC Gain Setting =0 Programmable DC gain DC Gain Setting =1 DC Gain Setting =2 Transmitter Data rate VOC M Differential on-chip termination resistors Return loss differential mode Return loss common mode Rise time (9) Fall time Intra-differential pair skew Intra-transceiver block skew Inter-transceiver block skew -- 0.65 V setting 100 setting PCI Express XAUI PCI Express -- -- -- PCI Express (PIPE) x4 PCI Express (PIPE) x8 50 50 -- -- -- -- -- -- -- -- 200 200 15 120 300 600 -- -- -- 650 100 3750 -- -- 600 -- -- -- 650 100 3750 -- -- 600 -- -- -- 650 100 3125 -- -- Mbps mV -- -- 65 -- 15 0 -- -- -- -- Typ 80 -- -- -- -- 100 -- 0 3 6 4000 4000 -- -- -- Max -- 7 175 75 Min -- -- 65 -- 15 0 -- -- -- -- Typ 80 -- -- -- -- 100 -- 0 3 6 Max -- 7 175 75 -- 4000 4000 -- -- -- Min -- -- 65 -- 15 0 -- -- -- -- Typ 80 -- -- -- -- 100 -- 0 3 6 Max -- 7 175 75 -- 4000 4000 -- -- -- UI dB mV s s ns ns dB dB dB C5, I5 C6 Unit
50 MHz to 1.25 GHz: -10dB 312 MHz to 625 MHz: -10dB 625 MHz to 3.125 GHz: -10dB/decade slope 50 MHz to 1.25 GHz: -6dB 50 50 -- -- -- -- -- -- -- -- 200 200 15 120 300 50 50 -- -- -- -- -- -- -- -- 200 200 15 120 300 ps ps ps ps ps
CMU PLL0 and CMU PLL1 CMU PLL lock time from CMUPLL_reset deassertion s
--
--
--
100
--
--
100
--
--
100
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Table 1-19. Arria II GX Transceiver Specification (Part 4 of 4)--Preliminary (Note 1) Symbol/ Description C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
PLD-Transceiver Interface Interface speed Digital reset pulse width
Notes to Table 1-19:
(1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Make sure that input specifications are not violated during this period. (2) The device cannot tolerate prolonged operation at this absolute maximum. (3) The 1.1-V RX VIC M setting must be used if the input serial data standard is LVDS and the link is DC-coupled. (4) The rate matcher supports only up to +/-300 parts per million (ppm). (5) Time taken to rx_pll_locked goes high from rx_analogreset deassertion. Refer to Figure 1-1. (6) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1-1. (7) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1-1. (8) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1-2. (9) Rise/fall time is specified from 20% to 80%. (10) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in receiver only or receiver and transmitter mode. For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II GX Devices. (11) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels physically located on the same side of the device; and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed.
-- --
25
--
200
25
--
200
25
--
200
MHz
Minimum is 2 parallel clock cycles
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Figure 1-1 shows the lock time parameters in manual mode. 1 LTD = lock-to-data. LTR = lock-to-reference.
Figure 1-1. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_locked
r x_locktodata
Invalid Data r x_dataout
Valid data
CDR LTR Time
LTD lock time
CDR Minimum T1b
Figure 1-2 shows the lock time parameters in automatic mode.
Figure 1-2. Lock Time Parameters for Automatic Mode
CDR status
LTR
LTD
r x_freqlocked
r x_dataout
Invalid
data
Valid
data
Data lock time from rx_freqlocked
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Figure 1-3 shows the differential receiver input waveform.
Figure 1-3. Receiver Input Waveform
Single-Ended Waveform Positive Channel (p) VID Negative Channel (n) VCM Ground
Differential Waveform
VID (diff peak-peak) = 2 x VID (single-ended) VID p-n=0V VID
Figure 1-4 shows the transmitter output waveform.
Figure 1-4. Transmitter Output Waveform--Preliminary
Single-Ended Waveform Positive Channel (p) VOD Negative Channel (n) VCM Ground
Differential Waveform
VOD (diff peak-peak) = 2 x VOD (single-ended) VOD p-n=0V VOD
Table 1-20 lists the typical VOD for TX term that equals 100 . .
Table 1-20. Typical VOD Setting, TX Termination = 100 Quartus II Setting 1 2 4 5 6 7 VOD Setting (mV) 400 600 800 900 1000 1200
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Table 1-21 lists the Arria II GX transceiver block AC specifications.
Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 1 of 6)--Preliminary Symbol/ Description C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
SONET/SDH Transmit Jitter Generation Peak-to-peak jitter at 622.08 Mbps RMS jitter at 622.08 Mbps Peak-to-peak jitter at 2488.32 Mbps RMS jitter at 2488.32 Mbps Pattern = PRBS23 Pattern = PRBS23 Pattern = PRBS23 Pattern = PRBS23 -- -- -- -- -- -- -- -- 0.1 0.01 0.1 0.01 -- -- -- -- -- -- -- -- 0.1 0.01 0.1 0.01 -- -- -- -- -- -- -- -- 0.1 0.01 0.1 0.01 UI UI UI UI
SONET/SDH Receiver Jitter Tolerance Jitter frequency = 0.03 KHz Pattern = PRBS23 Jitter tolerance at 622.08 Mbps Jitter frequency = 25 KHZ Pattern = PRBS23 Jitter frequency = 250 KHz Pattern = PRBS23 Jitter frequency = 0.06 KHz Pattern = PRBS23 Jitter frequency = 100 KHZ Jitter tolerance at 2488.32 Mbps Pattern = PRBS23 Jitter frequency = 1 MHz Pattern = PRBS23 Jitter frequency = 10 MHz Pattern = PRBS23 Fibre Channel Transmit Jitter Generation (3), (10) Total jitter FC-1 Deterministic jitter FC-1 Total jitter FC-2 Deterministic jitter FC-2 Pattern = CRPAT Pattern = CRPAT Pattern = CRPAT Pattern = CRPAT -- -- -- -- -- -- -- -- 0.23 0.11 0.33 0.2 -- -- -- -- -- -- -- -- 0.23 0.11 0.33 0.2 -- -- -- -- -- -- -- -- 0.23 0.11 0.33 0.2 UI UI UI UI > 0.15 > 0.15 > 0.15 UI > 0.15 > 0.15 > 0.15 UI > 1.5 > 1.5 > 1.5 UI > 15 > 15 > 15 UI > 0.15 > 0.15 > 0.15 UI > 1.5 > 1.5 > 1.5 UI > 15 > 15 > 15 UI
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Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 2 of 6)--Preliminary Symbol/ Description C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
Fibre Channel Receiver Jitter Tolerance (3), (11) Deterministic jitter FC-1 Random jitter FC-1 Sinusoidal jitter FC-1 Deterministic jitter FC-2 Random jitter FC-2 Sinusoidal jitter FC-2 Pattern = CJTPAT Pattern = CJTPAT Fc/25000 Fc/1667 Pattern = CJTPAT Pattern = CJTPAT Fc/25000 Fc/1667 > 0.37 > 0.31 > 1.5 > 0.1 > 0.33 > 0.29 > 1.5 > 0.1 > 0.37 > 0.31 > 1.5 > 0.1 > 0.33 > 0.29 > 1.5 > 0.1 > 0.37 > 0.31 > 1.5 > 0.1 > 0.33 > 0.29 > 1.5 > 0.1 UI UI UI UI UI UI UI UI
XAUI Transmit Jitter Generation (4) Total jitter at 3.125 Gbps Deterministic jitter at 3.125 Gbps Pattern = CJPAT Pattern = CJPAT -- -- -- -- 0.3 0.17 -- -- -- -- 0.3 0.17 -- -- -- -- 0.3 0.17 UI UI
XAUI Receiver Jitter Tolerance (4) Total jitter Deterministic jitter Peak-to-peak jitter Peak-to-peak jitter Peak-to-peak jitter Jitter frequency = 22.1 KHz Jitter frequency = 1.875 MHz Jitter frequency = 20 MHz > 0.65 > 0.37 > 8.5 > 0.1 > 0.1 > 0.65 > 0.37 > 8.5 > 0.1 > 0.1 > 0.65 > 0.37 > 8.5 > 0.1 > 0.1 UI UI UI UI UI
PCI Express Transmit Jitter Generation (5) Total jitter at 2.5 Gbps (Gen1) Compliance pattern -- -- 0.25 -- -- 0.25 -- -- 0.25 UI
PCI Express Receiver Jitter Tolerance (5) Total jitter at 2.5 Gbps (Gen1) Compliance pattern > 0.6 > 0.6 > 0.6 UI
Serial RapidIO Transmit Jitter Generation (6) Deterministic jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT -- -- 0.35 -- -- 0.35 -- -- 0.35 UI -- -- 0.17 -- -- 0.17 -- -- 0.17 UI
Total jitter (peak-to-peak)
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Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 3 of 6)--Preliminary Symbol/ Description C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
Serial RapidIO Receiver Jitter Tolerance (6) Deterministic jitter tolerance (peak-to-peak) Combined deterministic and random jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Jitter Frequency = 22.1 KHz Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Jitter Frequency = 1.875 MHz Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Jitter Frequency = 20 MHz Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT GIGE Transmit Jitter Generation (7) Deterministic jitter (peak-to-peak) Total jitter (peak-to-peak) Pattern = CRPAT Pattern = CRPAT -- -- -- -- 0.14 0.279 -- -- -- -- 0.14 0.279 -- -- -- -- 0.14 0.279 UI UI > 0.1 > 0.1 > 0.1 UI > 0.1 > 0.1 > 0.1 UI > 0.55 > 0.55 > 0.55 UI > 0.37 > 0.37 > 0.37 UI
> 8.5
> 8.5
> 8.5
UI
GIGE Receiver Jitter Tolerance (7) Deterministic jitter tolerance (peak-to-peak) Combined deterministic and random jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.4 > 0.4 > 0.4 UI
Pattern = CJPAT
> 0.66
> 0.66
> 0.66
UI
HiGig Transmit Jitter Generation (8) Deterministic jitter (peak-to-peak) Data Rate = 3.75 Gbps Pattern = CJPAT Data Rate = 3.75 Gbps Pattern = CJPAT -- -- 0.35 -- -- -- -- -- -- UI -- -- 0.17 -- -- -- -- -- -- UI
Total jitter (peak-to-peak)
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 4 of 6)--Preliminary Symbol/ Description C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
HiGig Receiver Jitter Tolerance (8) Deterministic jitter tolerance (peak-to-peak) Combined deterministic and random jitter tolerance (peak-to-peak) Data Rate = 3.75 Gbps Pattern = CJPAT Data Rate = 3.75 Gbps Pattern = CJPAT Jitter Frequency = 22.1 KHz Data Rate = 3.75 Gbps Pattern = CJPAT Jitter Frequency = 1.875MHz Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 3.75 Gbps Pattern = CJPAT Jitter Frequency = 20 MHz Data Rate = 3.75 Gbps Pattern = CJPAT SDI Transmitter Jitter Generation (9) Data Rate = 1.485 Gbps (HD) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz Data Rate = 2.97 Gbps (3G) Pattern = Color Bar Low-Frequency Roll-Off = 100 KHz > 0.1 -- -- -- -- -- -- UI > 0.1 -- -- -- -- -- -- UI > 8.5 -- -- -- -- -- -- UI > 0.65 -- -- -- -- -- -- UI > 0.37 -- -- -- -- -- -- UI
0.2
--
--
0.2
--
--
0.2
--
--
UI
Alignment jitter (peak-to-peak)
0.3
--
--
0.3
--
--
0.3
--
--
UI
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
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Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 5 of 6)--Preliminary Symbol/ Description C4 Conditions Min Typ Max Min Typ Max Min Typ Max C5, I5 C6 Unit
SDI Receiver Jitter Tolerance (9) Jitter Frequency = 15 KHz Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar Jitter Frequency = 100 KHz Sinusoidal jitter tolerance (peak-to-peak) Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar Jitter Frequency = 148.5 MHz Data Rate = 2.97 Gbps (3G) Pattern = Single Line Scramble Color Bar > 0.3 > 0.3 > 0.3 UI > 0.3 > 0.3 > 0.3 UI >2 >2 >2 UI
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
Table 1-21. Arria II GX Transceiver Block AC Specification (Note 1), (2) (Part 6 of 6)--Preliminary Symbol/ Description C4 Conditions Min Jitter Frequency = 20 KHz Data Rate = 1.485 Gbps (HD) Pattern = 75% Color Bar Sinusoidal Jitter Tolerance (peak-to-peak) Jitter Frequency = 100 KHz Data Rate = 1.485 Gbps (HD) Pattern = 75% Color Bar Jitter Frequency = 148.5 MHz Data Rate = 1.485 Gbps (HD) Pattern =75% Color Bar
Notes to Table 1-21:
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Dedicated refclk pins were used to drive the input reference clocks. The Jitter numbers specified are valid for the stated conditions only. The jitter numbers for Fibre Channel are compliant to the FC-PI-4 Specification revision 6.10. The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification. The jitter numbers for PCI Express (PIPE) are compliant to the PCIe Base Specification 2.0. The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3. The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. The jitter numbers for HiGig are compliant to the IEEE802.3ae-2002 Specification. The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications. The Fibre Channel transmitter jitter generation numbers are compliant to the specification at T inter operability point. The Fibre Channel receiver jitter tolerance numbers are compliant to the specification at R interpretability point.
C5, I5 Max Min Typ Max Min
C6 Unit Typ Max
Typ
>1
>1
>1
UI
> 0.2
> 0.2
> 0.2
UI
> 0.2
> 0.2
> 0.2
UI
Core Performance Specifications for Arria II GX Devices
This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), embedded memory, configuration, and JTAG specifications.
Clock Tree Specifications
Table 1-22 lists the clock tree specifications for Arria II GX devices.
Table 1-22. Arria II GX Clock Tree Performance --Preliminary Performance Clock Network C4 GCLK and RCLK PCLK 500 420 C5,I5 500 350 C6 400 280 MHz MHz Unit
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PLL Specifications
Table 1-23 lists the PLL specifications for Arria II GX devices.
Table 1-23. Arria II GX PLL Specifications (Part 1 of 2)--Preliminary Symbol Description Input clock frequency (from clock input pins residing in right/top/bottom banks) (-4 Speed Grade) fIN Input clock frequency (from clock input pins residing in right/top/bottom banks) (-5 Speed Grade) Input clock frequency (from clock input pins residing in right/top/bottom banks) (-6 Speed Grade) fINPF D fVC O fINDUTY fEINDUTY tINCC J (3) Input frequency to the PFD PLL VCO operating Range (2) Input clock duty cycle External feedback clock input duty cycle Input clock cycle-to-cycle jitter (Frequency 100 MHz) Input clock cycle-to-cycle jitter (Frequency 100 MHz) Output frequency for internal global or regional clock (-4 Speed Grade) fOUT Output frequency for internal global or regional clock (-5 Speed Grade) Output frequency for internal global or regional clock (-6 Speed Grade) Output frequency for external clock output (-4 Speed Grade) fOUT_EXT tOUTDUTY tOUTPJ _DC tOUTCC J_DC fOUTPJ _IO fOUTCC J_IO tCONF IGPLL tCONF IGPHAS E fSC ANC LK tLOCK tDLOCK Output frequency for external clock output (-5 Speed Grade) Output frequency for external clock output (-6 Speed Grade) Duty cycle for external clock output (when set to 50%) Dedicated clock output period jitter (fOUT 100 MHz) Dedicated clock output period jitter (fOUT 100 MHz) Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz) Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz) Regular I/O clock output period jitter (fOUT 100 MHz) Regular I/O clock output period jitter (fOUT 100 MHz) Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz) Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz) Time required to reconfigure PLL scan chains Time required to reconfigure phase shift SCANCLK frequency Time required to lock from end of device configuration Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) Min 5 5 5 5 600 40 40 -- -- -- -- -- -- -- -- 45 -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 -- -- -- -- -- -- -- -- 3.5 1 -- -- -- Max 670 (1) 622 (1) 500 (1) 325 1,300 60 60 0.15 750 500 500 400 670 (4) 622 (4) 500 (4) 55 300 30 300 30 650 65 650 65 -- -- 100 1 1 Unit MHz MHz MHz MHz MHz % % UI (p-p) ps (p-p) MHz MHz MHz MHz MHz MHz % ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) SCANCLK cycles SCANCLK cycles MHz ms ms
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
Table 1-23. Arria II GX PLL Specifications (Part 2 of 2)--Preliminary Symbol fCL B W tPLL_P SERR tARES ET Description PLL closed-loop low bandwidth PLL closed-loop medium bandwidth PLL closed-loop high bandwidth Accuracy of PLL phase shift Minimum pulse width on areset signal Min -- -- -- -- 10 Typ 0.3 1.5 4 -- -- Max -- -- -- 50 -- Unit MHz MHz MHz ps ns
Notes to Table 1-23:
(1) fIN is limited by I/O f MAX . (2) The VCO frequency reported by the Quartus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is less than 200 ps. (4) This specification is limited by the lower of the two: I/O fM AX or f OUT of the PLL.
DSP Block Specifications
Table 1-24 lists the Arria II GX DSP block performance specifications.
Table 1-24. Arria II GX DSP Block Performance Specifications (Note 1) --Preliminary Performance Unit Number of Multipliers 9 x 9-bit multiplier 12 x 12-bit multiplier 18 x 18-bit multiplier 36 x 36-bit multiplier 18 x 36-bit high-precision multiplier adder mode 18 x 18-bit multiply accumulator 18 x 18-bit multiply adder 18 x 18-bit multiply adder-signed full precision 18 x 18-bit multiply adder with loopback (2) 36-bit shift (32-bit data) Double mode
Notes to Table 1-24:
(1) Maximum is for fully-pipelined block with Round and Saturation disabled. (2) Maximum for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled.
Resources Used Mode C4 380 380 380 350 350 380 380 380 275 350 350
C5,I5 300 300 300 270 270 300 300 300 220 270 270
C6 250 250 250 220 220 250 250 250 180 220 220 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
1 1 1 1 1 4 4 2 2 1 1
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Embedded Memory Block Specifications
Table 1-25 lists the Arria II GX embedded memory block specifications.
Table 1-25. Arria II GX Embedded Memory Block Performance Specifications --Preliminary Resources Used Memory Memory Logic Array Block (MLAB) Mode ALUTs Single port 64 x 10 Simple dual-port 32 x 20 single clock Simple dual-port 64 x 10 single clock Single-port 256 x 36 Single-port 256 x 36, with the read-during-write option set to Old Data Simple dual-port 256 x 36 single CLK M9K Block Single-port 256 x 36 single CLK, with the read-during-write option set to Old Data True dual port 512 x 18 single CLK True dual-port 512 x 18 single CLK, with the read-during-write option set to Old Data 0 0 0 0 0 0 0 0 0 Embedded Memory 1 1 1 1 1 1 1 1 1 C4 500 500 500 400 280 400 280 400 280 Performance Unit C5,I5 450 450 450 360 250 360 250 360 250 C6 378 378 378 310 210 310 210 310 210 MHz MHz MHz MHz MHz MHz MHz MHz MHz
Configuration
Table 1-26 lists the Arria II GX configuration mode specifications.
Table 1-26. Arria II GX Configuration Mode Specifications--Preliminary Programming Mode Passive Serial Fast Passive Parallel Fast Active Serial Remote Update only in Fast AS mode DCLK FMAX 125 125 40 10 Unit MHz MHz MHz MHz
JTAG Specifications
Table 1-27 lists the JTAG timing parameters and values for Arria II GX devices.
Table 1-27. Arria II GX JTAG Timing Parameters and Values--Preliminary (Part 1 of 2) Symbol tJC P tJC H tJC L tJP SU (TDI) tJP SU (TMS ) tJP H tJP CO TCK clock period TCK clock high time TCK clock low time TDI JTAG port setup time TMS JTAG port setup time JTAG port hold time JTAG port clock to output Description Min 30 14 14 1 3 5 -- Max -- -- -- -- -- -- 11 (1) Unit ns ns ns ns ns ns ns
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
Table 1-27. Arria II GX JTAG Timing Parameters and Values--Preliminary (Part 2 of 2) Symbol tJP ZX tJP XZ Description JTAG port high impedance to valid output JTAG port valid output to high impedance Min -- -- Max 14 (1) 14 (1) Unit ns ns
Note to Table 1-27:
(1) A 1-ns adder is required for each VCC IO voltage step down from 3.3 V. For example, tJP CO = 12 ns if VCC IO of the TDO I/O bank = 2.5 V, or 13 ns if it equals to 1.8 V.
Periphery Performance
This section describes periphery performance, including high-speed I/O, external memory interface, and IOE programmable delay. I/O performance supports several system interfacing, for example the high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using general purpose I/O (GPIO) standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 200 MHz interfacing frequency with 10pF load. 1 Actual achievable frequency depends on design- and system-specific factors. You should perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specification
Table 1-28 lists the high-speed I/O timing for Arria II GX devices.
Table 1-28. High-Speed I/O Specifications (Part 1 of 3)--Preliminary C4 Symbol Clock fHSCLK_IN (input clock frequency)-Row I/O fHSCLK_IN (input clock frequency)-Column I/O fHSCLK_OUT (output clock frequency)-Row I/O fHSCLK_OUT (output clock frequency)-Column I/O Clock boost factor, W = 1 to 40 (1) 5 670 5 622 5 500 MHz Conditions Min Max Min Max Min Max C5,I5 C6 Unit
Clock boost factor, W = 1 to 40 (1)
5
500
5
472.5
5
472.5
MHz
--
5
670
5
622
5
500
MHz
--
5
500
5
472.5
5
472.5
MHz
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Table 1-28. High-Speed I/O Specifications (Part 2 of 3)--Preliminary C4 Symbol Transmitter fHSDR_TX (true LVDS output data rate) SERDES factor, J = 3 to 10 (using dedicated SERDES) SERDES factor, J = 4 to 10 (using logic elements as SERDES) SERDES factor, J = 2 (using DDR registers) and J = 1 (using SDR register) 150 1,250 (2) 150 1,050 (2) 150 840 Mbps Conditions Min Max Min Max Min Max C5,I5 C6 Unit
(3)
945
(3)
840
(3)
740
Mbps
fHSDR_TX (true LVDS output data rate)
(3)
(3)
(3)
(3)
(3)
(3)
Mbps
fHSDR_TX_E3R (emulated LVDS_E_3R output data rate) (7)
SERDES factor, J = 4 to 10
(3)
945
(3)
840
(3)
740
Mbps
True LVDS with dedicated SERDES (data rate 600-1,250 Mbps) True LVDS with dedicated SERDES (data rate < 600 Mbps) tTX_JITTER (4) True LVDS and Emulated LVDS_E_3R with logic elements as SERDES (data rate 600-945 Mbps) True LVDS and Emulated LVDS_E_3R with logic elements as SERDES (data rate < 600 Mbps) tTX_DCD True LVDS and Emulated LVDS_E_3R True LVDS and Emulated LVDS_E_3R
--
175
--
225
--
300
ps
--
0.105
--
0.135
--
0.18
UI
--
260
--
300
--
350
ps
--
0.16
--
0.18
--
0.21
UI
45
55
45
55
45
55
%
tRISE & t FALL
--
200
--
225
--
250
ps
True LVDS (5) TCCS Emulated LVDS_E_3R
--
150
--
175
--
200
ps
--
200
--
250
--
300
ps
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
Table 1-28. High-Speed I/O Specifications (Part 3 of 3)--Preliminary C4 Symbol Receiver (6) fHSDR_RX Soft-CDR PPM tolerance DPA run length SW
Notes to Table 1-28:
(1) fHS CLK_IN = f HS DR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate. (2) This applies to interfacing with DPA receivers. For interfacing with non-DPA receivers, maximum supported data rate is 945 Mbps. Beyond 840 Mbps, PCB trace compensation is required. PCB trace compensation refers to the adjustment of PCB trace length for LVDS channels to improve channel-to-channel skews, and is required to support date rate beyond 840 Mbps. (3) The minimum and maximum specification is dependent on the clock source (for example, PLL and clock pin) and the clock routing resource you use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate. (4) The specification is only applicable under the influence of core noise. (5) Specification is only applicable for true LVDS using dedicated SERDES. (6) Dedicated SERDES and DPA features are only available on right banks. (7) You are required to calculate the left over timing margin in the receiver by performing the link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew and the receiver sampling margin to determine the left over timing margin.
C5,I5 Max Min Max Min
C6 Unit Max
Conditions Min
DPA mode (6) Non-DPA mode (7) Soft-CDR mode DPA mode Non-DPA mode (5)
150 (3) -- -- --
1,250 945 (6) 300 10,000 300
150 (3) -- -- --
1,050 740 300 10,000 350
150 (3) -- -- --
840 640 300 10,000 400
Mbps Mbps PPM UI ps
Table 1-29 lists DPA lock time specifications for Arria II GX devices.
Table 1-29. DPA Lock Time Specifications (Note 1), (2), (3) Number of Data Transitions in One Repetition of the Training Pattern 2 2 4 8 8 Number of Repetitions per 256 Data Transitions (4) 128 128 64 32 32
Standard SPI-4 Parallel Rapid I/O Miscellaneous
Notes to Table 1-29:
(1) (2) (3) (4)
Training Pattern 00000000001111111111 00001111 10010000 10101010 01010101
Maximum 640 data transitions 640 data transitions 640 data transitions 640 data transitions 640 data transitions
The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1-to-0 transition. The DPA lock time stated in the table applies to both commercial and industrial grade. This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
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Figure 1-5 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification.
Figure 1-5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P Frequency baud/1667 20 MHz
External Memory Interface Specifications
f For the maximum clock rate supported for Arria II GX device family, refer to the External Memory Interface System Specifications. Table 1-30 lists DLL frequency range specifications for Arria II GX devices.
Table 1-30. Arria II GX DLL Frequency Range Specifications--Preliminary Frequency Range (MHz) Frequency Mode C4 0 1 2 3 4 5 60-140 80-180 100-220 120-270 160-340 190-410 C5,I5 60-130 80-170 100-210 120-260 160-310 190-380 C6 60-110 80-150 100-180 120-220 160-270 190-320 22.5 30 36 45 30 36 Resolution ()
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Chapter 1: Arria II GX Devices Data Sheet Switching Characteristics
Table 1-31 lists the DQS phase offset delay per stage for Arria II GX devices.
Table 1-31. DQS Phase Offset Delay Per Setting Speed Grade C4 C5, I5 C6
Notes to Table 1-31:
(1) The valid settings for phase offset are -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 5. (2) The typical value equals the average of the minimum and maximum values. (3) Delay settings are linear.
(Note 1), (2), (3)--Preliminary Max 13.0 15.0 18.0 Unit ps ps ps
Min 7.0 7.0 8.5
Duty Cycle Distortion (DCD) Specifications
Table 1-32 lists the worst-case DCD for Arria II GX devices.
Table 1-32. Duty Cycle Distortion on Arria II GX I/O Pins--Preliminary (Note 1) C4 Symbol Min Output Duty Cycle
Note to Table 1-32:
(1) DCD specification applies to clock outputs from PLL, global clock tree, and IOE driving dedicated as well as general purpose I/O pins.
C5,I5 Max 55 Min 45 Max 55 Min 45
C6 Unit Max 55 %
45
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IOE Programmable Delay
Table 1-33 lists the delay associated with each supported IOE programmable delay chain.
Table 1-33. Arria II GX IOE Programmable Delay Maximum Offset Parameter Available Settings (1) Minimum Offset (2) Fast Model Industrial Output Enable Pin delay Delay from Output Register to Output pin Input Delay form Pin to Internal Cell Input Delay form Pin to Input Register DQS Bus to Input Register Delay
Notes to Table 1-33:
(1) The available setting for every delay chain starts from zero and end with the specified maximum numbers of setting. (2) The minimum offset represented in the table does not include the intrinsic delay.
Slow Model C4 0.713 C5 0.796 C6 0.873 I5 0.801
Unit
Commercial 0.442
7
0
0.413
ns
7
0
0.339
0.362
0.585
0.654
0.722
0.661
ns
52
0
1.494
1.607
2.521
2.732
2.943
2.775
ns
52
0
1.494
1.607
2.520
2.733
2.944
2.775
ns
4
0
0.074
0.076
0.124
0.147
0.167
0.147
ns
I/O Timing
Altera offers two ways to determine I/O timing:

the Excel-based I/O Timing. the Quartus II Timing Analyzer.
The Excel-based I/O Timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Quartus II timing analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after place-and-route is complete. f The Excel-based I/O Timing spreadsheet is downloadable from the Arria II GX Devices Literature webpage.
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Chapter 1: Arria II GX Devices Data Sheet Glossary
Glossary
Table 1-34 shows the glossary for this chapter.
Table 1-34. Glossary (Part 1 of 4) Letter A B C Subject -- -- -- Receiver Input Waveforms Definitions -- -- --
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground
Differential Waveform
VOD p-n=0V VOD
D
Differential I/O Standards Transmitter Output Waveforms
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground
Differential Waveform
VID p-n=0V VID
E fHSCLK F fHSDR fHSDRDPA
-- Left/Right PLL input clock frequency.
-- High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (f HS DR = 1/TUI), non-DPA. High-Speed I/O Block: Maximum/minimum LVDS data transfer rate (f HS DRDPA = 1/TUI), DPA.
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Table 1-34. Glossary (Part 2 of 4) Letter G H I J Subject -- -- -- Definitions -- -- -- High-Speed I/O Block: Deserialization factor (width of parallel data bus). JTAG Timing Specifications are in the following figure:
TMS
TDI
J
JTAG Timing Specifications
TCK
t JCP t JCH t JCL t JPSU t JPH
tJPZX TDO
t JPCO
t JPXZ
K L M N O
-- -- -- -- -- Diagram of PLL Specifications (1)
-- -- -- -- -- The block diagram shown in the following figure highlights the PLL Specification parameters:
Switchover
CLKOUT Pins
fOUT_EXT
CLK
fIN
N
fINPFD
PFD CP LF VCO
P
PLL Specifications
K
fVCO
Core Clock
Counters C0..C9
fOUT
GCLK
RCLK
M
Key Reconfigurable in User Mode External Feedback
Note:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
Q R RL
--
-- Receiver differential input discrete resistor (external to the Arria II GX device).
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Chapter 1: Arria II GX Devices Data Sheet Glossary
Table 1-34. Glossary (Part 3 of 4) Letter Subject Definitions The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window: Timing Diagram SW (sampling window)
RSKM
Bit Time
0.5 x TCCS
Sampling Window (SW)
RSKM
0.5 x TCCS
The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. Once the receiver input has crossed the AC value, the receiver changes to the new logic state. S The new logic state is then maintained as long as the input stays beyond the AC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: Single-Ended Voltage Referenced I/O Standard Single-ended Voltage Referenced I/O Standard
VOH VIH (AC )
VCCIO
VIH(DC) VREF
VIL(DC) VIL(AC ) VOL
VSS
tC TCCS (channel-tochannelskew)
High-speed receiver and transmitter input and output clock period. The timing difference between the fastest and slowest output edges, including tC O variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under S in this table). High-speed I/O Block: Duty cycle on high-speed transmitter output clock.
T
tDUTY
Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC /w)
tFALL tINC CJ tOUTP J_IO tOUTP J_DC tRIS E U --
Signal high-to-low transition time (80-20%) Cycle-to-cycle jitter tolerance on PLL clock input Period jitter on general purpose I/O driven by a PLL Period jitter on dedicated clock output driven by a PLL Signal low-to-high transition time (20-80%) --
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Table 1-34. Glossary (Part 4 of 4) Letter VICM VID VDIF(A C) VDIF(DC ) VIH V VIH(AC ) VIH(DC) VIL VIL(AC ) VIL(DC) VOCM VOD W X Y Z W -- -- -- Subject VCM (DC ) DC Common Mode Input Voltage. Input Common Mode Voltage: The common mode of the differential signal at the receiver. Input differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. AC differential Input Voltage: Minimum AC input differential voltage required for switching. DC differential Input Voltage: Minimum DC input differential voltage required for switching. Voltage Input High: The minimum positive voltage applied to the input which is accepted by the device as a logic high. High-level AC input voltage High-level DC input voltage Voltage Input Low: The maximum positive voltage applied to the input which is accepted by the device as a logic low. Low-level AC input voltage Low-level DC input voltage Output Common Mode Voltage: The common mode of the differential signal at the transmitter. Output differential Voltage Swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. High-Speed I/O BLOCK: Clock Boost Factor -- -- -- Definitions
Document Revision History
Table 1-35 lists the revision history for this chapter.
Table 1-35. Document Revision History (Part 1 of 2) Date March 2010 Version 2.3 Changes Made Updated for the Quartus II version 9.1 SP2 release:
Updated Table 1-3, Table 1-7, Table 1-19, Table 1-21, Table 1-22, Table 1-24, Table 1-25 and Table 1-33. Updated "Recommended Operating Conditions" section. Minor text edits.

February 2010 February 2010
2.2 2.1
Updated Table 1-19. Updated for Arria II GX v9.1 SP1 release:

Updated Table 1-19, Table 1-23, Table 1-28, Table 1-30, and Table 1-33. Added Figure 1-5. Minor text edits.
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Chapter 1: Arria II GX Devices Data Sheet Document Revision History
Table 1-35. Document Revision History (Part 2 of 2) Date November 2009 Version 2.0 Changes Made Updated for Arria II GX v9.1 release:
Updated Table 1-1, Table 1-4, Table 1-13, Table 1-14, Table 1-19, Table 1-15, Table 1-22, Table 1-24, and Table 1-28. Added Table 1-6 and Table 1-33. Added "Bus Hold" on page 1-5. Added "IOE Programmable Delay" section. Minor text edit. Updated Table 1-1, Table 1-3, Table 1-7, Table 1-8, Table 1-18, Table 1-23, Table 1-25, Table 1-26, Table 1-29, Table 1-30, Table 1-31, Table 1-32, and Table 1-33. Added Table 1-32. Updated Equation 1-1.

June 2009
1.2

March 2009 February 2009
1.1 1.0
Added "I/O Timing" section. Initial release.
Arria II GX Device Handbook Volume 3
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Altera Corporation
2. Addendum to the Arria II GX Device Handbook
AIIGX53002-1.1
This chapter describes changes to the published version of the Arria II GX Device Handbook. It describes the new maximum data rate for high-speed LVDS I/O with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry, an additional device feature highlight, the emulated LVDS output buffers, external memory interface maximum performance, and guidelines for connecting serial configuration device to Arria(R) II GX device family on active serial (AS) interface. Table 2-1 lists the changes and chapter described in this addendum.
Table 2-1. Changes to the Arria II GX Device Handbook Change "Highlights" "High-Speed LVDS I/O with DPA and Soft CDR" "Auto-Calibrating External Memory Interfaces" "Guidelines for Connecting Serial Configuration Device to Arria II GX Device Family on AS Interface" Chapter
Arria II GX Device Family Overview Arria II GX Device Family Overview Arria II GX Device Family Overview Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
1
Any information not contained in this addendum is considered the same as the information contained in the published version of the Arria II GX Device Handbook.
Highlights
A new Arria II GX device feature highlight is the emulated LVDS output support with a data rate of up to 945 Mbps. The maximum data rate for high-speed LVDS I/O with serializer/deserializer (SERDES) and dynamic phase alignment (DPA) circuitry changed to 1.25 Gbps. The affected section is the "Highlights" section in the Arria II GX Device Family Overview chapter.
High-Speed LVDS I/O with DPA and Soft CDR
Dedicated circuitry for implementing LVDS interfaces at speeds from 150 Mbps to 1.25Gbps. DPA circuitry and soft-CDR circuitry at the receiver automatically compensates for channel-to-channel and channel-to-clock skew in sourcesynchronous interfaces and allows for implementation of asynchronous serial interfaces with embedded clocks at data rates from 150 Mbps to 1.25 Gbps. The emulated LVDS output buffers use two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS, and RSDS standards. The affected section is the "High-Speed LVDS I/O with DPA and Soft CDR" in the Arria II GX Device Family Overview chapter. 1 When this revision is included in the Arria II GX Device Family Overview chapter, the "High-Speed LVDS I/O with DPA and Soft CDR" section title will be changed to the "High-Speed LVDS I/O and DPA".
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Altera Corporation
Arria II GX Device Handbook Volume 3
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Chapter 2: Addendum to the Arria II GX Device Handbook Auto-Calibrating External Memory Interfaces
Auto-Calibrating External Memory Interfaces
Table 2-2 lists the changes to the external memory interface maximum performance for Arria II GX devices. The memory maximum performance in Table 2-2 is pending device characterization. f All external memory interface specifications not contained in this addendum remain the same as in "Table 1-7: Arria II GX Device External Memory Interface Maximum Performance" of the Arria II GX Device Family Overview chapter.
Table 2-2. Arria II GX Device External Memory Interface Maximum Performance Memory Type DDR2 SDRAM DDR3 SDRAM Maximum Performance 333 MHz 400 MHz
Guidelines for Connecting Serial Configuration Device to Arria II GX Device Family on AS Interface
For single- and multi-device AS configurations, the board trace length and loading between the supported serial configuration device and Arria II GX device family must follow the recommendations listed in Table 2-3.
Table 2-3. Maximum Trace Length and Loading for the AS Configuration Arria II GX Device Family AS Pins DCLK DATA[0] nCSO ASDO Maximum Board Trace Length from the Arria II GX Device Family to the Serial Configuration Devices (Inches) 10 10 10 10 Maximum Board Load (pF) 15 30 30 30
The affected section is the "Active Serial Configuration (Serial Configuration Devices)" in the Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices chapter. 1 When this revision is included in the Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices chapter, the "Guidelines for Connecting Serial Configuration Device to Arria II GX Device Family on AS Interface" section will be positioned before the "Estimating Active Serial Configuration Time" section.
Arria II GX Device Handbook Volume 3
(c) March 2010
Altera Corporation
Chapter 2: Addendum to the Arria II GX Device Handbook Document Revision History
2-3
Document Revision History
Table 2-4 lists the revision history for this chapter.
Table 2-4. Document Revision History Date March 2010 February 2010 Document Version
1.1 1.0
Changes Made Added "Guidelines for Connecting Serial Configuration Device to Arria II GX Device Family on AS Interface" Initial release.
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Altera Corporation
Arria II GX Device Handbook Volume 3
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Chapter 2: Addendum to the Arria II GX Device Handbook Document Revision History
Arria II GX Device Handbook Volume 3
(c) March 2010
Altera Corporation
Additional Information
About this Handbook
This handbook provides comprehensive information about the Altera Arria II GX family of devices.
How to Contact Altera
For the most up-to-date information about Altera products, see the following table.
Contact (Note 1) Technical support Technical training Product literature Non-technical support (General) (Software Licensing)
Note:
(1) You can also contact your local Altera sales office or sales representative.
Contact Method Website Website Email Website Email Email
Address www.altera.com/support www.altera.com/training custrain@altera.com www.altera.com/literature nacomp@altera.com authorization@altera.com
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue Bold Type with Initial Capital Letters bold type Meaning Indicates command names and dialog box titles. For example, Save As dialog box. Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file. Indicates document titles. For example, AN 519: Stratix IV Design Guidelines. Indicates variables. For example, n + 1. Variable names are enclosed in angle brackets (< >). For example, and .pof file. Initial Capital Letters "Subheading Title" Indicates keyboard keys and menu names. For example, Delete key and the Options menu. Quotation marks indicate references to sections within a document and titles of Quartus II Help topics. For example, "Typographic Conventions."
Italic Type with Initial Capital Letters Italic type
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Arria II GX Device Handbook Volume 3
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Additional Information
Visual Cue
Courier type
Meaning Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi, and input. Active-low signals are denoted by suffix n. For example, resetn. Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf. Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).
1., 2., 3., and a., b., c., and so on.
Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets indicate a list of items when the sequence of the items is not important. The hand points to information that requires special attention. A caution calls attention to a condition or possible situation that can damage or destroy the product or your work. A warning calls attention to a condition or possible situation that can cause you injury. The angled arrow instructs you to press Enter. The feet direct you to more information about a particular topic.
1 c w r f
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