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MC74HC112A Dual J-K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The MC74HC112A is identical in pinout to the LS112. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. Each flip-flop is negative-edge clocked and has active-low asynchronous Set and Reset inputs. The HC112A is identical in function to the HC76, but has a different pinout.
Features http://onsemi.com MARKING DIAGRAMS
16 16 1 PDIP-16 N SUFFIX CASE 648 1 16 16 1 SOIC-16 D SUFFIX CASE 751B 1 16 16 1 TSSOP-16 DT SUFFIX CASE 948F 1 16 16 1 SOEIAJ-16 F SUFFIX CASE 966 1 74HC112A ALYWG HC 112A ALYWG G HC112AG AWLYWW MC74HC112AN AWLYYWWG
* * * * * * * * *
Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Similar in Function to the LS112 Except When Set and Reset are Low Simultaneously Chip Complexity: 100 FETs or 25 Equivalent Gates Pb-Free Packages are Available*
A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2009
December, 2009 - Rev. 7
1
Publication Order Number: MC74HC112/D
MC74HC112A
CLOCK 1 K1 J1 SET 1 Q1 Q1 Q2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RESET 1 RESET 2 CLOCK 2 J1 K2 J2 SET 2 Q2 SET 2 K2 CLOCK 2 10 12 13 11 14 PIN 16 = VCC PIN 8 = GND 7 Q2 9 Q2 RESET 1 15 SET 1 K1 CLOCK 1 4 2 1 3 6 Q1 5 Q1
Figure 1. Pin Assignment FUNCTION TABLE
Inputs Set L H L H H H H H H H Reset Clock H L L H H H H H H H X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q Q
J2 RESET 2
L H
H L L H L* L* No Change L H H L Toggle No Change No Change No Change
Figure 2. Logic Diagram
*Both outputs will remain low as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
ORDERING INFORMATION
Device MC74HC112ANG MC74HC112ADG MC74HC112ADR2G MC74HC112ADTR2G MC74HC112AFELG Package PDIP-16 (Pb-Free) SOIC-16 (Pb-Free) SOIC-16 (Pb-Free) TSSOP-16* SOEIAJ-16 (Pb-Free) Shipping 500 Units / Rail 48 Units / Rail 2500 Units / Reel 2500 Units / Reel 2000 Units / Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC112A
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MAXIMUM RATINGS*
Symbol VCC Vin Iin Vout Iout PD Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP) *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC TA Vin, Vout tr, tf Parameter
Min 2.0 0
Max 6.0 VCC
Unit V V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
- 55 0 0 0
+ 125 1000 500 400
_C ns
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit v 85_C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9
Symbol VIH
Parameter
Test Conditions
VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
- 55 to 25_C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9
v 125_C 1.5 3.15 4.2 0.3 0.9 1.2 1.9 4.4 5.9
Unit V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL
VIL
Maximum Low-Level Input Voltage
V
VOH
Minimum High-Level Output Voltage
V
|Iout| v 4.0 mA |Iout| v 5.2 mA
3.98 5.48 0.1 0.1 0.1
3.84 5.34 0.1 0.1 0.1
3.70 5.20 0.1 0.1 0.1
VOL
Maximum Low-Level Output Voltage
V
|Iout| v 4.0 mA |Iout| v 5.2 mA
0.26 0.26 4
0.33 0.33 40
0.40 0.40 80
Iin
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Vin = VCC or GND Iout = 0 A
0.1
1.0
1.0
A A
ICC
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* Used to determine the no-load dynamic power consumption: P D = CPD VCC 2 f + ICC VCC .
III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL fmax Cin Power Dissipation Capacitance (Per Flip-Flop)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, Set to Q or Q (Figures 2 and 4) Maximum Propagation Delay, Reset to Q or Q (Figures 2 and 4) Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Symbol
CPD
tr, tf
trec
tsu
tw
tw
th
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Set or Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2)
Minimum Hold Time, Clock to J or K (Figure 3)
Minimum Setup Time, J or K to Clock (Figure 3)
Parameter
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MC74HC112A
4 VCC V VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 20 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- - 55 to 25_C - 55 to 25_C 1000 500 400 100 20 17 100 20 17 165 33 28 155 31 26 125 25 21 6.0 30 35 80 16 14 80 16 14 10 75 15 13 3 3 3 Typical @ 25C, VCC = 5.0 V Guaranteed Limit Guaranteed Limit v 85_C v 85_C 1000 500 400 100 20 17 100 20 17 125 25 21 125 25 21 205 41 35 195 39 33 155 31 26 4.8 24 28 10 95 19 16 35 3 3 3 v 125_C v 125_C 1000 500 400 120 24 20 120 24 20 150 30 26 150 30 26 250 50 43 235 47 40 190 38 32 110 22 19 4.0 20 24 10 3 3 3 MHz Unit Unit pF pF ns ns ns ns ns ns ns ns ns ns
MC74HC112A
SWITCHING WAVEFORMS
tf 90% 50% 10% tw 1/fmax tPLH tPHL Q or Q 90% 50% 10% Q OR Q tTLH tTHL CLOCK Q OR Q tr VCC GND SET OR RESET tw VCC 50% GND tPHL 50% tPLH 50% trec VCC 50% GND
CLOCK
Figure 1.
Figure 2.
VALID VCC J OR K 50% GND tsu CLOCK th VCC 50% GND DEVICE UNDER TEST OUTPUT TEST POINT
CL*
Figure 3.
*Includes all probe and jig capacitance
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
RESET 15, 14 5, 9 CL J 3, 11 CL
Q
K
2,12 CL CL
CL CL
CL
CL CL
CL
CL
CLOCK
1, 13 CL 6, 7 Q
SET
4, 10
CL
CL
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MC74HC112A
PACKAGE DIMENSIONS
PDIP-16 N SUFFIX CASE 648-08 ISSUE T
9
-A-
16
B
1 8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H K G D
16 PL
SEATING PLANE
J TA
M
M
0.25 (0.010)
M
-A-
SOIC-16 D SUFFIX CASE 751B-05 ISSUE K
9
16
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
DIM A B C D F G J K M P R
0.25 (0.010)
TB
S
A
S
SOLDERING FOOTPRINT
6.40
16X 8X
1.12 16
1
16X
0.58
1.27 PITCH 8 9
DIMENSIONS: MILLIMETERS
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MC74HC112A
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE B
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
16 9
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
J
N 0.15 (0.006) T U
S
0.25 (0.010) M
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT
7.06 1
0.36
16X
16X
1.26
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EE CC EE C CCC CCC
K1
SECTION N-N
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HC112A
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX CASE 966-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).
16
9
LE Q1 E HE M_ L DETAIL P
1
8
Z
D A VIEW P c
e
b 0.13 (0.005)
M
A1 0.10 (0.004)
DIM A A1 b c D E e HE L LE M Q1 Z
MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78
INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031
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