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DALSA IL-P1-XXXX-B Image Sensors
Features
n n n n n n
2 taps @ 25MHz data rate per tap Line rates to 87kHz Low voltage clocks (<5V) 10m (H) x 10m (V) pixels, 100% fill factor 512, 1024, or 2048 pixels Antiblooming and exposure control
TheIL-P1-XXXX-Bsetsnewlinescanstandards.Itsunprecedented design and fabrication sophistication has produced superiorperformance:highblueresponseandlowimagelag, two taps for high line rates, low-voltage clocksand DALSAs standard 100% fill factor.
n Highly sensitive, with responsivity reaching
12V/(J/cm2)
Description
Physical Characteristics Pixel dimensions Active area 10m x Active pixels per line Isolation pixels per line
IL-P1-XXXX-B
10m x 10m 5.1 / 10.2 / 20.5 512 / 1024 / 2048 14
Table 1. IL-P1-XXXX-B Pin Functional Description
Pin 1,13 2,18 3 4 5 6, 22 7, 23 8 9 10 11, 28 12, 27 14, 15, 17, 19 16 20, 21, 26 24 25, 29 30 31 32 Symbol VLOW VDD OS1 VSET CRLAST CR1S CR2S TCK PR VPR CR1B CR2B VHIGH NC VBB VSTOR VSS OS2 VOD RST Name Low Bias Voltage Amplifier Supply Voltage Output Signal 1 Output Node Set Gate Voltage Readout Clock, Last storage phase Readout Clock, Phase 1--Storage Phase Readout Clock, Phase 2Storage Phase Transfer Clock Pixel Reset Clock Pixel Reset Drain Voltage Readout Clock, Phase 1Barrier Phase Readout Clock, Phase 2--Barrier Phase High Bias Voltage No Connection Substrate Bias Voltage Storage Well Voltage Ground Reference Output Signal 2 Output Reset Drain Voltage Output Reset Clock
VLOW VDD OS1 VSET CRLAST CR1S CR2S TCK PR VPR CR1B CR2B VLOW VHIGH VHIGH NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
RST VOD OS2 VSS CR1B CR2B VBB VSS VSTOR CR2S CR1S VBB VBB VHIGH VDD VHIGH
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1 ISO 9001
IL-P1-XXXX-B Line Scan Sensors
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Figure 1. IL-P1-XXXX-B Block Diagram
CR1S, CR2S, CR1B, CR2B, CRLAST OS2
5I CCD Readout Shift Register 4I
Storage Well with Exposure Control and Reset Structure 32 S 4I N Photoelements (10m x 10m) Storage Well with Exposure Control and Reset Structure 4I 32 S
TCK VSTOR PR VPR
4I
VDD
5I CCD Readout Shift Register 32 S Light-shielded pixels 4 I Isolation pixels N = 512, 1024, or 2048
OS1
VBB RST VSET VOD VSS Relative position of package Pin 1
CR1S, CR2S, CR1B, CR2B, CRLAST
1
Table 2. # of Clock Drivers Required
Table 3. # of DC Biases Required
Clock Drivers Voltage Speed
Low High 1. High Low
Min. # Required PR off PR on
DC Biases Regulated?
Yes No 1. 2.
# Required PR off PR on
3 1
3 2
10 3
9 3
2.
Redundant clock drivers may be required to drive the CCD input capacitance. Refer to Figure 7 for details. PR = Pixel Reset (exposure control). 32
Refer to Figure 7 for details. PR = Pixel Reset (exposure control).
Shielded pixels per line
DALSA's IL-P1-XXXX-B series of linear CCD image sensors use proprietary technology to provide two outputs at 25 MHz each. The series employs buried channel CCD shift registers to maximize output speed and reduce noise. The sensor has a dynamic range of >3200:1 and provides output which is linear for the operating range of light input. The IL-P1-XXXX-B's exposure control allows integration times shorter than the readout time. Proprietary DALSA image sensor architecture provides low image lag pixels and high blue response. The IL-P1-XXXX-B sensor's superior performance makes it ideally suited for applications requiring maximum speed and high resolution, such as:
and two output amplifiers where the charge packets are converted to voltage pulses.
Detection
The IL-P1-XXXX-B series includes sensors with 512, 1024, or 2048 pixels with active imaging area lengths of 5, 10, and 20mm respectively. Photoelements are 10m square 2 for a photosensitive area of 100m and a 1:1 aspect ratio. Light incident on these photoelements is converted into charge packets whose size (i.e., number of electrons) is linearly dependent on the light intensity and the integration time. The charge is collected into a separate storage well (VSTOR) adjacent to each photoelement. This helps to minimize both image lag and nonuniformities associated with the use of pixel reset. With exposure control disabled, integration time is the period between successive pulses of the transfer (TCK) clock. Integration time can be further reduced with electronic exposure control using the pixel reset (PR) clock. The pixel reset clock resets not the photoelements themselves but the storage well adjacent to each photoelement. When PR is clocked, the integration time becomes the duration between the falling edge of the PR clock and the rising edge of the TCK clock.
n High performance document scanning n Inspection n Optical character recognition
Functional Description
The IL-P1-XXXX-B sensor is composed of three main functional groups: photodiodes in which the signal charge packets are generated, two CCD readout shift registers,
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When PR is clocked, the PR pulse must be damped to produce a smooth PR pulse. If PR switches too rapidly, the uniformity of the OSn signals will be affected by the PR clock feedthrough. Antiblooming is always present when biases fall within the specified operating conditions. By adjusting VSTOR however, the user has the added flexibility of selecting the antiblooming level (the signal level beyond which additional signal charges are drained away). A higher VSTOR bias results in a higher antiblooming level.
IL-P1-XXXX-B Line Scan Sensors
should preferably have a slower rise and fall time than CR1 and CR2. Additional details on driving the sensor are provided on Figure 7.
Output
Transfer
The TCK clock controls the transfer of electrons from the storage well into two discrete readout registers for alternating odd/even pixel readout. Transfer is from the storage wells into the CR1 phases of the readout registers. The readout registers are then used to serially shift the charge packets to the two high-speed low-noise output amplifiers. The two readout registers are pseudo-2-phase buriedchannel CCD shift registers. The CR1x and CR2x phases are complements of each other. Each of these two phases has a storage (CRxS) and a barrier (CRxB) gate. The storage and barrier gates of each phase are clocked in phase (i.e., CR1S is clocked in phase with CR1B, and CR2S is clocked in phase with CR2B). The only difference between the storage and barrier phase clocks is the bias levels applied to these clocks. AC-coupling and then DCshifting the CRxS phases will produce the CRxB phases. The final storage electrode of each readout register is connected separately to CRLAST. CRLAST should be clocked in phase with CR1. All CR clocks operate with 50% duty cycle. Unlike CR1 and CR2, the CRLAST pin is connected to only two CCD gates, one for each of the two CCD shift registers on each side. Consequently, the CRLAST capacitance is much smaller than the CR1 or CR2 capacitance. To prevent CRLAST from switching much faster than CR1 and CR2, we recommend that a 100 resistor be connected in series with CRLAST. The CRLAST clock
The signal charge packets from the readout shift registers are transferred serially from the last readout gate (CRLAST), over the set gate (VSET), to a floating sense node diffusion. The set gate isolates the sense node diffusion from the last readout gate and the rest of the readout shift register. As signal charge accumulates on the floating node diffusion, the potential of this diffusion decreases. The floating node diffusion is connected to the input of a 2.5-stage low-noise amplifier, producing an output signal voltage on the amplifier output (OSn). The floating diffusion is cleared of signal charge by the reset gate (RST) in preparation for the next signal charge packet. The voltage level of the floating diffusion after each reset is determined by the output reset drain voltage (VOD). AC coupling the output is recommended to eliminate the DC offset. Each of the output signals (OSn) requires an off-chip load drawing approximately 8mA of load current. If the sensor is running at greater than 35MHz data rate, or if the load capacitance (CLOAD) is greater than 10pF, larger load current (up to the 18mA limit) may be required. As the load current increases, the amplifier bandwidth increases. The amplifier can also drive larger capacitive loads when the load current is larger. We recommend however that just enough bandwidth be used since larger bandwidth also results in increased noise. If an off-chip current load is not available, each of the amplifier outputs (OSn) can be connected to a 1.2k load resistor. The use of a passive (resistive) load reduces the amplifier gain, resulting in lower responsivity and saturation output signal. The variations in charge conversion efficiency among the various outputs of the sensor, along with component variations in the drive electronics, result in output gain mismatch. To match outputs, we recommend that the camera electronics incorporate a gain correction of up to 15%.
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3 ISO 9001
IL-P1-XXXX-B Line Scan Sensors
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Table 4. IL-P1-XXXX-B Absolute Maximum Ratings
Parameter
Storage Temp Operating Temp Voltage on CR1x, CR2x, CRLAST, RST, VSET, VSTOR, TCK, PR with respect to VBB Voltage on OSn, VDD, VOD, VSS, VPR, VHIGH, VLOW with respect to VBB Voltage on OSn with respect to VSS Amplifier Load Current (ILOAD)
WARNING:
Unit
C C V V V mA per output
Min.
-20 -20 -10 0 VDD-8
Max.
80 60 18 18 VDD+1 20
Exceeding these values will void product warranty and may damage the device.
CAUTION! These devices are sensitive to damage from electrostatic discharge (ESD). The leads should be shorted together during storage or handling to prevent damage to the device.
Table 5. IL-P1-XXXX-B Input/Output Characteristics
Input Characteristics: Capacitance to VBB from CR1S, CR2S from CRLAST from RST from PR from TCK Output Characteristics: Output Impedance (ROUT) DC Output Offset (VOS)
4 5 1 2
Unit
512 pF pF pF pF pF pF mA V 90 100 12 10 40 70
Typical
1024 130 140 12 10 60 110 2048 220 240 12 10 110 200
from CR1B, CR2B
180 with ILOAD = 8mA 36mA with ILOAD = 8mA 10V with ILOAD = 8mA
Amplifier Supply Current (IDD)
6
Notes:
1. 2. 3. 4. 5. 6. Using 1V pk-pk 1MHz signal with +5V DC offset. The two CR1S pins (pins 6 and 22) are internally connected, as are the two CR2S pins (pins 7 and 23). The two CR1B pins (pins 11 and 28) are not internally connected, nor are the two CR2B pins (pins 12 and 27). Capacitance values indicated refer to the total capacitance of the two CRxB pins. In general, ROUT () ~ 520 * (ILOAD) , ILOAD in mA. In general, IDD (mA) = 2 * (10 + ILOAD), ILOAD in mA. 2 In general, VOFFSET (V) = 0.003 * (ILOAD) - 0.22 * (ILOAD) + 11.5, ILOAD in mA.
-0.5
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IL-P1-XXXX-B Line Scan Sensors
Table 6. IL-P1-XXXX-B DC Operating Conditions
Symbol
ILOAD VDD VOD VSET VSTOR VPR VBB VLOW VHIGH VSS
4 3 2
Description
Load current to each output (OSn) Amplifier supply voltage Output reset drain voltage Output node set gate voltage Storage well voltage Pixel reset drain voltage Substrate bias Low bias voltage High bias voltage Ground Reference
Unit
mA V V V V V V V V V
Min.
7.5 14.0 11.0 CRLAST offset +0.5 -1 13 -3 VBB 13
Rec.
8.0
Max.
18.0 15.0 VDD - 2 CRLAST offset +1.0 0.2 15 -1 0 15
14.0 11.3 0 0 14 -2 0 14 0
Notes:
1. Selecting a bias that deviates significantly from the recommended value can cause the recommended value of another bias to fall outside the Min. and Max. bias range. If this occurs, ignore the recommended value and ensure that each of the biases falls within its own Min. and Max. range. ILOAD needs to be > 10mA only if RST > 35MHz or CLOAD > 10pF. VSTOR may be adjusted to affect the antiblooming level. VSAT decreases by 418mV for every 1.0V reduction in VSTOR. If your implementation uses separate digital and analog grounds, connect VLOW to the digital ground.
2. 3. 4.
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IL-P1-XXXX-B Line Scan Sensors
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Table 7. IL-P1-XXXX-B AC Operating Conditions
Symbol
CRx CRxS CRxB CRLAST RST TCK PR RST DATA LINE
Description
All CR Clocks Readout Register Clocks (storage phase) Readout Register Clocks (barrier phase) Readout Register Clocks (last storage phase) Reset Clock Transfer Clock Pixel Reset Clock Data rate per output Effective data rate Line rate 0512 1024 2048 swing* offset* offset offset offset swing offset swing offset swing
Unit V V V V V V V V V V MHz MHz kHz
Min. 4.5 0 -(CRx swing)+1.5 CRxB offset+1.5 VOD-RST swing-6.8 4.8 VBB VSTOR+5.0 0.5 VSTOR+4.5
Rec. 5.0 0 -3.0 -0.8 -0.5 5.5 0 8 1.2 8 25 50 87.3 46.1 23.7
Max. 6.5 0.5 -(CRx swing)+2.5 CRxB offset+2.5 0 6.5 0 10 1.5 10 40 80 137.5 73.1 37.8
Notes:
1.
Selecting a bias that deviates significantly from the recommended value can cause the recommended value of another bias to fall outside the Min. and Max. bias range. If this occurs, ignore the recommended value and ensure that each of the biases falls within its own Min. and Max. range.
* Offset
Swing
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IL-P1-XXXX-B Line Scan Sensors
Table 8. IL-P1-XXXX-B Performance Specifications
Specification
Unit
Min.
700
Typ.
900 0.28 700 12.0 3200:1 5.0 23 75 180 0.5 2.0 2.2 3.5 2.5 3.8
Max.
1100 0.31 13.5 3900:1 5.3 28
Saturation Output Voltage (VSAT) mV rms Noise mV Wavelength of Peak Responsivity nm Peak Responsivity V/(J/cm2) Dynamic Range Charge Conversion Efficiency (CCE) V/e2 Noise Equivalent Exposure (NEE) pJ/cm Saturation Equivalent Exposure (SEE) nJ/cm2 Full Well Capacity ke 1,2 PR exposure control disabled mV Fixed Pattern Noise (FPN) PR exposure control enabled mV 3,4 Photoresponse Non-Uniformity (PRNU) PR exposure control disabled 8 pixel local neighborhood Global PR exposure control enabled 8 pixel local neighborhood Global Charge Transfer Efficiency (CTE) (readout register) First Field Lag 5 Dark Signal, Integration time = 84s
11.0 2250:1 4.7 21 52 132
1.0 5.0 6.0 8.5 6.5 8.8
0.99999 mV mV
0.999999 11.5 0.15
0.5
Notes:
1. 2. 3. 4. 5. Maximum peak-to-peak variation of all outputs. Due to its general purpose design, DALSA's camera and sensor evaluation hardware provides an output that cannot be used to directly measure low FPN. The peak-to-peak variation is measured at ~50% SEE. With output gain mismatch correction. Lag is measured at VSAT with LINE = 10kHz.
n n n n n n
Test Conditions:
Operating temperature = 35C. RST = data rate per output = 25MHz. ILOAD = 8mA. CLOAD = 10pF. Tungsten halogen light source, black body color temperature 3200K, filtered with 750nm IR cutoff filter. See Sensor Measurement Definitions (doc# 03-36-00149) for specification definitions.
Life Support Applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. DALSA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify DALSA for any damages resulting from such improper use or sale.
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IL-P1-XXXX-B Line Scan Sensors
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Figure 2. Performance Measurements
14
Responsivity [V/(J/cm )]
400W/cm2 100W/cm2 100
Signal Output (%) Saturation Output
12 10 8 6 4 2 0 400 500 600 700 800 900 1000 Wavelength (nm) 80 60 40 20 0 40W/cm
2
2
Responsivity
0.2 0.4 0.6 0.8 1.0 Integration Time (ms) Output vs. Integration Time (@700nm)
Table 9. IL-P1-XXXX-B Timing Parameters
Symbol Description
tCR t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Period of CRx clocks Integration time (PR disabled) Integration time (PR enabled) TCK to first valid pixel Overclock pixels CRxB falling edge to CRxS falling edge CR1B falling edge to CRLAST falling edge TCK high overlap with CR1S high TCK falling edge to CR1S falling edge CRLAST rising to RST rising edge RST falling edge to CRLAST falling edge RST pulse width (FWHM)
1
Unit
Min.
Rec.
Max.
pixels pixels ns ns ns ns ns ns ns ns ns
23 0 0 0 200 2 0 0 5 2 t12 0.5tCR - t11 0 5 5 t12 + 1 23 0 0 300
23
0.25tCR 0.25tCR
0.5tCR - t11 0.5tCR-t11 0.25tCR 0.25tCR 0.25tCR
CR1x and CR2x rise and fall time CRLAST rise and fall time Full Width Half Maximum
Notes:
1.
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IL-P1-XXXX-B Line Scan Sensors
Figure 3. IL-P1-XXXX-B Overall Timing
CR1x CR2x CRLAST TCK RST t2 PR OSn Line 1 t3 Active Pixels t4 t3 Line 2 Line 3 t1
Figure 4. IL-P1-XXXX-B Detailed Readout Register Timing
t5 CR1S CR1B CR2S CR2B CRLAST TCK RST OSn Overclock Overclock Pixel Pixel Isolation Pixel Isolation Pixel t6 t7 t9 t11 t13 t13 t10 t5 t8 tCR t12 t12
Figure 5. IL-P1-XXXX-B Gate Structure Diagram
VPR PR Pixel VSTOR VSS VDD OS n+
TCK
n+ CR1B CR1S CR2B CR2S CR1B CR1S CR2B CR2S CR1B CRLAST VSET RST
n+ VOD
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IL-P1-XXXX-B Line Scan Sensors
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Figure 6. IL-P1-XXXX-B Readout Register Timing
OC
I14
I10
S32
S17
I9
I8
Pixel N-1
Pixel N-3
Pixel 3
Pixel 1
I6
I5
S16
S1
I5
I1
I1
I5
S1
S16
I5
I6
Pixel 2 OS2 I Isolation Pixel. S Light-Shielded Pixel. OC Overclock Pixel. Sample video OC OC
CRLAST
CR1x
CR2x
TCK
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RST
OS1
OC
OC
Pixel 4
Pixel N-2
Pixel N
I8
I9
S17
S32
I10
I14
OC
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High-speed Low-voltage Clock Drivers 100nF CRLAST 100 CR1S CR1B, 10k 10k CR2B CR2S RST TCK PR (with exposure control) PR (without exposure control) VPR VLOW VHIGH VOD VDD6 VSS VBB VSET VSTOR7 OSx Buffer ILOAD BIAS 10k 511 1k TCK PR (PINS 7,23)3,4 (PIN 32) (PIN 8) (PIN 9) (PINS 12,27)4 100nF CRxBBIAS 100nF (PIN 5)5 (PINS 6,22)3,4 (PINS 11, 28)3,4 CRLAST BIAS CR11 10k
Low-speed High-voltage Clock Drivers Regulated DC Bias IL-P1 Non-Critical DC Bias Possible Interface Circuitry
CR22=CR1 RST
VPR VLOW VHIGH VOD VDD VSS VBB VSET VSTOR OSx
(PIN 10) (PINS 1,13) (PINS 14,15,17,19) (PIN 31) (PINS 2,18) (PINS 25,29) (PINS 20,21,26) (PIN 4) (PIN 24) (PINS 3,30)
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Figure 7. IL-P1-XXXX-B Sensor Operation Connections
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IL-P1-XXXX-B Line Scan Sensors
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IL-P1-XXXX-B Line Scan Sensors
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Notes to Figure 7.
1. 2. 3. 4. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total capacitances of CRLAST, CR1S, and CR1B (see Table 5) exceed CMAX, more than one CR1 driver is required. Clock drivers are designed to drive only up to a maximum capacitance (CMAX) at a given clock frequency. If the total capacitances of CR2S and CR2B (see Table 5) exceed CMAX, more than one CR2 driver is required. Both pins should be connected to clock drivers, though not necessarily to the same clock driver. If more than one clock driver is used, it is acceptable to drive each pin from separate drivers. Although the sensors are sufficiently robust that the rise and fall times of CRxS and CRxB do not need to be very closely matched, performance is more optimal if attempts are made to match the CRxS and CRxB rise and fall times. If more than one CRx clock driver is used, time constants are more closely matched if the sensor is driven using either one of the following configurations: Drive the CRxS pins with n CRx drivers. Tie the CRxB pins together. Drive the CRxB pins with a separate set of n CRx drivers. Drive the CRxS pins with 2n CRx drivers. Drive each CRxB pin separately with separate sets of n CRx drivers.
a. b. c.
Connect a 10 resistor in series with CRxS. Drive the CRxS pins with n CRx clock drivers. Connect a 20 resistor in series with each CRxB pin. Drive each CRxB pin with separate sets of n CRx drivers. Note that the CRxS pins are internally connected together, while the CRxB pins are not. 5. CRLAST should not have a fall time that is much faster than the fall time of CR1B. Unlike CR1B however, the CRLAST pin is connected to only two CCD gates, one for each of the CCD shift registers. Consequently, the CRLAST capacitance is much smaller than the CR2B capacitance. This is not an issue if the CRLAST clock is tapped from CR1. However, if CRLAST is being driven from a separate driver, we recommend that a 150 resistor be connected in series with CRLAST. 6. Need to source IDD = 2 * (10 + ILOAD) mA. 7. May have an optional antiblooming level adjustment.
ISO 9001 DALSA maintains a registered quality system meeting the ISO 9001 standard.
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IL-P1-XXXX-B Line Scan Sensors
Figure 8. IL-P1-XXXX-B Package Dimensions
31.80.3
0512
15.90.3 TO CL OF OPTICAL AREA No. 32 No. 17 0.40.1
1.10.3 DIE TO WINDOW SURFACE
12.50.1
OF OPTICAL AREA
6.30.3 TO CL
No. 1
PIXEL 1
2.80.3
5.00.3
NOTES: 1. DIMENSIONS ARE IN MM 2. MAXIMUM DIE ROTATION IS 0.6
0.50.1
1.80.1 26.70.1 (P=1.8 x 15)
2.50.3
31.80.3
1024
15.90.3 TO CL OF OPTICAL AREA No. 32 No. 17 0.40.1
1.10.3 DIE TO WINDOW SURFACE
12.50.1
+0.05 0.3 -0.03
No. 16
OF OPTICAL AREA
6.30.3 TO CL
No. 1
PIXEL 1
2.80.3
5.00.3
NOTES: 1. DIMENSIONS ARE IN MM 2. MAXIMUM DIE ROTATION IS 0.6
0.50.1
1.80.1 26.70.1 (P=1.8 x 15)
2.50.3
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+0.05 0.3 -0.03
No. 16
12.70.3
12.70.3
13 ISO 9001
IL-P1-XXXX-B Line Scan Sensors 2048
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31.80.3 15.90.3 TO CL OF OPTICAL AREA No. 32 No. 17 0.40.1
1.10.3 DIE TO WINDOW SURFACE
12.50.1
OF OPTICAL AREA
6.30.3 TO CL
No. 1
PIXEL 1
2.80.3
5.00.3
NOTES: 1. DIMENSIONS ARE IN MM 2. MAXIMUM DIE ROTATION IS 0.6
0.50.1
1.80.1 26.70.1 (P=1.8 x 15)
2.50.3
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+0.05 0.3 -0.03
No. 16
12.70.3
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