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DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Rev. 02 -- 13 August 2008 Product data sheet
1. General description
The DAC1003D160 is optimized to reduce architecture complexity and overall system cost. The Digital-to-Analog Converter (DAC) leads dynamic performance in multi-carrier support because of its direct IF conversion capabilities. With an internal sampling rate up to 160 MHz, the DAC1003D160 is an extremely competitive solution for broadband wireless systems transmitters, as well as a wide range of applications.
2. Features
I I I I I I I I I I Dual 10-bit resolution Spurious Free Dynamic Range (SFDR) = 80 dBc at 2.5 MHz Input data rate up to 80 MHz 2 x interpolation filter Output data rate up to 160 Mhz Single 3.3 V power supply Low noise capacitor free integrated Phase-Locked Loop (PLL) Low power dissipation HTQFP80 package Ambient temperature from -40 C to +85 C
3. Applications
I I I I I I Broadband wireless systems Digital radio links Cellular base stations Instrumentation Cable modems Cable Modem Termination System (CMTS)/Data Over Cable Service Interface Specification (DOCSIS)
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
4. Ordering information
Table 1. Ordering information Package Name DAC1003D160HW HTQFP80 Description plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad Version SOT841-1 Type number
5. Block diagram
DAC1003D160
VCCA
U/I
60
IVIRES
I9 to I0
11 to 16, 19 to 22
10
LATCH
10
FIR
10
DAC
73 72
IOUT IOUTN
(CLK x 2) CLK CLKN 5 6 CLOCK DRIVER PLL (CLK x 2) INTERNAL BAND GAP 58 57 DAC 69 68 GAPOUT GAPD QOUT QOUTN
(CLK x 2) Q9 to Q0 31 to 34, 37 to 42
10
LATCH
10
FIR
10
i.c. VCCD
2, 8 10, 51
(1) (2) (3) (4)
U/I VCCA
59
QVIRES
VCCA
014aaa532
AGND DGND
DEC
(1) Pins 1, 3, 61, 65, 76 and 80. (2) Pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79. (3) Pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56. (4) Pins 18, 26, 36, 43, 63 and 78.
Fig 1. Block diagram
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
2 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
6. Pinning information
6.1 Pinning
68 QOUTN 72 IOUTN 69 QOUT 80 VCCA 79 AGND 77 AGND 76 VCCA 75 AGND 74 AGND 71 AGND 70 AGND 67 AGND 66 AGND 65 VCCA 64 AGND 62 AGND
73 IOUT
78 DEC
VCCA i.c. VCCA AGND CLK CLKN AGND i.c. DGND
1 2 3 4 5 6 7 8 9
63 DEC
61 VCCA 60 IVIRES 59 QVIRES 58 GAPOUT 57 GAPD 56 DGND 55 DGND 54 DGND 53 DGND 52 DGND 51 VCCD 50 DGND 49 DGND 48 n.c. 47 n.c. 46 n.c. 45 n.c. 44 DGND 43 DEC 42 Q0 41 Q1 Q2 40
014aaa533
(c) NXP B.V. 2008. All rights reserved.
VCCD 10 I9 11 I8 12 I7 13 I6 14 I5 15 I4 16 DGND 17 DEC 18 I3 19 I2 20 I1 21 I0 22 n.c. 23 n.c. 24 DGND 25 DEC 26 n.c. 27 DGND
DAC1003D160
n.c. 28
DGND 29
DGND 30
Q9 31
Q8 32
Q7 33
Q6 34
DGND 35
DEC 36
Q5 37
Q4 38
Fig 2. Pin configuration
6.2 Pin description
Table 2. Symbol VCCA i.c. VCCA AGND CLK CLKN AGND i.c. DGND
DAC1003D160_2
Pin description Pin 1 2 3 4 5 6 7 8 9 Type[1] S I/O S G I I G O G Description analog supply voltage internally connected; leave open analog supply voltage analog ground clock input complementary clock input analog ground internally connected; leave open digital ground
Product data sheet
Rev. 02 -- 13 August 2008
Q3 39
3 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Pin description ...continued Pin 10 11 12 13 14 15 16 17 18 19 20 21 22 23 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Type[1] S I I I I I I G O I I I I I I G O I I G G I I I I G O I I I I I I O G I I I I G G Description digital supply voltage I data input bit 9 (Most Significant Bit (MSB)) I data input bit 8 I data input bit 7 I data input bit 6 I data input bit 5 I data input bit 4 digital ground decoupling node I data input bit 3 I data input bit 2 I data input bit 1 I data input bit 0 (Least Significant Bit (LSB)) not connected not connected digital ground decoupling node not connected not connected digital ground digital ground Q data input bit 9 (MSB) Q data input bit 8 Q data input bit 7 Q data input bit 6 digital ground decoupling node Q data input bit 5 Q data input bit 4 Q data input bit 3 Q data input bit 2 Q data input bit 1 Q data input bit 0 (LSB) decoupling node digital ground not connected not connected not connected not connected digital ground digital ground
(c) NXP B.V. 2008. All rights reserved.
Table 2. Symbol VCCD I9 I8 I7 I6 I5 I4 DGND DEC I3 I2 I1 I0 n.c. n.c. DGND DEC n.c. n.c. DGND DGND Q9 Q8 Q7 Q6 DGND DEC Q5 Q4 Q3 Q2 Q1 Q0 DEC DGND n.c. n.c. n.c. n.c. DGND DGND
DAC1003D160_2
Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Pin description ...continued Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Type[1] S G G G G G I I/O I I S G O G S G G O O G G O O G G S G O G S Description digital supply voltage digital ground digital ground digital ground digital ground digital ground internal band gap power disable input band gap output voltage Q DAC biasing resistor I DAC biasing resistor analog supply voltage analog ground decoupling node analog ground analog supply voltage analog ground analog ground complementary Q DAC output current Q DAC output current analog ground analog ground complementary I DAC output current I DAC output current analog ground analog ground analog supply voltage analog ground decoupling node analog ground analog supply voltage
Table 2. Symbol VCCD DGND DGND DGND DGND DGND GAPD GAPOUT QVIRES IVIRES VCCA AGND DEC AGND VCCA AGND AGND QOUTN QOUT AGND AGND IOUTN IOUT AGND AGND VCCA AGND DEC AGND VCCA
[1]
Type description: S: Supply; G: Ground; I: Input; O: Output.
DAC1003D160_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 13 August 2008
5 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
7. Functional description
The DAC1003D160 is a segmented architecture composed of a 7-bit thermometer sub-DAC and the remaining 3-bit in a binary weighted sub-DAC. The device produces two complementary current outputs on both channels, respectively pins IOUT/IOUTN and QOUT/QOUTN which need to be connected via a load resistor to the ground. Figure 3 shows the equivalent analog output circuit of one DAC, which consists of a parallel combination of PMOS current sources and associated switches for each segment. The cascade source configuration enables the increase of the output impedance of the source and the improvement of the dynamic performance of the DAC by introducing less distortion. Figure 4 shows the internal reference configuration. In this case the bias current is given by the output of the internal regulator connected to the inverting input of the internal operational amplifiers, while external resistors RI and RQ are connected respectively to pins IVIRES and QVIRES. Thus the output current of the two DACs is typically fixed to 20 mA with an appropriate choice of these resistors. This configuration is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. The relation between full-scale output current IO(fs) and the RI (RQ) is: 2048 x V GAPOUT R I = ----------------------------------------- 82 x I O ( FS ) The output current can also be adjusted by imposing an external reference voltage to the inverting input pin GAPOUT and disabling the internal band gap with pin GAPD set to HIGH. At a voltage lower than 1.2 V the current can be set at values lower than 20 mA. The input references at pins IVIRES and QVIRES may also be driven by separate reference voltages to adjust independently the two DAC currents.
DAC1003D160
GAPD AGND GAPOUT INTERNAL BAND GAP
DAC1003D160
IOUT/QOUT RL IOUTN/QOUTN RL
RI
IVIRES
I DAC current sources array
RQ
QVIRES
Q DAC current sources array
AGND
AGND
014aaa537 014aaa538
Fig 3. Equivalent analog output circuit
DAC1003D160_2
Fig 4. Internal reference configuration
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Product data sheet
Rev. 02 -- 13 August 2008
6 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
8. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCD VCCA VCC Parameter digital supply voltage analog supply voltage supply voltage difference between the analog and digital supply voltages pins Qn and In referenced to DGND pins IVIRES, QVIRES, GAPD, CLK and CLKN referenced to AGND VO output voltage pins IOUT, IOUTN, QOUT and QOUTN referenced to DAGND Conditions
[1] [1]
Min -0.3 -0.3 -150
Max +3.9 +3.9 +150
Unit V V mV
VI
input voltage
-0.3
VCCD + 0.3 V
-0.3
VCCA + 0.3 V
-0.3
VCCA + 0.3 V
Tstg Tamb Tj
[1]
storage temperature ambient temperature junction temperature
All supplies are connected together.
-55 -40 -
+150 +85 125
C C C
9. Thermal characteristics
Table 4. Symbol Rth(j-a) Rth(c-a) Thermal characteristics Parameter thermal resistance from junction to ambient thermal resistance from case to ambient Conditions in free air in free air Typ 27.1 11.8 Unit K/W K/W
10. Characteristics
Table 5. Characteristics VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = -40 C to +85 C; typical values measured at VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol Supplies VCCD VCCA ICCD
DAC1003D160_2
Parameter digital supply voltage analog supply voltage digital supply current
Conditions
Min 3.0 3.0 -
Typ 3.3 3.3 55
Max 3.6 3.6 65
Unit V V mA
7 of 19
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 13 August 2008
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Table 5. Characteristics ...continued VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = -40 C to +85 C; typical values measured at VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol ICCA Ptot Parameter analog supply current total power dissipation fclk = 80 MHz; fIOUT = fQOUT = 5 MHz Conditions Min Typ 73 422 Max 85 540 Unit mA mW
Clock inputs (CLK and CLKN) VI(cm) Vi(dif)(p-p) common-mode input voltage peak-to-peak differential input voltage full-scale output current output resistance output capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current voltage on pin GAPOUT current on pin GAPOUT external voltage VIL = 0.3 VCCD VIH = 0.7 VCCD differential outputs
[1] [1]
-
1.65 1.0
-
V V
Analog outputs (IOUT, IOUTN, QOUT and QOUTN) IO(fs) Ro Co VIL VIH IIL IIH VGAPOUT IGAPOUT 4 DGND 150 3 5 5 1.31 1 133 20 mA k pF
Digital inputs (I0 to I9, Q0 to Q9 and GAPD) 0.3 VCCD V VCCD V A A V A ppm/C 0.7 VCCD -
Reference voltage output (GAPOUT)
VGAPOUT voltage variation on pin GAPOUT Clock timing inputs (CLK and CLKN) fclk tw(clk)H tw(clk)L th(i) tsu(i) ts fdata ripple(pb) Bp stpb td(grp) INL DNL
DAC1003D160_2
clock frequency HIGH clock pulse width LOW clock pulse width input hold time input set-up time settling time data rate pass-band ripple power bandwidth stop-band attenuation group delay time integral non-linearity differential non-linearity fdata/fclk; 0.005 dB attenuation fdata/fclk; 3 dB attenuation fdata/fclk = 0.6 dB to 1 dB to 0.5 LSB
[1]
5 5 1.1 -1.5 16 0.405 0.479 69 11 Tclk 0.2 0.1
80 3.4 +0.7 80 -
MHz ns ns ns ns ns MHz
Input timing (I0 to I9 and Q0 to Q9); see Figure 5
Output timing (IOUT, IOUTN, QOUT, QOUTN) Digital filter specification (FIR); order N = 42 see Figure 6 and 7 and Table 7
dB ns LSB LSB
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Analog signal processing
Product data sheet
Rev. 02 -- 13 August 2008
8 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
Table 5. Characteristics ...continued VCCD = VCCA = 3.0 V to 3.6 V; AGND and DGND connected together; Tamb = -40 C to +85 C; typical values measured at VCCD = VCCA = 3.3 V, IO(fs) = 20 mA and Tamb = 25 C; dynamic parameters measured using output schematic given in Figure 10; unless otherwise specified. Symbol In(o) Eoffset EG GIQ SFDR Parameter output noise current offset error gain error IQ gain mismatch spurious free dynamic range relative to full-scale relative to full-scale between I and Q, relative to full-scale fclk = 80 MHz; B = Nyquist fo = 2.5 MHz at 0 dBFS fo = 5 MHz at 0 dBFS fo = 13 MHz at 0 dBFS 2H 3H IMD2 IMD3 THD second harmonic level third harmonic level second-order intermodulation distortion fo = 5 MHz fo = 13 MHz fo = 5 MHz fo = 13 MHz fclk = 80 MHZ; fo 1 = 10 MHz; fo 2 = 12 MHz; B = Nyquist 80 72 64 73 65 88 86 65 84 dBc dBc dBc dBc dBc dBc dBc dBc dBc Conditions Min -5.4 Typ 120 -0.3 0.2 Max +5.4 Unit pA/Hz % % %
third-order intermodulation fclk = 80 MHz; fo 1 = 10 MHz; fo 2 = 12 MHz distortion total harmonic distortion fo = 2.5 MHz fo = 5 MHz
fclk = 80 MHz; B = Nyquist; Tamb = 25 C 68 70 75 71 -155 -155 -153 80 80 78 60 61 dBc dBc dBm/Hz dBm/Hz dBm/Hz dBc dBc dBc dBc dBc
NSD
noise spectral density
fclk = 80 MHz fo = 2.5 MHz fo = 5 MHz fo = 19 MHz
S/N
signal-to-noise ratio
fclk = 80 Msample/s; B = Nyquist fo = 2.5 MHz fo = 5 MHz fo = 19 MHz
ACPR
adjacent channel power ratio
baseband; 5 MHz channel spacing; B = 3.84 MHz fo = 2.5 MHz fo = 20 MHz
[1]
Guaranteed by design.
Table 6. LOW HIGH
Band gap Band gap input/output (GAPOUT) output (VGAPOUT = 1.2 V) input Internal band gap enable disable
Band gap disable (GAPD)
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
tsu(i) I0 to I9, Q0 to Q9
CLKN CLK th(i)
50 %
IOUT/IOUTN, QOUT/QOUTN
014aaa534
Fig 5. Input timing diagram
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
20 output (dB) -20
014aaa535
0.6 normalized output
014aaa536
0.4 -60 0.2 -100 0
-140
-180 0 0.2 0.4 0.6 0.8 normalized frequency fo/fclk 1.0
-0.2 0 10 20 30 t (sample) 40
Fig 6. FIR filter frequency response Table 7. H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22)
Fig 7. FIR filter impulse response
Interpolation FIR filter coefficient Coefficient H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) Value 10 0 -31 0 69 0 -138 0 248 0 -419 0 678 0 -1083 0 1776 0 -3282 0 10364 16384
Coefficient
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
11. Application information
AGND
DAC1003D160
1 k 100 nF
CLK
DAC1003D160
Rs
CLK VCCA
100 nF
1 k
VCCA AGND
1 k
Vth
1 k
CLKN
100 nF 100 nF
1 k
CLKN
1 k
AGND
014aaa539
AGND
014aaa540
Fig 8. Single-ended clock schematic
Fig 9. Differential clock schematic
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
50 (RLOAD)
50 (RLOAD)
1:1 AGND AGND
50 50 C
1:1 AGND AGND
50 50 C
AGND AGND AGND AGND 3.3 V
C C
AGND AGND AGND AGND AGND 3.3 V
C C
3.3 V
C
3.3 V
C
QOUTN
IOUTN
QOUT
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VCCA
VCCA
VCCA
3.3 V
C
VCCA i.c. VCCA
C
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 60 59 58 57 56 55 54 53 52 51
VCCA
IOUT
DEC
DEC
IVIRES QVIRES GAPOUT GAPD DGND DGND DGND DGND DGND VCCD DGND DGND n.c. n.c. n.c. n.c. DGND DEC Q0 Q1
1.5 k 1.5 k
3.3 V AGND
AGND CLK CLKN
C
AGND
AGND
AGND i.c.
DGND
C
DGND VCCD I9 I8 I7 I6 I5 I4
DGND 3.3 V
C
3.3 V
DAC1003D160
50 49 48 47 46 45 44 43 42
DGND
DGND
C
DGND DEC I3 I2
C
DGND
41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I1 I0 n.c. n.c. DEC n.c. n.c. DGND DGND Q9 Q8 Q7 Q6 DGND DEC Q5 Q4 Q3 DGND Q2
C
C
DGND
DGND
DGND
014aaa541
All resistors are 1 % precision resistors. C = 100 nF.
Fig 10. Application diagram
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
13 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
11.1 Alternative parts
The following alternative parts are also available:
Table 8. Alternative parts Description Dual 14 bits DAC, with 2 x interpolating Dual 12 bits DAC, with 2 x interpolating
[1]
Type number DAC1403D160 DAC1203D160
[1] Pin to pin compatible
Sampling frequency 160 MHz 160 MHz
[1]
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
12. Package outline
HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad SOT841-1
c y exposed die pad X
Dh 60 61 41 40 ZE
A
e Eh w bp
M
E
HE
A A2
(A 3) A1 detail X L Lp
pin 1 index 80 1 w D HD
M
21 20 ZD B v
M
v
M
A
e
bp
B
0 DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 12.1 11.9 Dh 6.05 5.95 E (1) 12.1 11.9 Eh 6.05 5.95
5 scale
10 mm
e 0.5
HD
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.1
ZD(1) ZE(1) 1.45 1.05 1.45 1.05
7 0
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT841-1 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 04-01-15
Fig 11. Package outline SOT841-1 (HTQFP80)
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
13. Abbreviations
Table 9. Acronym FIR IF LSB MSB PLL PMOS Abbreviations Description Finite Impulse Response Intermediate Frequency Least Significant Bit Most Significant Bit Phase-Locked Loop Positive-Metal Oxide Semiconductor
14. Glossary
14.1 Static parameters
DNL -- Differential Non-Linearity. The difference between the ideal and the measured output value between successive DAC codes. INL -- Integral Non-Linearity. The deviation of the transfer function from a best-fit straight line (linear regression computation).
14.2 Dynamic parameters
IMD2 -- Second-order intermodulation distortion. From a dual-tone digital input sine wave (these two frequencies are close together), the intermodulation distortion product IMD2 is the ratio of the RMS value of either tone and the RMS value of the worst 2nd-order intermodulation product. IMD3 -- Third-order intermodulation distortion. From a dual-tone digital input sine wave (these two frequencies are close together), the intermodulation distortion product IMD3 is the ratio of the RMS value of either tone and the RMS value of the worst 3rd-order intermodulation product. SFDR -- Spurious Free Dynamic Range. The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain. S/N -- Signal-to-Noise ratio. The ratio of the RMS value of the reconstructed output sine wave to the RMS value of the noise excluding the harmonics and the DC component. THD -- Total Harmonic Distortion. The ratio of the RMS value of the harmonics of the output frequency to the RMS value of the output sine wave. Usually, the calculation of THD is done on the first 5 harmonics.
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
15. Revision history
Table 10. Revision history Release date 20080813 Data sheet status Product data sheet Change notice Supersedes DAC1003D160_1 Document ID DAC1003D160_2 Modifications: DAC1003D160_1
* *
Added condition to ts in Table 5. Correction to Figure 10. Product data sheet -
20080612
DAC1003D160_2
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Product data sheet
Rev. 02 -- 13 August 2008
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NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
DAC1003D160_2
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 -- 13 August 2008
18 of 19
NXP Semiconductors
DAC1003D160
Dual 10 bits DAC, up to 160 MHz, 2 x interpolation
18. Contents
1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 14.1 14.2 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics. . . . . . . . . . . . . . . . . . . 7 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . 12 Alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Static parameters . . . . . . . . . . . . . . . . . . . . . . 16 Dynamic parameters. . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 August 2008 Document identifier: DAC1003D160_2

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