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VND670SP
Dual high-side switch with dual Power MOSFET gate driver (bridge configuration)
Features
Type VND670SP RDS(on) 30m(1) IOUT 15A(1) VCC 40V
10
1. Per each channel.
1

5V logic level compatible inputs Gate drive for two external power MOSFET Undervoltage and overvoltage shutdown Overvoltage clamp Thermal shutdown Cross-conduction protection Current limitation Very low standby power consumption PWM operation up to 10 KHz Protection against loss of ground and loss of VCC Reverse battery protection
PowerSO-10
Description
The VND670SP is a monolithic device made using STMicroelectronics VIPower technology M0-3, intended for driving motors in full bridge configuration. The device integrates two 30 mW Power MOSFET in high-side configuration, and provides gate drive for two external Power MOSFET used as low side switches. INA and INB allow to select clockwise or counter clockwise drive or brake; DIAGA/ENA, DIAGB/ENB allow to disable one half bridge and feedback diagnostic. Built-in thermal shutdown, combined with a current limiter, protects the chip in overtemperature and short circuit conditions. Short to battery protects the external connected low-side Power MOSFET.
Table 1.
Device summary Order codes Package Tube
PowerSO-10 VND670SP
Tape and reel
VND670SP13TR
December 2008
Rev 2
1/20
www.st.com 20
Contents
VND670SP
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 2.2 2.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 Normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Fault conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSO-10 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
VND670SP
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data (per island) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Truth table in fault conditions (detected on OUTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PowerSO-10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3/20
List of figures
VND670SP
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test conditions for high-side switching times measurement. . . . . . . . . . . . . . . . . . . . . . . . . 9 Test conditions for external Power MOSFET switching times measurement . . . . . . . . . . 10 Definition of the external Power MOSFET turn-on dead time tdel . . . . . . . . . . . . . . . . . . . 10 Typical application circuit for DC to 10 KHz PWM operation . . . . . . . . . . . . . . . . . . . . . . . 11 Typical application circuit for a 20 KHz PWM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Waveforms (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Waveforms (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PowerSO-10 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PowerSO-10 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PowerSO-10 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SO-28 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4/20
VND670SP
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC
Undervolt. INA
INTERNAL SUPPLY Short to battery OUTA
INB DIAGA/ENA LOGIC
Short to battery DIAGB/ENB
OUTB
GATEA PWM Overtemp. A Overtemp. B Current Limiter B Current Limiter A GND GATEB
Figure 2.
Configuration diagram (top view)
INPUT B DIAGB/ENB PWM DIAGA/ENA INPUT A
6 7 8 9 10 11 VCC
5 4 3 2 1
OUTPUT B GATE B GROUND GATE A OUTPUT A
Table 2.
Suggested connections for unused and not connected pins
Status X N.C. X X Output X Input X Through 10K resistor
Connection / pin Floating To ground
5/20
Electrical specifications
VND670SP
2
Electrical specifications
Figure 3. Current and voltage conventions
ICC IINA IINB IENA IENB INA INB DIAGA/ENA DIAGB/ENB PWM Ipw IGND VCC VCC OUTA OUTB GATEA GATEB GND VgsB IgsB VgsA IgsA VOUTB IOUTB VOUTA IOUTA
VINA VINB VENA VENB
Vpw
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3.
Symbol VCC Imax1 Imax2 IR IIN IEN Ipw Igs VESD Tj Tstg Supply voltage Maximum output current (continuous) Maximum output current (250ms pulse duration) Reverse DC output current Input current Enable pin current PWM pin current Output gate current Electrostatic discharge ( R = 1.5K; C = 100pF) Junction operating temperature Storage temperature
Absolute maximum ratings
Parameter Value -0.3..40 15 20 - 15 +/- 10 +/- 10 +/- 10 +/- 20 2000 - 40 to 150 - 55 to 150 Unit V A A A mA mA mA mA V C C
6/20
VND670SP
Electrical specifications
2.2
Thermal data
Table 4.
Symbol Rthj-case Rthj-amb
Thermal data (per island)
Parameter Thermal resistance junction-case Thermal resistance junction-ambient Max. value 1.4 50(1) Unit C/W C/W
1. When mounted using the recommended pad size on FR-4 board (see AN515 Application Note).
2.3
Electrical characteristics
Values specified in this section are for 9V < VCC < 18V; -40C < Tj < 150C, unless otherwise stated. Table 5.
Symbol VCC RON
Power
Parameter Operating supply voltage On-state resistance ILOAD = 12A ILOAD = 12A Tj = 25C On-state Off-state 5.0 Igs= - 1 mA 6.0 6.8 Test conditions Min. 5.5 Typ. Max. 36 50 30 15 40 8.5 8.0 Unit V m m mA A V V
26
Is Vgate Vgs,cl
Supply current Gate output voltage Gate output clamp voltage
Table 6.
Symbol tD(on) tD(off) tr tf (dVOUT/dt)on (dVOUT/dt)off tdong trg tdoffg tfg tdel
Switching (VCC = 13V, RLOAD = 1.1)
Parameter Turn-on delay time Turn-off delay time Output voltage rise time Output voltage fall time Turn-on voltage slope Turn-off voltage slope Vgsturn-on delay time Vgs rise time Vgsturn-off delay time Vgs fall time External MOSFET turn-on dead time C1=4.7nF Break to ground configuration (see Figure 5) (see Figure 6) Input rise time < 1s (see Figure 4) Test conditions Min. Typ. 50 45 50 40 160 230 0.5 2.6 1.0 2.2 600 Max. 150 135 150 120 500 1200 2 10 5.0 10 1800 Unit s s s s V/ ms V/ ms s s s s s
7/20
Electrical specifications Table 7.
Symbol VUSD VOV ILIM TTSD Vocl
VND670SP
Protection and diagnostic
Parameter Undervoltage shutdown Overvoltage shutdown Current limitation Thermal shutdown temperature Output turn-off clamp voltage External MOSFET saturation voltage detection threshold VIN = 3.25 V ILOAD = 12A, L = 6mH 36 30 150 VCC55 2.5 4.2 43 45 170 200 VCC41 5.5 Test conditions Min. Typ. Max. 5.5 Unit V V A C V
Vsat
V
Table 8.
Symbol Vpwl Ipwl Vpwh Ipwh Vpwhhyst Vpwcl Vpwtest Ipwtest
PWM
Parameter PWM low level voltage PWM pin current PWM high level voltage PWM pin current PWM hysteresis voltage PWM clamp voltage Test mode PWM pin voltage Test mode PWM pin current Vpwtest = -2.0 V Ipw = 1 mA Ipw = -1 mA Vpw = 3.25V 0.5 VCC+0.3 -5.0 -3.5 -2000 VCC+0.7 -3.5 -2.0 -500 VCC+1.0 -2.0 -0.5 Vpw = 1.5V 1 3.25 10 Test conditions Min. Typ. Max. 1.5 Unit V A V A V V V V A
Table 9.
Symbol VIL IINL VIH IINH VIHYST VICL
Logic inputs
Parameter Input low level voltage Input current Input high level voltage Input current Input hysteresis voltage Input clamp voltage IIN=1mA IIN=-1mA VIN = 3.25 V 0.5 6.0 -1.0 6.8 -0.7 8.0 -0.3 VIN = 1.5 V 1 3.25 10 Test conditions Min. Typ. Max. 1.5 Unit V A V A V V V
8/20
VND670SP Table 10.
Symbol
Electrical specifications Enable
Parameter Test conditions Normal operation (DIAGX/ENX pin acts as an input pin) VEN = 1.5 V Normal operation (DIAGX/ENX pin acts as an input pin) VEN = 3.25 V Normal operation (DIAGX/ENX pin acts as an input pin) IEN = 1mA IEN = -1mA Fault operation (DIAGX/ENX pin acts as an input pin) IEN = 1.6 mA 0.5 6.0 -1.0 6.8 -0.7 8.0 -0.3 1 3.25 10 Min. Typ. Max. Unit
VENL IENL VENH IENH VEHYST
Enable low level voltage Enable pin current Enable high level voltage Enable pin current Enable hysteresis voltage
1.5
V A V A V V V
VENCL
Enable clamp voltage
VDIAG
Enable output low level voltage
0.4
V
Figure 4.
Test conditions for high-side switching times measurement
VOUTA, B
80%
90%
(dVOUT/dt)on 10%
(dVOUT/dt)off
t
VINA, B
td(on) tr
td(off) tf
t
9/20
Electrical specifications Figure 5. Test conditions for external Power MOSFET switching times measurement
VND670SP
VgsA, B
80%
90%
10%
Vpw tdong trg tdoffg
20%
t
tfg
t
Figure 6.
Definition of the external Power MOSFET turn-on dead time tdel
INA
INB
OUTA
VgsA tdel
10/20
VND670SP
Application information
3
Application information
Figure 7. Typical application circuit for DC to 10 KHz PWM operation
+5V R1 Rprot
1K
+5V VCC R1 Rprot
1K
DIAGA/ENA
DIAGB/ENB
VND670SP
Rprot
1K
PWM
OUTA
GND Rgnd(*)
OUTB
Rprot
1K
Rprot INA GATEA INB
1K
UP M DOWN
GATEB
External Power Mos A
External Power Mos B
Note:
1 2
Reverse battery protection: series relay in VCC line: Rgnd=0 Ohms; series fuse in VCC line with antiparallel diode between ground and VCC: Rgnd=10 Ohms. Layout hints: the connection between GND pin of the VN670SP and the Power MOSFET SOURCE connections should be kept short enough to ensure that the dynamic difference between these two points never exceed 1V for the bridge to operate properly.
11/20
Application information Figure 8. Typical application circuit for a 20 KHz PWM operation
+5V R1 Rprot
1K
VND670SP
+5V VCC R1 Rprot
1K
DIAGA/ENA
DIAGB/ENB
VND670SP
Rprot
1K
INA
OUTA Rgnd(*)
OUTB
Rprot
1K
Rprot PWM GATEA
UP M
D1 D2
INB GATEB
1K
DOWN
27 External Power Mos A External Power Mos B 27
Note:
1
Reverse battery protection: series relay in VCC line: Rgnd = 0 Ohms; series fuse in VCC line with antiparallel diode between ground and VCC: Rgnd=10 Ohms.
3.1
Normal operating conditions
Table 11.
INA 1 1 0 0 X 1 0 X X
Truth table in normal operating conditions
INB 1 0 1 0 X X X 1 0 DIAGA/ENA 1 1 1 1 0 1 1 0 0 DIAGB/ENB 1 1 1 1 0 0 0 1 1 OUTA H H L L L H L L L OUTB H L H L L L L H L GATEA L L H H L L H L L GATEB L H L H L L L L H Comment Brake to VCC Clockwise Counter cw Brake to GND Stand by HSA only MOSA only HSB only MOSB only
Note:
1 2
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. PWM pin usage: In all cases, a "0" on the PWM pin will turn-off both GATEA and GATEB outputs. When PWM rises back to "1", GATEA or GATEB turn on again depending on the input pin state.
12/20
VND670SP
Application information
3.2
Fault conditions
In case of a fault conditions the DIAGX/ENX pin is considered as an output pin by the device. The fault conditions are:

overtemperature on one or both high-sides; short to battery condition on the output (saturation detection on the external connected Power MOSFET). OUTA is shorted to ground ---> overtemperature detection on high-side A. OUTA is shorted to VCC ---> external Power MOSFET saturation detection (driven by GATEA).
Possible origins of fault conditions may be:

When a fault condition is detected, the user can know which power element is in fault by monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty half bridge is latched off. To turn-on the respective output (GATEX or OUTX) again, the input signal must rise from low to high level. Table 12.
INA 1 1 0 0 X 1 0 X X INB 1 0 1 0 X X X 1 0
Truth table in fault conditions (detected on OUTA)
DIAGA/ENA 0 0 0 0 0 0 0 0 0 DIAGB/ENB 1 1 1 1 0 0 0 1 1 OUTA Open Open Open Open Open Open Open Open Open OUTB H Open H Open Open Open Open H Open GATEA L L L L L L L L L GATEB L L L L L L L L L
3.3
Test mode
The PWM pin allows to test the load connection between two half-bridges. In the test mode (Vpwm=-2V) the external Power Mos gate drivers are disabled. The INA or INB inputs allow to turn-on the high-side A or B, respectively, in order to connect one side of the load at VCC voltage. The check of the voltage on the other side of the load allow to verify the continuity of the load connection. In case of load disconnection the DIADX/ENX pin corresponding to the faulty output is pulled down.
13/20
Application information Table 13.
ISO T/R 7637/1 Test pulse 1 2 3a 3b 4 5 I - 25V(1) + 25V(1)
(1)
VND670SP Electrical transient requirements
Test level II - 50V(1) + 50V - 50V
(1)
III - 75V(1) + 75V
(1) (1)
IV - 100V(1) + 100V - 150V
(1)
Delays and impedance 2ms, 10 0.2ms, 10 0.1s, 50 0.1s, 50 100ms, 0.01 400ms, 2
- 25V
(1)
- 100V
(1)
+ 25V(1) 4V(1)
(1)
+ 50V(1) - 5V
(1) (2)
+ 75V(1) - 6V
(1) (2)
+ 100V(1) - 7V
(1) (2)
+ 26.5V
+ 46.5V
+ 66.5V
+ 86.5V
1. All functions of the device are performed as designed after exposure to disturbance. 2. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device.
Figure 9.
Waveforms (1)
OUTA shorted to VCC and undervoltage shutdown
INA INB OUTA OUTB GATEA GATEB DIAGB/ENB DIAGA/ENA normal operation
OUTA shorted to VCC
normal operation
undervoltage shutdown
Load disconnection test (INA=1, PWM=-2V)
INA INB PWM (test mode) OUTA OUTB GATEA GATEB DIAGA/ENA DIAGB/ENB load connected load disconnected load connected back
14/20
VND670SP Figure 10. Waveforms (2)
Application information
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB GATEA GATEB
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB GATEA GATEB
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA INB ILIM IOUTA TTSD
Tj
DIAGA/ENA DIAGB/ENB GATEA GATEB normal operation OUTA shorted to ground normal operation
15/20
Package and packing information
VND670SP
4
4.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark.
4.2
PowerSO-10 mechanical data
Figure 11. PowerSO-10 package dimensions
B
0.10 A B
10
H
E
E2
E
E4
1
S EATING P LANE e
0.25
B
DETAIL "A"
A
C D = D1 = = =
h
A F A1
S EATING PLANE A1
DETAIL "A"
L
16/20
VND670SP Table 14. PowerSO-10 mechanical data
Package and packing information
mm Dim. Min. A A(1) A1 B B(1) C C(1) D D1 E E2 E2(1) E4 E4(1) e F F(1) H H(1) h L L(1) (1)
1. Muar only POA P013P.
Typ.
Max. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30
3.35 3.4 0 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2
1.35 1.40 14.40 14.35
1.80 1.10 8 8
17/20
Package and packing information
VND670SP
4.3
PowerSO-10 packing information
Figure 12. PowerSO-10 suggested Figure 13. PowerSO-10 tube shipment pad layout (no suffix)
14.6 - 14.9 10.8 - 11 6.30
B C
CASABLANCA
MUAR
A
0.67 - 0.73 1 9.5 2 3 4 5 10 9 8 7 6 0.54 - 0.6
A B
C
All dimensions are in mm.
1.27
Base Q.ty Bulk Q.ty Casablanca Muar 50 50 1000 1000
Tube length ( 0.5) 532 532
A
B
10.4 16.4 4.9 17.2
C ( 0.1) 0.8 0.8
Figure 14. PowerSO-10 tape and reel shipment (suffix "TR")
Reel dimensions
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
Tape dimensions
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
18/20
VND670SP
Revision history
5
Revision history
Table 15.
Date 03-May-2006 11-Dec-2008
Document revision history
Revision 1 2 Initial release. Document reformatted and restructured. Added contents, list of tables and figures. Added ECOPACK(R) packages information. Changes
19/20
VND670SP
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Price & Availability of VND670SP13TR

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