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ISL95811
Single Digitally Controlled Potentiometer (XDCPTM)
Data Sheet October 6, 2008 FN6759.1
I2C Bus, 256 Taps, 5 Bytes General Purpose Memory, Low Noise, Low Power
The ISL95811 integrates a digitally controlled potentiometer (XDCP) and non-volatile memory on a monolithic CMOS integrated circuit. The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the I2C bus interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR), that can be directly written to and read by the user. The content of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP's IVR to the WR. The DCP can be used as three-terminal potentiometer or as two-terminal variable resistor in a wide variety of applications including control, parameter adjustments and signal processing.
Features
* 256 Resistor Taps - 0.4% Resolution * I2C Serial Interface * 5 General Purpose Non-Volatile Bytes * Non-volatile Storage of Wiper Position * Write Protection * Wiper Resistance: 70 Typical @ VCC = 3.3V * Standby Current 10A Max * Power Supply: 2.7V to 5.5V * 50k, 10k Total Resistance * High Reliability - Endurance: 1,000,000 Data Changes per Bit per Register - Register Data Retention: 50 Years @ T +55C * 8 Ld MSOP and 8 Ld TDFN Packaging * Pb-Free (RoHS compliant)
Pinouts
ISL95811 (8 LD MSOP) TOP VIEW
WP SCL SDA GND 1 2 3 4 8 7 6 5 VCC RH RL RW WP 1 SCL 2 SDA 3 GND 4
ISL95811 (8 LD TDFN) TOP VIEW
8 VCC 7 RH 6 RL 5 RW
Ordering Information
PART NUMBER (Note) ISL95811WFUZ ISL95811WFUZ-T* ISL95811WFUZ-TK* ISL95811WFRTZ ISL95811WFRTZ-TK* ISL95811UFUZ ISL95811UFUZ-T* ISL95811UFUZ-TK* ISL95811UFRTZ ISL95811UFRTZ-TK* PART MARKING 5811W 5811W 5811W 811W 811W 5811U 5811U 5811U 811U 811U RTOTAL (k) 10 10 10 10 10 50 50 50 50 50 TEMP. RANGE (C) -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 -40 to +125 PACKAGE (Pb-Free) 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld 3x3 TDFN 8 Ld 3x3 TDFN 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld 3x3 TDFN 8 Ld 3x3 TDFN PKG. DWG. # MDP0043 MDP0043 MDP0043 L8.3x3A L8.3x3A MDP0043 MDP0043 MDP0043 L8.3x3A L8.3x3A
*Please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Corporation. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL95811 Block Diagram
VCC
RH
SDA I2C AND CONTROL WP
WIPER REGISTER
SCL
RW NON-VOLATILE REGISTER RL
GND
Pin Descriptions
MSOP PIN NUMBER 1 2 3 4 5 6 7 8 TDFN PIN NUMBER 1 2 3 4 5 6 7 8 SYMBOL WP SCL SDA GND RW RL RH VCC EPAD* DESCRIPTION Hardware write protection. Active low. Prevents any "Write" operation of the I2C interface. I2C interface input clock Open Drain Serial Data I/O for the I2C interface Ground "Wiper" terminal of the DCP "Low" terminal of the DCP "High" terminal of the DCP Power supply Exposed Die Pad internally connected to GND
*NOTE: PCB thermal land for QFN/TDFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf.
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Absolute Maximum Ratings
Voltage at any Digital Interface Pin with respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Voltage at any DCP Pin with respect to GND . . . . . . . . . .0V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 8 Ld TDFN (Notes 1, 2). . . . . . . . . . . . 52 9 8 Ld MSOP (Note 1) . . . . . . . . . . . . . . 160 N/A Maximum Junction Temperature (Plastic Package). . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Latchup (Note 3) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40C to +125C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. Jedec Class II pulse conditions and failure criterion used. Level B exceptions is using a max positive pulse of 6.5V on the WP pin.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. PARAMETER TEST CONDITIONS RTOTAL = (VRH - VRL)/IDCP W option U option MIN (Note 18) TYP (Note 4) 10 50 -20 VCC = 3.3V @ +25C Wiper current = VCC/RTOTAL Wiper at the middle scale, 1kHz 1VRMS input to RH pin 70 -110 10/10/25 Voltage at pin from GND to VCC 0.1 1 +20 200 MAX (Note 18) UNIT k k % dBV pF A
RH to RL Resistance
RH to RL Resistance Tolerance RW RWnoise (Note 16) CH/CL/CW (Note 16) ILkgDCP Wiper Resistance Noise Level Potentiometer Capacitance Leakage on DCP Pins
VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 9) Integral Non-Linearity DCP register set between 1 hex and FFhex. Monotonic over all tap positions. W and U options DCP register set between 1 hex and FF hex. Monotonic over all tap positions W option U option FSerror (Note 7) Full-Scale Error W option U option TCV (Note 10, 16) fCUTOFF (Note 16) Ratiometric Temperature Coefficient 3dB Cut-Off Frequency DCP Register set to 80 hex Wiper at the middle scale W option U option W option U option -1 1 LSB (Note 5) LSB (Note 5) LSB (Note 5) LSB (Note 5) ppm/C kHz kHz
DNL (Note 8)
Differential Non-Linearity
-0.75 -0.5 0 0 -5 -2 1 0.5 -1 -0.5 4 1250 250
0.75 0.5 5 2 0 0
ZSerror (Note 6) Zero-Scale Error
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Analog Specifications
SYMBOL Over recommended operating conditions unless otherwise stated. (Continued) PARAMETER TEST CONDITIONS MIN (Note 18) TYP (Note 4) MAX (Note 18) UNIT
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 14) Integral Non-Linearity DCP register set between 1 hex and FF hex. Monotonic over all tap positions. W option U option W option U option -3 -1 -0.75 -0.5 0 0 1 0.5 45 3 1 0.75 0.5 5 2 MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) MI (Note 11) ppm/C
RDNL (Note 13) Differential Non-Linearity
DCP register set between 1 hex and FF hex. Monotonic over all tap positions
Roffset (Note 12) Offset
W option U option
TCR (Note 15, 16)
Resistance Temperature Coefficient
DCP register set between 20 hex and FF hex
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 ICC2 ISB PARAMETER VCC Supply Current (Volatile Write/Read) VCC Supply Current (Non-volatile Write) VCC Current (Standby) TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, Active, Read and Volatile Write States only) fSCL = 400kHz; SDA = Open; (for I2C, Active, Non-volatile Write State only) VCC = +5.5V, I2C Interface in Standby State VCC = +3.6V, I2C Interface in Standby State ILkgDig tDCP Vpor VCCRamp tD Leakage Current, at Pins SDA, SCL, Voltage at pin from GND to VCC and WP Pins DCP Wiper Response Time Power-On Recall Voltage VCC Ramp Rate Power-Up Delay VCC above VPOR, to DCP Initial Value Register recall completed, and I2C Interface in standby state SCL falling edge of last bit of DCP Data Byte to wiper change Minimum VCC at which memory recall occurs 1.8 0.2 3 -1 MIN TYP MAX (Note 18) (Note 4) (Note 18) UNITS 100 2 10 5 1 1 2.6 A mA A A A s V V/ms ms
EEPROM SPECIFICATIONS EEPROM Endurance EEPROM Retention SERIAL INTERFACE SPECIFICATIONS VIL VIH WP, SDA, and SCL Input Buffer LOW Voltage WP, SDA, and SCL Input Buffer HIGH Voltage -0.3 0.7*VCC 0.05*VCC 0 0.4 10 0.3*VCC VCC + 0.3 V V V V pF Temperature +55C 1,000,000 50 Cycles Years
Hysteresis (Note 16) SDA and SCL Input Buffer Hysteresis VOL Cpin (Note 16) SDA Output Buffer LOW Voltage, Sinking 4mA WP, SDA, and SCL Pin Capacitance
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Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL fSCL tIN tAA tBUF PARAMETER SCL Frequency Pulse Width Suppression Time at SDA and SCL Inputs SCL Falling Edge to SDA Output Data Valid Time the Bus Must be Free Before the Start of a New Transmission Clock LOW Time Clock HIGH Time START Condition Setup Time START Condition Hold Time Input Data Setup Time Any pulse narrower than the max spec is suppressed. SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. Measured at the 30% of VCC crossing. Measured at the 70% of VCC crossing. SCL rising edge to SDA falling edge. Both crossing 70% of VCC. From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window. From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC. 1300 TEST CONDITIONS MIN TYP MAX (Note 18) (Note 4) (Note 18) UNITS 400 50 900 kHz ns ns ns
tLOW tHIGH tSU:STA tHD:STA tSU:DAT
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT tSU:STO tHD:STO tHD:STO:NV tDH
Input Data Hold Time STOP Condition Setup Time
0 600 600 2 0
ns ns ns s ns
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge. Both or Volatile Only Write crossing 70% of VCC. STOP Condition Hold Time for Non- From SDA rising edge to SCL falling edge. Both Volatile Write crossing 70% of VCC. Output Data Hold Time From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window. From 30% to 70% of VCC From 70% to 30% of VCC Total on-chip and off-chip
tR (Note 16) tF (Note 16) Cb (Note 16) Rpu (Note 16)
SDA and SCL Rise Time SDA and SCL Fall Time Capacitive Loading of SDA or SCL
20 + 0.1 * Cb 20 + 0.1 * Cb 10 1
250 250 400
ns ns pF k
SDA and SCL Bus Pull-Up Resistor Maximum is determined by tR and tF. Off-Chip For Cb = 400pF, max is about 2k~2.5k. For Cb = 40pF, max is about 15k~20k Non-Volatile Write Cycle Time WP Setup Time WP Hold Time Before START condition After STOP condition
tWC (Note 17) tSU:WP tHD:WP NOTES:
12 600 600
20
ms ns ns
4. Typical values are for TA = +25C and 3.3V supply voltage. 5. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)255 - VCC]/LSB. 8. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.
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NOTES: (continued) 9. INL = [V(RW)i - (i * LSB - V(RW)0)]/LSB for i = 1 to 255. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 10. TC V = --------------------------------------------------------------------------------------------- x -------------------- for i = 16 to 240 decimal, T = -40C to +125C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 +165C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. MI = |R255 - R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. Roffset = R0/MI, when measuring between RW and RL. 12. Roffset = R255/MI, when measuring between RW and RH. 13. RDNL = (Ri - Ri-1)/MI, for i = 16 to 255. 14. RINL = [Ri - (MI * i) - R0]/MI, for i = 16 to 255. [ Max ( Ri ) - Min ( Ri ) ] 10 15. TC R = --------------------------------------------------------------- x -------------------- for i = 32 to 255, T = -40C to +125C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) + Min ( Ri ) ] 2 +165C the minimum value of the resistance over the temperature range. 16. Limits established by characterization and are not production tested. 17. tWC is the time from a valid STOP condition at the end of a Write sequence of a I2C serial interface Write operation, to the end of the self-timed internal non-volatile write cycle. The Acknowledge Polling method can be used to determine the end of the non-volatile write cycle. 18. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
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SDA vs SCL Timing
tF tHIGH tLOW tR tWC
SCL tSU:STA tHD:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tAA SDA (OUTPUT TIMING)
tDH
tBUF
WP Pin Timing
START SCL CLK 1 STOP tHD:STO tHD:STO:NV
SDA IN tSU:WP WP tHD:WP
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ISL95811 Typical Performance Curves
140 T = -40C WIPER RESISTANCE () 120 100 80 60 40 20 T = -40C 0 0 50 T = +25C T = +125C VCC = 5.5V 250 100 150 200 TAP POSITION (DECIMAL) 0.00 2.7 VCC = 2.7V STANDBY ICC (A) 1.20 T = +125C T = +25C T = +125C 1.60
0.80
0.40 T = +25C
T = -40C
3.2
3.7 4.2 4.7 SUPPLY VOLTAGE (V)
5.2
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC/RTOTAL] FOR 10k (W)
FIGURE 2. STANDBY ICC vs VCC
0.50 VCC = 2.7V 0.25 DNL (LSB) INL (LSB) T = +25C
0.50 VCC = 2.7V 0.25 T = +25C
0
0 VCC = 5.5V -0.25
-0.25 VCC = 5.5V -0.50 0 50 100 150 200 TAP POSITION (DECIMAL) 250
-0.50
0
50
100 150 200 TAP POSITION (DECIMAL)
250
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
0.50 VCC = 2.7V 0.25 RDNL (MI) RINL (MI) T = +25C
2.0 T = +25C VCC = 2.7V 1.5
1.0
0
0.5
-0.25 VCC = 5.5V -0.50 0
0 VCC = 5.5V 200 250 -0.5 0 50 100 150 200 TAP POSITION (DECIMAL) 250
50
100 150 TAP POSITION (DECIMAL)
FIGURE 5. RDNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 6. RINL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
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2.0 ZERO SCALE ERROR (LSB) FULL SCALE ERROR (LSB) VCC = 2.7V
(Continued)
0
1.6
-0.5
VCC = 5.5V
1.2
-1.0
0.8 VCC = 5.5V 0.4
-1.5 VCC = 2.7V -2.0 -40 0 40 80 TEMPERATURE (C) 120
0 -40
0
40 TEMPERATURE (C)
80
120
FIGURE 7. ZSerror vs TEMPERATURE
FIGURE 8. FSerror vs TEMPERATURE
0.2 VCC = 2.7V 0.1 DNL (LSB) INL (LSB) T = +25C
0.50 T = +25C VCC = 2.7V 0.25
0
0 VCC = 5.5V
-0.1
VCC = 5.5V
-0.25
-0.2 0
50
100 150 200 TAP POSITION (DECIMAL)
250
-0.50 0
50
100 150 200 TAP POSITION (DECIMAL)
250
FIGURE 9. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
FIGURE 10. INL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
0.2 VCC = 2.7V 0.1 RDNL (MI) RINL (MI) T = +25C
0.5 0.4 0.3 0.2 0.1 0 VCC = 5.5V -0.1 250 -0.2 0 50 VCC = 5.5V VCC = 2.7V T = +25C
0
-0.1
-0.2 0
50
100 150 200 TAP POSITION (DECIMAL)
100 150 200 TAP POSITION (DECIMAL)
250
FIGURE 11. RDNL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
FIGURE 12. RINL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
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ISL95811 Typical Performance Curves
250 T = -40C TO +125C 200 TCr (ppm/C) VCC = 2.7V TCv (ppm/C) 200 VCC = 2.7V 150
(Continued)
250 T = -40C TO +125C
150
100
100
VCC = 5.5V
50 VCC = 5.5V 0 15 65 115 165 TAP POSITION (DECIMAL) 215
50
0 15
65
115 165 TAP POSITION (DECIMAL)
215
FIGURE 13. TCr FOR RHEOSTAT MODE 10k (W) IN ppm
FIGURE 14. TCv FOR VOLTAGE DIVIDER MODE 10k (W) IN ppm
END-TO-END RTOTAL CHANGE (%)
0.8 VCC = 2.7V END-TO-END RTOTAL CHANGE (%)
1.0 VCC = 2.7V 0.5
0.6
0.4
0.0
0.2
0.0
VCC = 5.5V
-0.5
VCC = 5.5V
-0.2 40
0
40 80 TEMPERATURE (C)
120
-1.0 -40
0
40 80 TEMPERATURE (C)
120
FIGURE 15. END-TO-END RTOTAL % CHANGE vs TEMPERATURE, 10k (W)
FIGURE 16. END-TO-END RTOTAL % CHANGE vs TEMPERATURE, 50k (U)
Pin Description
Potentiometers Pins
RH AND RL The high (RH) and low (RL) terminals of the ISL95811 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 255 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW RW is the wiper terminal, and it is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register.
address and data from an I2C external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock. SDA requires an external pull-up resistor, since it is an open drain input/output. SERIAL CLOCK (SCL) This input is the serial clock of the I2C serial interface. SCL requires an external pull-up resistor. WRITE PROTECT (WP) When this pin is kept LOW, the data is written to the device will be ignored. This pin protectS the non-volatile memory from being overwritten.
Principles of Operation
The ISL95811 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and an I2C serial interface providing direct communication between a host and the potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for I2C interface. It receives device address, operation code, wiper
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either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR are recalled and loaded into the WR to set the wiper to the initial value.
TABLE 1. MEMORY MAP ADDRESS (hex) 8 7 6 5 4 3 2 1 0 General Purpose General Purpose General Purpose General Purpose General Purpose Device ID (read only) IVR NON-VOLATILE NA Reserved N/A N/A N/A N/A N/A N/A WR VOLATILE ACR
DCP Description
The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR register of a DCP contains all ones (WR[7:0] = FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the position closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL95811 is being powered up, the WR is reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reloaded with the value stored in a non-volatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the I2C serial interface, as described in the following sections.
The ISL95811 is pre-programed with 80h in the IVR. The non-volatile IVR and volatile WR registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR[7]) determines whether the access to wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # NAME
7 VOL 6 0 5 0
4 0
3 0
2 0
1 0
0 0
If VOL bit is 0, the non-volatile IVR register and General Purpose registers are accessible. If VOL bit is 1, only the volatile WR is accessible. Note: Value written to the IVR register is also written to the WR. The default value of this bit is 0. The Device ID register is read only and it contains chip revision information, as shown in Table 3.
TABLE 3. DEVICE ID REGISTER BIT # VALUE
7 1 6 0 5 0
4 0
3 0
2 0
1 0
0 0
Memory Description
The ISL95811 contains one non-volatile 8-bit Initial Value Register (IVR), five General Purpose non-volatile 8-bit registers and two volatile 8-bit registers: Wiper Register (WR) and Access Control Register (ACR). The Memory map of the ISL95811 is shown in Table 1. The non-volatile register (IVR) at address 0 contains the initial wiper position and the volatile register (WR) contains the current wiper position.
I2C Serial Interface
The ISL95811 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL95811 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
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ISL95811
Protocol Conventions
Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (see Figure 17). On power-up of the ISL95811, the SDA pin is in the input mode. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL95811 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (see Figure 17). A START condition is ignored during the power-up sequence and during internal non-volatile write cycles. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (see Figure 17). A STOP condition at the end of a read operation, or at the end of a write operation to volatile bytes only places the device in its standby mode. A STOP condition during a write operation to a non-volatile byte initiates an internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting 8 bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the 8 bits of data (see Figure 18). The ISL95811 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL95811 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation. A valid Identification Byte contains 0101000 as the seven MSBs. The LSB is the Read/Write bit. Its value is "1" for a Read operation and "0" for a Write operation (see Table 4).
TABLE 4. IDENTIFICATION BYTE FORMAT 0 (MSB) 1 0 1 0 0 0 R/W (LSB)
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 17. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9 HIGH IMPEDANCE
SDA OUTPUT FROM TRANSMITTER
SDA OUTPUT FROM RECEIVER
HIGH IMPEDANCE
START
ACK
FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER
11
FN6759.1 October 6, 2008
ISL95811
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL95811
01 01 0 000 A C K
0000 A C K A C K
FIGURE 19. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W = 0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W = 1
A C K
A C K
S T O P
SIGNAL AT SDA
01010000 A C K
0000 A C K
01010001 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 20. READ SEQUENCE
Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL95811 responds with an ACK. At this time, if the Data Byte is to be written only to volatile registers, then the device enters its standby state. If the Data Byte is to be written also to non-volatile memory, the ISL95811 begins its internal write cycle to non-volatile memory. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. When the internal non-volatile write cycle is completed, the ISL95811 enters its standby state (see Figure 19). The byte at address 08h determines if the Data Byte is to be written to volatile and/or non-volatile memory (see "Memory Description" on page 10).
received. If the Address Byte is 0 or 8, the Data Byte is transferred to the Wiper Register (WR) or to the Access Control Register respectively, at the falling edge of the SCL pulse that loads the last bit (LSB) of the Data Byte. If the Address Byte is 0, and the Access Control Register is all zeros (default), then the STOP condition initiates the internal write cycle to non-volatile memory.
Read Operation
A Read operation consists of a three byte instruction followed by one or more Data Bytes (see Figure 20). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL95811 responds with an ACK. The ISL95811 then transmits the Data Byte and the master then terminates the read operation (issuing a STOP condition) following the last bit of the Data Byte. The byte at address 08h determines if the Data Bytes being read are from volatile or non-volatile memory (see "Memory Description" on page 10).
Data Protection
The WP pin has to be at logic HIGH to perform any Write operation to the device. When the WP is active (LOW), the device ignores Data Bytes of a Write Operation and does not respond to the Data Bytes with an ACK; rather it goes into standby state waiting for a new START condition. A STOP condition also acts as a protection of non-volatile memory. A valid Identification Byte, Address Byte, and total number of SCL pulses act as a protection of both volatile and non-volatile registers. During a Write sequence, the Data Byte is loaded into an internal shift register as it is 12
FN6759.1 October 6, 2008
ISL95811 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
13
FN6759.1 October 6, 2008
ISL95811 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.15 C A A D 2X 0.15 C B
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 MIN 0.70 NOMINAL 0.75 0.02 0.20 REF 0.25 0.30 3.00 BSC 2.20 2.30 3.00 BSC 1.40 1.50 0.65 BSC 0.25 0.20 0.30 8 4 0.40 1.60 2.40 0.35 MAX 0.80 0.05 NOTES 5, 8 7, 8, 9 7, 8, 9 8 2 3 Rev. 3 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals.
E 6 INDEX AREA TOP VIEW B
A3 b D D2 E
// 0.10 C 0.08 C
E2 e k L N Nd
A C SEATING PLANE
SIDE VIEW
A3
D2 (DATUM B) 1 2 D2/2
7
8
6 INDEX AREA (DATUM A)
NX k E2 E2/2
3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance.
NX L N 8 N-1 e 5 (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" TERMINAL TIP FOR EVEN TERMINAL/SIDE e (A1) L1 10 L 0.10 M C A B NX b
8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-WEEC-2 except for the "L" min dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6759.1 October 6, 2008

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