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| TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Rev. 01 -- 17 March 2008 Product data sheet 1. General description The TDA9955HL is a triple 8-bit video converter interface. The TDA9955HL converts an RGB analog signal into a RGB or YUV (YCBCR) digital signal or converts a YUV (YPBPR) analog signal into a YUV (YCBCR) or RGB digital signal with a sampling rate up to 170 MHz. The TDA9955HL supports analog TV resolutions from 480i (720 x 480i at 60 Hz) to High-Definition TV (HDTV) (up to 1920 x 1080p at 60 Hz) and analog PC resolutions from VGA (640 x 480p at 60 Hz) to UXGA (1600 x 1200p at 60 Hz). The YUV digital output signal can be 4 : 4 : 4 or 4 : 2 : 2 ITU-R BT.656 standard or semi-planar format following the ITU-R BT.601 standard. All settings are controlled via the I2C-bus. 2. Features I I I I I I I I I I I I I I I I Triple 8-bit Analog-to-Digital Converter (ADC) Three independent analog video sources, up to 170 MHz selectable via the I2C-bus Analog composite sync slicer and recognition integrated Frame and field detection for interlaced video signal Video analog voltage input from 0.45 V to 0.9 V (p-p) to produce a full-scale ADC input of 1.0 V (p-p) Three clamps for programming a 8-bit clamping code from 0 to +191 in steps of 1 LSB for RGB and YUV signals Three video amplifiers controlled via I2C-bus to reach the full-scale resolution Amplifier bandwidth of 100 MHz Low gain variation with temperature I2C-bus controlled Phase-Locked Loop (PLL) to generate the ADCs, formatter and output clocks which can be locked into a line frequency from 15 kHz to 95 kHz Integrated PLL divider Programmable clock phase adjustment cells Matrix and offsets available for conversion of RGB or YUV signal coming from analog video sources into YUV or RGB Output format RGB 4 : 4 : 4, YUV 4 : 4 : 4, YUV 4 : 2 : 2 ITU-R BT.656 or YUV 4 : 2 : 2 semi-planar standard on output bus Integrated downsampling-by-two with selectable filters on CB and CR channels in the 4 : 2 : 2 mode IC controlled via the I2C-bus, 5 V tolerant and bit rate up to 400 kbit/s NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV I I I I TTL inputs 5 V tolerant LV-TTL outputs Power-down mode 1.8 V and 3.3 V power supplies 3. Applications I I I I I Set Top Box (STB) YUV or RGB high-speed video digitizer Projector, plasma and LCD TV Rear projection TV High-end TV 4. Ordering information Table 1. Ordering information Package Name TDA9955HL LQFP100 Description plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm Version SOT407-1 Type number 5. Block diagram REF VPA[7:0] RGB (or YPBPR) 1 RGB (or YPBPR) 2 CLAMP GAIN ADC 8 bits (x3) VIDEO OUTPUT FORMATTER VPB[7:0] VPC[7:0] VCLK SOG/Y 1 SLICERS SOG/Y 2 CLOCKS GENERATOR VHREF TIMING GENERATOR VREF, HREF, FREF VS, HS, CS VSYNC1/HCSYNC1 VSYNC2/HCSYNC2 ACTIVITY DETECTION AND SYNC SELECTION SYNC SEPARATOR TDA9955HL SYNC TIMING MEASUREMENT I2C SLAVE INTERFACE POWER MANAGEMENT SDA/SCL 001aag612 Fig 1. Block diagram TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 2 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 6. Functional diagram I2C B1 (or PB) B/U CHANNEL 4:2:2 DOWNSAMPLE FILTERS COLOR CONVERSION VIDEO PORT SELECTION 4:2:2 FORMATTER B2 (or PB) G1 (or Y) G/Y CHANNEL G2 (or Y) R1 (or PR) R2 (or PR) R/PR CHANNEL (GAIN) I2C + (CLAMP) I2C CLAMP (CLK PIX) (CLK FOR) VCLK VHREF TIMING GENERATOR + - - - FREF VPA[7:0] I2C I2C I2C VPB[7:0] VPC[7:0] VREF + HREF AVI CLOCK GENERATOR + SOG/Y 1 SOG/Y 2 SYNC SLICERS - HS TDA9955HL + HCSYNC1 HCSYNC2 VSYNC1 VSYNC2 I2C I2C I2C ACTIVITY DETECTION SYNC SELECTION - VS SDRS & + - CS + - DE MCLK SYNC TIME MEASUREMENT I2C POWER MANAGEMENT I2C 001aah352 Fig 2. Functional diagram TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 3 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 7. Pinning information 7.1 Pinning 100 76 75 1 TDA9955HL 25 26 50 51 001aag613 Fig 3. Pin configuration 7.2 Pin description Table 2. Symbol VPC1 VPC2 VPC3 VDDC(1V8) VSSC VDDO(3V3) VSSO VPC4 VPC5 VPC6 VPC7 VDDO(3V3) VSSO VCLK FREF/CS VREF/VS HREF/HS DE VAI_N VDDA(OSC)(3V3) VSSA(OSC) VSSA(BIAS) TDA9955HL_1 Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 Type[1] Description O O O P G P G O O O O P G O O O O O O P G P G video port C output bit 1 video port C output bit 2 video port C output bit 3 supply voltage for the digital core (1.8 V) ground for the digital core supply voltage for the video port output (3.3 V) ground for the video port output video port C output bit 4 video port C output bit 5 video port C output bit 6 video port C output bit 7 supply voltage for the video port output (3.3 V) ground for the video port output pixel clock output filed reference output or composite synchronization vertical reference output or vertical synchronization horizontal reference output or horizontal synchronization data enable signal output video activity indication output (active LOW) analog supply for the free running oscillator (3.3 V) analog ground for the free running oscillator bias analog supply voltage (3.3 V) bias analog ground (c) NXP B.V. 2008. All rights reserved. VDDA(BIAS)(3V3) 22 Product data sheet Rev. 01 -- 17 March 2008 4 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Pin description ...continued Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Type[1] Description I G G P I I I P G G P I I I P G G P I I I P G I I P G P G G G P P I I I I bias input PCB ground analog ground for the blue (or blue chrominance) channel analog supply voltage for blue (or blue chrominance) channel (3.3 V) blue channel input 2 blue channel reference input blue channel input 1 analog supply voltage for blue (or blue chrominance) channel ADC (1.8 V) analog ground for blue (or blue chrominance) channel ADC analog ground for green (or green luminance) channel analog supply voltage for green (or green luminance) channel (3.3 V) green channel input 2 green channel reference input green channel input 1 analog supply voltage for green (or green luminance) channel ADC (1.8 V) analog ground for green (or green luminance) channel ADC analog ground for red (or red chrominance) channel analog supply voltage for red (or red chrominance) channel (3.3 V) red channel input 2 red channel reference input red channel input 1 analog supply voltage for red (or red chrominance) channel ADC (1.8 V) analog ground for red (or red chrominance) channel ADC Sync-On-Green (SOG) input 2 sync-on-green input 1 analog supply voltage for SOG (3.3 V) analog ground for SOG analog supply voltage for SOG (3.3 V) analog ground for SOG analog ground for PLL analog ground for PLL analog supply voltage for PLL (3.3 V) analog supply voltage for PLL (1.8 V) reserved for test (connected to the digital ground of the core) reserved for test (connected to the digital ground of the core) horizontal (composite) SYNC input 1 horizontal (composite) SYNC input 2 (c) NXP B.V. 2008. All rights reserved. Table 2. Symbol BIAS VSSA VSSA(B) VDDA(B)(3V3) B2 REF_B B1 VDDA(B)(1V8) VSSA(B) VSSA(G) VDDA(G)(3V3) G2 REF_G G1 VDDA(G)(1V8) VSSA(G) VSSA(R) VDDA(R)(3V3) R2 REF_R R1 VDDA(R)(1V8) VSSA(R) SOG2 SOG1 VDDA(SOG)(3V3) VSSA(SOG) VDDA(SOG)(3V3) VSSA(SOG) VSSA(PLL) VSSA(PLL) VDDA(PLL)(3V3) VDDA(PLL)(1V8) TEST0 TEST1 HCSYNC1 HCSYNC2 TDA9955HL_1 Product data sheet Rev. 01 -- 17 March 2008 5 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Pin description ...continued Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Type[1] Description I I I I I I I P I I G P G P G O O O O P G O O O O P G O O O O P G O O O O P G O vertical SYNC input 1 vertical SYNC input 2 synchronization timing measurement clock clamp input (external mode) coast (PLL) input (external mode) external clock input (external mode) I2C-bus address select bit 0 digital supply for the input (3.3 V) I2C-bus clock I2C-bus data analog ground digital supply for core (1.8 V) digital ground of the core (1.8 V) supply voltage for the video port output (3.3 V) ground for video port output video port A output bit 0 video port A output bit 1 video port A output bit 2 video port A output bit 3 supply voltage for the video port output (3.3 V) ground for video port output video port A output bit 4 video port A output bit 5 video port A output bit 6 video port A output bit 7 supply voltage for the video port output (3.3 V) ground for video port output video port output bit 0 video port output bit 1 video port output bit 2 video port output bit 3 supply voltage for the video port output (3.3 V) ground for video port output video port output bit 4 video port output bit 5 video port output bit 6 video port output bit 7 supply voltage for the video port output (3.3 V) ground for video port output video port C output bit 0 Table 2. Symbol VSYNC1 VSYNC2 MCLK CLAMP COAST CKEXT A0 VDDI(3V3) SCL SDA VSSA VDDC(1V8) VSSC VDDO(3V3) VSSO VPA0 VPA1 VPA2 VPA3 VDDO(3V3) VSSO VPA4 VPA5 VPA6 VPA7 VDDO(3V3) VSSO VPB0 VPB1 VPB2 VPB3 VDDO(3V3) VSSO VPB4 VPB5 VPB6 VPB7 VDDO(3V3) VSSO VPC0 [1] TDA9955HL_1 P = power supply; G = ground; I = input and O = output. (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 6 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 8. Functional description This high-rate front end is designed to convert analog signals coming from an analog source (RGB or YUV) into parallel digital data used by media processor ICs such as the NXP Semiconductors Nexperia devices for HDTV or by other video signal ICs. The high-rate front end is able to output RGB 4 : 4 : 4, YUV 4 : 4 : 4, YUV 4 : 2 : 2 semi-planar and YUV 4 : 2 : 2 ITU-R BT.656 formats and accepts progressive and interlaced input formats. The high-rate front end also contains a RGB-to-YUV and YUV-to-RGB conversion matrix, downsampling filters and range control function. 8.1 Analog multiplexers The choice between the two analog video inputs is either automatic (activity detection) or controlled by the I2C-bus. An analog video input is defined by pins SOGx, Rx, Bx, Gx, HCSYNCx and VSYNCx (where x equals 1 or 2). 8.2 R/PR, B/PB and G/Y channels 8.2.1 Clamps Three independent parallel clamping circuits are used to clamp the video input signals on programmable black/blanking levels. The clamp level of each channel can be changed from 0 to 191 in steps of 1 LSB. The clamp signal comes from the VHREF timing generator or from the CLAMP pin. The clamping circuits can be inhibited during the vertical sync pulse and also during false black/blanking level in the end of active video signal in a frame/field. 8.2.2 ADCs Three ADCs convert analog signals into three series of 8-bit codes, with a maximum sampling frequency of 170 MHz. The ADCs input range is 1 V (p-p). During the gain calibration pulse period, the ADCs are used to calibrate the video amplifiers and during the clamp active period the ADCs are used to set the clamp level to the desired values. 8.2.3 Automatic Gain Control (AGC) Gain registers, one per channel, control directly the gain of each video amplifier. The programming of these registers is done by I2C-bus and their content is validated only on the next horizontal synchronization pulse. These contrast registers are programmable from 0 dB to 5 dB (gain registers on 11 bits). The gain calibration control signal comes from the VHREF timing generator. 8.3 Sync slicing Two sync slicers extract the composite sync from the green, luminance or CVBS signal through SOGx pins. This synchronization signal can be bi-level or tri-level. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 7 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 8.4 Activity detection The device detects the presence of signals on each sync input VSYNCx, HCSYNCx and SOGx after slicing to indicate which kind of synchronization is present (where x equals 1 or 2): * Digital separated syncs on VSYNCx and HCSYNCx * Analog composite sync on SOGx A change of activity is notified by a HIGH-to-LOW transition on the VAI_N output pin. 8.5 Sync detection and selection The management of the synchronization is done by using vertical sync, horizontal sync and analog composite sync on the green/luminance signal. The device scans if a signal is present on the VSYNCx pin. If a signal is detected on this pin, it means that there is a digital separated sync signal. If no signal is detected on the HCSYNCx pin, the device scans if a signal is present on the SOGx pin. If a signal is detected on this pin (and not on the HCSYNCx pin), it means that there is an analog composite sync signal and the signal is sent into the sync recognition function after slicing. If the analog composite sync signal is on the green or on the luminance of the video signal, the SOGx pin must be connected to this signal. 8.6 Sync Detection Recognition and Separation The Sync Detection Recognition and Separation (SDRS) allows to retrieve the horizontal and the vertical synchronizations from composite sync. This composite sync comes from the sync slicing function when the sync is on the green, luminance or CVBS signal or from the digital composite sync on the HCSYNCx pin. This function is able to eliminate any additional synchronization pulses which may be added in the vertical blanking. 8.7 Clock generator An internal PLL locked to the reference HSYNC signal from sync recognition provides three different clocks, one pixel-clock for R/PR, B/PB and G/Y channels sampling and for the VHREF timing generator, one formatter-clock at double frequency for the 4 : 2 : 2 formatter and one output-clock for the VCLK output pin. The COAST signal, coming from SDRS and/or VHREF timing generator or coming from the COAST input pin, allows to freeze the PLL phase frequency detector during the vertical blanking. A phase-locked flag indicates if the PLL is locked. 8.8 Sync multiplexers The sync multiplexer allow to select via the I2C-bus the origin of the synchronization pulses signals HS, VS, CS and DE. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 8 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV The origin of those pulses can be the VHREF timing generator or the SDRS block. 8.9 Color conversion The color conversion allows an RGB signal coming from the analog video interface to convert into YUV format or to convert a YUV signal coming from the analog video interface into an RGB format. The color matrix formula is: C 11 C 12 C 13 Oin 1 GY YG VR = C 21 C 22 C 23 x RV - Oin 2 UB C 31 C 32 C 33 Oin 3 BU Oout 1 + Oout 2 Oout 3 Activation of the matrix function and programming of all coefficients is made by I2C-bus. 8.10 4 : 2 : 2 downsample filters These filters downsample the U and V signals with a factor 2. A delay is added on the G/Y channel corresponding to the pipeline delay of the filters to put the Y channel in phase with the UV channel. Four filters are selectable by I2C-bus, from the simple cut to the ITU-R BT.656 compliant digital filter. 8.11 Range control The range control function truncates the range of data at specified ceiling and floor values to remove super-white and super-black pixels. 8.12 4 : 2 : 2 formatter The 4 : 2 : 2 formatter contains the YUV 4 : 2 : 2 semi-planar and the YUV 4 : 2 : 2 ITU-R BT.656 formatting functions. The choice between these functions is done using the I2C-bus. A delay is added on the G/Y channel corresponding to the pipeline delay of the YUV 4 : 2 : 2 semi-planar formatting function to put the Y channel in phase with the UV channel. In the case of the YUV 4 : 2 : 2, the data frequency corresponding to the Y signal is at pixel clock frequency and the data frequency corresponding to the U and V signals is at half the pixel clock frequency. For semi-planar, the output clock should be at the same frequency as the pixel clock and for ITU-R BT.656 at the same frequency as the formatter clock (double of the pixel-clock). The Start Active Video (SAV) and End Active Video (EAV) timing reference codes can be included in the data stream according the HREF, VREF and FREF signal positions from the VHREF timing generator. Specific codes programmed via the I2C-bus can replace the data stream during the blanking period to mask gain and clamp calibration. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 9 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 8.13 Video port selection Each channel (R or G or B in RGB 4 : 4 : 4 mode, Y or CB or CR in YUV 4 : 4 : 4 mode, Y or CBCR in 4 : 2 : 2 semi-planar mode, CBYCRY in 4 : 2 : 2 ITU-R BT.656 mode) can be affected to a specified video port VPA, VPB or VPC via the I2C-bus. 8.14 Output buffers The levels of the output buffers are LV-TTL compatible. The switch of the outputs between active and high-impedance is set by the I2C-bus. 8.15 VHREF timing generator The VHREF timing generator outputs all the timing signals used by the device: gain and clamp pulses for calibration, coast signal to manage the PLL, VREF, HREF and FREF signals for SAV/EAV and other, VS and HS signals to change width and position compared with the synchronization inputs. 8.16 I2C-bus serial interface The I2C-bus serial interface allows to program the internal registers of the device. The slave address of the device is selected by pin A0. The programmed values in the registers remain valid. 8.17 Power management Only the serial interface (and the I2C-bus registers) and the activity detection are powered up in all cases even in the case when the device is set to power-down with the PD-registers. 8.18 Sync timing measurement To assist the recognition of the input format, the vertical and horizontal periods are measured based on the externally provided MCLK frequency (13.5 MHz). The width of the horizontal pulse is also measured. 9. I2C-bus interface 9.1 I2C-bus protocol The TDA9955HL is a slave I2C-bus device and the SCL pin is only an input pin. The timing and protocol for I2C-bus are standard. Bit A0 of the I2C-bus device address is externally selected by the A0 pin. The main device I2C-bus address is given in Table 3. Table 3. A6 1 I2C-bus slave address R/W A4 0 A3 1 A2 1 A1 1 A0 A0 0/1 A5 0 Device address TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 10 of 52 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 9.2 Registers definitions The configuration of the registers is given in Table 4. Table 4. Register VERSION INPUT_SEL Reserved for test Reserved for test SDRS_CTRL1 Reserved for test Reserved for test Reserved for test I2C-bus registers; (R): reading register[1] Sub R/W Bit definition addr 7 (MSB) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h R W W W W W W W W W 0 x x x x x x x x x x ASD x MDIV[1:0] CLKOUT_PRST[2:0] CLKOUT_DIV[1:0] CLKOUT_TOG CLKOUT_SEL[2:0] 6 0 x x ASD_DIS x x x x x x x SOGD2 5 0 x x x SOGF x x x x x x x CLKFOR_PRST[1:0] CLKFOR_DIV[1:0] CLKPIX_DIV[1:0] CLKFOR_SEL[1:0] BRIGHT_GY[7:0] BRIGHT_BU[7:0] BRIGHT_RV[7:0] x x x x x x x x x x x 4 1 x x x DCSF x x x x x x x x DSSD2 NDIV[7:0] PHASE[4:0] CLKPIX_PRST[2:0] PR_DEL x x x 3 0 x x x x x x x x x x x x EDG 2 1 x x x x x x x x x x x SOGD1 x NDIV[11:8] x x x x x x x x x x x x 1 0 VINS[1:0] x x x x x x x x x x x DSSD1 x 0 (LSB) 0 Default value 0001 0100 0000 0100 0000 0000 0110 0000 0000 0000 0000 0010 0001 0100 0001 0000 0000 0000 0111 1111 0010 0101 0000 0000 0000 0000 0000 0000 0000 0000 1100 0011 0110 0000 PLL_LOCK 0000 0000 0001 0000 1101 0111 0100 0110 0001 0000 1000 0000 1000 0000 0000 0000 0000 0000 PH_CORR 0011 1011 Product data sheet Rev. 01 -- 17 March 2008 11 of 52 TDA9955HL_1 NXP Semiconductors Reserved for test Reserved for test Reserved for test Reserved for test Reserved for test SDRS_FLAGS PLL_CTRL PLL_MNDIV_MSB PLL_NDIV_LSB LOCK_FLAG DLL_PHASE PIXCLKGEN_PRST PIXCLKGEN_CTRL0 PIXCLKGEN_CTRL1 (c) NXP B.V. 2008. All rights reserved. 0Ah W 0Bh R 0Ch R 0Dh R 10h 11h 12h 13h 14h 15h 16h 17h W W W R W W W W Triple 8-bit analog-to-digital video converter for HDTV TDA9955HL BRIGHT_GY BRIGHT_BU BRIGHT_RV Reserved for test Reserved for test 1Ah W 1Bh W 1Ch W 1Dh W 1Eh W xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 4. Register COARSE_GAINRV FINE_GAINRV AGC_HIGHRV AGC_LOWRV COARSE_GAINBU FINE_GAINBU AGC_HIGHBU AGC_LOWBU AGC_CONTGY AGC_OFFSETGY AGC_HIGHGY AGC_LOWGY V_PER_MSB V_PER_ISB H_PER_MSB HS_WIDTH_MSB STM_LSB MAT_CTRL MAT_OI1_MSB MAT_OI1_LSB MAT_OI2_MSB MAT_OI2_LSB MAT_OI3_MSB MAT_OI3_LSB MAT_P11_MSB MAT_P11_LSB MAT_P12_MSB MAT_P12_LSB MAT_P13_MSB MAT_P13_LSB (c) NXP B.V. 2008. All rights reserved. I2C-bus registers; (R): reading register[1] ...continued Sub R/W Bit definition addr 7 (MSB) 20h 21h 22h 23h W W W W x x x FINE_GY[6:0] HIGH_GY[7:0] LOW_GY[6:0] V_PER[19:12] V_PER[11:4] H_PER[9:2] HS_WIDTH[9:2] V_PER[3:0] P11[7:0] P12[7:0] P13[7:0] P13[10:8] P12[10:8] H_PER[1:0] HS_WIDTH[1:0] MAT_SC[1:0] MAT_OI1[8:6] MAT_OI2[8:6] MAT_OI3[8:6] P11[10:8] FINE_BU[6:0] HIGH_BU[7:0] LOW_BU[6:0] COARSE_GY[3:0] 6 5 4 FINE_RV[6:0] HIGH_RV[7:0] LOW_RV[6:0] COARSE_BU[3:0] 3 2 1 0 (LSB) Default value 0000 0100 0101 1100 1111 0000 1001 0000 0000 0100 0101 1100 1111 0000 1001 0000 0000 0100 0101 1100 1110 1011 1001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0001 0000 0110 0000 0000 0110 0100 Product data sheet Rev. 01 -- 17 March 2008 12 of 52 TDA9955HL_1 NXP Semiconductors COARSE_RV[3:0] 2Ah W 2Bh W 2Ch W 2Dh W 34h 35h 36h 37h 40h 41h 42h 43h 44h 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h W W W W R R R R R W W W W W W W W W W Triple 8-bit analog-to-digital video converter for HDTV OFFSET_IN1[5:0] OFFSET_IN2[5:0] OFFSET_IN3[5:0] TDA9955HL 8Ah W 8Bh W 8Ch W xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 4. Register MAT_P21_MSB MAT_P21_LSB MAT_P22_MSB MAT_P22_LSB MAT_P23_MSB MAT_P23_LSB MAT_P31_MSB MAT_P31_LSB MAT_P32_MSB MAT_P32_LSB MAT_P33_MSB MAT_P33_LSB MAT_OO1_MSB MAT_OO1_LSB MAT_OO2_MSB MAT_OO2_LSB MAT_OO3_MSB MAT_OO3_LSB MAT_BYPASS Reserved for test PXCNT_PR_LSB PXCNT_MSB PXCNT_NPIX_LSB LCNT_PR_LSB LCNT_MSB LCNT_NLIN_LSB HREF_S_LSB HREF_MSB HREF_E_LSB HS_S_LSB (c) NXP B.V. 2008. All rights reserved. I2C-bus registers; (R): reading register[1] ...continued Sub R/W Bit definition addr 7 (MSB) 8Dh W 8Eh W 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h W W W W W W W W W W W x x x P33[7:0] x x x OFFSET_OUT1[5:0] OFFSET_OUT2[5:0] OFFSET_OUT3[5:0] P32[7:0] P31[7:0] P23[7:0] P31[10:8] P32[10:8] P33[10:8] OFFSET_OUT1[8:6] OFFSET_OUT2[8:6] OFFSET_OUT3[8:6] x MAT_BP x P22[7:0] P23[10:8] 6 5 4 P21[7:0] P22[10:8] 3 2 1 P21[10:8] 0 (LSB) Default value 0000 0110 1000 1001 0000 0001 1100 0000 0000 0111 1011 0111 0000 0110 1101 0111 0000 0111 0110 1001 0000 0001 1100 0000 0000 0000 0100 0000 0000 0010 0000 0000 0000 0010 0000 0000 0000 0001 0001 0000 0000 0011 PXCNT_NPIX[11:8] PXCNT_NPIX[7:0] LCNT_PR[7:0] LCNT_PR[11:8] PXCNT_NLIN[7:0] HREF_START[7:0] HREF_START[11:8] HREF_END[7:0] HS_START[7:0] HREF_END[11:8] LCNT_NLIN[11:8] 0000 0011 0110 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Product data sheet Rev. 01 -- 17 March 2008 13 of 52 TDA9955HL_1 NXP Semiconductors 9Ah W 9Bh W 9Ch W 9Dh W 9Eh W 9Fh W A0h W A1h W A2h W A3h W A4h W A5h W A6h W A7h W A8h W A9h W AAh W Triple 8-bit analog-to-digital video converter for HDTV PXCNT_PR[7:0] PXCNT_PR[11:8] TDA9955HL xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 4. Register HS_MSB HS_E_LSB VREF_F1_S_MSB VREF_F1_S_LSB VREF_F1_WIDTH VREF_F2_S_MSB VREF_F2_S_LSB VREF_F2_WIDTH VS_F1_LINE_S_LSB VS_F1_LINE_WIDTH VS_F2_LINE_S_LSB VS_F2_LINE_WIDTH VS_F1_PIX_S_LSB VS_F1_PIX_MSB VS_F1_PIX_E_LSB VS_F2_PIX_S_LSB VS_F2_PIX_MSB VS_F2_PIX_E_LSB FREF_F1_S_LSB FREF_POL_MSB FREF_F2_S_LSB CLAMP_PIX_S_LSB CLAMP_PIX_MSB CLAMP_PIX_E_LSB (c) NXP B.V. 2008. All rights reserved. I2C-bus registers; (R): reading register[1] ...continued Sub R/W Bit definition addr 7 (MSB) ABh W ACh W ADh W AEh W AFh W B0h W B1h W B2h W B4h W B5h W B7h W B8h W B9h W BAh W BBh W BCh W BDh W BEh W BFh W C0h W C1h W C8h W C9h W CAh W CLAMP_PIX_START[11:8] CLAMP_PIX_END[7:0] CLAMP_F1_LINE_START[10:8] CLAMP_F1_LINE_START[7:0] CLAMP_F1_LINE_WIDTH[7:0] CLAMP_F2_LINE_START[10:8] FPOL VS_F2_PIX_START[11:8] VS_F2_PIX_END[7:0] FREF_F1_START[7:0] FREF_F1_START[10:8] FREF_F2_START[10:8] FREF_F2_START[7:0] CLAMP_PIX_START[7:0] CLAMP_PIX_END[11:8] VS_F1_PIX_START[11:8] VS_F1_PIX_END[7:0] VS_F2_PIX_START[7:0] VS_F2_PIX_END[11:8] 6 5 4 HS_END[7:0] VREF_F1_START[10:8] VREF_F1_START[7:0] VREF_F1_WIDTH[7:0] VREF_F2_START[10:8] VREF_F2_START[7:0] VREF_F2_WIDTH[7:0] VS_F1_LINE_START[10:8] VS_F1_LINE_START[7:0] VS_F1_LINE_WIDTH[7:0] VS_F2_LINE_START[10:8] VS_F2_LINE_START[7:0] VS_F2_LINE_WIDTH[7:0] VS_F1_PIX_START[7:0] VS_F1_PIX_END[11:8] 3 2 1 0 (LSB) Default value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0001 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Product data sheet Rev. 01 -- 17 March 2008 14 of 52 TDA9955HL_1 NXP Semiconductors HS_START[11:8] HS_END[11:8] VS_F1_LINE_S_MSB B3h W VS_F2_LINE_S_MSB B6h W Triple 8-bit analog-to-digital video converter for HDTV TDA9955HL CLP_F1_LINE_S_MSB CBh W CLP_F1_LINE_S_LSB CCh W CLP_F1_LINE_WIDTH CDh W CLP_F2_LINE_S_MSB CEh W xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 4. Register I2C-bus registers; (R): reading register[1] ...continued Sub R/W Bit definition addr 7 (MSB) 6 5 4 3 2 1 0 (LSB) Default value 0000 0000 0000 0000 0000 0001 GAIN_END[11:8] GAIN_END[7:0] FDW_START[7:0] FDW_START[11:8] FDW_END[7:0] x x x x x x BLK_GY[5:0] BLK_BU[5:0] BLK_RV[5:0] BLK_GY[7:6] OUT x HR_PXQ VPL x CS_SEL[2:0] HR_SEL CS_POL DE_PXQ VPC_SEL[1:0] DE_POL RST_MAN x BLC x HS_POL BLK_BU[7:6] C_CEIL[5:0] C_FLOOR[5:0] Y_CEIL[5:0] Y_FLOOR[5:0] TRC x x VS_SEL[1:0] VS_POL RST_AVI VPB_SEL[1:0] x x FOR_SEL[1:0] x x HS_SEL[2:0] VPA_SEL[1:0] x x FILTERBU[1:0] x MEAS_PIX[7:0] x x x x BLK_RV[7:6] FILTERRV[1:0] x x MEAS_LINES[10:8] MEAS_PIX[11:8] MEAS_LINES[7:0] FDW_END[11:8] 0000 0000 0101 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 0001 0010 0010 0010 1100 0000 0100 0000 1010 1100 0100 0000 0100 0010 0000 0001 0000 0000 0000 0000 1010 0100 0000 1000 0000 0101 Product data sheet Rev. 01 -- 17 March 2008 (c) NXP B.V. 2008. All rights reserved. TDA9955HL_1 NXP Semiconductors CLP_F2_LINE_S_LSB CFh W CLP_F2_LINE_WIDTH D0h W GAIN_S_LSB GAIN_MSB GAIN_E_LSB FDW_S_LSB FDW_MSB FDW_E_LSB ASD_MEASLIN_MSB MEASLIN_LSB MEASPIX_MSB MEASPIX_LSB Reserved for test BLK_GY_LSB BLK_BU_LSB BLK_RV_LSB BLK_MSB PRE_FILTERS OF_CCEIL OF_CFLOOR OF_YCEIL OF_YFLOOR OF_CTRL Reserved for test Reserved for test CSVSHS_SEL POL_CTRL OUTPUT_CTRL DE_CNTRL RESET_CNTRL D1h W D2h W D3h W D4h W D5h W D6h W D7h R D8h R D9h R DAh R DBh W DCh W DDh W DEh W DFh W E0h W E1h W E2h W E3h W E4h W E5h W E6h W E7h W E8h W E9h W EAh W EBh W F1h W GAIN_START[11:8] CLAMP_F2_LINE_START[7:0] CLAMP_F2_LINE_WIDTH[7:0] GAIN_START[7:0] Triple 8-bit analog-to-digital video converter for HDTV TDA9955HL FREF_POL HREF_POL VREF_POL 0000 0000 15 of 52 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 4. Register PD_AVI_CNTRL0 PD_AVI_CNTRL1 FVH_SEL LSB_OUT_SEL OR_SEL [1] I2C-bus registers; (R): reading register[1] ...continued Sub R/W Bit definition addr 7 (MSB) F4h F5h F6h F7h F9h W W W W W x x x 6 5 4 PD_SOG2 LSB_SEL[7:0] x x x x x 3 PD_SOG1 2 PD_DLL 1 PD_PLL 0 (LSB) PD_AVI FVH_SEL Default value 0000 0000 0000 0001 0000 0000 0000 0000 Product data sheet Rev. 01 -- 17 March 2008 16 of 52 TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. NXP Semiconductors PD_ADC_B PD_ADC_G PD_ADC_R 0010 0000 The symbol `x' indicates a bit reserved for test and the symbol `-' indicates that the bit is not used. Triple 8-bit analog-to-digital video converter for HDTV TDA9955HL NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 9.2.1 Version register Table 5. VERSION register (address 00h) bit description Legend: * = default value Bit Symbol Access Value Description R 14h* the version register gives the version of the device, version is 0001 0100 7 to 0 - 9.2.2 Input selection register Table 6. INPUT_SEL register (address 01h) bit description Legend: * = default value Bit Symbol Access Value W W 00* 01 Description video input selection: enables analog video input 1, analog video input 2 video input 1 video input 2 7 to 2 x 1 to 0 VINS[1:0] 00 0001* for test: must be set to default value for proper operation 9.2.3 Sync detection recognition and separation registers Table 7. SDRS_CTRL1 register (address 04h) bit description Legend: * = default value Bit 7 6 Symbol x ASD_DIS Access Value Description R/W W 0* 1 5 SOGF W 0* for test: must be set to default value for proper operation automatic sync detection disable: Digital Separated Syncs > Digital Composite Sync > Sync On Green enable disable sync on green forced: when set, forces the use of SOGx (where x corresponds to the selected analog video input) input when the automatic sync detection is disabled 0* 1 4 DCSF W enable disable digital composite sync forced: when set, forces the use of HCSYNCx (where x corresponds to the selected analog video input) input when the automatic sync detection is disabled 0* 1 3 to 0 x W enable disable 0000* for test: must be set to default value for proper operation Table 8. SDRS_FLAGS register (address 0Dh) bit description[1] Legend: * = default value Bit Symbol Access Value Description 7 ASD R 0* 1 TDA9955HL_1 additional sync pulses detected: additional sync pulses on the selected analog input are not detected are detected (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 17 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 8. SDRS_FLAGS register (address 0Dh) bit description[1] ...continued Legend: * = default value Bit Symbol Access Value Description 6 SOGD2 R 0* 1 5 4 DSSD2 R 0* 1 3 2 SOGD1 R 0* 1 1 0 DSSD1 R 0* 1 [1] sync on green detected: on pin SOG2 pulses are not detected pulses are detected not used digital separated syncs detected: on pins VSYNC2 and HCSYNC2 pulses are not detected pulses are detected not used sync on green detected: on pin SOG1 pulses are not detected pulses are detected not used digital separated syncs detected: on pins VSYNC1 and HCSYNC1 pulses are not detected pulses are detected When one of these bits changes, the VAI_N pin is pulled down until SDRS_FLAGS0 is read. 9.2.4 PLL registers Table 9. PLL_CTRL register (address 10h) bit description Legend: * = default value Bit 7 6 to 4 3 EDG Symbol Access Value Description R R R 0* 1 2 to 0 [1] reserved for test not used edge: synchronizes the PLL on the internal HSYNC pulses on the rising edge on the falling edge reserved for test R By default, the SDRS toggles automatically the HSYNC to have an internal positive HSYNC signal TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 18 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 10. PLL_MNDIV registers (address 11h and 12h) bit description Legend: * = default value Address Register 11h PLL_MNDIV_MSB Bit Symbol Access Value Description W master divider: selects the master divider to adjust the sampling frequency range with the PLL frequency range from 110 MHz to 200 MHz 00 01 10 11* 5 to 4 3 to 0 NDIV[11:8] 12h PLL_NDIV_LSB 7 to 0 NDIV[7:0] W W W 00* 3h* 60h* divided by 1; > 110 Msample/s divided by 2; 50 Msample/s to 110 Msample/s divided by 4; 25 Msample/s to < 50 Msample/s divided by 8; 12.5 Msample/s to < 25 Msample/s not used pixel divider: pixel division value 7 to 6 MDIV[1:0] Table 11. LOCKFLAG register (address 13h) bit description Legend: * = default value Bit 7 to 2 1 0 Symbol x PLL_LOCK Access Value W W R 0* 1 0* Description for test; must be set to default value for proper operation PLL_lock: indicates when the PLL is locked not locked locked 00 0000* not used 9.2.5 Pixel clocks generation registers Table 12. DLL_PHASE register (address 14h) bit description Legend: * = default value Bit Symbol Access Value W W 000* Description not used 7 to 5 4 to 0 PHASE[4:0] 1 0000* phase: these bits set the phase shift for the three clock signals CLKPIX, CLKFOR and CLKOUT; it is the fine adjustment of the phase, see Table 15 TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 19 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 13. PIXCLKGEN_PRST register (address 15h) bit description Legend: * = default value Bit Symbol Access Value Description 110* output clock preset: these bits set the phase shift for the output clock CLKOUT; it is the rough adjustment of the phase and there is the same number of steps as the division factor selected for CLKOUT formatter clock preset used to program the phase shift for the 4 : 2 : 2 formatter clock CLKFOR It Is the rough adjustment of the phase and there is the same number of steps than the division factor selected for CLKFOR pixel clock preset: these bits set the phase shift for the ADC and VHREF pixel clock CLKPIX; it is the rough adjustment of the phase and there is the same number of steps as the division factor selected for CLKPIX 7 to 5 CLKOUT_PRST[2:0] W 4 to 3 CLKFOR_PRST[1:0] W 10* 2 to 0 CLKPIX_PRST[2:0] W 111* Table 14. PIXCLKGEN_CTRL0 register (address 16h) bit description Legend: * = default value Bit Symbol Access Value Description W output clock division factor: selects the PLL frequency division factor for the output clock CLKOUT. For 4 : 2 : 2 semi-planar or 4 : 4 : 4 output formats, the division factor must be the same as the master division factor. In case of the 4 : 2 : 2 ITU-R BT.656 formats, it must be half of the master division factor 00* 01 10 11 5 to 4 CLKFOR_DIV[1:0] W divide by 2 divide by 4 divide by 8 not defined formatter clock division factor: selects the PLL frequency division factor for the ITU-R BT.656 formatter clock CLKFOR The division factor must be the half of the master division factor 00 01 10 11* 3 to 2 CLKPIX_DIV[1:0] W divide by 2 divide by 4 not defined not defined pixel clock division factor: selects the PLL frequency division factor for the pixel clock CLKPIX. The division factor must be the same as the master division factor 00 01 10* 11 divide by 2 divide by 4 divide by 8 not defined 7 to 6 CLKOUT_DIV[1:0] TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 20 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 14. PIXCLKGEN_CTRL0 register (address 16h) bit description ...continued Legend: * = default value Bit 1 Symbol PR_DEL Access Value Description W 0 1* 0 PH_CORR W phase delay: delays the rough adjustment of the three clock signals, see Table 15 no delay delay of one PLL period phase correction: selects the falling or rising edge of the horizontal reference signal from the PLL to synchronize the three clock divisions, see Table 15 0 1* Table 15. 0 to 7 8 to 15 16 to 31 Table 16. falling edge selected rising edge selected Relationship between bits PR_DEL, PH_CORR and phase value PR_DEL 0 1 1 PH_CORR 0 1 0 PHASE[4:0] Relation between master division and clock division 4 : 4 : 4 or semi-planar CLKOUT _DIV 10 01 00 11 CLKOUT _PRST 0 to 7 0 to 3 0 or 1 0 4 : 2 : 2 ITU-R BT.656 formatter clock CLKOUT _DIV 01 00 11 CLKOUT _PRST 0, 1, 2, 3 0 or 1 0 CLKFOR _DIV 01 00 11 CLKFOR _PRST 0, 1, 2, 3 0 or 1 0 pixel clock CLKPIX _DIV 10 01 00 00 CLKPIX _PRST 0 to 7 0 to 3 0 or 1 0 MDIV[1:0] Master division 11 10 01 00 8 4 2 1 not available not available 9.2.6 Pixel clocks generation registers Table 17. PIXCLKGEN_CTRL1 register (address 17h) bit description Legend: * = default value Bit 7 Symbol CLKOUT_TOG Access Value Description W 0* 1 6 to 4 CLKOUT_SEL[2:0] W 000 001 010 011 100* 101 110 111 TDA9955HL_1 output clock toggle does not toggle the signal CLKOUT toggles the signal CLKOUT output clock selection: select the clock available on pin VCLK reserved for test reserved for test not defined not defined CLKOUT CLKFOR CLKPIX not defined (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 21 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 17. PIXCLKGEN_CTRL1 register (address 17h) bit description ...continued Legend: * = default value Bit Symbol Access Value Description formatter clock selection: select the clock for the ITU-R656 formatter 00 01* 10 11 1 to 0 x W 10* reserved for test CLKFOR not defined 0 for test: must be set to default value for proper operation 3 to 2 CLKFOR_SEL[1:0] W 9.2.7 Clamp levels registers Table 18. Bright levels registers (address 1Ah to 1Ch) bit description Legend: * = default value Addr 1Ah 1Bh 1Ch Register Bit Symbol Access Value Description 10h* 80h* 80h* G/Y brightness: these bits control the clamp level of the G/Y channel B/PB brightness: these bits control the clamp level of the B/PB channel R/PR brightness: these bits control the clamp level of the R/PR channel BRIGHT_GY 7 to 0 BRIGHT_ GY[7:0] W BRIGHT_BU 7 to 0 BRIGHT_ BU[7:0] W BRIGHT_RV 7 to 0 BRIGHT_ RV[7:0] W Table 19. Decimal 0 : 247 Relationship between the brightness code and the clamp level Clamp code (decimal) Binary MSB/LSB 0000 0000 : 1111 0111 0 : 247 Programmed code (8-bits) 9.2.8 Video gain registers (GAIN_RV, GAIN_BU, GAIN_GY) Table 20. R/V video gain registers (addresses 20h to 23h) bit description Legend: * = default value Addr 20h 21h 22h 23h Register Bit Symbol Access Value W 04h* 5Ch* F0h* 90h* W W W W W Description not used coarse_rv: coarse gain value for channel R/V not used fine_rv: fine gain value for channel R/V high_rv: AGC high value for channel R/V not used low_rv: AGC low value for channel R/V COARSE_GAINRV 7 to 4 FINE_GAINRV AGC_HIGHRV AGC_LOWRV 7 - 3 to 0 COARSE_RV[3:0] W 6 to 0 FINE_RV[6:0] 7 to 0 HIGH_RV[7:0] 7 6 to 0 LOW_RV[6:0] TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 22 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 21. B/U video gain registers (addresses 2Ah to 2Dh) bit description Legend: * = default value Addr 2Ah 2Bh 2Ch 2Dh Register Bit Symbol Access Value W 04h* 5Ch* F0h* 90h* W W W W W Description not used coarse_bu: coarse gain value for channel B/U not used fine_bu: fine gain value for channel B/U high_bu: AGC high value for channel B/U not used low_bu: AGC low value for channel B/U COARSE_GAINBU 7 to 4 FINE_GAINBU AGC_HIGHBU AGC_LOWBU 7 - 3 to 0 COARSE_GY[3:0] W 6 to 0 FINE_BU[6:0] 7 to 0 HIGH_BU[7:0] 7 6 to 0 LOW_BU[6:0] Table 22. G/Y video gain registers (addresses 34h to 37h) bit description Legend: * = default value Addr 34h Register Bit Symbol Access Value Description W 04h* not used coarse_gy: coarse gain value for the channel G/Y not used 5Ch* F0h* 90h* fine_gy: fine gain value for the channel G/Y high_gy: AGC high value for the channel G/Y not used low_gy: AGC low value for the channel G/Y COARSE_GAINGY 7 to 4 - 3 to 0 COARSE_GY[3:0] W 35h 36h 37h FINE_GAINGY AGC_HIGHGY AGC_LOWGY 7 W W W W W 6 to 0 FINE_GY[6:0] 7 to 0 HIGH_GY[7:0] 7 6 to 0 LOW_GY[6:0] 9.2.9 Sync timing measurement registers Table 23. Addr 40h 41h 44h 42h 44h 43h 44h [1] Sync timing measurement registers (address 40h to 44h) bit description Bit Symbol Access Value Description R R R R R 00h* 00h* 0000* 00h* 00* 00h* 00* vertical period: indicates the period of two fields (interlaced) or frames (progressive), counted in MCLK clock periods[1] horizontal period: indicates the period of the line, counted in MCLK clock periods[1] horizontal sync width: indicates the width of the horizontal sync pulse, counted in MCLK clock periods[1] 7 to 0 V_PER[19:12] 7 to 0 V_PER[11:4] 7 to 4 V_PER[3:0] 7 to 0 H_PER[9:2] 3 to 2 H_PER[1:0] Register V_PER_MSB V_PER_ISB STM_LSB H_PER_MSB STM_LSB STM_LSB HS_WIDTH_MSB 7 to 0 HS_WIDTH[9:2] R 1 to 0 HS_WIDTH[1:0] R The recommended frequency for MCLK signal is 13.5 MHz. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 23 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 9.2.10 Color space conversion registers Table 24. MAT_CTRL register (address 80h) bit description Legend: * = default value Bit 7 to 2 Symbol Access Value W 00 0000* Description not used scale factor selection: fix the scale factor to convert the floating matrix [Cxy] into an integer matrix 1 and 0 MAT_SC[1:0] W P 11 P 12 P 13 [Pxy]: P 21 P 22 P 23 P 31 P 32 P 33 C 11 C 12 C 13 = INT S x C 21 C 22 C 23 C 31 C 32 C 33 . The choice depends on the biggest coefficient in absolute value |Cxy|: 00 01 10* 11 when 2 |Cxy| < 4; S = 256 when 1 |Cxy| < 2; S = 512 when |Cxy| < 1; S = 1024 undefined Table 25. Offset input registers (address 81h to 86h) bit description Legend: * = default value[1] Addr 81h 82h Register Bit Symbol Access Value W W W W W W W W 000* 00h* 00* 000* 00h* 00* Description offset in 1 compensate the brightness value for the channel G/Y, e.g. with YCBCR input, -16 for Y so OFFSET_IN1 = 1111 0000b = F0h[2] not used offset in 2 compensate the brightness value for the channel R/V, e.g. with YCBCR input, -128 for CR so OFFSET_IN2 = 1000 0000b = 80h[2] not used MAT_OI1_MSB 7 to 3 2 to 0 MAT_OI1[8:6] MAT_OI1_LSB 7 to 2 OFFSET_IN1[5:0] 1 to 0 83h 84h MAT_OI2_MSB 7 to 3 2 to 0 MAT_OI2[8:6] MAT_OI2_LSB 7 to 2 OFFSET_IN2[5:0] 1 to 0 0 0000* not used 0 0000* not used TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 24 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 25. Offset input registers (address 81h to 86h) bit description ...continued Legend: * = default value[1] Addr 85h 86h Register Bit Symbol Access Value W W W W 000* 00h* 00* Description offset_in3 compensate the brightness value for the channel B/U, e.g. with YCBCR input, -128 for CB so OFFSET_IN3 = 1000 0000b = 80h[2] not used MAT_OI3_MSB 7 to 3 2 to 0 MAT_OI3[8:6] MAT_OI3_LSB 7 to 0 OFFSET_IN3[5:0] [1] [2] 0 0000* not used 1 to 0 - The default values correspond with the RGB full-scale to YCBCR ITU-R BT.601 reduced-scale conversion. The value is signed 11-bit two's complement integer. Table 26. Coefficient registers (address 87h to 98h) bit description Legend: * = default value[1] Addr 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h [1] [2] Register Bit Symbol Access Value W W W W W W W W W W W W W W W W W W 010* 02h* 001* 06h* 000* 64h* 110* 89h* 001* C0h* 111* B7h* 110 D7h* 111* 69h* 001* C0h* Description coefficient (1,1): coefficient from the G/Y channel to the G/Y channel[2] MAT_P11_MSB 7 to 3 MAT_P11_LSB 7 to 0 P11[7:0] 0 0000* not used 2 to 0 P11[10:8] W MAT_P12_MSB 7 to 3 MAT_P12_LSB 7 to 0 P12[7:0] 0 0000* not used coefficient (1,2): coefficient from the R/CR channel to the G/Y channel[2] 2 to 0 P12[10:8] W MAT_P13_MSB 7 to 3 MAT_P13_LSB 7 to 0 P13[7:0] 0 0000* not used coefficient (1,3): coefficient from the B/CB channel to the G/Y channel[2] 2 to 0 P13[10:8] W MAT_P21_MSB 7 to 3 MAT_P21_LSB 7 to 0 P21[7:0] 0 0000* not used coefficient (2,1): coefficient from the G/Y channel to the R/CR channel[2] 2 to 0 P21[10:8] W MAT_P22_MSB 7 to 3 MAT_P22_LSB 7 to 0 P22[7:0] 0 0000* not used coefficient (2,2): coefficient from the R/CR channel to the R/CR channel[2] 2 to 0 P22[10:8] W MAT_P23_MSB 7 to 3 MAT_P23_LSB 7 to 0 P23[7:0] 0 0000* not used coefficient (2,3): coefficient from the B/CB channel to the R/CR channel[2] 2 to 0 P23[10:8] W MAT_P31_MSB 7 to 3 MAT_P31_LSB 7 to 0 P31[7:0] 0 0000* not used coefficient (3,1): coefficient from the G/Y channel to the B/CB channel[2] 2 to 0 P31[10:8] W MAT_P32_MSB 7 to 3 MAT_P32_LSB 7 to 0 P32[7:0] 0 0000* not used coefficient (3,2): coefficient from the R/CR channel to the B/CB channel[2] 2 to 0 P32[10:8] W MAT_P33_MSB 7 to 3 MAT_P33_LSB 7 to 0 P33[7:0] 0 0000* not used coefficient (3,3): coefficient from the B/CB channel to the B/CB channel[2] 2 to 0 P33[10:8] W The default values of the coefficients correspond with the RGB full-scale to YCBCR ITU-R BT601 reduced scale conversion. The value is signed 11-bit two's complement integer. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 25 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 27. Offset output registers (address 99h to 9Eh) bit description Legend: * = default value[1] Addr Register 99h Bit Symbol Access Value W W W W W W W W 0 1* [1] [2] Description offset output 1: the new brightness values for the channel G/Y, e.g. with YCBCR output, 16 for Y so OFFSET_OUT1 = 0 0001 0000b = 10h[2] offset output 2: the new brightness values for the channel R/V e.g. with YCBCR output, 128 for CR so OFFSET_OUT2 = 0 1000 0000b = 80h[2] offset output 3: the new brightness values for the channel B/U e.g. with YCBCR output, 128 for CB so OFFSET_OUT3 = 0 1000 0000b = 80h[2] not used matrix bypassed: bypasses or not the matrix and offsets conversion not bypassed bypassed MAT_OO1_MSB 7 to 3 7 to 0 OFFSET_OUT1[7:0] 0 0000* not used 000* 40h* 2 to 0 OFFSET_OUT1[10:8] W 9Ah MAT_OO1_LSB 9Bh MAT_OO2_MSB 7 to 3 9Ch MAT_OO2_LSB 7 to 0 OFFSET_OUT2[7:0] 0 0000* not used 010* 00h* 2 to 0 OFFSET_OUT2[10:8] W 9Dh MAT_OO3_MSB 7 to 3 9Eh MAT_OO3_LSB 9Fh MAT_BYPASS 7 to 0 OFFSET_OUT3[7:0] 7 to 1 0 MAT_BP 0 0000* not used 010* 00h* 00h* 2 to 0 OFFSET_OUT3[10:8] W The default values correspond with the RGB full-scale to YCBCR ITU-R BT.601 reduced-scale conversion. The value is signed 11-bit two's complement integer. 9.2.11 Line and pixel counters Table 28. Pixel counter registers (address A1h to A3h) bit description Legend: * = default value Address Register A1h A2h PXCNT_PR_LSB PXCNT_MSB Bit Symbol Access Value Description W W 03h* 0h* 3h* 60h* pixel counter preset: preset value stored in the pixel counter on the rising edge of the internal HSYNC pixel counter number of pixels: modulo of the pixel counter; this counter counts from 1 to PXCNT_NPIX and rolls-over to 1; the recommended value is the total number of pixels per line 7 to 0 PXCNT_PR[7:0] 7 to 4 PXCNT_PR[11:8] 3 to 0 PXCNT_NPIX[11:8] W A3h PXCNT_NPIX_LSB 7 to 0 PXCNT_NPIX[7:0] W Table 29. Line counter registers (address A4h to A6h) bit description Legend: * = default value Address Register A4h A5h LCNT_PR_LSB LCNT_MSB Bit Symbol Access Value Description W W 01h* 0h* 0h* 00h* line counter preset: preset value stored in the line counter on the rising edge of the internal VSYNC line counter number of lines: modulo of the line counter; this counter counts from 1 to LCNT_NLIN and rolls-over to 1; the recommended value is the total number of lines per frame; if value is set to 000h the line counter uses the value of MEAS_LINES 7 to 0 LCNT_PR[7:0] 7 to 4 LCNT_PR[11:8] 3 to 0 LCNT_NLIN[11:8] W A6h LCNT_NLIN_LSB 7 to 0 LCNT_NLIN[7:0] W TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 26 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV PXCNT_NPIX: [4:4095] pixels line 1 pixel 1 pixel counter counts CLKPIX pulses modulo NPIX iVS LCNT_NLIN: [1:4095] lines line counter counts iHS pulses modulo NLIN in case of interlaced signal, line counter don't care the iVS of second field PXCNT_PR LCNT_PR rising edge of iVS loads the line counter with the LCNT_PR value iHS rising edge of iHS loads the pixel counter with the PXCNT_PR value 001aaa290 Fig 4. Line and pixel counters Table 30. Horizontal reference registers (address A7h to A9h) bit description Legend: * = default value Address Register A7h A8h HREF_S_LSB HREF_MSB Bit Symbol Access Value Description W 00h* 0h* horizontal reference start: index of the first active pixel, and also the position of the rising edge of HREF signal and the position of SAV; if null, HREF stays LOW and no SAV is inserted in the data stream horizontal reference end (LSB): index after the last active pixel, and also the position of the falling edge of HREF signal and the position of EAV; if null, HREF falls at the beginning of a new line and no EAV is inserted in the data stream 7 to 0 HREF_START[7:0] 7 to 4 HREF_START[11:8] W 3 to 0 HREF_END[11:8] A9h HREF_E_LSB 7 to 0 HREF_END[7:0] W W 0h* 00h* Table 31. Horizontal reference registers (address AAh to ACh) bit description Legend: * = default value Address Register AAh ABh HS_S_LSB HS_MSB Bit Symbol Access Value Description W W W W 00h* 0h* 0h* 00h* horizontal sync start: define the position of the rising edge of the HS signal generated by the timing generator[1] horizontal sync end: define the position of the falling edge of the HS signal generated by the timing generator[1] 7 to 0 HS_START[7:0] 7 to 4 HS_START[11:8] 3 to 0 HS_END[11:8] ACh [1] HS_E_LSB 7 to 0 HS_END[7:0] If 0, HS signal corresponds with the horizontal sync internal signal. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 27 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 32. Vertical reference registers (address ADh to B2h) bit description[1] Legend: * = default value Addr ADh AEh Register VREF_F1_S_MSB VREF_F1_S_LSB Bit Symbol Access Value W W W 000* 00h* Description vertical reference start for field 1: index of the first blanking line for field 1, and also the position of the rising edge of VREF signal and the value of bit V in SAV/EAV code; if 0, VREF stays LOW vertical reference width for field 1: width of the vertical blanking for field 1, and also the width of VREF signal and the value of bit V in SAV/EAV code; if 0, VREF stays LOW vertical reference start for field 2: index of the first blanking line for field 2, and also the position of the rising edge of VREF signal and the value of bit V in SAV/EAV code vertical reference width for field 2: width of the vertical blanking for field 2, and also the width of VREF signal and the value of bit V in SAV/EAV code 7 to 3 2 to 0 VREF_F1_START[10:8] 7 to 0 VREF_F1_START[7:0] 0 0000* not used AFh VREF_F1_WIDTH 7 to 0 VREF_F1_WIDTH[7:0] W 00h* B0h B1h VREF_F2_S_MSB VREF_F2_S_LSB 7 to 3 2 to 0 VREF_F2_START[10:8] 7 to 0 VREF_F2_START[7:0] W W W 0 0000* not used 000* 00h* B2h VREF_F2_WIDTH 7 to 0 VREF_F2_WIDTH[7:0] W 00h* [1] In progressive case, bits VREF_F2_START[10:0] and VREF_F2_WIDTH[7:0] must be set to logic 0. Table 33. Vertical sync registers (address B3h to BEh) bit description Legend: * = default value Addr B3h B4h Register Bit Symbol Access Value W W 000* 00h* Description vertical sync line start for field 1: position in number of lines of the VS signal generated by the timing generator for the field 1; if 0, VS stays LOW vertical sync line width for field 1: width in number of lines of the VS signal generated by the timing generator for field 1; if 0, VS stays LOW vertical sync line start for field 2: position in number of lines of the VS signal generated by the timing generator for the field 2[1] vertical sync line width for field 2: width in number of lines of the VS signal generated by the timing generator for field 2[1] VS_F1_LINE_S_MSB 7 to 3 VS_F1_LINE_S_LSB 7 to 0 VS_F1_LINE_START[7:0] 0 0000* not used 2 to 0 VS_F1_LINE_START[10:8] W B5h VS_F1_LINE_WIDTH 7 to 0 VS_F1_LINE_WIDTH[7:0] W 00h* B6h B7h VS_F2_LINE_S_MSB 7 to 3 VS_F2_LINE_S_LSB 7 to 0 VS_F2_LINE_START[7:0] W W 0 0000* not used 000* 00h* 2 to 0 VS_F2_LINE_START[10:8] W B8h VS_F2_LINE_WIDTH 7 to 0 VS_F2_LINE_WIDTH[7:0] W 00h* TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 28 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 33. Vertical sync registers (address B3h to BEh) bit description ...continued Legend: * = default value Addr B9h BAh Register VS_F1_PIX_S_LSB VS_F1_PIX_MSB Bit Symbol Access Value W W 01h* 0h* Description vertical sync pixel start for field 1: position in number of pixels of the rising edge of the VS signal generated by the timing generator for field 1; if 0, VS stays LOW vertical sync pixel end for field 1 (LSB): position in number of pixels of the falling edge of the VS signal generated by the timing generator for field 1; if 0, VS stays LOW vertical sync pixel start for field 2: position in number of pixels of the rising edge of the VS signal generated by the timing generator for field 2 vertical sync pixel end for field 2: position in number of pixels of the falling edge of the VS signal generated by the timing generator for field 2 7 to 0 VS_F1_PIX_START[7:0] 7 to 4 VS_F1_PIX_START[11:8] 3 to 0 VS_F1_PIX_END[11:8] BBh VS_F1_PIX_E_LSB 7 to 0 VS_F1_PIX_END[7:0] W W 0h* 01h* BCh BDh VS_F2_PIX_S_LSB VS_F2_PIX_MSB 7 to 0 VS_F2_PIX_START[7:0] 7 to 4 VS_F2_PIX_START[11:8] W W 01h* 0h* 3 to 0 VS_F2_PIX_END[11:8] BEh VS_F2_PIX_E_LSB 7 to 0 VS_F2_PIX_END[7:0] W W 0h* 01h* [1] In progressive case bits VS_F2_LINE_START[12:0] and VS_F2_LINE_WIDTH[7:0] must be set to logic 0. line 1 pixel 1 VREF VREF_F1_START[10:0] VREF_F1_WIDTH[7:0] active video field 1 LOW during active video; HIGH during vertical blanking period VREF_F2_START[10:0] blanking period VREF_F2_WIDTH[7:0] active video field 2 VREF changes state at pixel 1(1) VREF_F1_START[10:0] HREF (1) HREF_START[11:0] VREF_F1_WIDTH[7:0] HIGH during active video; LOW during horizontal blanking period HREF_END[11:0] 001aaa291 Fig 5. HREF and VREF in interlaced case TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 29 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV line 1 pixel 1 VREF VREF_F1_WIDTH[7:0] LOW during active video; HIGH during vertical blanking period blanking period active video VREF_F2 registers must be set to 0 VREF changes state at pixel 1(1) VREF_F1_START[10:0] VREF_F1_WIDTH[7:0] HREF (1) HREF_START[11:0] HIGH during active video; LOW during horizontal blanking period HREF_END[11:0] 001aaa292 Fig 6. HREF and VREF in progressive case Table 34. Field reference registers (address BFh to C1h) bit description Legend: * = default value Addr BFh Register Bit Symbol Access Value Description W 00h* field reference for field 1 start (LSB): index of the first line for field 1 which corresponds to the line where the FREF signal toggles, see register FREF_POL_MSB bit 6 to bit 4 field polarity: defines the polarity of the FREF signal and bit F in the SAV/EAV code 0* 1 6 to 4 FREF_F1_START[10:8] W 000* field 1 is LOW and field 2 is HIGH field 1 is HIGH and field 2 is LOW field reference for field 1 start (MSB): index of the first line for field 1 which corresponds to the line where the FREF signal toggles, see register FREF_F1_S_LSB bit 7 to bit 0 not used field reference for field 2 start: index of the first line for field 2 which corresponds to the line where the FREF signal toggles FREF_F1_S_LSB 7 to 0 FREF_F1_START[7:0] C0h FREF_POL_MSB 7 FPOL W 3 C1h - W W 0* 000* 00h* 2 to 0 FREF_F2_START[10:8] W FREF_F2_S_LSB 7 to 0 FREF_F2_START[7:0] TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 30 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV line 1 pixel 1 FREF FREF_F1_START[10:0] active video field 1 LOW during field 1; HIGH during field 2 (can be changed with bit FIELD_POL) blanking period FREF_F2_START[10:0] active video field 2 FREF changes state at pixel 1 001aaa293 Fig 7. FREF in interlaced case Table 35. Clamp signal registers (address C8h to CAh) bit description[1] Legend: * = default value Addr C8h C9h Register CLAMP_PIX_MSB Bit Symbol Access Value Description W 00h* 0h* clamp signal pixel start: position, in number of pixels, of the beginning of the clamp signal generated by the timing generator clamp signal pixel end: position, in number of pixels, of the end of the clamp signal generated by the timing generator CLAMP_PIX_S_LSB 7 to 0 CLAMP_ PIX_ START[7:0] 7 to 4 CLAMP_ PIX_ START[11:8] W 3 to 0 CLAMP_ PIX_ END[11:8] CAh CLAMP_PIX_E_LSB 7 to 0 CLAMP_PIX_ END[7:0] W W 0h* 00h* [1] Minimum width of the clamp pulse is 40 pixels and it must be active only during the horizontal back porch. Table 36. CLP_Fx_LINE_nnn registers (address CBh to D0h) bit description Legend: * = default value Addr CBh Register Bit Symbol Access Value Description W W W 0 not used 0000* 000* 00h* clamp signal line start for field 1 (LSB): position, in number of lines, from which no clamp pulses are generated for field 1, typically during the vertical pulse in case of the sync on green signal clamp signal line width for field 1: width, in number of lines, where no clamp pulses are generated for field 1 CLP_F1_LINE_S_MSB 7 to 3 2 to 0 CLAMP_F1_ LINE_ START[10:8] CCh CLP_F1_LINE_S_LSB 7 to 0 CLAMP_F1_LINE_START[7:0] CDh CLP_F1_LINE_WIDTH 7 to 0 CLAMP_F1_LINE_WIDTH[7:0] W 00h* TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 31 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 36. CLP_Fx_LINE_nnn registers (address CBh to D0h) bit description ...continued Legend: * = default value Addr CEh Register Bit Symbol Access Value Description W 0 not used 0000* 000* 00h* clamp signal line start for field 2 (LSB): position, in number of lines, from which no clamp pulses are generated for field 2, typically during the vertical pulse in case of the sync on green signal clamp signal line width for field 2: width, in number of lines, where no clamp pulses are generated for field 2 CLP_F2_LINE_S_MSB 7 to 3 - 2 to 0 CLAMP_F2_LINE_START[10:8] W CFh CLP_F2_LINE_S_LSB 7 to 0 CLAMP_F2_LINE_START[7:0] W D0h CLP_F2_LINE_WIDTH 7 to 0 CLAMP_F2_LINE_WIDTH[7:0] W 00h* Table 37. GAIN signal registers (address D1h to D3h) bit description[1] Legend: * = default value Address Register D1h D2h D3h [1] Bit Symbol Access Value Description W W W 00h* 0h* 0h* 51h* gain start signal: position of the gain signal generated by the timing generator gain end signal: position of the end of the gain signal generated by the timing generator GAIN_S_LSB 7 to 0 GAIN_START[7:0] GAIN_MSB 3 to 0 GAIN_ END[11:8] GAIN_E_LSB 7 to 0 GAIN_END[7:0] 7 to 4 GAIN_ START[11:8] W The minimum width of the gain pulse (GAIN_END - GAIN_START) is 80 pixels and can include the horizontal sync pulse. The gain pulse and the clamp pulse should not overlap. Table 38. Horizontal sync registers (address D4h to D6h) bit description Legend: * = default value Addr D4h D5h Register FDW_S_LSB FDW_MSB Bit Symbol Access Value Description W W W W 00h* 0h* 0h* 00h* frame detection window start: position of the start of the frame detection window; the recommended value is 78 of total number of pixels per line frame detection window end: position of the end of the frame detection window; the recommended value is 38 of total number of pixels per line 7 to 0 FDW_START[7:0] 7 to 4 FDW_START[11:8] 3 to 0 FDW_END[11:8] D6h FDW_E_LSB 7 to 0 FDW_END[7:0] TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 32 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 39. Measured lines and pixels registers (address D7h to DAh) bit description Legend: * = default value Addr D7h Register Bit Symbol INTD Access Value Description R 0* 1 6 AUTO_OK R 0* 1 5 525 R 0* 1 4 to 3 D8h D9h DAh MEASLIN_LSB MEASPIX_MSB MEASPIX_LSB 7 to 0 MEAS_LINES[7:0] 7 to 4 3 to 0 MEAS_PIX[11:8] 7 to 0 MEAS_PIX[7:0] R 000* 00h* 0h* 0h* 00h* R R R R interlaced detected: indicates an interlaced or progressive signal progressive interlaced automatic detection: the number of measured lines per frame correspond to 625 or 525 (2 lines of tolerance) the timing generator is forced to 576i or 480i standard interlaced detected: when AUTO_OK = 1 is forced to 480i standard 525 (2 lines of tolerance) lines per frame are counted not used measured number of lines: indicates the number of lines per frame measured by the timing generator not used measured number of pixels: indicates the number of pixels per line measured by the timing generator; in Analog mode, the value is the same as the PLL division value ASD_MEASLIN_MSB 7 2 to 0 MEAS_LINES[10:8] R Table 40. Blanking code registers (address DCh to DFh) bit description[1] Legend: * = default value Addr DCh Register Bit Symbol Access Value Description 10h* blanking code of the G/Y channel (MSB), see address DFh bit 7 to bit 6 not used 80h* blanking code of the B/CB channel (MSB), see address DFh bit 4 to bit 3 not used 80h* blanking code of the R/CR channel (MSB), see address DFh bit 1 to bit 0 not used 00* 0* 10* 0* 10* blanking code bits 7 and 6 of the G/Y channel (MSB), see address DCh not used blanking code bits 7 and 6 of the B/CB channel (MSB), see address DDh not used blanking code bits 7 and 6 of the R/CR channel (MSB), see address DEh BLK_GY_LSB 7 to 2 BLK_GY[5:0] W 1 to 0 DDh BLK_BU_LSB W 7 to 2 BLK_BU[5:0] W 1 to 0 W DEh BLK_RV_LSB 7 to 2 BLK_RV[5:0] W 1 to 0 W DFh BLK_MSB 7 to 6 BLK_GY[7:6] W 5 W 4 to 3 BLK_BU[7:6] W 2 W 1 to 0 BLK_RV[7:6] W TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 33 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV [1] These register control the blanking code of the x/x channel; this code is output during the horizontal blanking (HREF is LOW) or the vertical blanking (VREF is HIGH) 9.2.12 Prefiltering register (PRE_FILTERS) This register is used to downsample the R/PR and B/PB channels for the YUV 4 : 2 : 2 semi-planar and ITU-R BT.656 formats. Table 41. PRE_FILTER register (address E0h) bit description Legend: * = default value Bit Symbol Access Value Description W 00* not used B/CB downsampling filter: enables the shape of the prefilter for the B/CB channel 00 01 10* 11 3 and 2 W 00* 1 and 0 FILTER_RV[1:0] W 00 01 10* 11 no filter (used in 4 : 4 : 4 mode) average of two samples simple 7-taps filter 27 taps ITU-R BT.601 compliant half-band filter not used R/CR downsampling filter: enables the shape of the prefilter for the R/CR channel no filter (used in 4 : 4 : 4 mode) average of two samples simple 7-taps filter 27 taps ITU-R BT.601 compliant half-band filter 7 and 6 - 5 and 4 FILTER_BU[1:0] W 9.2.13 Range control registers Table 42. Range control registers (address E1h to E4h) bit description Legend: * = default value Addr E1h Register OF_CCEIL Bit Symbol Access Value Description W W W 40h* C0h* not used chrominance ceiling level: fix the maximum code of B/CB and R/CR channels[1] not used chrominance floor level: fix the minimum code of B/CB and R/CR channels[2] not used ACh* luminance ceiling level: fix the maximum code of the G/Y channel[1] not used 40h* luminance floor level: fix the minimum code of G/Y channel[2] 7 to 6 5 to 0 C_CEIL[5:0] E2h OF_CFLOO R OF_YCEIL 7 to 6 - 5 to 0 C_FLOOR[5:0] W 7 to 6 5 to 0 Y_CEIL[5:0] W W W E3h E4h OF_YFLOO R 7 to 6 - 5 to 0 Y_FLOOR[5:0] W [1] [2] The maximum level can be chosen between the code words C0h (00h programmed) and FFh (3Fh programmed), the 2 MSBs are set to logic 1 by the device; all higher codes are truncated. The minimum level can be chosen between the code words 000h (00h programmed) and 0FFh (FFh programmed), the 2 MSBs are set to logic 0 by the device; all lower codes are truncated. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 34 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 9.2.14 Output formatter register Table 43. OF_CTRL register (address E5h) bit description Legend: * = default value Bit 7 Symbol OUT Access Value Description W output control: sets the outputs (VPA[11:0], VPB[11:0], VPC[11:0], VCLK, HS, VS, CS, HREF, VREF, FREF, DE, OR_R, OR_B, OR_G, CTL0 to CTL3, PL) 0* 1 6 VPL W 0 1* 5 4 BLC W W 0* 1 3 TRC W 0* outputs active outputs high-impedance video ports LOW forces the unused video port outputs to high-impedance forces the unused video port outputs to LOW not used blanking codes inserts the blanking codes removes the blanking codes timing reference codes inserts the timing reference codes; the signals HREF and VREF must be programmed into the VHREF timing generator to insert the timing reference codes; timing reference codes are inserted in all video port streams and are present during the vertical blanking; see Table 44 removes the timing reference codes for test; must be set to logic 0 for proper operation formatter selection 00 01 10* 11 [1] [2] [3] 1 2 W 0* 1 and 0 FOR_SEL[1:0] W 4 : 4 : 4 format[1] 4 : 2 : 2 semi-planar format[2] 4 : 2 : 2 ITU-R BT.656 format[3] undefined In 4 : 4 : 4, the video is output on three video ports, one per color. In 4 : 2 : 2 semi-planar, the video is output on two video ports, one for luminance (Y) and one for chrominance (CB and CR alternately). In 4 : 2 : 2 ITU-R BT.656, the video is output on one video port (CB-Y-CR-Y sequence). Table 44. Codeword 3FFh 000h 000h SAV/EAV[1] [1] Timing reference codes A9 1 0 0 1 A8 1 0 0 F A7 1 0 0 V A6 1 0 0 H A5 1 0 0 P3 A4 1 0 0 P2 A3 1 0 0 P1 A2 1 0 0 P0 A1 1 0 0 0 A0 1 0 0 0 F = 0 during field 1; F = 1 during field 2; V = 1 during field blanking; V = 0 elsewhere; H = 0 in SAV, H = 1 in EAV and P0 to P3 are protection bits. TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 35 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 9.2.15 Sync output selection registers Table 45. CSVSHS_SEL register (address E8h) bit description Legend: * = default value Bit 7 to 5 Symbol Access Value Description composite sync selection: selects the signal outputs on pin CS 000* 001 xxx 4 to 3 VS_SEL[1:0] W 00* 01 10 11 2 to 0 HS_SEL[2:0] W 000* 001 010 011 100 101 110 111 composite signal from the SDRS combination of HS and VS for test vertical sync selection: selects the signal outputs on pin VS vertical sync from the SDRS vertical sync from the VHREF timing generator undefined undefined horizontal sync selection: selects the signal outputs on HS pin horizontal sync from the PLL output for test horizontal sync from the SDRS horizontal sync from the HDMI receiver HS signal generated by the VHREF timing generator undefined undefined undefined CS_SEL[2:0] W 9.2.16 Output polarity control register Table 46. POL_CTRL register (address E9h) bit description Legend: * = default value Bit 5 Symbol CS_POL Access Value Description W W 0* 1 4 HS_POL W 0* 1 3 VS_POL W 0* 1 2 FREF_POL W 0* 1 not used composite sync polarity: pin CS; composite sync signal does not toggle; positive signal toggles; negative signal horizontal sync polarity: pin HS; horizontal sync signal does not toggle; positive signal toggles; negative signal vertical sync polarity: pin VS; vertical sync signal does not toggle; positive signal toggles; negative signal field reference polarity: pin FREF; field reference signal does not toggle; positive signal toggles; negative signal 7 to 6 - TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 36 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 46. POL_CTRL register (address E9h) bit description ...continued Legend: * = default value Bit 1 Symbol Access Value Description horizontal reference polarity: pin HREF; horizontal reference signal 0* 1 0 VREF_POL W 0* 1 does not toggle; positive signal toggles; negative signal vertical reference polarity: pin VREF; vertical reference signal does not toggle; positive signal toggles; negative signal HREF_POL W 9.2.17 Video ports control register Table 47. OUTPUT_CTRL register (address EAh) bit description Legend: * = default value Bit Symbol Access Value Description W 10* 01* 00* not used video port C selection: select the data stream to be output on video port C; see Table 48 video port B selection: select the data stream to be output on video port B; see Table 48 video port A selection: select the data stream to be output on video port A; see Table 48 7 and 6 - 5 and 4 VPC_SEL[1:0] W 3 and 2 VPB_SEL[1:0] W 1 and 0 VPA_SEL[1:0] W Table 48. Data stream selection 4 : 4 : 4 RGB R B G high-impedance 4 : 4 : 4 YCBCR V U Y high-impedance 4 : 2 : 2 YCBCR semi-planar CB-CR not used (VPL) Y high-impedance 4 : 2 : 2 YCBCR ITU-R BT.656 CB-Y-CR-Y not used (VPL) not used (VPL) high-impedance VPx_SEL[1:0] 00 01 10 11 9.2.18 Data enable signal control register Table 49. DE_CTRL register (address EBh) bit description Legend: * = default value Bit 7 Symbol HR_PXQ Access Value Description W 0* 1 6 HR_SEL W 0* 1 horizontal reference pixel qualification: HREF signals the XAV-codes not signaled signaled horizontal reference selection: HREF dependence of VREF independent of VREF logic combination (HREF AND VREF) TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 37 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 49. DE_CTRL register (address EBh) bit description ...continued Legend: * = default value Bit 5 Symbol DE_PXQ Access Value Description W 0* 1 4 DE_POL W 0* 1* 3 to 0 data enable pixel qualification: expands or not the data enable signal to include the SAV/EAV codes does not expand expands data enable polarity: selects the signal outputs on pin DE does not toggle toggles not used apx : active panel - 3FF 000 000 SAV apx1 apx2 apxn-1 apxn 3FF 000 000 EAV - HREF_PXQ = 0 HREF HREF_PXQ = 1 DE_PXQ = 0 DE DE_PXQ = 1 001aaa509 Fig 8. Pixel qualification 9.2.19 Software reset registers Table 50. RESET_CNTRL register (address F1h) bit description Legend: * = default value Bit 4 Symbol Access Value W Description not used reset manual: activates the manual software reset for the digital clamp loop, the video gain and the digital processing 0* 1 3 RST_AVI W automatic mode; the reset is enabled when no activity is detected manual mode software reset analog video interface: resets the digital clamp loop and the registers depending on the CLKPIX clock in manual mode 0* 1 2 to 0 W -* normal operation reset mode not used 7 to 5 - RST_MAN W TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 38 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Registers that are reset to the default value are as follows: * * * * * * Video gain registers (address 20h to 3Eh) Color space conversion registers (address 80h to 9Eh) VHREF timing registers (address A0h to DFh) Prefiltering registers (address E0h) Output formatter registers (address E1h to E5h) Output register (address E9h to EBh) Register CSVBHS_SEL (address E8h) is not reset. 9.2.20 Power-down control registers Table 51. PD_AVI_CTRL0 register (address F4h) bit description Legend: * = default value Bit 4 Symbol PD_SOG2 Access Value Description W W 0* 1 3 PD_SOG1 W 0* 1 2 PD_DLL W 0* 1 1 PD_PLL W 0* 1 0 PD_AVI W 0* 1 0* not used power-down SOG2: enables the power-down of the slicer of input 2 normal operation Power-down mode power-down SOG1: enables the power-down of the slicer of input 1 normal operation Power-down mode power-down DLL: enables the power-down of the delay-locked loop normal operation Power-down mode power-down PLL: enables the power-down of the PLL normal operation Power-down mode power-down AVI: enables the power-down of the analog video interface normal operation Power-down mode 7 to 5 - Table 52. PD_AVI_CTRL1 register (address F5h) bit description Legend: * = default value Bit 2 Symbol Access Value Description W not used power-down B/PB ADC: enables the power-down of the blue channel (B/PB) ADC 0* 1 normal operation Power-down mode 7 to 3 - PD_ADC_BU W TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 39 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 52. PD_AVI_CTRL1 register (address F5h) bit description ...continued Legend: * = default value Bit 1 Symbol Access Value Description power-down G/Y ADC: enables the power-down of the green channel (G/Y) ADC 0* 1 0 PD_ADC_RV W 0* 1 normal operation Power-down mode power-down R/PR ADC: enables the power-down of the red channel (R/PR) ADC normal operation Power-down mode PD_ADC_GY W Table 53. FVH_SEL register (address F6h) bit description Legend: * = default value Bit 0 Symbol FVH_SEL Access Value Description W W 0 1* not used timing signals: defiines the output on pins 15, 16 and 17 HREF; VREF; FREF HS; VS; CS 7 to 1 - Table 54. LSB_OUT_SEL register (address F7h) bit description Legend: * = default value Bit Symbol Access Value Description W 00h* 81h 82h LSB signal: selects the signal on the LSB pin of each digital port (pins 75, 88 and 100). VPA[0]; VPB[0]; VPC[0] HREF; VREF; FREF ORGY; ORBU; ORRV 7 to 0 LSB_SEL Table 55. ORX_SEL register (address F9h) bit description[1][2] Legend: * = default value Bit 7 and 6 Symbol Access Value Description W 00 01 10 Orr signals: selects the signal applied on internal Orr (over range channel red) signal or_rv_agc: an ADC output underflow or overflow of the range defined by the registers 22h and 23h or_rv_datapath: an ADC output underflow or overflow of the range defined by the registers E1h and E2h gain: monitors the gain calibration signal. see Figure 12 and Figure 13 TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 40 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 55. ORX_SEL register (address F9h) bit description[1][2] ...continued Legend: * = default value Bit 5 to 3 Symbol Access Value Description W x00 x01 x10 2 to 0 W x00 x01 Org signals: selects the signal applied on internal Org (over range channel green) signal or_gy_agc: an ADC output underflow or overflow of the range defined by the registers 36h and 37h or_gy_datapath: an ADC output underflow or overflow of the range defined by the registers E3h and E4h clamp: monitors the clamp calibration signal. see Figure 12 and Figure 13 Orb signals: selects the signal applied on internal Orb (over range channel blue) signal or_bu_agc: an ADC output underflow or overflow of the range defined by the registers 2Ch and 2Dh or_bu_datapath: an ADC output underflow or overflow of the range defined by the registers E1h and E2h [1] [2] Defines the internal signals on ORGY, ORBU and ORRV. The signals are not effected by changing the position of the digital output ports with register EAh. 10. Limiting values Table 56. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDDx(3V3) VDDx(1V8) VDD VI IO Tstg Tamb Tj Vesd Parameter supply voltage on all 3.3 V pins supply voltage on all 1.8 V pins supply voltage difference input voltage 5 V tolerant output current storage temperature ambient temperature junction temperature electrostatic discharge voltage human body model Conditions Min -0.5 -0.5 -0.5 -0.5 -0.5 -40 0 2000 Max +4.6 +2.5 +0.5 +6.0 35 +125 70 150 Unit V V V V mA C C C V VDD + 0.5 V 11. Thermal characteristics Table 57. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions in free air Typ 29.7 Unit K/W TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 41 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 12. Characteristics Table 58. Characteristics VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.15 V to 3.45 V; VDDA(1V8) = VDDC(1V8) = 1.75 V to 1.85 V; Tamb = 0 C to 70 C; typical values measured at VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.3 V, VDDA(1V8) = VDDC(1V8) = 1.8 V and Tamb = 25 C; unless otherwise specified. Symbol Supplies VDDA(3V3) VDDA(1V8) VDDI(3V3) VDDC(1V8) VDDO(3V3) IDDA(1V8) IDDA(3V3) IDDI(3V3) IDDO(3V3) IDDC(1V8) VDD(1V8-1V8) VDD(3V3-3V3) VDD(3V3-1V8) P Ppd analog supply voltage (3.3 V) analog supply voltage (1.8 V) input supply voltage (3.3 V) core supply voltage (1.8 V) output supply voltage (3.3 V) analog supply current (1.8 V) analog supply current (3.3 V) input supply current (3.3 V) output supply current (3.3 V) core supply current (1.8 V) supply voltage difference between two start-up and established 1.8 V supplies conditions supply voltage difference between two start-up and established 3.3 V supplies conditions supply voltage difference between one start-up and established 3.3 V supply and one 1.8 V supply conditions power dissipation power dissipation in power-down mode analog interface; fs = 170 MHz and activity detection power-up channel plus multiplexer minimum gain; code = 0 maximum gain; code = 4095 G/(GxT) Vi(p-p) Ci MG(CTC)(rms) relative gain variation over temperature peak-to-peak input voltage input capacitance channel-to-channel gain matching (RMS value) delay time rise time sync pulse 10 % to 90 %; bi-level or tri-level horizontal sync pulse; 4 clock interval 90 % to 10 %; bi-level or tri-level horizontal sync pulse; 4 clock interval black-to-white I2C-bus 3.15 1.75 3.15 1.75 3.15 3.3 1.8 3.3 1.8 3.3 151 33 48 48 96 3.45 1.85 3.45 1.85 3.45 160 40 80 115 V V V V V mA mA mA mA mA Parameter Conditions Min Typ Max Unit -0.15 -0.3 1.35 750 47 +0.15 V +0.3 1.65 945 74 V V mW mW Analog inputs (R1, R2, G1, G2, B1, B2) B-3dB G -3 dB bandwidth gain 350 0.65 380 0 5 0.7 0.3 2.5 400 0.9 6.7 MHz dB dB V pF % 0.003 0.008 ppm/C Sync on green/luminance inputs (SOG1, SOG2), see Figure 9 td tr 108 320 ns ns tf fall time - 320 - ns TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 42 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 58. Characteristics ...continued VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.15 V to 3.45 V; VDDA(1V8) = VDDC(1V8) = 1.75 V to 1.85 V; Tamb = 0 C to 70 C; typical values measured at VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.3 V, VDDA(1V8) = VDDC(1V8) = 1.8 V and Tamb = 25 C; unless otherwise specified. Symbol Clamps NCL MCL(CTC) tjit(PLL)(p-p) Npix fclk(ref) fclk(o)(PLL) step fs INL DNL S/N clamping accuracy channel-to-channel clamp matching peak-to-peak PLL jitter time number of pixels reference clock frequency PLL output clock frequency phase difference phase shift step sampling frequency integral non-linearity differential non-linearity signal-to-noise ratio standard at 170 MHz manual controls; Tamb = 25 C maximum fs = 170 MHz fs = 170 MHz without harmonics; fi = 1 MHz; sinewave input; fs = 170 MHz fs = 170 MHz; during 3 s pixels per line [1] Parameter Conditions Min 256 15 12.5 170 - Typ 0.1 1.14 0.16 2.7 Max 1.8 1.20 1.60 4095 65 170 4.2 Unit LSB LSB ns kHz MHz step deg MHz LSB LSB dB Phase-locked loop (PLL) of analog video part 11.25 0.5 0.7 45 - ADCs (+ AGCs) Clock timing input (CKEXT) fclk(max) clk fclk(max) maximum clock frequency clock duty cycle maximum clock frequency analog inputs; RGB/YUV/YUV 4:2:2 semi-planar/ITU-R BT.656 170 170 50 MHz % MHz Clock timing output (VCLK) clk td(pipe) clock duty cycle pipeline delay time horizontal sync pulse delay; in phase with data outputs referenced to VCLK 45 - 50 15.4 55 - % clock interval ns ns ns V V A ns ns Horizontal timing output (HS) Timing output (VPA0 to VPA7, VPB0 to VPB7, VPC0 to VPC7), see Figure 10 td(s) tsu(Q) th(Q) VIL VIH Ii tr tf sampling delay time data output set-up time data output hold time LOW-level input voltage HIGH-level input voltage input current rise time fall time VI = 0 V or VI = VDD 20 % to 80 % 80 % to 20 % 2 2.0 3.2 4.5 0.8 5.5 5 3 3 TTL digital inputs (HCSYNC1, HCSYNC2, VSYNC1, VSYNC2 and CKEXT) TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 43 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 58. Characteristics ...continued VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.15 V to 3.45 V; VDDA(1V8) = VDDC(1V8) = 1.75 V to 1.85 V; Tamb = 0 C to 70 C; typical values measured at VDDA(3V3) = VDDI(3V3) = VDDO(3V3) = 3.3 V, VDDA(1V8) = VDDC(1V8) = 1.8 V and Tamb = 25 C; unless otherwise specified. Symbol VOL VOH Parameter LOW-level output voltage HIGH-level output voltage Conditions VDDO = 3.0 V; IOL = 2 mA; CL = 10 pF VDDO = 3.0 V; IOH = -2 mA; CL = 10 pF Min 2.4 Typ Max 0.4 Unit V V LV-TTL digital outputs (VPA0 to VPA7, VPB0 to VPB7, VPC0 to VPC7, VCLK, DE, HS, VS, CS, HREF, VREF, FREF) I2C-bus (fast-mode, 5 V tolerant; SCL and SDA) fSCL Cb [1] SCL clock frequency capacitive load for each bus line - - 400 400 kHz pF 1 6 = 6 x 0,02UI x ---- Where UI = Unit Interval fs SOG/Y tf 90% 10% tr mgw806 Fig 9. Horizontal sync pulse on SOG/Y VCLK 50 % tsu(Q) VPA[11:0] VPB[11:0] VPC[11:0] 2.4 V 0.4 V th(Q) 001aaf542 Fig 10. Output timing TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 44 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Table 59. Signal VPA0 VPA1 VPA2 VPA3 VPA4 VPA5 VPA6 VPA7 VPB0 VPB1 VPB2 VPB3 VPB4 VPB5 VPB6 VPB7 VPC0 VPC1 VPC2 VPC3 VPC4 VPC5 VPC6 VPC7 [1] Output formats (register OUTPUT_CTRL = EAh)[1] RGB R0 R1 R2 R3 R4 R5 R6 R7 B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 YUV V0 V1 V2 V3 V4 V5 V6 V7 U0 U1 U2 U3 U4 U5 U6 U7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 YUV 4 : 2 : 2 (semi-planar) U0 U1 U2 U3 U4 U5 U6 U7 Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y07 V0 V1 V2 V3 V4 V5 V6 V7 Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 YUV 4 : 2 : 2 (ITU-R BT.656) U0 U1 U2 U3 U4 U5 U6 U7 Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y00 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L V0 V1 V2 V3 V4 V5 V6 V7 Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z/L Z: high-impedance; L: LOW level. VPA0 to VPA7 R0 R1 R2 R3 R4 Rn - 1 Rn VPB0 to VPB7 B0 B1 B2 B3 B4 Bn - 1 Bn VPC0 to VPC7 G0 G1 G2 G3 G4 Gn - 1 Gn VCLK 001aag615 Fig 11. RGB 4 : 4 : 4 format data timing TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 45 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV VPA0 to VPA7 V0 V1 V2 V3 V4 Vn - 1 Vn VPB0 to VPB7 U0 U1 U2 U3 U4 Un - 1 Un VPC0 to VPC7 Y0 Y1 Y2 Y3 Y4 Yn - 1 Yn VCLK 001aag616 Fig 12. YUV 4 : 4 : 4 format data timing VPA0 to VPA7 U0 V0 U2 V2 U4 U2n V2n VPB0 to VPB7 VPC0 to VPC7 Y0 Y1 Y2 Y3 Y4 Y2n Y2n + 1 VCLK HREF start of active line end of active line 001aag617 Fig 13. YUV 4 : 2 : 2 semi-planar format data timing VI PL, MR, Dn input GND tPLH VOH TCU, TCD output VOL 001aag418 VM tPHL VM (1) With SAV/EAV timing codes (2) Without SAV/EAV timing codes Fig 14. YUV 4 : 2 : 2 ITU-R BT.656 format data timing with blanking code TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 46 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Y 621 HREF 622 623 624 625 1 2 3 4 5 6 23 24 25 VREF V=0 FREF 2nd field F=1 1st field F=0 V=1 V=0 Y 310 HREF 311 312 313 314 315 316 317 318 319 335 336 VREF V=1 FREF 2nd field F=1 mgw813 Fig 15. 576i timing in automatic mode TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 47 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV Y 521 HREF 522 523 524 525 1 2 3 4 5 17 18 VREF V=1 FREF 1st field F=0 Y 258 HREF 259 260 261 262 263 264 265 266 267 268 279 280 281 VREF V=0 FREF 1st field F=0 2nd field F=1 001aah018 V=1 V=0 Fig 16. 480i timing in automatic mode TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 48 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 13. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X L Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0 16.25 16.25 15.75 15.75 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-02-01 03-02-20 Fig 17. Package outline SOT407-1 (LQFP100) TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 49 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 14. Soldering An in-depth account of reflow soldering can be found in Application Note AN10365 "Surface mount reflow soldering description". 15. Revision history Table 60. Revision history Release date 20080317 Data sheet status Product data sheet Change notice Supersedes Document ID TDA9955HL_1 TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 50 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com TDA9955HL_1 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 -- 17 March 2008 51 of 52 NXP Semiconductors TDA9955HL Triple 8-bit analog-to-digital video converter for HDTV 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 9 9.1 9.2 9.2.1 9.2.2 9.2.3 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 7 Analog multiplexers. . . . . . . . . . . . . . . . . . . . . . 7 R/PR, B/PB and G/Y channels. . . . . . . . . . . . . . 7 Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Automatic Gain Control (AGC) . . . . . . . . . . . . . 7 Sync slicing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Activity detection. . . . . . . . . . . . . . . . . . . . . . . . 8 Sync detection and selection . . . . . . . . . . . . . . 8 Sync Detection Recognition and Separation . . 8 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . 8 Sync multiplexers . . . . . . . . . . . . . . . . . . . . . . . 8 Color conversion . . . . . . . . . . . . . . . . . . . . . . . . 9 4 : 2 : 2 downsample filters . . . . . . . . . . . . . . . . 9 Range control . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 : 2 : 2 formatter . . . . . . . . . . . . . . . . . . . . . . . 9 Video port selection . . . . . . . . . . . . . . . . . . . . 10 Output buffers . . . . . . . . . . . . . . . . . . . . . . . . . 10 VHREF timing generator. . . . . . . . . . . . . . . . . 10 I2C-bus serial interface . . . . . . . . . . . . . . . . . . 10 Power management . . . . . . . . . . . . . . . . . . . . 10 Sync timing measurement . . . . . . . . . . . . . . . 10 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 10 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 10 Registers definitions . . . . . . . . . . . . . . . . . . . . 11 Version register. . . . . . . . . . . . . . . . . . . . . . . . 17 Input selection register . . . . . . . . . . . . . . . . . . 17 Sync detection recognition and separation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9.2.4 PLL registers. . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.2.5 Pixel clocks generation registers . . . . . . . . . . 19 9.2.6 Pixel clocks generation registers . . . . . . . . . . 21 9.2.7 Clamp levels registers. . . . . . . . . . . . . . . . . . . 22 9.2.8 Video gain registers (GAIN_RV, GAIN_BU, GAIN_GY). . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2.9 Sync timing measurement registers . . . . . . . . 23 9.2.10 Color space conversion registers . . . . . . . . . . 24 9.2.11 9.2.12 9.2.13 9.2.14 9.2.15 9.2.16 9.2.17 9.2.18 9.2.19 9.2.20 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 Line and pixel counters . . . . . . . . . . . . . . . . . Prefiltering register (PRE_FILTERS) . . . . . . . Range control registers . . . . . . . . . . . . . . . . . Output formatter register . . . . . . . . . . . . . . . . Sync output selection registers . . . . . . . . . . . Output polarity control register . . . . . . . . . . . . Video ports control register . . . . . . . . . . . . . . Data enable signal control register. . . . . . . . . Software reset registers . . . . . . . . . . . . . . . . . Power-down control registers . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Thermal characteristics . . . . . . . . . . . . . . . . . Characteristics . . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 34 34 35 36 36 37 37 38 39 41 41 42 49 50 50 51 51 51 51 51 51 52 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 March 2008 Document identifier: TDA9955HL_1 |
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