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ispLSI 1032E
(R)
In-System Programmable High Density PLD Functional Block Diagram
Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 A0
DQ
Features
* HIGH DENSITY PROGRAMMABLE LOGIC -- 6000 PLD Gates -- 64 I/O Pins, Eight Dedicated Inputs -- 192 Registers -- High Speed Global Interconnect
C7
Output Routing Pool
A2 A3 A4 A5 A6 A7
-- Small Logic Block Size for Random Logic * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 125 MHz Maximum Operating Frequency --
Logic Array
tpd = 7.5 ns Propagation Delay
Global Routing Pool (GRP)
B0 B1 B2 B3 B4 B5 B6 B7
D
-- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- In-System Programmable (ISPTM) 5V Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality
EW
Output Routing Pool
0139A(A1)-isp
-- Reprogram Soldered Devices for Faster Prototyping
-- Four Dedicated Clock Input Pins
03
-- Enhanced Pin Locking Capability
2E
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs
The ispLSI 1032E is a High Density Programmable Logic Device containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1032E device offers 5V non-volatile in-system programmability of the logic, as well as the interconnects to provide truly reconfigurable systems. A functional superset of the ispLSI 1032 architecture, the ispLSI 1032E device adds two new global output enable pins. The basic unit of logic on the ispLSI 1032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 1032E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
-- Flexible Pin Placement
-- Optimized Global Routing Pool Provides Global Interconnectivity
U
Copyright (c) 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SE
is
-- Lead-Free Package Options
pL S
-- Programmable Output Slew Rate Control to Minimize Switching Noise
I1
-- Synchronous and Asynchronous Clocks
A
FO
R
N
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1032e_09
1
ES IG N
DQ
-- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
C5 C4 C3 C2 C1 C0
DQ
GLB
DQ
CLK
August 2006
Output Routing Pool
A1
C6
S
Specifications ispLSI 1032E
Functional Block Diagram
Figure 1. ispLSI 1032E Functional Block Diagram
I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 7 IN 6
RESET
Input Bus
D7
D6
D5
D4
D3
D2
D1
D0
C7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 SDI/IN 0 MODE/IN 1
A0 A1
Output Routing Pool (ORP)
C6
Output Routing Pool (ORP)
A3 A4 A5 A6 A7
EW
Global Routing Pool (GRP)
C4 C3 C2 C1 C0
lnput Bus
lnput Bus
A2
D
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
C5
N
B0
B1
B2
B3
FO
B4
B5
R
B6
B7
Clock Distribution Network
Output Routing Pool (ORP)
2E
ispEN
SDO/IN 2 SCLK/IN 3
A
Megablock
Input Bus
I/O 16 I/O 17 I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI 1032E device contains four Megablocks.
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The device also has 64 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise.
03
LS
The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1032E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (C0 on the ispLSI 1032E device). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
I1
2
I/O 28 I/O 29 I/O 30 I/O 31
Y0 Y1 Y2 Y3
ES IG N
GOE 1/IN 5 GOE 0/IN 4 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32
Generic Logic Blocks (GLBs)
Output Routing Pool (ORP)
S
Specifications ispLSI 1032E
Absolute Maximum Ratings 1
Supply Voltage Vcc ...................................-0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
EW
D
MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1 UNITS V V V V
Table 2-0005/1032E
VCC VIL VIH
TA = 0C to + 70C
2E
A
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER
FO
R
TA = -40C to + 85C
N
TYPICAL 8 15
UNITS pf pf
C2
03
C1
Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) Y0 Clock Capacitance
I1
PARAMETER Erase/Reprogram Cycles
LS
Data Retention Specifications
MINIMUM 20 10000 MAXIMUM - - UNITS Years Cycles
Table 2-0008/1032E
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Data Retention
3
ES IG N
TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1032E
S
Specifications ispLSI 1032E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -125 Others 1.5V 1.5V See Figure 2
Table 2-0003/1032E
Figure 2. Test Load
2 ns 3 ns
+ 5V R1 Device Output
ES IG N
R2 CL*
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
EW
D
C
DC Electrical Characteristics
SYMBOL
A
Over Recommended Operating Conditions
FO
Table 2-0004/1032E
R
N
2E
PARAMETER Output Low Voltage Output High Voltage
CONDITION
MIN. - 2.4 - - - - -
TYP. - - - - - - - 190 190
3
MAX. UNITS 0.4 - -10 10 -150 -150 -200 - - V V A A A A mA mA mA
I/O Active Pull-Up Current Output Short Circuit Current
LS
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fCLOCK = 1 MHz Commercial Industrial
Input or I/O Low Leakage Current
Input or I/O High Leakage Current ispEN Input Low Leakage Current
I1
03
Operating Power Supply Current
is p
- -
Table 2-0007/1032E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC .
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SE
4
S
Test Point
0213a
Specifications ispLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
4
#
2
DESCRIPTION
1
-125 - - 125
1 tsu2 + tco1
-100 - - 100 71.0 125 7.0 - 10.0 12.5 - -
MIN. MAX. MIN. MAX. 7.5 10.0 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
03
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
A A A - - - A - - - - A - B C B C - - - -
1 2 3 4 5 6 7 8 9
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback Clock Frequency, Max. Toggle
3
Clock Frequency with External Feedback (
)
91.0 167 5.0 -
( twh 1+ tw1 )
GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
D
6.0 - 0.0 - 5.0 - - - - 3.0 3.0 3.0 0.0
0.0
EW
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
N
R
FO
A
18 External Synchronous Clock Pulse Duration, High
2E
19 External Synchronous Clock Pulse Duration, Low 20 21 I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3)
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LS
I1
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
5
ES IG N
- - 5.0 - - 6.0 - 10.0 - 12.0 12.0 7.0 7.0 - - - - 6.0 - 0.0 8.0 - 0.0 - 6.5 - - - - 4.0 4.0 3.5 0.0 - 7.0 - 13.5 - 15.0 15.0 9.0 9.0 - - - -
Table 2-0030A/1032E
S
Specifications ispLSI 1032E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST COND.
4
#
2
DESCRIPTION
1
-90 - - 90.0
1 tsu2 + tco1
-80 - - 80.0 61.0 111 8.5 - 12.0 15.0 - - - - - -
-70 15.0 17.5 - - -
MIN. MAX. MIN. MAX. MIN. MAX. 10.0 12.5 - - - - 6.0 - - 7.0 - - 15.0 15.0 9.0 9.0 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
03
tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
A A A - - - A - - - - A - B C B C - - - -
1 2 3 4 5 6 7 8 9
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback 3 Clock Frequency with External Feedback ( Clock Frequency, Max. Toggle
)
69.0 125 7.5 - 0.0 8.5 - - - - - - 4.0 4.0 0.0 6.5
(
1 twh + tw1
)
GLB Reg. Setup Time before Clock,4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
D
0.0 - 0.0 - 8.0 - - - - 4.5 4.5 3.5 0.0 10.0
EW
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
N
13.5
R
FO
A
18 External Synchronous Clock Pulse Duration, High
2E
19 External Synchronous Clock Pulse Duration, Low 20 21
I/O Reg. Setup Time before Ext. Sync Clock (Y2, Y3) 3.5 I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) 0.0
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LS
I1
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
6
ES IG N
70.0 100 9.0 - 56.0 - 6.5 - - 7.5 - 14.0 - 16.5 16.5 10.0 10.0 - - - - 7.0 - - 8.0 - 15.0 - 18.0 18.0 12.0 12.0 - - - - 0.0 11.0 - 0.0 - 10.0 - - - - 5.0 5.0 4.0 0.0
Table 2-0030B/1032E
S
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM. #
2
DESCRIPTION
-125
-100
MIN. MAX. MIN. MAX. - - 3.0 0.0 - - - 0.3 1.9 - - - - 3.5 0.0 - - -
UNITS
Inputs
24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 32 GLB Loads 34 4 Prod.Term Bypass Path Delay (Combinatorial) 35 4 Prod. Term Bypass Path Delay (Registered) 36 1 Prod.Term/XOR Path Delay 37 20 Prod. Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 39 GLB Register Bypass Delay
ES IG N
- - 4.6 4.6 2.3 5.0 5.0 2.7 1.8 2.0 2.3 2.8 3.8 3.9 4.0 3.6 5.0 5.0 0.4 - - 2.3 4.9 3.9 5.4 4.0 1.0 0.0 - - - - - - - - - - - 0.5 5.8 - - - - 3.5 - - 1.9 2.4 2.4 3.0 4.2 5.3 5.3 4.6 5.8 6.3 1.0 - - 2.5 6.2 4.5 7.2 4.7 1.0 0.0
tiobp tiolat tiosu tioh tioco tior tdin
GRP
23 I/O Latch Delay
2.3
tgrp1 tgrp4 tgrp8 tgrp16 tgrp32
GLB
D EW
- - - - - - - - - - - 0.1 4.5 - - - - 2.9 - -
N
46 GLB Prod. Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay
is p
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
FO
R
A
2E
41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Prod.Term Reset to Register Delay 45 GLB Prod. Term Output Enable to I/O Cell Delay
03
40 GLB Register Setup Time before Clock
I1
LS
SE
torp torpbp
U
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/1032E
7
S
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
22 I/O Register Bypass
0.3
ns
Specifications ispLSI 1032E
Internal Timing Parameters1
-90 -80 -70
PARAM. #
2
DESCRIPTION
MIN. MAX. MIN. MAX. MIN. MAX. - - 3.5 0.0 - - - - 0.3 2.3 - - 5.0 5.0 2.6 2.1 - - 3.5 0.0 - - - 0.3 2.7 - - - - 4.0 0.0 - - - 0.3 3.3 - -
UNITS
Inputs
GRP
GLB
is p
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
FO
R
tgrp1 tgrp4 tgrp8 tgrp16 tgrp32
30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 33 GRP Delay, 32 GLB Loads 34 4 Prod.Term Bypass Path Delay (Combinatorial) 35 4 Prod. Term Bypass Path Delay (Registered)
EW
29 GRP Delay, 1 GLB Load
D
- - - - - - - - - - - 0.5 7.9 - - - - 4.5 - -
tiobp tiolat tiosu tioh tioco tior tdin
22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay
ES IG N
5.4 5.4 2.8 6.1 6.0 2.8 2.2 2.5 2.8 3.5 4.8 7.1 6.7 6.6 7.8 8.2 1.3 - - 2.9 6.4 5.5 8.0 5.8 1.0 0.0 - - - - - - - - - - - 0.5 8.8 - - - - 4.8 - - 2.5 2.5 3.2 4.0 5.6 8.8 7.2 8.3 8.7 9.2 1.6 - - 2.9 6.8 5.8 9.0 6.2 1.0 0.0
- -
2.3 2.6
N
- - - - - - - -
3.2 4.4 5.7 6.1 5.6 6.8 7.1 0.4 - - 2.9 6.3 5.1 7.1 5.3 1.0 0.0
37 20 Prod. Term/XOR Path Delay 38 XOR Adjacent Path Delay
3
A
36 1 Prod.Term/XOR Path Delay
2E
39 GLB Register Bypass Delay
03
40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock
0.2 6.8 - - - - 4.1 - -
42 GLB Register Clock to Output Delay 44 GLB Prod.Term Reset to Register Delay 45 GLB Prod. Term Output Enable to I/O Cell Delay 46 GLB Prod. Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay
I1
LS
43 GLB Register Reset to Output Delay
SE
torp torpbp
U
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/1032E
8
S
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM. # DESCRIPTION -125 -100 UNITS
MIN. MAX. MIN. MAX. - - - - 1.3 9.9 4.3 4.3 2.7 - - - - 2.0 5.1 5.1 3.9
Outputs
51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global OE 54 Clk Delay, Y0 to Global GLB Clk Line (Ref. clk) 55 Clk Delay, Y1 or Y2 to Global GLB Clk Line 56 Clk Delay, Clock GLB to Global GLB Clk Line 57 Clk Delay, Y2 or Y3 to I/O Cell Global Clk Line 58 Clk Delay, Clk GLB to I/O Cell Global Clk Line 59 Global Reset to GLB and I/O Registers
ES IG N
- 1.4 1.4 1.8 0.0 1.8 2.8 1.5 1.5 0.8 0.0 0.8 - 1.5 1.5 1.8 0.0 1.8 4.3
tob tsl toen todis tgoe
Clocks
50 Output Buffer Delay, Slew Limited Adder
10.0
-
EW
tgy0 tgy1/2 tgcp tioy2/3 tiocp tgr
1.4 1.4 0.8 0.0 0.8 -
D N R
9
Global Reset
1. Internal Timing Parameters are not tested and are for reference only.
Table 2-0037A/1032E
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LS
I1
03
2E
A
FO
S
ns ns ns ns ns ns ns ns ns ns
49 Output Buffer Delay
ns
Specifications ispLSI 1032E
Internal Timing Parameters1
PARAM. # DESCRIPTION -90 -80 -70 UNITS
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - 1.4 2.4 0.8 0.0 0.8 - 1.7 10.0 5.3 5.3 3.7 1.4 2.9 1.8 0.0 1.8 - - - - 2.1 10.0 5.7 5.7 4.3 - - - - - 2.6 6.2 6.2 5.8
Outputs
51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global OE 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 56 Clock Delay, Clock GLB to Global GLB Clock Line 57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 59 Global Reset to GLB and I/O Registers
ES IG N
1.5 3.1 1.8 0.0 1.8 4.5 1.5 1.5 0.8 0.0 0.8 - 1.5 1.5 1.8 0.0 1.8 4.6
tob tsl toen todis tgoe
Clocks
50 Output Buffer Delay, Slew Limited Adder
10.0
-
EW
tgy0 tgy1/2 tgcp tioy2/3 tiocp tgr
1.5 2.6 0.8
D
0.0 0.8 -
N
Global Reset
1. Internal Timing Parameters are not tested and are for reference only.
4.5
R
Table 2-0037B/1032E
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is p
LS
I1
03
2E
A
FO
10
S
ns ns ns ns ns ns ns ns ns ns
49 Output Buffer Delay
ns
Specifications ispLSI 1032E
ispLSI 1032E Timing Model
I/O Cell GRP Feedback Ded. In #34 GRP4 #30 GRP Loading Delay #29, 31 - 33 Comb 4 PT Bypass GLB Reg Bypass #39 GLB Reg Delay D RST Reset #59 #40 - 43 Q ORP Bypass #48 ORP Delay #47 GLB ORP I/O Cell
#28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27
#35 20 PT XOR Delays #36 - 38
#59
D R N
Table 2-0042a/1032E
Clock Distribution Y1,2,3 #55 - 58
Control RE PTs OE #44 - 46 CK
Y0 GOE 0,1
#54 #53
Derivations of tsu, th and tco from the Product Term Clock 1
th
tco
Derivations of tsu, th and tco from the Clock GLB 1
SE
th
= = = 2.7 ns = = = = 5.5 ns =
U
tco
1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
is p
tsu
= = = 2.9 ns =
Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 2.0 + 5.0) + (0.1) - (1.4 + 2.3 + 0.8)
Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (1.4 + 2.3 + 1.8) + (4.5) - (0.3 + 2.0 + 5.0) Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
LS
= = = 10.9 ns =
Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
I1
03
= = = 3.5 ns =
Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 2.0 + 4.0) + (4.5) - (0.3 + 2.0 + 5.0)
2E
A
FO
tsu
= = = 2.2 ns =
Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 2.0 + 5.0) + (0.1) - (0.3 + 2.0 + 2.9)
11
EW
ES IG N
#51, 52
0491
S
I/O Pin (Input)
Reg 4 PT Bypass
#49, 50
I/O Pin (Output)
Specifications ispLSI 1032E
Maximum GRP Delay vs GLB Loads
6.0
ispLSI 1032E-70
GRP Delay (ns)
5.0 4.0
ispLSI 1032E-80 ispLSI 1032E-90/100 ispLSI 1032E-125
3.0 2.0
1.0
GLB Load
GRP/GLB/1032E
Figure 3. Typical Device Power Consumption vs fmax
300
2E
350
A
ICC (mA)
250 200 150
is p
LS
100
I1
03
0
20
40
FO
Power consumption in the ispLSI 1032E device depends on two primary factors: the speed at which the device is operating, and the number of product terms used. Figure
ispLSI 1032E
R
3 shows the relationship between power and operating speed.
80 fmax (MHz)
60
100
I CC can be estimated for the ispLSI 1032E using the following equation:
U
I CC (mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I CC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists. These values are for estimates only. Since the value of I CC is sensitive to operating conditions and the program in the device, the actual I CC should be verified.
SE
Notes: Configuration of eight 16-bit counters Typical current at 5V, 25C
N
Power Consumption
125
EW
1
4
8
16
32
D
0127/1032E
12
ES IG N
S
Specifications ispLSI 1032E
Pin Description
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 GOE 0/IN 43 GOE 1/IN 53
PLCC PIN NUMBERS
26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, 67 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18
TQFP PIN NUMBERS
17, 21, 29, 33, 40, 44, 48, 56, 67, 71, 79, 83, 90, 94, 98, 6, 66 18, 22, 30, 34, 41, 45, 53, 57, 68, 72, 80, 84, 91, 95, 3, 7, 19, 23, 31, 35, 42, 46, 54, 58, 69, 73, 81, 85, 92, 96, 4, 8,
DESCRIPTION
20, Input/Output Pins - These are the general purpose I/O pins used by the logic 28, array. 32, 36, 43, 47, 55, 59, 70, 78, 82, 86, 93, 97, 5, 9 This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin.
84
87
IN 6, IN 7 ispEN SDI/IN 02
2, 23
19
89, 14
10
Dedicated input pins to the device. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 is also used as one of the two control pins for the isp state machine. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high.
25
16
SDO/IN 22
44
39
I1
03
SCLK/IN 32
61
60
RESET Y0 Y1
24 20 66
15 11 65
LS
is p
Y2
63
62
Y3
62
61
SE
U
GND VCC NC1
1,
22, 43, 64
13, 38, 63, 88 12, 64 1, 26, 51, 76, 2, 27, 52, 77, 24, 49, 74, 99,
21, 65
2E
25, No connect. 50, 75, 100
Table 2-0002A/1032E
1. NC pins are not to be connected to any active signals, Vcc or GND. 2. Pins have dual function capability. 3. Pins have dual function capability which is software selectable.
A
MODE/IN 12
42
37
Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated input pin when ispEN is logic high.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. Ground (GND) Vcc
FO
13
R
N
EW
D
ES IG N
S
Specifications ispLSI 1032E
Pin Configurations
ispLSI 1032E 84-Pin PLCC Pinout Diagram
GOE 1/IN 52
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
GND
IN 6
11 10 9 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND ispEN RESET
1SDI/IN
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D EW N R
Top View
FO
ispLSI 1032E
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
2E
I/O 0
A
0
03
I1
is p
LS
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1
GND
2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
1MODE/IN
U
SE
1. Pins have dual function capability. 3. Pins have dual function capability which is software selectable.
0123-32-isp
14
1SDO/IN
I/O 24
I/O 7
I/O 8
I/O 9
ES IG N
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0/IN 42 Y1 VCC GND Y2 Y3 SCLK/IN 31 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25
S
Specifications ispLSI 1032E
Pin Configurations
ispLSI 1032E 100-Pin TQFP Pinout Diagram
NC3 NC3 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 6 GND GOE 1/IN 52 I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39 NC3 NC3
3NC 3NC
U
SE
1. Pins have dual function capability. 2. Pins have dual function capability which is software selectable. 3. NC pins are not to be connected to any active signal, VCC or GND.
is p
I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 1MODE/IN1 GND 1SDO/IN 2 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 3NC 3NC
LS
3NC
3NC
I1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
03
I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 VCC GND ispEN RESET 1SDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 3NC 3NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
2E
A
FO
Top View
R
ispLSI 1032E
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
N
EW
D
15
ES IG N
NC3 NC3 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 GOE 0/IN 42 Y1 VCC GND Y2 Y3 SCLK/IN 31 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25 NC3 NC3
0766A-32E-isp
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
S
Specifications ispLSI 1032E
Part Number Description
ispLSI 1032E - XXX
Device Family
X
X
X
Grade Blank = Commercial I = Industrial
Device Number
ispLSI 1032E Ordering Information Conventional Packaging
COMMERCIAL
FO
FAMILY
fmax (MHz) 125 125 100 100 90
tpd (ns) 7.5 7.5 10 10 10 10 12
ORDERING NUMBER ispLSI 1032E-125LJ ispLSI 1032E-100LJ ispLSI 1032E-100LT ispLSI 1032E-90LJ1 ispLSI 1032E-90LT ispLSI 1032E-80LJ ispLSI 1032E-80LT
1 1
R
N
EW
Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 90 = 90 MHz fmax 80 = 80 MHz fmax 70 = 70 MHz fmax
D
ispLSI 1032E-125LT
Power L = Low
A
2E
ispLSI
03
90 80 80 70 70
I1
12 15 15
1
ispLSI 1032E-70LJ ispLSI 1032E-70LT
1. Converted to -100 speed grade per PCN# 001-97.
is p
LS
INDUSTRIAL
tpd (ns) 15 15 ORDERING NUMBER ispLSI 1032E-70LJI ispLSI 1032E-70LTI PACKAGE 84-Pin PLCC 100-Pin TQFP
FAMILY ispLSI
fmax (MHz) 70 70
U
SE
16
ES IG N
PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC 100-Pin TQFP
Package J = PLCC T = TQFP JN = Lead-Free PLCC TN = Lead-Free TQFP
S
Specifications ispLSI 1032E
ispLSI 1032E Ordering Information (Cont.) Lead-Free Packaging
COMMERCIAL
FAMILY fmax (MHz) 125 125 ispLSI 100 100 70 70 tpd (ns) 7.5 7.5 10 10 15 15 ORDERING NUMBER ispLSI 1032E-125LJN ispLSI 1032E-125LTN ispLSI 1032E-100LJN ispLSI 1032E-100LTN ispLSI 1032E-70LJN ispLSI 1032E-70LTN PACKAGE Lead-Free 84-Pin PLCC1 Lead-Free 100-Pin TQFP
1. 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com.
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 70 70 tpd (ns) 15 15 ORDERING NUMBER ispLSI 1032E-70LJNI ispLSI 1032E-70LTNI
D EW
PACKAGE
Lead-Free 84-Pin PLCC1 Lead-Free 100-Pin TQFP
Date -- August 2006
Version 08 09
FO
R
Revision History
Previous Lattice release.
U
SE
is p
LS
I1
03
2E
A
Updated for lead-free package options.
17
N
1. 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com.
Change Summary
ES IG N
Lead-Free 84-Pin PLCC1 Lead-Free 84-Pin PLCC1
Lead-Free 100-Pin TQFP Lead-Free 100-Pin TQFP
S

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