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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Mitsubishi microcomputers
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
The M30220 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. The M30220 group has LCD controller/driver. M30220 group is packaged in a 144-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.
Features
* Basic machine instructions .................. Compatible with the M16C/60 series * Memory capacity .................................. See figure memory expansion * Shortest instruction execution time ...... 100ns (f(XIN)=10MHz) * Supply voltage ..................................... 4.0V to 5.5V (f(XIN)=10MHz) 2.7V to 5.5V (f(XIN)=7MHz with software one-wait) * Interrupts .............................................. 26 internal and 8 external interrupt sources, 4 software, 7 levels (including key input interrupt) * Multifunction 16-bit timer ...................... Timer A (output) x 8, timer B (input) x 6 * Real time port outputs .......................... 8 bits X 4 lines * Serial I/O .............................................. 3 channel for UART or clock synchronous * DMAC .................................................. 2 channels (trigger: 26 sources) * A-D converter ....................................... 10 bits X 8 channels * D-A converter ....................................... 8 bits X 3 channels * Watchdog timer .................................... 1 line * Programmable I/O ............................... 104 lines (32 lines are shared with LCD outputs) * Output port ........................................... 16 lines (shared with LCD outputs) _______ * Input port .............................................. 1 line (P77, shared with NMI pin) * LCD drive control circuit ....................... 1/2, 1/3 bias 2, 3 and 4 time sharing 4 common outputs 48 segment outputs built-in Charge-pump * Key input interrupt ................................ 20 lines * Clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Camera, Home appliances, Portable equipment, Drop meter, Audio, Office equipment, etc.
------Table of Contents-----Central Processing Unit (CPU) ....................... 9 Reset ............................................................. 12 Clock Generating Circuit ............................... 20 Protection ...................................................... 29 Interrupt ......................................................... 30 Watchdog Timer ............................................ 53 DMAC ........................................................... 55 Timer ............................................................. 65 Real time Port ............................................... 85 Serial I/O ....................................................... 87 LCD Drive Control Circuit ............................ 123 A-D Converter ............................................. 130 D-A Converter ............................................. 140 Programmable I/O Port ............................... 142 Electric Characteristics ............................... 155 Flash Memory Version ................................ 171
1
Mitsubishi microcomputers
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Configuration
Figure 1.1.1 shows the pin configurations (top view).
PIN CONFIGURATION (top view)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
P103/SEG19 P104/SEG20 P105/SEG21 P106/SEG22 P107/SEG23 P110/SEG24 P111/SEG25 P112/SEG26 P113/SEG27 P114/SEG28 P115/SEG29 P116/SEG30 P117/SEG31 P120/SEG32 P121/SEG33 VSS P122/SEG34 VCC P123/SEG35 P124/SEG36 P125/SEG37 P126/SEG38 P127/SEG39 P00/SEG40 P01/SEG41 P02/SEG42 P03/SEG43 P04/SEG44 P05/SEG45 P06/SEG46 P07/SEG47 P10/KI0 P11/KI1 P12/KI2 P13/KI3 P14/KI4
P102/SEG18 P101/SEG17 P100/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 C2 C1 VL3 VL2 VL1 Vss P132/DA2 P131/DA1 AVSS P130/ADTRG/DA0 VREF AVCC P97/AN7
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
M30220MX-XXXGP/RP
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P15/KI5 P16/KI6 P17/KI7 P20/KI8 P21/KI9 P22/KI10 P23/KI11 P24/KI12 P25/KI13 P26/KI14 P27/KI15 P30/KI16 P31/KI17 P32/KI18 P33/KI19 P34 P35 P40/TA0OUT P41/TA0IN P42/TA1OUT P43/TA1IN P44/TA2OUT P45/TA2IN P46/TA3OUT/INT4 P47/TA3IN/INT4 P50/TB0IN P51/TB1IN P52/TB2IN P53/TB3IN P54/TB4IN P55/TB5IN P56/INT3 P57/CKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0
N o te : P 7 0 a n d P 7 1 a re N ch a n n e l o p e n -d ra in o u tp u t p in .
Figure 1.1.1. Pin configuration (top view)
2
P96/AN6 P95/AN5 P94/AN4 P93/AN3 P92/AN2 P91/AN1 P90/AN0 P87/TA7IN P86/TA7OUT P85/TA6IN P84/TA6OUT P83/TA5IN P82/TA5OUT P81/TA4IN/INT5 P80/TA4OUT/INT5 CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC P77/NMI P76/INT2 P75/INT1 P74/INT0 P73/CTS2/RTS2 P72/CLK2 P71/RXD2/SCL(Note) P70/TXD2/SDA(Note) P67/T xD 1 P66/RxD1 P65/CLK1 P64/CTS1/RTS1/CLKS1 P63/TxD0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Package: 144P6Q-A, 144PFB-A
Mitsubishi microcomputers
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Diagram
Figure 1.1.2 is a block diagram of the M30220 group.
8
8
8
7
1
8
8
I/O ports
Port P3 6
Port P4
Port P5
Port P6
Port P7
Port P77
Port P8
Port P9
Internal peripheral functions
Port P10
Timer
Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TA5 (16 bits) Timer TA6 (16 bits) Timer TA7 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits)
System clock generator A-D converter
(10 bits X 8 channels
UART/clock synchronous SI/O
XIN-XOUT XCIN-XCOUT
8
(8 bits X 3 channels)
Port P2
8
LCD drive control circuit (4COM X 48SEG)
Port P11
8
M16C/60 series 16-bit CPU core
Registers R0H R0L R0H R0L R1H R1 R1HR R1L L R2 R 2 R3 A 3 A 0 A0 FA1 1B FB SB Program counter PC Stack pointer ISP USP Vector table INTB
Memory
Port P12
ROM (Note 1) RAM (Note 2)
Port P1
8
Watchdog timer (15 bits) DMAC (2 channels)
8
Port P13
Port P0
D-A converter (8 bits X 3 channels)
8
Flag register
FLG
Multiplier
3
Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.
Figure 1.1.2. Block diagram of M30220 group
3
Mitsubishi microcomputers
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Performance Outline
Table 1.1.1 is performance outline of M30220 group. Table 1.1.1. Performance outline of M30220 group Item Number of basic instructions Shortest instruction execution time Memory ROM capacity RAM I/O port P0 to P13 (except P77) Input port P77 Output port SEG0 to SEG15 Multifunction TA0 to TA7 timer TB0 to TB5 Real time port outputs Serial I/O UART0 to UART2 A-D converter D-A converter DMAC LCD COM0 to COM3 SEG0 to SEG47 Watchdog timer Interrupt Clock generating circuit Performance 91 instructions 100ns (f(XIN)=10MHz 96 Kbytes 6 Kbytes 8 bits x 11, 3 bits x 1, 6 bits x 1, 7 bits x 1 1 bit x 1 2 bits x 8 16 bits x 8 16 bits x 6 8 bits x 4 lines (UART or clock synchronous) x 3 10 bits x 8 channels 8 bits x 3 channels 2 channel(trigger:26 sources) 4 lines 48 lines (32 lines are shared with I/O ports) 15 bits x 1 (with prescaler) 26 internal and 8 external sources, 4 software sources 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) 4.0V to 5.5V (f(XIN)=10MHz) 2.7V to 5.5V (f(XIN)=7MHz with software one-wait) 18mW (VCC=3V, f(XIN)=7MHz with software one-wait) 5V 5 mA 0.1mA("H" output), 2.5mA("L" output) CMOS high-performance silicon gate 144-pin plastic mold QFP
Supply voltage Power consumption I/O char- I/O withstand voltage (P0 to P13) acteristics Output current P1 to P9,P13 P0, P10 to P12 Device configuration Package
4
Mitsubishi microcomputers
M30220 Group
Description
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi plans to release the following products in the M30220 group: (1) Support for mask ROM version, flash memory version (2) ROM capacity (3) Package 144P6Q-A : Plastic molded QFP (mask ROM and flash memory versions) 144PFB-A : Plastic molded QFP(mask ROM and flash memory versions) Figure 1.1.3 shows the ROM expansion and figure 1.1.4 shows the Type No., memory size, and package.
Dec. 2001
RAM (Byte) 10K
Under development M30220FCGP/RP
6K
M30220MA-XXXGP/RP
96K
128K
ROM (Byte)
Figure 1.1.3. Memory expansion
Type No. M30 22 0 M A
- XXX GP
Package type: GP: Package144P6Q-A RP: 144PFB-A ROM No. Omitted for flash memory version Shows characteristic, use None: General ROM capacity: 8 : 64K bytes A : 96K bytes
C : 128K bytes
Memory type: M : Mask ROM version F : Flash memory version Shows RAM capacity, pin count, etc. (The value itself has no specific meaning) M16C/22 Group(built-in LCDC) M16C Family
Figure 1.1.4. Type No., memory size, and package
5
Mitsubishi microcomputers
M30220 Group
Pin Description
Pin Description
Pin name VCC, VSS CNVSS RESET XIN XOUT Signal name Power supply input CNVSS Reset input Clock input Clock output I I I O I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin. Connect it to the VSS pin via resistor. A "L" on this input resets the microcomputer. These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the XIN and the XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. These pins are provided for the sub clock generating circuit. Connect a ceramic resonator or crystal between the XCIN and the XCOUT pins. To use an externally derived clock, input it to the XCIN pin and leave the XCOUT pin open. This pin is a power supply input for the A-D converter. Connect it to VCC. This pin is a power supply input for the A-D converter. Connect it to VSS.
XCIN XCOUT
Clock input Clock output
I O
AVCC AVSS
Analog power supply input Analog power supply input Reference voltage input I/O port P0 I I/O
VREF P00 to P07
This pin is a reference voltage input for the A-D converter. This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistor. Pins in this port also use as LCD segment output and real time port output. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for the key input interrupt function and real time port output. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as input pins for the key input interrupt function and real time port output. This is a 6-bit I/O port equivalent to P0. P30 to P33 also function as input pins for the key input interrupt function. This is a 8-bit I/O port equivalent to P0. Pins in this port also function as timer A0 to A3 I/O pins, INT4 input pin as selected by software. This is a 8-bit I/O port equivalent to P0. Pins in this port also function as timer B0 to B5 and INT3 input pins, CKOUT output pin as selected by software. This is an 8-bit I/O port equivalent to P0. Pins in this port also function as UART0 and UART1 I/O pins as selected by software.
P10 to P17
I/O port P1
I/O
P20 to P27
I/O port P2
I/O
P30 to P35 P40 to P47
I/O port P3 I/O port P4
I/O I/O
P50 to P57
I/O port P5
I/O
P60 to P67
I/O port P6
I/O
6
Mitsubishi microcomputers
M30220 Group
Pin Description
Pin Description Pin name P70 to P76 Signal name I/O port P7 I/O I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function P70 to P76 are I/O ports equivalent to P0 (P70 and P71 are N channel open-drain output). Pins in this port also function as UART2 I/O pin, INT0 to INT2 input pins as selected by software. P77 is an input-only port that also functions for NMI.
P77 P80 to P87 I/O port P8
I
I/O This is a 8-bit I/O port equivalent to P0. Pins in this port also function as timer A4 to A7 I/O pins, INT5 input pin as selected by software. I/O This is an 8-bit I/O port equivalent to P0. Pins in this port also function as A-D converter analog input pins as selected by software. I/O This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD as selected by software. I/O This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD as selected by software. I/O This is an 8-bit I/O port equivalent to P0. Pins in this port also function as SEG output for LCD and real time port output. I/O This is an 3-bit I/O port equivalent to P0. Pins in this port also function as D-A converter analog output pins or start trigger for A-D input pins. Pins in this port function as SEG output for LCD drive circuit. Pins in this port function as common output for LCD drive circuit. Power supply input for LCD drive circuit. Pins in this port function as external pin for LCD step-up condenser. Connect a condenser between C1 and C2.
P90 to P97
I/O port P9
P100 to P107 P110 to P117 P120 to P127 P130 to P132
I/O port P10 I/O port P11 I/O port P12 I/O port P13
SEG0 to SEG15 COM0 to COM3 VL1 to VL3 C1, C2
Segment output Common output Power supply input for LCD Step-up condenser connect port
O O
7
Mitsubishi microcomputers
M30220 Group
Memory
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Operation of Functional Blocks
The M30220 group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, real time port, serial I/O, LCD drive control circuit, D-A converter, A-D converter, DMAC and I/O ports. The following explains each unit.
Memory
Figure 1.4.1 is a memory map of the M30220 group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30220MA-XXXGP, there is 96K bytes of internal ROM from E800016 to FFFFF16. The vector table for fixed interrupts such as the _______ reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30220MA-XXXGP, 6K bytes of internal RAM is mapped to the space from 0040016 to 01BFF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, timers, and LCD, etc. Figures 1.7.1 to 1.7.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area For details, see Figures 1.7.1 to 1.7.3
RAM size 4K bytes 6K bytes 10K bytes
Address XXXXX16 013FF16 01BFF16 02BFF16
0040016 Internal RAM area XXXXX16 FFE0016 Special page vector table FFFDC16 Internal RAM area Undefined instruction Overflow BRK instruction Address match YYYYY16 Internal ROM area FFFFF16 FFFFF16 Single step Watchdog timer DBC NMI Reset
ROM size 64K bytes 96K bytes 128K bytes
Address YYYYY16 F000016 E800016 E000016
Figure 1.4.1. Memory map
8
Mitsubishi microcomputers
M30220 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.5.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
b15
b8 b7
b0
R0(Note)
H
L
b15
b8 b7
b0
b19
b0
R1(Note)
H
L Data registers
PC
Program counter
b15
b0
b19
b0
R2(Note)
INTB
H
L
Interrupt table register
b0
b15
b0
b15
R3(Note)
USP
User stack pointer
b15
b0
b15
b0
A0(Note) Address registers
ISP
Interrupt stack pointer
b15
b0
b15
b0
A1(Note)
SB
Static base register
b15
b0
b15
b0
FB(Note)
Frame base registers
FLG
Flag register
IPL
U
I OBS Z DC
Note: These registers consist of two register banks.
Figure 1.5.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
9
Mitsubishi microcomputers
M30220 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.5.2 shows the flag register (FLG). The following explains the function of each flag: * Bit 0: Carry flag (C flag) This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. * Bit 1: Debug flag (D flag) This flag enables a single-step interrupt. When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is cleared to "0" when the interrupt is acknowledged. * Bit 2: Zero flag (Z flag) This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0". * Bit 3: Sign flag (S flag) This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0". * Bit 4: Register bank select flag (B flag) This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is selected when this flag is "1". * Bit 5: Overflow flag (O flag) This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0". * Bit 6: Interrupt enable flag (I flag) This flag enables a maskable interrupt. An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to "0" when the interrupt is acknowledged.
10
Mitsubishi microcomputers
M30220 Group
CPU
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Bit 7: Stack pointer select flag (U flag) Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected when this flag is "1". This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed. * Bits 8 to 11: Reserved area * Bits 12 to 14: Processor interrupt priority level (IPL) Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled. * Bit 15: Reserved area The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
b15
b0
IPL
U
I
OBSZDC
Flag register (FLG)
Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area Processor interrupt priority level Reserved area
Figure 1.5.2. Flag register (FLG)
11
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See "Software Reset" for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level "L" (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the "H" level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.6.1 shows the example reset circuit. Figure 1.6.2 shows the reset sequence.
5V 4.0V VCC 0V RESET VCC 5V RESET 0.8V 0V Example when f(XIN)=10MHZ, VCC=5V.
Figure 1.6.1. Example reset circuit
XIN
More than 20 cycles are needed
RESET
BCLK 24 cycles
BCLK
FFFFC16
Content of reset vector
FFFFE16
Address (Internal Address signal)
Figure 1.6.2. Reset sequence
____________
Table 1.6.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.6.3 and 1.6.4 show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.6.1. Pin status when RESET pin level is "L"
Pin name P0, P10 to P12 P1 to P9, P13 SEG0 to SEG15 COM0 to COM3
Status Input port(with a pull up resistor) Input port (floating) "H" level is output "H" level is output
12
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(1)Processor mode register 0 (2)Processor mode register 1 (3)System clock control register 0 (4)System clock control register 1 (5)Address match interrupt enable register (6)Protect register (7)Watchdog timer control register (8)Address match interrupt register 0
(000416)*** (000516)*** (000616)*** (000716)*** (000916)*** (000A16)*** (000F16)*** (001016)*** (001116)*** (001216)*** 0
0000 00
(27)UART1 transmit interrupt control register (28)UART1 receive interrupt control register (29)Timer A0 interrupt control register (30)Timer A1 interrupt control register (31)Timer A2 interrupt control register (32)Timer A3 / INT4 interrupt control register (33)Timer A4 / INT5 interrupt control register (34)Timer B0 interrupt control register (35)Timer B1 interrupt control register (36)Timer B2 interrupt control register (37)INT0 interrupt control register (38)INT1 interrupt control register (39)INT2 interrupt control register (40)LCD mode register (41)Segment output enable register (42)Key input mode register (43)Count start flag 1 (44)One-shot start flag 1 (45)Trigger select flag 1 (46)Up-down flag 1 (47)Timer A5 mode register (48)Timer A6 mode register (49)Timer A7 mode register (50)Timer B3 mode register (51)Timer B4 mode register (52)Timer B5 mode register (53)Interrupt cause select register 0 (54)Interrupt cause select register 1 (55)Clock division counter control register (56)UART2 special mode register 2 (57)UART2 special mode register (58)UART2 transmit/receive mode register
(005316)*** (005416)*** (005516)*** (005616)*** (005716)*** (005816)*** (005916)*** (005A16)*** (005B16)*** (005C16)*** (005D16)*** (005E16)*** (005F16)*** (012016)*** (012216)*** (012616)*** (034016)*** (034216)*** (034316)*** (034416)*** (035616)*** (035716)*** (035816)*** (035B16)*** (035C16)*** (035D16)*** (035E16)*** (035F16)*** (036016)*** (037616)*** (037716)*** (037816)*** 0 00? 00? 00? 0 0
?000 ?000 ?000 ?000 ?000 00?000 00?000 ?000 ?000 ?000 00?000 00?000 00?000 000 000
01001000 00100000 00 00 000????? 0016 0016 0000 0016 0016 0000 00000?00 00000?00 00?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000 ?000
(9)Address match interrupt register 1
(001416)*** (001516)*** (001616)***
(10)DMA0 control register (11)DMA1 control register (12)INT3 interrupt control register (13)Timer B5 interrupt control register (14)Timer B4 interrupt control register (15)Timer B3 interrupt control register (16)Timer A7 interrupt control register (17)Timer A6 interrupt control register (18)Timer A5 interrupt control register (19)DMA0 interrupt control register (20)DMA1 interrupt control register (21)Key input interrupt control register (22)A-D conversion interrupt control register (23)UART2 transmit interrupt control register (24)UART2 receive interrupt control register (25)UART0 transmit interrupt control register (26)UART0 receive interrupt control register
(002C16)*** (003C16)*** (004416)*** (004516)*** (004616)*** (004716)*** (004816)*** (004916)*** (004A16)*** (004B16)*** (004C16)*** (004D16)*** (004E16)*** (004F16)*** (005016)*** (005116)*** (005216)***
0 0000 000 01 100 0 00 000 00 000 000 0000 000 0016 0016 0016 0 000 0 000 0 000
000 0000 0016
0016 0016 0016
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
x : Nothing is mapped to this bit ? : Undefined
Figure 1.6.3. Device's internal status after a reset is cleared
13
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(59)UART2 transmit/receive control register 0 (037C16)* * * 0 0 0 0 1 0 0 0 (60)UART2 transmit/receive control register 1 (037D16)* * * 0 0 0 0 0 0 1 0 (61)Count start flag 0 (62) Clock prescaler reset flag (63)One-shot start flag 0 (64)Trigger select flag 0 (65)Up-down flag 0 (66)Timer A0 mode register (67)Timer A1 mode register (68)Timer A2 mode register (69)Timer A3 mode register (70)Timer A4 mode register (71)Timer B0 mode register (72)Timer B1 mode register (73)Timer B2 mode register (74)UART0 transmit/receive mode register (038016)* * * (038116)* * * 0 (038216)* * * 0 0 (038316)* * * (038416)* * * (039616)* * * (039716)* * * (039816)* * * (039916)* * * (039A16)* * * (039B16)* * * 0 0 ? (039C16)* * * 0 0 ? (039D16)* * * 0 0 ? (03A016)* * *
(85)A-D control register 0 (86)A-D control register 1 (87)D-A control register (88)Port P0 direction register
(03D616)* * * (03D716)* * * (03DC16)* * * (03E216)* * * (03E316)* * * (03E616)* * * (03E716)* * * (03EA16)* * * (03EB16)* * * (03EE16)* * * (03EF16)* * * (03F216)* * * (03F316)* * * (03F616)* * * (03F716)* * * (03FA16)* * * (03FB16)* * *
000???
0016
0016
000
0016
0016
00000
0016
(89)Port P1 direction register (90)Port P2 direction register (91)Port P3 direction register (92)Port P4 direction register (93)Port P5 direction register (94)Port P6 direction register (95)Port P7 direction register (96)Port P8 direction register (97)Port P9 direction register (98)Port P10 direction register (99)Port P11 direction register
0016
0016
000000
0016
0016
0016
0016
0016
0016
0016
0000000
0016
0016
0000
0016
0000
0016
0000
0016
0016
(100)Port P12 direction register (101)Port P13 direction register (102)Pull-up control register 0 (103)Pull-up control register 1 (104)Pull-up control register 2 (105)Real time port control register (106)Data registers (R0/R1/R2/R3) (107)Address registers (A0/A1) (108)Frame base register (FB) (109)Interrupt table register (INTB) (110)User stack pointer (USP) (111)Interrupt stack pointer (ISP) (112)Static base register (SB) (113)Flag register (FLG)
0016
(75)UART0 transmit/receive control register 0 (03A416)* * * 0 0 0 0 1 0 0 0 (76)UART0 transmit/receive control register 1 (03A516)* * * 0 0 0 0 0 0 1 0 (77)UART1 transmit/receive mode register (03A816)* * *
000
(03FC16)* * * 0 0 0 0 0 0 1 1 (03FD16)* * *
0016
0016
(78)UART1 transmit/receive control register 0 (03AC16)* * * 0 0 0 0 1 0 0 0 (79)UART1 transmit/receive control register 1 (03AD16)* * * 0 0 0 0 0 0 1 0 (80)UART transmit/receive control register 2 (03B016)* * *
(03FE16)* * * 1 1 1 1 0 0 0 0 (03FF16)* * * *** *** *** *** *** *** *** ***
0016
000016
0000000
(81)Flash memory control register (Note) (03B416)* * * (82)DMA0 cause select register (83)DMA1 cause select register (84) A-D control register 2 (03B816)* * * (03BA16)* * * (03D416)* * *
0
0016
01
000016
000016
0016
0000016
0000
000016
000016
000016
000016
x : Nothing is mapped to this bit ? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note : This register is only exist in flash memory version.
Figure 1.6.4. Device's internal status after a reset is cleared
14
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
004016
000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16
004116 004216 004316 004416
Processor mode register 0 (PM0) Processor mode register 1(PM1) System clock control register 0 (CM0) System clock control register 1 (CM1) Address match interrupt enable register (AIER) Protect register (PRCR)
004516 004616 004716 004816 004916 004A16 004B16 004C16 004D16 004E16 004F16 005016 005116 005216 005316 005416
Watchdog timer start register (WDTS) Watchdog timer control register (WDC) Address match interrupt register 0 (RMAD0)
INT3 interrupt control register (INT3IC) Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC) Timer B3 interrupt control register (TB3IC) Timer A7 interrupt control register (TA7IC) Timer A6 interrupt control register (TA6IC) Timer A5 interrupt control register (TA5IC) Bus collision detection interrupt control register (BCNIC) DMA0 interrupt control register (DM0IC) DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC) A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC) UART2 receive interrupt control register (S2RIC) UART0 transmit interrupt control register (S0TIC) UART0 receive interrupt control register (S0RIC) UART1 transmit interrupt control register (S1TIC) UART1 receive interrupt control register (S1RIC)
Address match interrupt register 1 (RMAD1)
005516 005616 005716 005816 005916 005A16 005B16 005C16 005D16 005E16
DMA0 source pointer (SAR0)
005F16
010016 010116
Timer A0 interrupt control register (TA0IC) Timer A1 interrupt control register (TA1IC) Timer A2 interrupt control register (TA2IC) Timer A3 interrupt control register (TA3IC) INT4 interrupt control register (INT4IC) Timer A4 interrupt control register (TA4IC) INT5 interrupt control register (INT5IC) Timer B0 interrupt control register (TB0IC) Timer B1 interrupt control register (TB1IC) Timer B2 interrupt control register (TB2IC) INT0 interrupt control register (INT0IC) INT1 interrupt control register (INT1IC) INT2 interrupt control register (INT2IC) LCD RAM0(LRAM0) LCD RAM1(LRAM1) LCD RAM2(LRAM2) LCD RAM3(LRAM3) LCD RAM4(LRAM4) LCD RAM5(LRAM5) LCD RAM6(LRAM6) LCD RAM7(LRAM7) LCD RAM8(LRAM8) LCD RAM9(LRAM9) LCD RAM10(LRAM10) LCD RAM11(LRAM11) LCD RAM12(LRAM12) LCD RAM13(LRAM13) LCD RAM14(LRAM14) LCD RAM15(LRAM15) LCD RAM16(LRAM16) LCD RAM17(LRAM17) LCD RAM18(LRAM18) LCD RAM19(LRAM19) LCD RAM20(LRAM20) LCD RAM21(LRAM21) LCD RAM22(LRAM22) LCD RAM23(LRAM23) LCD mode register (LCDM) Segment output enable register (SEG) LCD frame frequency counter (LCDTIM) Key input mode register (KUPM)
DMA0 destination pointer (DAR0)
010216 010316 010416 010516 010616 010716 010816
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
010916 010A16 010B16 010C16 010D16
DMA1 source pointer (SAR1)
010E16 010F16 011016 011116
DMA1 destination pointer (DAR1)
011216 011316 011416 011516
DMA1 transfer counter (TCR1)
011616 011716
012016 012116 012216 012316 012416 012516 012616
DMA1 control register (DM1CON)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.7.1. Location of peripheral unit control registers (1)
15
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
034016 034116 034216 034316 034416 034516 034616 034716 034816 034916 034A16 034B16 034C16 034D16 034E16 034F16 035016 035116 035216 035316 035416 035516 035616 035716 035816 035916 035A16 035B16 035C16 035D16 035E16 035F16 036016 036116 036216 036316 036416 036516 036616 036716 036816 036916 036A16 036B16 036C16 036D16 036E16 036F16 037016 037116 037216 037316 037416 037516 037616 037716 037816
Count start flag 1 (TABSR1) One-shot start flag 1 (ONSF1) Trigger select register 1 (TRGSR1) Up-down flag 1(UDF1) Timer A5 register (TA5) Timer A6 register (TA6) Timer A7 register (TA7)
038016 038116 038216 038316 038416 038516 038616 038716 038816 038916 038A16 038B16 038C16 038D16 038E16 038F16
Count start flag 0 (TABSR0) Clock prescaler reset flag (CPSRF) One-shot start flag 0 (ONSF0) Trigger select register 0 (TRGSR0) Up-down flag 0 (UDF0) Timer A0 register (TA0) Timer A1 register (TA1) Timer A2 register (TA2) Timer A3 register (TA3) Timer A4 register (TA4) Timer B0 register (TB0) Timer B1 register (TB1) Timer B2 register (TB2) Timer A0 mode register (TA0MR) Timer A1 mode register (TA1MR) Timer A2 mode register (TA2MR) Timer A3 mode register (TA3MR) Timer A4 mode register (TA4MR) Timer B0 mode register (TB0MR) Timer B1 mode register (TB1MR) Timer B2 mode register (TB2MR)
Timer B3 register (TB3) Timer B4 register (TB4) Timer B5 register (TB5) Timer A5 mode register (TA5MR) Timer A6 mode register (TA6MR) Timer A7 mode register (TA7MR) Timer B3 mode register (TB3MR) Timer B4 mode register (TB4MR) Timer B5 mode register(TB5MR) Interrupt cause select register 0 (IFSR0) Interrupt cause select register 1 (IFSR1) Clock division counter control register (CDCC)
039016 039116 039216 039316 039416 039516 039616 039716 039816 039916 039A16 039B16 039C16 039D16 039E16 039F16 03A016 03A116 03A216 03A316 03A416 03A516 03A616 03A716 03A816 03A916 03AA16 03AB16 03AC16 03AD16
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG) UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0) UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG) UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
Clock division counter (CDC)
03AE16 03AF16 03B016 03B116 03B216 03B316 03B416 03B516
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Flash memory control register (FMCR)(Note 1)
UART2 special mode register 2(U2SMR2) UART2 special mode register (U2SMR)
03B616 03B716 03B816 03B916 03BA16 03BB16 03BC16 03BD16 03BE16 03BF16
UART2 transmit/receive mode register (U2MR) 037916 UART2 bit rate generator (U2BRG)
037A16 037B16 037C16 037D16 037E16 037F16
DMA0 request cause select register (DM0SL) DMA1 request cause select register (DM1SL)
UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0) UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB)
Note 1: This register is only exist in flash memory version. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.7.2. Location of peripheral unit control registers (2)
16
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
03C016 03C116 03C216 03C316 03C416 03C516 03C616 03C716 03C816 03C916 03CA16 03CB16 03CC16 03CD16 03CE16 03CF16 03D016 03D116 03D216 03D316 03D416 03D516 03D616 03D716 03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016 03E116 03E216 03E316 03E416 03E516 03E616 03E716 03E816 03E916 03EA16 03EB16 03EC16 03ED16 03EE16 03EF16 03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16 03FD16 03FE16 03FF16
A-D register 0 (AD0) A-D register 1 (AD1) A-D register 2 (AD2) A-D register 3 (AD3) A-D register 4 (AD4) A-D register 5 (AD5) A-D register 6 (AD6) A-D register 7 (AD7)
A-D control register 2 (ADCON2) A-D control register 0 (ADCON0) A-D control register 1 (ADCON1) D-A register 0 (DA0) D-A register 1 (DA1) D-A control register (DACON) D-A register 2 (DA2) Port P0 register (P0) Port P1 register (P1) Port P0 direction register (PD0) Port P1 direction register (PD1) Port P2 register (P2) Port P3 register (P3) Port P2 direction register (PD2) Port P3 direction register (PD3) Port P4 register (P4) Port P5 register (P5) Port P4 direction register (PD4) Port P5 direction register (PD5) Port P6 register (P6) Port P7 register (P7) Port P6 direction register (PD6) Port P7 direction register (PD7) Port P8 register (P8) Port P9 register (P9) Port P8 direction register (PD8) Port P9 direction register (PD9) Port P10 register (P10) Port P11 register (P11) Port P10 direction register (PD10) Port P11 direction register (PD11) Port P12 register (P12) Port P13 register (P13) Port P12 direction register (PD12) Port P13 direction register (PD13) Pull-up control register 0 (PUR0) Pull-up control register 1 (PUR1) Pull-up control register 2 (PUR2) Real time port control register (RTP)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.7.3. Location of peripheral unit control registers (3)
17
Mitsubishi microcomputers
M30220 Group
Software Reset Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved. Figure 1.8.1 shows the processor mode register 0 and 1.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor mode register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol PM0
Address 000416
When reset XXXX00002
Bit symbol
PM00
Bit name
Processor mode bit
b1 b0
Function
0 0: Single-chip mode 0 1: Must not be set 1 0: Must not be set 1 1: Must not be set
RW
PM01
Reserved bit
PM03
Must always be set to "0"
Software reset bit
The device is reset when this bit is set to "1". The value of this bit is "0" when read.
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Symbol PM1
Address 000516
When reset 0XXXXX002
Bit symbol
Reserved bit Nothing is assigned.
Bit name
Function
Must always be set to "0"
RW
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
PM17
Wait bit
0 : No wait state 1 : Wait state inserted
Note: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Figure 1.8.1. Processor mode register 0 and 1
18
Mitsubishi microcomputers
M30220 Group
Software Wait Software wait
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 000516). (Note) A software wait is inserted in the internal ROM/RAM area. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". Set this bit after referring to the recommended operating conditions (main clock input oscillation frequency) of the electric characteristics. The SFR area is always accessed in two BCLK cycles regardless of the setting of this control bit. Table 1.8.1 shows the software waits and bus cycles. Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000A16) to "1".
Table 1.8.1. Software waits and bus cycles
Area SFR Internal ROM/RAM Wait bit Invalid 0 1 2 BCLK cycles 1 BCLK cycle 2 BCLK cycles Bus cycle
19
Mitsubishi microcomputers
M30220 Group
Clock Generating Circuit Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units. Table 1.9.1. Main clock and sub-clock generating circuits Use of clock Main clock generating circuit * CPU's operating clock source * Internal peripheral units' operating clock source Sub-clock generating circuit * CPU's operating clock source * Timer A/B's count clock source * Intermittent pullup operation clock source of key input * LCD operation clock source Crystal oscillator XCIN, XCOUT Available Stopped
Usable oscillator Pins to connect oscillator Oscillation stop/restart function Oscillator status immediately after reset Other
Ceramic or crystal oscillator XIN, XOUT Available Oscillating
Externally derived clock can be input
Example of oscillator circuit
Figure 1.9.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.9.2 shows some examples of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 1.9.1 and 1.9.2 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.
M30220
(Built-in feedback resistor)
M30220
(Built-in feedback resistor)
XIN
XOUT
(Note) Rd
XIN
XOUT Open
Externally derived clock
CIN COUT
Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN and XOUT following the instruction.
Figure 1.9.1. Examples of main clock
M30220
(Built-in feedback resistor)
M30220
(Built-in feedback resistor)
XCIN
XCOUT (Note) RCd
XCIN
XCOUT Open
Externally derived clock CCIN CCOUT Vcc Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN and XCOUT following the instruction.
Figure 1.9.2. Examples of sub-clock
20
Mitsubishi microcomputers
M30220 Group
Clock Generating Circuit Clock Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.9.3 shows the block diagram of the clock generating circuit.
CM14=1 fC1 fC132 CM14=0
XCIN CM04
XCOUT
1/32
fC32
f1
fAD
f8
f32
fC
Sub clock
CM10 "1" Write signal
SQ
XIN
XOUT
b c
R
RESET Software reset NMI Interrupt request level judgment output
a
Divider
d
CM07=0
BCLK
CM05
Main clock CM02
fC CM07=1
SQ
WAIT instruction
R
b
c
1/2
1/2
a
1/2
1/2
1/2
CM06=0 CM17,CM16=11 CM06=1 CM06=0 CM17,CM16=10
d
CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=00
CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 WDCi : Bit i at address 000F16
Details of divider
Figure 1.9.3. Clock generating circuit
21
Mitsubishi microcomputers
M30220 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to "1" when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to "1" and then executing a WAIT instruction.
(5) fC132
This clock is derived by dividing the sub-clock by 1 or 32. The clock is selected by fC132 clock select bit (bit4 at address 000716). It is used for the timer A and timer B counts, intermittent pull up operation of key input.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer. Figure 1.9.4 shows the system clock control registers 0 and 1.
22
Mitsubishi microcomputers
M30220 Group
Clock Generating Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CM0 Bit symbol
CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07
Address 000616 Bit name
Clock output function select bit
When reset 4816 Function
b1 b0
RW
0 0 : I/O port P57 0 1 : fC1 output 1 0 : f1 output 1 1 : Clock divide counter output 0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8)
WAIT peripheral function clock stop bit
XCIN-XCOUT drive capacity 0 : LOW select bit (Note 2) 1 : HIGH Sub clock (XCIN-XCOUT) oscillation enable bit Main clock (XIN-XOUT) stop bit (Note 3, 4, 5) Main clock division select bit 0 (Note 7) System clock select bit (Note 6) 0 : Off 1 : On 0 : On 1 : Off 0 : CM16 and CM17 valid 1 : Division by 8 mode 0 : XIN, XOUT 1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: Changes to "1" when shifting to stop mode and at a reset. Note 3: When entering power saving mode, main clock stops using this bit. When returning from stop mode and operating with XIN, set this bit to "0". When main clock oscillation is operating by itself, set system clock select bit (CM07) to "1" before setting this bit to "1". Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT ("H") via the feedback resistor. Note 6: Sub clock (XCIN-XCOUT) oscillation enable bit (CM04) to "1" and stabilize the sub-clock oscillating before setting to this bit from "0" to "1". Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the main clock oscillating before setting this bit from "1" to "0". Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 8: fC132, fC1, fC32 is not included. Do not set to "1" when using low-speed or low power dissipation mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
Symbol CM1 Bit symbol
CM10
Address 000716 Bit name
All clock stop control bit (Note 4)
When reset 2016 Function
0 : Clock on 1 : All clocks off (stop mode) Must always be set to "0" Must always be set to "0" Must always be set to "0" 0 : fC32 1 : fC1 0 : LOW 1 : HIGH
b7 b6
RW
Reserved bit Reserved bit Reserved bit CM14 CM15 CM16 CM17 fC132 clock select bit XIN-XOUT drive capacity select bit (Note 2) Main clock division select bit 1 (Note 3)
0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register. Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is fixed at 8. Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is cut off. XCIN and XCOUT turn highimpedance state.
Figure 1.9.4. System clock control registers 0 and 1
23
Mitsubishi microcomputers
M30220 Group
Clock Output Clock Output
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The clock output function select bit allows you to choose the clock from f1, fC1, or a divide-by-n clock that is output from the P57/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and its divide ratio can be set in the range of 0016 to FF16. Also, the clock divided counter can be controlled for start or stop by the clock divide counter start flag. Figure 1.9.5 shows a block diagram of clock output. Figure 1.9.6 shows a clock divided counter related register.
Clock source selection
P57 f1 fC1
P57/CKOUT
1/2
f32
Clock divided counter (8)
Division n+1 n=0016 to FF16
Reload register (8)
Low-order 8 bits
Address 036E16
Data bus low-order bits
Example: When f(XIN)=10MHz, count source = f32 n=0716 : approx. 19.5kHz n=2616 : approx. 4.0kHz n=4D16 : approx. 2.0kHz n=9B16 : approx. 1.0kHz
Figure 1.9.5. Block diagram of clock output
Clock divided counter
b7 b0
Symbol CDC
Address 036E16
When reset XX16
Function
8-bit timer
Values that can be set
0016 to FF16
RW
Clock divided counter control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CDCC Bit symbol
Address 036016 Bit name
When reset 0XXXXXXX2 Function RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. CDCS
Clock divided counter start flg
0 : Stop 1 : Start
Figure 1.9.6. Clock divided counter related register
24
Mitsubishi microcomputers
M30220 Group
Stop Mode, Wait Mode Stop Mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation , BCLK, f1 to f32, fC, fC132, fC1, fC32 and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B operate provided that the event counter mode is set to an external pulse, and UART0 to UART2 functions provided an external clock is selected. Table 1.9.2 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Table 1.9.2. Port status during stop mode Pin Port CKOUT When fC1 selected When f1, clock devided counter output selected Status Retains status before stop mode "H" Retains status before stop mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC132, fC1, and fC32 do not stop so that the peripherals using fC132, fC1, and fC32 do not contribute to the power saving. When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to "1". Table 1.9.3 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel wait mode, that interrupt must first have been enabled. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed. Table 1.9.3. Port status during wait mode Pin Port CKOUT When fC1 selected When f1, clock devided counter output selected Status Retains status before wait mode Does not stop Retains status before stop mode Does not stop when the WAIT peripheral function clock stop bit is "0". When the WAIT peripheral function clock stop bit is "1", the status immediately prior to entering wait mode is main-tained.
25
Mitsubishi microcomputers
M30220 Group
Status Transition of BCLK Status Transition Of BCLK
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.9.4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address 000616) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped. Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock.
Table 1.9.4. Operating modes dictated by settings of system clock control registers 0 and 1 CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK 0 1 Invalid 1 0 Invalid Invalid 1 0 Invalid 1 0 Invalid Invalid 0 0 0 0 0 1 1 0 0 1 0 0 Invalid Invalid 0 0 0 0 0 0 1 Invalid Invalid Invalid Invalid Invalid 1 1 Division by 2 mode Division by 4 mode Division by 8 mode Division by 16 mode No-division mode Low-speed mode Low power dissipation mode
26
Mitsubishi microcomputers
M30220 Group
Power control Power control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The following is a description of the three available power control modes:
Modes
Power control is available in three modes. (a) Normal operation mode * High-speed mode Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the internal clock selected. Each peripheral function operates according to its assigned clock. * Medium-speed mode Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK. The CPU operates according to the internal clock selected. Each peripheral function operates according to its assigned clock. * Low-speed mode fC becomes the BCLK. The CPU operates according to the fc clock. The fc clock is supplied by the secondary clock. Each peripheral function operates according to its assigned clock. * Low power consumption mode The main clock operating in low-speed mode is stopped. The CPU operates according to the fC clock. The fc clock is supplied by the secondary clock. The only peripheral functions that operate are those with the sub-clock selected as the count source. (b) Wait mode The CPU operation is stopped. The oscillators do not stop. (c) Stop mode All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three modes listed here, is the most effective in decreasing power consumption. Figure 1.9.7 is the state transition diagram of the above modes.
27
Mitsubishi microcomputers
M30220 Group
Power control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Transition of stop mode, wait mode Reset
All oscillators stopped
WAIT instruction Interrupt WAIT instruction Interrupt WAIT instruction Interrupt
CPU operation stopped
Stop mode
All oscillators stopped
CM10 = "1" Interrupt Interrupt CM10 = "1"
Medium-speed mode (divided-by-8 mode)
Wait mode
CPU operation stopped
Stop mode
All oscillators stopped
High-speed/mediumspeed mode
Wait mode
CPU operation stopped
Stop mode
CM10 = "1" Interrupt
Low-speed/low power dissipation mode
Wait mode
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating Sub clock is stopped Medium-speed mode (divided-by-8 mode)
CM06 = "1" BCLK : f(XIN)/8 CM07 = "0" CM06 = "1" CM04 = "1" (Notes 1, 3) CM07 = "0" (Note 1) CM06 = "1" CM04 = "0"
Main clock is oscillating CM04 = "0" Sub clock is oscillating High-speed mode
BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0"
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1"
Medium-speed mode (divided-by-8 mode)
BCLK : f(XIN)/8 CM07 = "0" CM06 = "1"
Main clock is oscillating Sub clock is oscillating Low-speed mode
CM07 = "0" (Note 1, 3) BCLK : f(XCIN) CM07 = "1" CM07 = "1" (Note 2)
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0"
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1"
CM05 = "0" CM04 = "0"
CM05 = "1"
Main clock is oscillating Sub clock is stopped
CM04 = "1"
High-speed mode
BCLK : f(XIN) CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "0" CM06 = "0" (Notes 1,3)
Medium-speed mode (divided-by-2 mode)
BCLK : f(XIN)/2 CM07 = "0" CM06 = "0" CM17 = "0" CM16 = "1"
Main clock is stopped Sub clock is oscillating Low power dissipation mode
CM07 = "1" (Note 2) CM05 = "1" BCLK : f(XCIN) CM07 = "1" CM07 = "0" (Note 1) CM06 = "0" (Note 3) CM04 = "1"
Medium-speed mode (divided-by-4 mode)
BCLK : f(XIN)/4 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "0"
Medium-speed mode (divided-by-16 mode)
BCLK : f(XIN)/16 CM07 = "0" CM06 = "0" CM17 = "1" CM16 = "1"
Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow.
Figure 1.9.7. State transition diagram of Power control mode
28
Mitsubishi microcomputers
M30220 Group
Protection Protection
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.9.8 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) can only be changed when the respective bit in the protect register is set to "1". The system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to "0" after a value has been written to an address. The program must therefore be written to return these bits to "0".
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PRCR Bit symbol
PRC0
Address 000A16 Bit name
When reset XXXXXX002 Function RW
Enables writing to system clock control registers 0 and 1 (addresses 0 : Write-inhibited 1 : Write-enabled 000616 and 000716) Enables writing to processor mode 0 : Write-inhibited registers 0 and 1 (addresses 000416 1 : Write-enabled and 000516)
PRC1
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Figure 1.9.8. Protect register
29
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of Interrupt Type of Interrupts
Figure 1.10.1 lists the types of interrupts.
Software
Interrupt
Special
Hardware
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system. Figure 1.10.1. Classification of interrupts
* Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level. * Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.
30

Undefined instruction (UND instruction) Overflow (INTO instruction) BRK instruction INT instruction Reset NMI ________ DBC Watchdog timer Single step Address matched
_______

Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. * Undefined instruction interrupt An undefined instruction interrupt occurs when executing the UND instruction. * Overflow interrupt An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to "1". The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB * BRK interrupt A BRK interrupt occurs when executing the BRK instruction. * INT interrupt An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/ O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
31
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Hardware Interrupts
Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts. (1) Special interrupts Special interrupts are non-maskable interrupts. * Reset ____________ Reset occurs if an "L" is input to the RESET pin. _______ * NMI interrupt _______ _______ An NMI interrupt occurs if an "L" is input to the NMI pin. ________ * DBC interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. * Watchdog timer interrupt Generated by the watchdog timer. * Single-step interrupt This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed. * Address match interrupt An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) Peripheral I/O interrupts A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts. * Bus collision detection interrupt This is an interrupt that the serial I/O bus collision detection generates. * DMA0 interrupt, DMA1 interrupt These are interrupts that DMA generates. * Key-input interrupt ___ A key-input interrupt occurs if either a falling edge or a both edge is input to the KI pin. * A-D conversion interrupt This is an interrupt that the A-D converter generates. * UART0, UART1, UART2 transmission interrupt These are interrupts that the serial I/O transmission generates. * UART0, UART1, UART2 reception interrupt These are interrupts that the serial I/O reception generates. * Timer A0 interrupt through timer A7 interrupt These are interrupts that timer A generates * Timer B0 interrupt through timer B5 interrupt These are interrupts that timer B generates. ________ ________ * INT0 interrupt through INT5 interrupt ______ ______ An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
32
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.10.2 shows the format for specifying the address. Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.
MSB
LSB Low address Mid address 0000 0000 High address 0000
Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3
Figure 1.10.2. Format for specifying interrupt vector addresses
* Fixed vector tables The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.10.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. Table 1.10.1. Interrupts assigned to the fixed vector tables and addresses of vector tables Interrupt source Undefined instruction Overflow BRK instruction Vector table addresses Address (L) to address (H) FFFDC16 to FFFDF16 FFFE016 to FFFE316 FFFE416 to FFFE716 Remarks Interrupt on UND instruction Interrupt on INTO instruction If the vector contains FF16, program execution starts from the address shown by the vector in the variable vector table There is an address-matching interrupt enable bit Do not use
Address match FFFE816 to FFFEB16 Single step (Note) FFFEC16 to FFFEF16 Watchdog timer FFFF016 to FFFF316 ________ DBC (Note) FFFF416 to FFFF716 Do not use _______ _______ NMI FFFF816 to FFFFB16 External interrupt by input to NMI pin Reset FFFFC16 to FFFFF16 Note: Interrupts used for debugging purposes only.
33
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Variable vector tables The addresses in the variable vector table can be modified, according to the user's settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.10.2 shows the interrupts assigned to the variable vector tables and addresses of vector tables. Table 1.10.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Software interrupt number Software interrupt number 0 Vector table address
Address (L) to address (H)
Interrupt source BRK instruction
Remarks Cannot be masked I flag
+0 to +3 (Note 1)
Software interrupt number 4 Software interrupt number 5 Software interrupt number 6 Software interrupt number 7 Software interrupt number 8 Software interrupt number 9 Software interrupt number 10
+16 to +19 (Note 1) +20 to +23 (Note 1) +24 to +27 (Note 1) +28 to +31 (Note 1) +32 to +35 (Note 1) +36 to +39 (Note 1) +40 to +43 (Note 1)
INT3 Timer B5 Timer B4 Timer B3 Timer A7 Timer A6 Timer A5/Bus collision detection (Note 2)
Software interrupt number 11 Software interrupt number 12 Software interrupt number 13 Software interrupt number 14 Software interrupt number 15 Software interrupt number 16 Software interrupt number 17 Software interrupt number 18 Software interrupt number 19 Software interrupt number 20 Software interrupt number 21 Software interrupt number 22 Software interrupt number 23 Software interrupt number 24 Software interrupt number 25 Software interrupt number 26 Software interrupt number 27 Software interrupt number 28 Software interrupt number 29 Software interrupt number 30 Software interrupt number 31 Software interrupt number 32 to Software interrupt number 63
+44 to +47 (Note 1) +48 to +51 (Note 1) +52 to +55 (Note 1) +56 to +59 (Note 1) +60 to +63 (Note 1) +64 to +67 (Note 1) +68 to +71 (Note 1) +72 to +75 (Note 1) +76 to +79 (Note 1) +80 to +83 (Note 1) +84 to +87 (Note 1) +88 to +91 (Note 1) +92 to +95 (Note 1) +96 to +99 (Note 1) +100 to +103 (Note 1) +104 to +107 (Note 1) +108 to +111 (Note 1) +112 to +115 (Note 1) +116 to +119 (Note 1) +120 to +123 (Note 1) +124 to +127 (Note 1) +128 to +131 (Note 1) to +252 to +255 (Note 1)
DMA0 DMA1 Key input interrupt A-D UART2 transmit / NACK (Note 3) UART2 receive / ACK (Note 3) UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer A1 Timer A2 Timer A3/INT4 (Note 4) Timer A4/INT5 (Note 4) Timer B0 Timer B1 Timer B2 INT0 INT1 INT2
Software interrupt
Cannot be masked I flag
Note 1: Address relative to address in interrupt table register (INTB). Note 2: It is selected by interrupt request cause select bit (bit 4 in address 035E16 ). Note 3: When IIC mode is selected, NACK and ACK interrupts are selected. Note 4: It is selected by interrupt request cause select bit (bit 6, 7 in address 035F16 ).
34
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selection bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.10.3 shows the memory map of the interrupt control registers.
Interrupt control register (Note2)
Symbol TBiIC(i=3 to 5) TAiIC(i=6, 7) TA5IC/BCNIC DMiIC(i=0, 1) KUPIC ADIC SiTIC(i=0 to 2) SiRIC(i=0 to 2) TAiIC(i=0 to 2) TBiIC(i=0 to 2) Address 004516 to 004716 004816, 004916 004A16 004B16, 004C16 004D16 004E16 005116, 005316, 004F16 005216, 005416, 005016 005516 to 005716 005A16 to 005C16 When reset XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002 XXXXX0002
b7
b6
b5
b4
b3
b2
b1
b0
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
000: 001: 010: 011: 100: 101: 110: 111: Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7
R
W
ILVL1
ILVL2
IR
Interrupt request bit
0 : Interrupt not requested 1 : Interrupt requested
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
b7
b6
b5
b4
b3
b2
b1
b0
0
Symbol Address INTiIC(i=0 to 2) 005D16 to 005F16 (i=3) 004416 TAiIC/INTjIC(i=3, 4) 005816, 005916 (j=4, 5) 005816, 005916
When reset XX00X0002 XX00X0002 XX00X0002 XX00X0002
Bit symbol
ILVL0
Bit name
Interrupt priority level select bit
b2 b1 b0
Function
0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7 0: Interrupt not requested 1: Interrupt requested 0 : Selects falling edge 1 : Selects rising edge Must always be set to "0"
R
W
ILVL1
ILVL2
IR
Interrupt request bit
(Note 1)
POL
Polarity select bit
Reserved bit Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.10.3. Interrupt control registers
35
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
36
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to "0" disables the interrupt. Table 1.10.3 shows the settings of interrupt priority levels and Table 1.10.4 shows the interrupt levels enabled, according to the contents of the IPL. The following are conditions under which an interrupt is accepted: * interrupt enable flag (I flag) = 1 * interrupt request bit = 1 * interrupt priority level > IPL The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.
Table 1.10.3. Settings of interrupt priority levels
Interrupt priority level select bit
b2 b1 b0
Table 1.10.4. Interrupt levels enabled according to the contents of the IPL
IPL
IPL2 IPL1 IPL0
Interrupt priority level
Priority order
Enabled interrupt priority levels
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Level 0 (interrupt disabled) Level 1 Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 High Low
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled Interrupt levels 5 and above are enabled Interrupt levels 6 and above are enabled Interrupt levels 7 and above are enabled All maskable interrupts are disabled
37
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
38
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt Sequence
An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed -- is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given: (1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 0000016. After this, the corresponding interrupt request bit becomes "0". (2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence in the temporary register (Note) within the CPU. (3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed) (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL. After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.10.4 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction
(a)
Interrupt sequence
(b)
Instruction in interrupt routine
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.
Figure 1.10.4. Interrupt response time
39
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.10.5. Table 1.10.5. Time required for executing the interrupt sequence
Interrupt vector address Even Even Odd (Note 2) Odd (Note 2) Stack pointer (SP) value Even Odd Even Odd
________
16-Bit bus, without wait 18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1)
8-Bit bus, without wait 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK Internal address bus Internal data bus Internal read signal Internal write signal The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs. Address 0000
Interrupt information
Indeterminate Indeterminate Indeterminate
SP-2 SP-2 contents
SP-4 SP-4 contents
vec vec contents
vec+2 vec+2 contents
PC
Figure 1.10.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.10.6 is set in the IPL.
Table 1.10.6. Relationship between interrupts without interrupt priority levels and IPL Interrupt sources without priority levels
_______
Value set in the IPL 7 0 Not changed
Watchdog timer, NMI
Reset
Other
40
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. Figure 1.10.6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).
Address MSB
Stack area LSB
Address MSB
Stack area LSB [SP] New stack pointer value
m-4 m-3 m-2 m-1 m m+1 Content of previous stack Content of previous stack [SP] Stack pointer value before interrupt occurs
m-4 m-3 m-2 m-1 m m+1
Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
Content of previous stack Content of previous stack
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 1.10.6. State of stack before and after acceptance of interrupt request
41
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.10.7 shows the operation of the saving registers. Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Address Stack area Sequence in which order registers are saved
[SP] - 5 (Odd) [SP] - 4 (Even) [SP] - 3(Odd) [SP] - 2 (Even) [SP] - 1(Odd) [SP] (Even) Finished saving registers in two operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH) (1) Saved simultaneously, all 16 bits (2) Saved simultaneously, all 16 bits
(2) Stack pointer (SP) contains odd number
Address Stack area Sequence in which order registers are saved
[SP] - 5 (Even) [SP] - 4(Odd) [SP] - 3 (Even) [SP] - 2(Odd) [SP] - 1 (Even) [SP] (Odd) Finished saving registers in four operations. Program counter (PCL) Program counter (PCM) Flag register (FLGL) Flag register (FLGH) Program counter (PCH)
(3) (4) (1) (2)
Saved simultaneously, all 8 bits
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 1.10.7. Operation of saving registers
42
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.10.8 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.
_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.10.8. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. Figure 1.10.9 shows the circuit that judges the interrupt priority level.
43
Mitsubishi microcomputers
M30220 Group
Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3/INT4 Timer A1 Timer B4 INT3 INT2 INT0 Timer B1 Timer A4/INT5 Timer A2 Timer B3 Timer B5 UART1 reception UART0 reception UART2 reception / ACK A-D conversion DMA1 Timer A5/Bus collision detection Timer A7 Timer A0 UART1 transmission UART0 transmission UART2 transmission / NACK Key input interrupt DMA0 Timer A6
Processor interrupt priority level (IPL)
Level 0 (initial value)
High
Priority of peripheral I/O interrupts (if priority levels are same)
Low
Interrupt request level judgment output
Interrupt enable flag (I flag) Address match Watchdog timer DBC NMI Reset
Interrupt request accepted
Figure 1.10.9. Maskable interrupts priorities (peripheral I/O interrupts)
44
Mitsubishi microcomputers
______
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INT Interrupt
______
INT Interrupt
________ ________
INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity select bit. ________ Of interrupt control registers, 005816 is used both as timer A3 and external interrupt INT4 input control register, and ________ 005916 is used both as timer A4 and as external interrupt INT5 input control register. Use the interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register 1 (address 035F16) - to specify which interrupt ________ request cause to select. When INT4 is selected as an interrupt source, the input port for it can be selected by bits 0 and ________ 1 of the interrupt source select register 0 (address 035E16). Similarly, when INT5 is selected as an interrupt source, the input port for it can be selected by bits 2 and 3 of the interrupt source select register 0 (address 035E16). After having set an interrupt request cause and interrupt input ports, be sure to set the corresponding interrupt request bit to "0" before enabling an interrupt. Either of the interrupt control registers - 005816, 005916 - has the polarity-switching bit. Be sure to set this bit to "0" to select an timer as the interrupt request cause. As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by setting _______ "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register 1 (035F16). To select two edges, set the polarity switching bit of the corresponding interrupt control register to `falling edge' ("0"). ________ ________ ________ When INT4 input pin select bits = "11", INT4 interrupt polarity switching bit = "0", and polarity select bit = "1" of the INT4 interrupt control register, an interrupt is generated by a rising edge on the input port when the exclusive pin is "H", as shown by "Single edge, Rise" in Figure 1.10.12. When the exclusive pin is "H", interrupts can only be generated by an ________ active transition on a single edge. The same applies to INT5. Figure 1.10.10 shows the interrupt request cause select register.
Interrupt request cause select register 0
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol IFSR0
Bit symbol
Address 035E16
When reset X00000002
Bit name
INT4 input pin select bit
Function 00: No INT4 input 01: P46 input enabled 10: P47 input enabled 11: P46, P47 input enabled 00: No INT5 input 01: P80 input enabled 10: P81 input enabled 11: P80, P81 input enabled
0 : Timer A5 1 : Bus collision detection Must always be set to "0"
RW
IFSR00 IFSR01 IFSR02 IFSR03 IFSR04
INT5 input pin select bit
Interrupt request cause select bitt
Reserved bit Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
Interrupt request cause select register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol IFSR1
Bit symbol
Address 035F16
When reset 0016
Bit name
INT0 interrupt polarity switching bit INT1 interrupt polarity switching bit INT2 interrupt polarity switching bit INT3 interrupt polarity switching bit INT4 interrupt polarity switching bit INT5 interrupt polarity switching bit Interrupt request cause select bit Interrupt request cause select bit
Function
0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : One edge 1 : Two edges 0 : Timer A3 1 : INT4 0 : Timer A4 1 : INT5
RW
IFSR10 IFSR11 IFSR12 IFSR13 IFSR14 IFSR15 IFSR16 IFSR17
Figure 1.10.10. Interrupt request cause select registers 0, 1
45
Mitsubishi microcomputers
______ _______
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INT Interrupt, NMI Interrupt
TAiOUT/INTi+1
Interrupt edge select bit
i=3, 4 Two edge detect
TAiIN/INTi+1
INTi+1 input pin select bit
Two edge detect
Interrupt request
________
________
Figure 1.10.11. Constitution of INT4 and INT5
Polarity select bit (bit4 of interrupt control register)
0: Falling edge
(Bits 4, 5 of interrupt request cause select register 1)
INT4, INT5 interrupt polarity switching bit
1: Rising edge "H" "L" "H" "L"
"H"
0: One edge 1: Two edges
"L" "H" "L"
"H" "L" "H" "L"
________
________
Figure 1.10.12. Typical timings in two input interrupt of INT4 and INT5 selected
______
NMI Interrupt
______ ______ ______
An NMI interrupt is generated when the input to the P77/NMI pin changes from "H" to "L". The NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P77 register (bit 7 at address 03ED16). This pin cannot be used as a normal port input.
46
Mitsubishi microcomputers
M30220 Group
Key Input Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key Input Interrupt
A key input interrupt request is generated when an active edge selected by the key input mode register's P1, P2 key input select bits occurs on one of input ports P10 to P17, P20 to P27, or P30 to P33 whose direction register is set for input and which has been enabled for key input by the key input enable bit. For P30 to P33, key input interrupt requests are always generated by a falling edge. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. When using an oscillator connected between XCIN--XCOUT and the corresponding port has been set to have a pullup, if the P1, P2 key input select bits (bits 0, 2 at address 012616) are set for "Two edges" and the P1, P2 key input enable bits (bits 1, 3 at address 012616) are "Enabled", pullups on P10 to P17 and P20 to P27 are automatically turned on and the port is pulled "H" for only a period of about 244 us (Note) at intervals of approximately 7.8 ms (Note), as shown in Figure 1.10.15. And if the key input enable bit (bit 1, 3 and 4 at the address 012616) is set to "enable", sometimes the interrupt request bit may be set to "1", therefore set the interrupt request bit to "0" with a program. Figure 1.10.13 shows a block diagram for key input interrupts. Note that when a "L" signal is applied to any pin which has had its key input enable bit set to "0" and is not processed for input inhibition, input to other pins are not detected as an interrupt. The fC32 is affected by a clock prescaler reset flag. Note : XCIN = 32.768kHZ
Port P10 direction register Port P10-P13 pull-up select bit P1 key input select bit P1 key input enable bit One-shot generating circuit 1/8 fC32
Pull-up transistor
Port P1, P2 pull-up select bit P1 key input select bit * P1 key input enable bit
CK Q D "1" "0"
Two edge detect
"1"
P1 key input enable bit
"0"
P10/KI0 Pull-up transistor Port P10 direction register
CK Q D "1" "0"
Two edge detect
"1"
"0"
P17/KI7 Pull-up transistor
D
Key input interrupt control register
(Address 004D16)
P2 key input enable bit Port P17 direction register
CK Q "1" "0" "1"
Two edge detect
Interrupt control circuit
"0"
Key input interrupt request
P20/KI8 Pull-up transistor Port P20 direction register
CK Q D "1" "1"
Two edge detect
"0" "0"
P27/KI15 Port P27 direction register Port P30 direction register Pull-up transistor P30/KI16 Port P3 pull-up select bit Port P30 direction register P3 key input enable bit
Pull-up transistor P33/KI19
Port P33 direction register
Figure 1.10.13. Block diagram of key input interrupt
47
Mitsubishi microcomputers
M30220 Group
Key Input Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key input mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KUPM
Bit symbol
Address 012616
When reset 011000002
Bit name
P1 key input select bit (Note 1) P1 key input enable bit P2 key input select bit (Note 1) P2 key input enable bit P3 key input enable bit P120 to P123 pull-up (Note 3) P124 to P127 pull-up (Note 3) P130 to P132 pull-up (Note 3)
Function
0 : Falling edge 1 : Two edges (Note 2) 0 : Disable 1 : Enable 0 : Falling edge 1 : Two edges (Note 2) 0 : Disable 1 : Enable 0 : Disable 1 : Enable The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
R
W
P1KIS
P1KIE P2KIS P2KIE P3KIE
PUP12L PUP12H PUP13
Note 1 : If this bit is set for "Two edges" when the corresponding port has been specified to have a pullup, the port is automatically pulled high intermittently. Operating sub-clock. Note 2 : When this bit is set for "Two edges" and the input from either of the corresponding pin is "L", if the pullup control register 0 of the corresponding port (bit 2 to 5 at the address 03FC16) is changed, there may be the thing that the key input interruption request is set to "1". Note 3 : The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register.
Figure 1.10.14. Key input mode register
Intermittent pull-up operation starts Not pulled high
Pull-up control
Pulled high
Direction register
Key input select bit
Key input enable bit
Output
Falling edge
Disable
Input
Two edges
Enable
Approx. 7.8ms (Note 1) Pull-up
("H" : Pulled high "L" : Not pulled high)
Approx. 7.8ms (Note 1)
Approx. 244s (Note 1)(Note 2)
Approx. 244s (Note 1)
Key input value latch Note 1 : XCIN = 32.768kHz
Key input value latch
Note 2 : There may be the thing that the key input interrupt request bit is set to "1" when input "L" in the first key input value latch timing.
Figure 1.10.15. Intermittent pull-up operation
48
Mitsubishi microcomputers
M30220 Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC) for an address match interrupt varies depending on the instruction being executed. Figure 1.10.16 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol AIER Bit symbol
Address 000916 Bit name Address match interrupt 0 enable bit Address match interrupt 1 enable bit
When reset XXXXXX002 Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled RW
AIER0 AIER1
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated.
Address match interrupt register i (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol RMAD0 RMAD1
Address 001216 to 001016 001616 to 001416
When reset X0000016 X0000016
Function Address setting register for address match interrupt
Values that can be set R W 0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminated.
Figure 1.10.16. Address match interrupt-related registers
49
Mitsubishi microcomputers
M30220 Group
Precautions for Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts (1) Reading address 0000016
* When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.
(2) Setting the stack pointer
* The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in _______ the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat_______ ing any interrupts including the NMI interrupt is prohibited.
_______
(3) The NMI interrupt
_______ _______
*The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a resistor (pull-up) if unused. Be sure to work on it. _______ * The NMI pin also serves as P77, which is exclusively input. Reading the contents of the P7 register allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time _______ when the NMI interrupt is input. _______ * Do not reset the CPU with the input to the NMI pin being in the "L" state. _______ * Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to _______ the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned down. _______ * Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to _______ the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved. In this instance, the CPU is returned to the normal state by a later interrupt. _______ * Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
* Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0 ________ through INT5 regardless of the CPU operation clock. ________ ________ * When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". Figure 1.10.17 shows the procedure for ______ changing the INT interrupt generate factor.
50
Mitsubishi microcomputers
M30220 Group
Precautions for Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear the interrupt enable flag to "0" (Disable interrupt)
Set the interrupt priority level to level 0 (Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7 (Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to "1" (Enable interrupt)
______
Figure 1.10.17. Switching condition of INT interrupt request
51
Mitsubishi microcomputers
M30220 Group
Precautions for Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(5) Rewrite the interrupt control register
* To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
* When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
52
Mitsubishi microcomputers
M30220 Group
Watchdog Timer Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an error due to the prescaler. With XIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (16 or 128) X watchdog timer count (32768) BCLK With XCIN chosen for BCLK Watchdog timer period = prescaler dividing ratio (2) X watchdog timer count (32768) BCLK For example, suppose that BCLK runs at 10 MHz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 52.4 ms. The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or state are released. Figure 1.11.1 shows the block diagram of the watchdog timer. Figure 1.11.2 shows the watchdog timerrelated registers.
Prescaler
"CM07 = 0" "WDC7 = 0"
1/16
BCLK
1/128
"CM07 = 0" "WDC7 = 1"
Watchdog timer
Watchdog timer interrupt request
"CM07 = 1"
1/2
Write to the watchdog timer start register (address 000E16)
Set to "7FFF16"
RESET
Figure 1.11.1. Block diagram of watchdog timer
53
Mitsubishi microcomputers
M30220 Group
Watchdog Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol WDC
Bit symbol
Address 000F16
Bit name
When reset 000XXXXX2
Function RW
High-order bit of watchdog timer
Reserved bit Reserved bit
WDC7
Must always be set to "0" Must always be set to "0"
Prescaler select bit
0 : Divided by 16 1 : Divided by 128
Watchdog timer start register
b7 b0
Symbol WDTS
Address 000E16
When reset Indeterminate
RW
Function The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to "7FFF16" regardless of whatever value is written.
Figure 1.11.2. Watchdog timer control and start registers
54
Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.12.1 shows the block diagram of the DMAC. Table 1.12.1 shows the DMAC specifications. Figures 1.12.2 to 1.12.4 show the registers used by the DMAC.
Address bus
DMA0 source pointer SAR0(20) (addresses 002216 to 002016) DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416)
DMA0 forward address pointer (20) (Note)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20) (addresses 003216 to 003016) DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416)
(addresses 002916, 002816) DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 forward address pointer (20) (Note)
(addresses 003916, 003816) DMA1 transfer counter TCR1 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.12.1. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level. The DMA transfer doesn't affect any interrupts either. If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. For details, see the description of the DMA request bit.
55
Mitsubishi microcomputers
M30220 Group
DMAC
Table 1.12.1. DMAC specifications Item No. of channels Transfer memory space Specification 2 (cycle steal method) * From any address in the 1M bytes space to a fixed address * From a fixed address to any address in the 1M bytes space * From a fixed address to a fixed address (Note that DMA-related registers [002016 to 003F16] cannot be accessed) 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________ ________
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Maximum No. of bytes transferred DMA request factors (Note)
Falling edge of INT0 or INT1 or both edge Timer A0 to timer A7 interrupt requests Timer B0 to timer B5 interrupt requests UART0 transfer and reception interrupt requests UART1 transfer and reception interrupt requests UART2 transfer and reception interrupt requests A-D conversion interrupt requests Software triggers Channel priority DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously Transfer unit 8 bits or 16 bits Transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) Transfer mode * Single transfer mode After the transfer counter underflows, the DMA enable bit turns to "0", and the DMAC turns inactive * Repeat transfer mode After the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. The DMAC remains active unless a "0" is written to the DMA enable bit. DMA interrupt request generation timing When an underflow occurs in the transfer counter Active When the DMA enable bit is set to "1", the DMAC is active. When the DMAC is active, data transfer starts every time a DMA transfer request signal occurs. Inactive * When the DMA enable bit is set to "0", the DMAC is inactive. * After the transfer counter underflows in single transfer mode Reload timing for forward ad- At the time of starting data transfer immediately after turning the DMAC active, the value of one of source pointer and destination pointer - the one specified for the dress pointer and transfer forward direction - is reloaded to the forward direction address pointer, and the value counter of the transfer counter reload register is reloaded to the transfer counter. Writing to register Registers specified for forward direction transfer are always write enabled. Registers specified for fixed address transfer are write-enabled when the DMA enable bit is "0". Reading the register Can be read at any time. However, when the DMA enable bit is "1", reading the register set up as the forward register is the same as reading the value of the forward address pointer. Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the interrupt priority level.
56
Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA0 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM0SL
Address 03B816
When reset 0016
Bit symbol
Bit name DMA request cause select bit
b3 b2 b1 b0
Function
0 0 0 0 : Falling edge of INT0 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2 0 1 0 1 : Timer A3 0 1 1 0 : Timer A4 (DMS=0) /two edges of INT0 pin (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /Timer B3 (DMS=1) 1 0 0 0 : Timer B1 (DMS=0) /Timer B4 (DMS=1) 1 0 0 1 : Timer B2 (DMS=0) /Timer B5 (DMS=1) 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 transmit
R
W
DSEL0
DSEL1
DSEL2
DSEL3
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMS DSR
DMA request cause expansion select bit Software DMA request bit
0 : Normal 1 : Expanded cause If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
Figure 1.12.2. DMAC register (1)
57
Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA1 request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DM1SL
Address 03BA16
When reset 0016
Bit symbol
Bit name
Function
b3 b2 b1 b0
R
W
DSEL0
DMA request cause select bit
DSEL1
DSEL2
DSEL3
0 0 0 0 : Falling edge of INT1 pin 0 0 0 1 : Software trigger 0 0 1 0 : Timer A0 0 0 1 1 : Timer A1 0 1 0 0 : Timer A2(DMS=0) /timer A5(DMS=1) 0 1 0 1 : Timer A3(DMS=0) /timer A6 (DMS=1) 0 1 1 0 : Timer A4 (DMS=0) /timer A7 (DMS=1) 0 1 1 1 : Timer B0 (DMS=0) /two edges of INT1 (DMS=1) 1 0 0 0 : Timer B1 1 0 0 1 : Timer B2 1 0 1 0 : UART0 transmit 1 0 1 1 : UART0 receive 1 1 0 0 : UART2 transmit 1 1 0 1 : UART2 receive 1 1 1 0 : A-D conversion 1 1 1 1 : UART1 receive
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMS
DMA request cause expansion select bit
0 : Normal 1 : Expanded cause
DSR
Software DMA request bit
If software trigger is selected, a DMA request is generated by setting this bit to "1" (When read, the value of this bit is always "0")
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DMiCON(i=0,1)
Address 002C16, 003C16
When reset 00000X002
Bit symbol
DMBIT DMASL DMAS DMAE DSD DAD
Bit name Transfer unit bit select bit
Repeat transfer mode select bit DMA request bit (Note 1) DMA enable bit Source address direction select bit (Note 3) 0 : 16 bits 1 : 8 bits
Function
R
W
0 : Single transfer 1 : Repeat transfer 0 : DMA not requested 1 : DMA requested 0 : Disabled 1 : Enabled 0 : Fixed 1 : Forward
(Note 2)
Destination address 0 : Fixed direction select bit (Note 3) 1 : Forward
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: DMA request can be cleared by resetting the bit. Note 2: This bit can only be set to "0". Note 3: Source address direction select bit and destination address direction select bit cannot be set to "1" simultaneously.
Figure 1.12.3. DMAC register (2)
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Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAi source pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol SAR0 SAR1
Address 002216 to 002016 003216 to 003016
When reset Indeterminate Indeterminate
Function * Source pointer Stores the source address
Transfer address specification 0000016 to FFFFF16
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMAi destination pointer (i = 0, 1)
(b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0
Symbol DAR0 DAR1
Address 002616 to 002416 003616 to 003416
When reset Indeterminate Indeterminate RW
Function * Destination pointer Stores the destination address
Transfer address specification 0000016 to FFFFF16
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
DMAi transfer counter (i = 0, 1)
(b15) b7 (b8) b0 b7 b0
Symbol TCR0 TCR1
Address 002916, 002816 003916, 003816
When reset Indeterminate Indeterminate RW
Function * Transfer counter Set a value one less than the transfer count
Transfer count specification 000016 to FFFF16
Figure 1.12.4. DMAC register (3)
59
Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area (source read) and the bus cycle in which the data is written to memory or to the SFR area (destination write). The number of read and write bus cycles depends on the source and destination addresses. Also, the bus cycle itself is longer when software waits are inserted. (a) Effect of source and destination addresses When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) Effect of software wait When the SFR area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK. Figure 1.12.5 shows the example of the transfer cycles for a source read. For convenience, the destination write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.
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Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) 8-bit transfers 16-bit transfers and the source address is even.
BCLK
(Internal signal)
Address bus
(Internal signal)
CPU use
Source
Destination
Dummy cycle
CPU use
RD signal
(Internal signal)
WR signal
(Internal signal)
Data bus
(Internal signal)
CPU use
Source
Destination
Dummy cycle
CPU use
(2) 16-bit transfers and the source address is odd
BCLK
(Internal signal)
Address bus
(Internal signal)
CPU use
Source
Source + 1 Destination
Dummy cycle
CPU use
RD signal
(Internal signal)
WR signal
(Internal signal)
Data bus
(Internal signal)
CPU use
Source
Source + 1 Destination
Dummy cycle
CPU use
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
(Internal signal)
Address bus
(Internal signal)
CPU use
Source
Destination
Dummy cycle
CPU use
RD signal
(Internal signal)
WR signal
(Internal signal)
Data bus
(Internal signal)
CPU use
Source
Destination
Dummy cycle
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
BCLK
(Internal signal)
Address bus
(Internal signal)
CPU use
Source
Source + 1
Destination
Dummy cycle
CPU use
RD signal
(Internal signal)
WR signal
(Internal signal)
Data bus
(Internal signal)
CPU use
Source
Source + 1
Destination
Dummy cycle
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.12.5. Example of the transfer cycles for a source read
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Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) DMAC transfer cycles Any combination of even or odd transfer read and write addresses is possible. Table 1.12.2 shows the number of DMAC transfer cycles. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k Table 1.12.2. No. of DMAC transfer cycles Transfer unit 8-bit transfers (DMBIT= "1") 16-bit transfers (DMBIT= "0") Access address Even Odd Even Odd No. of read cycles 1 1 1 2 No. of read cycles 1 1 1 2
Coefficient j, k Internal ROM/RAM No wait 1 Internal memory Internal ROM/RAM With wait 2 SFR area 2
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Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMA enable bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations at the time data transfer starts immediately after DMAC is turned active. (1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the forward direction - to the forward direction address pointer. (2) Reloads the value of the transfer counter reload register to the transfer counter. Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA enable bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request factors for each channel. DMA request factors include the following. * Factors effected by using the interrupt request signals from the built-in peripheral functions and software DMA factors (internal factors) effected by a program. * External factors effected by utilizing the input from external interrupt signals. For the selection of DMA request factors, see the descriptions of the DMAi factor selection register. The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless of whether the DMA enable bit is set "1" or "0"). It turns to "0" immediately before data transfer starts. In addition, it can be set to "0" by use of a program, but cannot be set to "1". There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is changed. The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit. Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to turn to "1" due to several factors. Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately before the transfer starts.
(2) External factors
An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on which DMAC channel is used). Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from these pins to become the DMA transfer request signals. The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes with the trailing edge of the input signal to each INTi pin, for example). With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data transfer starts similarly to the state in which an internal factor is selected.
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Mitsubishi microcomputers
M30220 Group
DMAC
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer. When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus access, then DMA1 starts data transfer and gives the bus right to the CPU. An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer request signals due to external factors concurrently occur. Figure 1.12.6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum cycles at the time when DMA transmission request signals due to external factors concurrently occur.
BCLK
DMA0
DMA1
CPU
INT0
Obtainm ent of the bus right
DMA0 request bit
INT1
DMA1 request bit
Figure 1.12.6. An example of DMA transfer effected by external factors
64
Mitsubishi microcomputers
M30220 Group
Timer Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
There are fourteen 16-bit timers. These timers can be classified by function into timers A (eight) and timers B (six). All these timers function independently. Figures 1.13.1 and 1.13.2 show the block diagram of timers.
fC1 Clock prescaler fC32 1/32 Reset fC132 fc132 clock select bit (bit 4 at address 000716)
XIN 1/8 1/4 f1 f8 f32 fC132
f1 f8 f32
XCIN
Clock prescaler reset flag (bit 7 at address 038116) set to "1"
Timer B2 overflow
* Timer mode * One-shot mode * PWM mode
Timer A0 interrupt TA0IN
Noise filter
Timer A0
* Event counter mode
Port P0 real time output trigger
* Timer mode * One-shot mode * PWM mode
Timer A1 interrupt Timer A1
TA1IN
Noise filter
* Event counter mode * Timer mode * One-shot mode * PWM mode
Port P1 real time output trigger
Timer A2 interrupt TA2IN
Noise filter
Timer A2
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A3 interrupt TA3IN
(Note 1)
Noise filter
Timer A3
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A4 interrupt TA4IN
(Note 2)
Noise filter
Timer A4
* Event counter mode
* Timer mode * One-shot mode * PWM mode
Timer A5 interrupt TA5IN
Noise filter
Timer A5
* Event counter mode
Port P2 real time output trigger
* Timer mode * One-shot mode * PWM mode
TA6IN
Noise filter
Timer A6
* Event counter mode * Timer mode * One-shot mode * PWM mode
Timer A6 interrupt
Port P12 real time output trigger
TA7IN
Noise filter
Timer A7
* Event counter mode
Timer A7 interrupt
Timer B5 overflow
Note 1: The TA3IN pin (P47) is shared with INT4 pin, so be careful. Note 2: The TA4IN pin (P81) is shared with INT5 pin, so be careful.
Figure 1.13.1. Timer A block diagram
65
Mitsubishi microcomputers
M30220 Group
Timer
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
fC1 Clock prescaler fC32 1/32 Reset fC132 fc132 clock select bit (bit 4 at address 000716)
XIN 1/8 1/4 f1 f8 f32 fC132
f1 f8 f32
XCIN
Clock prescaler reset flag (bit 7 at address 038116) set to "1"
Timer A0 to timer A4
* Timer mode * Pulse width measuring mode
TB0IN
Noise filter
Timer B0 interrupt Timer B0
* Event counter mode
* Timer mode * Pulse width measuring mode
TB1IN
Noise filter
Timer B1 interrupt
Timer B1
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B2 interrupt
TB2IN
Noise filter
Timer B2
* Event counter mode
Timer A5 to timer A7
* Timer mode * Pulse width measuring mode
Timer B3 interrupt
TB3IN
Noise filter
Timer B3
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B4 interrupt
TB4IN
Noise filter
Timer B4
* Event counter mode
* Timer mode * Pulse width measuring mode
Timer B5 interrupt
TB5IN
Noise filter
Timer B5
* Event counter mode
Figure 1.13.2. Timer B block diagram
66
Mitsubishi microcomputers
M30220 Group
Timer A Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.13.3 shows the block diagram of timer A. Figures 1.13.4 to 1.13.8 show the timer A-related registers. Use the timer Ai mode register (i = 0 to 7) bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer over flow. * One-shot timer mode: The timer stops counting when the count reaches "000016". * Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source selection
f1 f8 f32 fC132
Polarity selection
TAiIN (i = 0 to 7)
* Timer * One shot * PWM * Timer (gate function) * Event counter
Data bus low-order bits Low-order 8 bits Reload register (16) High-order 8 bits
Counter (16) Clock selection
Up count/down count Always down count except in event counter mode
Count start flag
(Address 034016, 038016) Down count
5)
TBm overflow
(m = 2 when i 4, m = 5 when i
TAj overflow
(j = i -1. Note, however, that j = 4 when i = 0, j = 6 when i = 5, j = 5 when i = 7)
External trigger
Up/down flag
(Address 034416, 038416)
TAi Timer A0 Timer A1 Timer A2 Timer A3 Timer A4 Timer A5 Timer A6 Timer A7 Addresses 038716 038616 038916 038816 038B16 038A16 038D16 038C16 038F16 038E16 034716 034616 034916 034816 034B16 034A16 TAj Timer A4 Timer A0 Timer A1 Timer A2 Timer A3 Timer A7 Timer A5 Timer A6 TAk Timer A1 Timer A2 Timer A3 Timer A4 Timer A0 Timer A6 Timer A7 Timer A5 TBm Timer B2 Timer B2 Timer B2 Timer B2 Timer B2 Timer B5 Timer B5 Timer B5
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4, k = 7 when i = 5, k = 6 when i = 7)
TAiOUT
(i = 0 to 7)
Pulse output
Toggle flip-flop
Figure 1.13.3. Block diagram of timer A
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TAiMR(i=0 to 4) (i=5 to 7)
Address 039616 to 039A16 035616 to 035816
When reset 0016 0016
Bit symbol
TMOD0
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation (PWM) mode
RW
TMOD1
MR0 MR1 MR2 MR3 TCK0 TCK1
Function varies with each operation mode
Count source select bit (Function varies with each operation mode)
Figure 1.13.4. Timer A-related registers (1)
67
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai register (Note 1)
(b15) b7 (b8) b0 b7 b0
Symbol TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7
Address 038716,038616 038916,038816 038B16,038A16 038D16,038C16 038F16,038E16 034716,034616 034916,034816 034B16,034A16
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
Function * Timer mode Counts an internal count source * Event counter mode Counts pulses from an external source or timer overflow * One-shot timer mode Counts a one shot width * Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator * Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator
RW
000016 to FFFF16 000016 to FFFF16 000016 to FFFF16 (Note 2, Note 4) 000016 to FFFE16 (Note 3, Note 4)
0016 to FE16
(High-order address) (Low-order address)
0016 to FF16
(Note 3, Note 4)
Note 1: Read and write data in 16-bit units. Note 2: When the timer Ai register is set to "000016", the counter does not operate and the timer Ai interrupt request is not generated. When the pulse is set to output, the pulse does not output from the TAiOUT pin. Note 3: When the timer Ai register is set to "000016", the pulse width modulator does not operate and the output level of the TAiOUT pin remains "L" level, therefore the timer Ai interrupt request is not generated. This also occurs in the 8-bit pulse width modulator mode when the significant 8 high-order bits in the timer Ai register are set to "0016". Note 4: Use MOV instruction to write to this register.
Count start flag 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR0
Address 038016
When reset 0016
Bit symbol
Bit name
Function
RW
TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
0 : Stops counting 1 : Starts counting
Count start flag 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR1
Address 034016
When reset 000XX0002
Bit symbol
Bit name
Function
RW
TA5S TA6S TA7S
Timer A5 count start flag Timer A6 count start flag Timer A7 count start flag
0 : Stops counting 1 : Starts counting
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
TB3S TB4S TB5S
Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag
0 : Stops counting 1 : Starts counting
Figure 1.13.5. Timer A-related registers (2)
68
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Up/down flag 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF0
Address 038416
When reset 0016
Bit symbol TA0UD TA1UD TA2UD TA3UD TA4UD TA2P TA3P TA4P
Bit name Timer A0 up/down flag Timer A1 up/down flag Timer A2 up/down flag Timer A3 up/down flag Timer A4 up/down flag
Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause
RW
Timer A2 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled Timer A3 two-phase pulse signal processing select bit When not using the two-phase Timer A4 two-phase pulse pulse signal processing function, signal processing select bit set the select bit to "0"
Note : Use MOV instruction to write to this register.
Up/down flag 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UDF1
Address 034416
When reset XX0XX0002
Bit symbol TA5UD TA6UD TA7UD
Bit name Timer A5 up/down flag Timer A6 up/down flag Timer A7 up/down flag
Function 0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
TA7P
Timer A7 two-phase pulse 0 : two-phase pulse signal processing disabled signal processing select bit 1 : two-phase pulse signal processing enabled When not using the two-phase pulse signal processing function, set the select bit to "0"
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note : Use MOV instruction to write to this register.
One-shot start flag 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF0
Address 038216
When reset 00X000002
Bit symbol
TA0OS TA1OS TA2OS TA3OS TA4OS
Bit name Timer A0 one-shot start flag Timer A1 one-shot start flag Timer A2 one-shot start flag Timer A3 one-shot start flag Timer A4 one-shot start flag
Function 1 : Timer start When read, the value is "0"
RW
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. TA0TGL TA0TGH
Timer A0 event/trigger select bit
b7 b6
0 0 : Input on TA0IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA4 overflow is selected 1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to "0".
Figure 1.13.6. Timer A-related registers (3)
69
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
One-shot start flag 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ONSF1
Address 034216
When reset 00XXX0002
Bit symbol
TA5OS TA6OS TA7OS
Bit name Timer A5 one-shot start flag Timer A6 one-shot start flag Timer A7 one-shot start flag
Function 1 : Timer start When read, the value is "0"
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate. TA5TGL TA5TGH
Timer A5 event/trigger select bit
b7 b6
0 0 : Input on TA5IN is selected (Note) 0 1 : TB5 overflow is selected 1 0 : TA6 overflow is selected 1 1 : TA7 overflow is selected
Note: Set the corresponding port direction register to "0".
Trigger select register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR0
Address 038316
When reset 0016
Bit symbol
TA1TGL
Bit name Timer A1 event/trigger select bit
b1 b0
Function 0 0 : Input on TA1IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TA2 overflow is selected
b3 b2
RW
TA1TGH TA2TGL
Timer A2 event/trigger select bit
TA2TGH TA3TGL TA3TGH
0 0 : Input on TA2IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA1 overflow is selected 1 1 : TA3 overflow is selected
b5 b4
Timer A3 event/trigger select bit
0 0 : Input on TA3IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA2 overflow is selected 1 1 : TA4 overflow is selected
b7 b6
TA4TGL TA4TGH
Timer A4 event/trigger select bit
0 0 : Input on TA4IN is selected (Note) 0 1 : TB2 overflow is selected 1 0 : TA3 overflow is selected 1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Trigger select register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TRGSR1
Address 034316
When reset XXXX00002
Bit symbol
TA6TGL
Bit name Timer A6 event/trigger select bit
Function
b1 b0
RW
TA6TGH TA7TGL
0 0 : Input on TA6IN is selected (Note) 0 1 : TB5 overflow is selected 1 0 : TA5 overflow is selected 1 1 : TA7 overflow is selected
b3 b2
Timer A7 event/trigger select bit
TA7TGH
0 0 : Input on TA7IN is selected (Note) 0 1 : TB5 overflow is selected 1 0 : TA5 overflow is selected 1 1 : TA6 overflow is selected
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note: Set the corresponding port direction register to "0".
Figure 1.13.7. Timer A-related registers (4)
70
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol
Bit name
Function
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
CPSR
Clock prescaler reset flag
0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Figure 1.13.8. Timer A-related registers (5)
71
Mitsubishi microcomputers
M30220 Group
Timer A (1) Timer mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer counts an internally generated count source. (See Table 1.13.1.) Figure 1.13.9 shows the timer Ai mode register in timer mode. Table 1.13.1. Specifications of timer mode Item Count source Count operation Divide ratio Count start condition Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer Specification f1, f8, f32, fC132 * Down count * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) When the timer underflows Programmable I/O port or gate input Programmable I/O port or pulse output Count value can be read out by reading timer Ai register * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) * Gate function Counting can be started and stopped by the TAiIN pin's input signal * Pulse output function Each time the timer underflows, the TAiOUT pin's polarity is reversed
Select function
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Symbol TAiMR(i=0 to 4) (i=5 to 7) Bit symbol TMOD0 TMOD1 MR0
Address When reset 039616 to 039A16 0016 035616 to 035816 0016 Bit name Function
b1 b0
RW
Operation mode select bit Pulse output function select bit
0 0 : Timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
b4 b3
MR1
Gate function select bit
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
MR2
1 0 : Timer counts only when TAiIN pin is held "L" (Note 3) 1 1 : Timer counts only when TAiIN pin is held "H" (Note 3) 0 (Must always be "0" in timer mode) Count source select bit
b7 b6
MR3 TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: The bit can be "0" or "1". Note 3: Set the corresponding port direction register to "0" .
Figure 1.13.9. Timer Ai mode register in timer mode
72
Mitsubishi microcomputers
M30220 Group
Timer A (2) Event counter mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0, A1, A5 and A6 can count a single-phase external signal. Timers A2, A3, A4 and A7 can count a single-phase and a twophase external signal. Table 1.13.2 lists timer specifications when counting a single-phase external signal. Figure 1.13.10 shows the timer Ai mode register in event counter mode. Table 1.13.3 lists timer specifications when counting a two-phase external signal. Figure 1.13.11 shows the timer Ai mode register in event counter mode. Table 1.13.2. Timer specifications in event counter mode (when not processing two-phase pulse signal) Item Specification Count source * External signals input to TAiIN pin (effective edge can be selected by software) * TB2 overflow, TB5 overflow, TAj overflow, TAk overflow Count operation * Up count or down count can be selected by external signal or software * When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note) Divide ratio 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer overflows or underflows TAiIN pin function Programmable I/O port or count source input TAiOUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer Ai register Write to timer * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time) Select function * Free-run count function Even when the timer overflows or underflows, the reload register content is not reloaded to it * Pulse output function Each time the timer overflows or underflows, the TAiOUT pin's polarity is reversed Note: This does not apply when the free-run function is selected.
Timer Ai mode register (When not using two-phase pulse signal processing)
Symbol Address TAiMR(i = 0 to 4) 039616 to 039A16 (i = 5 to 7) 035616 to 035816 When reset 0016 0016
b7
b6
b5
b4
b3
b2
b1
b0
0
01
Bit symbol TMOD0 TMOD1 MR0
Bit name Operation mode select bit Pulse output function select bit
b1 b0
Function 0 1 : Event counter mode (Note 1) 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 2) (TAiOUT pin is a pulse output pin) 0 : Counts external signal's falling edge 1 : Counts external signal's rising edge 0 : Up/down flag's content 1 : TAiOUT pin's input signal (Note 4)
RW
MR1 MR2 MR3 TCK0 TCK1
Count polarity select bit (Note 3) Up/down switching cause select bit
0 (Must always be "0" in event counter mode) Count operation type select bit 0 : Reload type 1 : Free-run type
Invalid in event counter mode Can be "0" or "1"
Note 1: In event counter mode, the count source is selected by the event / trigger select bit. (addresses 034216, 034316, 038216, and 038316) Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Valid only when counting an external signal. Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When "H", the upcount is activated. Set the corresponding port direction register to "0".
Figure 1.13.10. Timer Ai mode register in event counter mode
73
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.13.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, A4 and A7) Item Count source Count operation Specification * Two-phase pulse signals input to TAiIN or TAiOUT pin * Up count or down count can be selected by two-phase pulse signal * When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note 1) 1/ (FFFF16 - n + 1) for up count 1/ (n + 1) for down count n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) Timer overflows or underflows Two-phase pulse input Two-phase pulse input Count value can be read out by reading timer A2, A3, A4 or A7 register * When counting stopped When a value is written to timer A2, A3, A4 or A7 register, it is written to both reload register and counter * When counting in progress When a value is written to timer A2, A3, A4 or A7 register, it is written to only reload register. (Transferred to counter at next reload time.) * Normal processing operation The timer counts up rising edges or counts down falling edges on the TAiIN pin when input signal on the TAiOUT pin is "H"
Divide ratio Count start condition Count stop condition
Interrupt request generation timing
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Select function (Note 2)
TAiOUT TAiIN (i=2, 3, 7)
Up count
Up count
Up count
Down count
Down count
Down count
* Multiply-by-4 processing operation If the phase relationship is such that the TAiIN pin goes "H" when the input signal on the TAiOUT pin is "H", the timer counts up rising and falling edges on the TAiOUT and TAiIN pins. If the phase relationship is such that the TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count up all edges Count down all edges
TAiIN (i=3, 4)
Count up all edges Count down all edges
Note 1: This does not apply when the free-run function is selected. Note 2: Timer A3 alone can be selected. Timer A2 and timer A7 are fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation.
74
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Ai mode register (When using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
010001
Symbol Address When reset TAiMR(i = 2 to 4) 039816 to 039A16 0016 (i = 7) 035816 0016
Bit symbol
TMOD0 TMOD1 MR0 MR1 MR2 MR3
TCK0
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
RW
0 (Must always be "0" when using two-phase pulse signal processing) 0 (Must always be "0" when using two-phase pulse signal processing)
1 (Must always be "1" when using two-phase pulse signal processing)
0 (Must always be "0" when using two-phase pulse signal processing)
Count operation type select bit Two-phase pulse processing operation select bit (Note 1)(Note 2) 0 : Reload type 1 : Free-run type 0 : Normal processing operation 1 : Multiply-by-4 processing operation
TCK1
Note 1 : This bit is valid for timer A3 mode register. Timer A2 and timer A7 are fixed to normal processing operation, and timer A4 is fixed to multiply-by-4 processing operation. Note 2 : When performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (addresses 038416 and 034416) is set to "1". Also, always be sure to set the event/trigger select bit (addresses 038316 and 034316) to "00".
Figure 1.13.11. Timer Ai mode register in event counter mode
75
Mitsubishi microcomputers
M30220 Group
Timer A (3) One-shot timer mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer operates only once. (See Table 1.13.4.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.13.12 shows the timer Ai mode register in one-shot timer mode. Table 1.13.4. Timer specifications in one-shot timer mode Item Count source Count operation Specification f1, f8, f32, fC132 * The timer counts down * When the count reaches 000016, the timer stops counting after reloading a new count * If a trigger occurs when counting, the timer reloads a new count and restarts counting 1/n n : Set value * An external trigger is input * The timer overflows * The one-shot start flag is set (= 1) * A new count is reloaded after the count has reached 000016 * The count start flag is reset (= 0) The count reaches 000016 Programmable I/O port or trigger input Programmable I/O port or pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)
Divide ratio Count start condition
Count stop condition
Interrupt request generation timing
TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
10
Symbol Address When reset TAiMR(i = 0 to 4) 039616 to 039A16 0016 (i = 5 to 7) 035616 to 035816 0016 Bit symbol TMOD0 TMOD1 MR0 Pulse output function select bit Bit name Operation mode select bit
b1 b0
Function 1 0 : One-shot timer mode 0 : Pulse is not output (TAiOUT pin is a normal port pin) 1 : Pulse is output (Note 1) (TAiOUT pin is a pulse output pin)
0 : Falling edge of TAiIN pin's input signal (Note 3) 1 : Rising edge of TAiIN pin's input signal (Note 3)
RW
MR1 MR2
External trigger select bit (Note 2) Trigger select bit
0 : One-shot start flag is valid 1 : Selected by event/trigger select register
MR3 TCK0 TCK1
0 (Must always be "0" in one-shot timer mode) Count source select bit
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132
Note 1: The settings of the corresponding port register and port direction register are invalid. Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216, 034316, 038216 and 038316). If timer overflow is selected, this bit can be "1" or "0" . Note 3: Set the corresponding port direction register to "0" .
Figure 1.13.12. Timer Ai mode register in one-shot timer mode
76
Mitsubishi microcomputers
M30220 Group
Timer A (4) Pulse width modulation (PWM) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.13.5.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.13.13 shows the timer Ai mode register in pulse width modulation mode. Figure 1.13.14 shows the example of how a 16-bit pulse width modulator operates. Figure 1.13.15 shows the example of how an 8bit pulse width modulator operates. Table 1.13.5. Timer specifications in pulse width modulation mode
Item
Count source Count operation
Specification
f1, f8, f32, fC132 * The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) * The timer reloads a new count at a rising edge of PWM pulse and continues counting * The timer is not affected by a trigger that occurs when counting * High level width n / fj n : Set value fj=f1, f8, f32, fC132 * Cycle time (216-1) / fj fixed * High level width n (m+1) / fj n : values set to timer Ai register's high-order address * Cycle time (28-1) (m+1) / fj m : values set to timer Ai register's low-order address * External trigger is input * The timer overflows * The count start flag is set (= 1) * The count start flag is reset (= 0) PWM pulse goes "L" Programmable I/O port or trigger input Pulse output When timer Ai register is read, it indicates an indeterminate value * When counting stopped When a value is written to timer Ai register, it is written to both reload register and counter * When counting in progress When a value is written to timer Ai register, it is written to only reload register (Transferred to counter at next reload time)
16-bit PWM 8-bit PWM Count start condition
Count stop condition Interrupt request generation timing TAiIN pin function TAiOUT pin function Read from timer Write to timer
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
11
1
Symbol TAiMR(i=0 to 4) (i=5 to 7)
Address When reset 039616 to 039A16 0016 035616 to 035816 0016
Bit symbol
Bit name
Function
b1 b0
RW
TMOD0 TMOD1 MR0 MR1 MR2
Operation mode select bit
1 1 : PWM mode
1 (Must always be "1" in PWM mode) External trigger select bit (Note 1) Trigger select bit
0: Falling edge of TAiIN pin's input signal (Note 2) 1: Rising edge of TAiIN pin's input signal (Note 2)
0: Count start flag is valid 1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator
b7 b6
MR3
16/8-bit PWM mode select bit
Count source select bit
TCK0
TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses 034216, 034316, 038216 and 038316 ). If timer overflow is selected, this bit can be "1" or "0". Note 2: Set the corresponding port direction register to "0" .
Figure 1.13.13. Timer Ai mode register in pulse width modulation mode
77
Mitsubishi microcomputers
M30220 Group
Timer A
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Condition : Reload register = 000316, when external trigger (rising edge of TAiIN pin input signal) is selected
1 / fj X (2
16
- 1)
Count source
TAiIN pin input signal
"H" "L"
Trigger is not generated by this signal 1 / fj X n
PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fj : Frequency of count source (f1, f8, f32, fC132) Cleared to "0" when interrupt request is accepted, or cleared by software Note: n = 000016 to FFFE16.
Figure 1.13.14. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216 Reload register low-order 8 bits = 0216 External trigger (falling edge of TAiIN pin input signal) is selected
1 / fj X (m + 1) X (2 8 - 1) Count source (Note1)
TAiIN pin input signal
"H" "L"
1 / fj X (m + 1) Underflow signal of 8-bit prescaler (Note2) "L"
"H"
1 / fj X (m + 1) X n PWM pulse output from TAiOUT pin Timer Ai interrupt request bit
"H" "L" "1" "0"
fj : Frequency of count source (f1, f8, f32, fC132)
Cleared to "0" when interrupt request is accepted, or cleaerd by software
Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 0016 to FF16; n = 0016 to FE16.
Figure 1.13.15. Example of how an 8-bit pulse width modulator operates
78
Mitsubishi microcomputers
M30220 Group
Timer B Timer B
Figure 1.13.16 shows the block diagram of timer B. Figures 1.13.17 and 1.13.18 show the timer B-related registers. Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows: * Timer mode: The timer counts an internal count source. * Event counter mode: The timer counts pulses from an external source or a timer overflow. * Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or pulse width.
Data bus high-order bits Data bus low-order bits Low-order 8 bits High-order 8 bits
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock source selection
f1 f8 f32 fC132
TBiIN (i = 0 to 5)
* Timer * Pulse period/pulse width measurement
Reload register (16)
* Event counter Polarity switching and edge pulse Count start flag (address 038016) Counter reset circuit Can be selected in only event counter mode TBj overflow (j = i - 1. Note, however, j = 2 when i = 0, j = 5 when i = 3) TBi Timer B0 Timer B1 Timer B2 Timer B3 Timer B4 Timer B5
Counter (16)
Address 039116 039016 039316 039216 039516 039416 035116 035016 035316 035216 035516 035416
TBj Timer B2 Timer B0 Timer B1 Timer B5 Timer B3 Timer B4
Figure 1.13.16. Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address TBiMR(i = 0 to 2) 039B16 to 039D16 TBiMR(i = 3 to 5) 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width measurement mode 1 1 : Must not be set
R
W
MR0 MR1 MR2
Function varies with each operation mode
(Note 1) (Note 2)
MR3 TCK0 TCK1 Count source select bit (Function varies with each operation mode)
Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.13.17. Timer B-related registers (1)
79
Mitsubishi microcomputers
M30220 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer Bi register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol TB0 TB1 TB2 TB3 TB4 TB5
Address 039116, 039016 039316, 039216 039516, 039416 035116, 035016 035316, 035216 035516, 035416
When reset Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
Values that can be set
Function
* Timer mode Counts the timer's period * Event counter mode Counts external pulses input or a timer overflow * Pulse period / pulse width measurement mode Measures a pulse period or width
RW
000016 to FFFF16
000016 to FFFF16
Note: Read and write data in 16-bit units.
Count start flag 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR 0
Address 038016
When reset 0016
Bit symbol TA0S TA1S TA2S TA3S TA4S TB0S TB1S TB2S
Bit name
Timer A0 count start flag Timer A1 count start flag Timer A2 count start flag Timer A3 count start flag Timer A4 count start flag Timer B0 count start flag Timer B1 count start flag Timer B2 count start flag
Function
0 : Stops counting 1 : Starts counting
RW
Count start flag 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol TABSR1
Address 034016
When reset 000XX0002
Bit symbol TA5S TA6S TA7S
Bit name Timer A5 count start flag Timer A6 count start flag Timer A7 count start flag
Function 0 : Stops counting 1 : Starts counting
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
TB3S TB4S TB5S
Timer B3 count start flag Timer B4 count start flag Timer B5 count start flag
0 : Stops counting 1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol CPSRF
Address 038116
When reset 0XXXXXXX2
Bit symbol Nothing is assigned.
Bit name
Function
RW
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
CPSR Clock prescaler reset flag 0 : No effect 1 : Prescaler is reset (When read, the value is "0")
Figure 1.13.18. Timer B-related registers (2)
80
Mitsubishi microcomputers
M30220 Group
Timer B (1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.13.6.) Figure 1.13.19 shows the timer Bi mode register in timer mode. Table 1.13.6. Timer specifications in timer mode Item Count source Count operation Specification f1, f8, f32, fC132 * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting 1/(n+1) n : Set value Count start flag is set (= 1) Count start flag is reset (= 0) The timer underflows Programmable I/O port Count value is read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Divide ratio Count start condition Count stop condition Interrupt request generation timing TBiIN pin function Read from timer Write to timer
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol TBiMR(i=0 to 2) (i=3 to 5) Bit symbol TMOD0 TMOD1 MR0 MR1 MR2
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit name
Operation mode select bit
b1 b0
Function
0 0 : Timer mode
R
W
Invalid in timer mode Can be "0" or "1" 0 (Must always be "0" in timer mode ; i = 0, 3)
Nothing is assiigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 1) (Note 2)
MR3
Invalid in timer mode. In an attempt to write to this bit, write "0". The value, if read in timer mode, turns out to be indeterminate. Count source select bit
b7 b6
TCK0 TCK1
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132
Note 1: Timer B0, timer B3. Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.13.19. Timer Bi mode register in timer mode
81
Mitsubishi microcomputers
M30220 Group
Timer B (2) Event counter mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.13.7.) Figure 1.13.20 shows the timer Bi mode register in event counter mode. Table 1.13.7. Timer specifications in event counter mode Specification * External signals input to TBiIN pin * Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software Count operation * Counts down * When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing The timer underflows TBiIN pin function Read from timer Write to timer Count source input Count value can be read out by reading timer Bi register * When counting stopped When a value is written to timer Bi register, it is written to both reload register and counter * When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time) Item Count source
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol TBiMR(i=0 to 2) (i=3 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit
b1 b0
Function
0 1 : Event counter mode
b3 b2
R
W
Count polarity select bit (Note 1)
MR1
0 0 : Counts external signal's falling edges 0 1 : Counts external signal's rising edges 1 0 : Counts external signal's falling and rising edges 1 1 : Must not be set
(Note 2)
MR2
0 (Must always be "0" in event counter mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Invalid in event counter mode. In an attempt to write to this bit, write "0". The value, if read in event counter mode, turns out to be indeterminate. Invalid in event counter mode. Can be "0" or "1". Event clock select 0 : Input from TBiIN pin (Note 4) 1 : TBj overflow
(j = i - 1; however, j = 2 when i = 0, j = 5 when i = 3)
(Note 3)
MR3
TCK0 TCK1
Note 1: Valid only when input from the TBiIN pin is selected as the event clock. If timer's overflow is selected, this bit can be "0" or "1". Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5. Note 4: Set the corresponding port direction register to "0".
Figure 1.13.20. Timer Bi mode register in event counter mode
82
Mitsubishi microcomputers
M30220 Group
Timer B (3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.13.8.) Figure 1.13.21 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure 1.13.22 shows the operation timing when measuring a pulse period. Figure 1.13.23 shows the operation timing when measuring a pulse width. Table 1.13.8. Timer specifications in pulse period/pulse width measurement mode Item Count source Count operation Specification f1, f8, f32, fC132 * Up count * Counter value "000016" is transferred to reload register at measurement pulse's effective edge and the timer continues counting Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing * When measurement pulse's effective edge is input (Note 1) * When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to "1". The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Bi mode register.) TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register's content (measurement result) (Note 2) Write to timer Cannot be written to Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting. Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
10
Symbol TBiMR(i=0 to 2) (i=3 to 5)
Address 039B16 to 039D16 035B16 to 035D16
When reset 00XX00002 00XX00002
Bit symbol
TMOD0 TMOD1 MR0
Bit name
Operation mode select bit Measurement mode select bit
b1 b0
Function
1 0 : Pulse period / pulse width measurement mode
b3 b2
R
W
MR1
0 0 : Pulse period measurement (Interval between measurement pulse's falling edge to falling edge) 0 1 : Pulse period measurement (Interval between measurement pulse's rising edge to rising edge) 1 0 : Pulse width measurement (Interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : Must not be set
(Note 2)
MR2
0 (Must always be "0" in pulse period/pulse width measurement mode; i = 0, 3) Nothing is assigned (i = 1, 2, 4, 5). In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
(Note 3)
MR3 TCK0 TCK1
Timer Bi overflow flag ( Note 1) Count source select bit
0 : Timer did not overflow 1 : Timer has overflowed
b7 b6
0 0 : f1 0 1 : f8 1 0 : f32 1 1 : fC132
Note 1: The timer Bi overflow flag changes to "0" when the count start flag is "1" and a value is written to the timer Bi mode register. This flag cannot be set to "1" by software. Note 2: Timer B0, timer B3. Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 1.13.21. Timer Bi mode register in pulse period/pulse width measurement mode
83
Mitsubishi microcomputers
M30220 Group
Timer B
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
When measuring measurement pulse time interval from falling edge to falling edge
Count source
Measurement pulse
"H" "L" Transfer (indeterminate value) Transfer (measured value)
Reload register transfer timing
counter (Note 1) (Note 1) (Note 2)
Timing at which counter reaches "000016" Count start flag
"1" "0"
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 1.13.22. Operation timing when measuring a pulse period
Count source
Measurement pulse
"H" "L"
Transfer (indeterminate value) Transfer (measured value) Transfer (measured value) Transfer (measured value)
Reload register transfer timing
counter
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
Timing at which counter reaches "000016"
"1" "0"
Count start flag
Timer Bi interrupt request bit
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software. Timer Bi overflow flag
"1" "0"
Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.
Figure 1.13.23. Operation timing when measuring a pulse width
84
Mitsubishi microcomputers
M30220 Group
Real time Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Real time Port
When real time port output is selected, the real time port data written to the port Pm register is latched into the real time port latch each time the corresponding timer Ai underflows, with the data output from each corresponding port. The real time port data is written to the corresponding port Pm register. When the real time port mode select bit changes state from "0" to "1", the value of the real time port latch becomes "0", which is output from the corresponding pin. It is when timer Ai underflows first that the real time port data is output. If the real time port data is modified when the real time port function is enabled, the modified value is output when timer Ai underflows next time. The port functions as an ordinary port when the real time port function is disabled. Make sure timer Ai for real time port output is set for timer mode, and is set to have "no gate function" using the gate function select bit. Also, before setting the real time port mode select bit to "1", temporarily turn off the timer Ai used and write its set value to the timer Ai register. Figure 1.14.1 shows the block diagram for real time port output. Figure 1.14.2 shows the real time control register.
Pm4 to Pm7 real time port mode select bit
TQ
Data bus f1 f8 f32 fC132 Timer Bj overflow Timer Ak overflow
Port latch
Pm7
D
Pm4 to Pm7 real time port mode select bit
TQ * Timer mode
Data bus TAiIN
Noise filter
Timer Ai Timer Ai interrupt
Port latch
Pm4
D
Pm0 to Pm3 real time port mode select bit Timer Ai+1 overflow Data bus j=2, k=4, 0, m=0, 1 when i=0, 1 j=5, k=7, 5, m=2, 12 when i=5, 6 Timer Ai mode register's set value used in real time port Timer Ai mode register (Addresses 035616, 035716, 039616 and 039716)
b7 b6 b5 b4 b3 b2 b1 b0
TQ
Pm3
Port latch
D
Pm0 to Pm3 real time port mode select bit
TQ
Data bus
Port latch
Pm0
D
0
0
0
0 Real time port latch
Figure 1.14.1. Block diagram for real time port output
85
Mitsubishi microcomputers
M30220 Group
Real time Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Real time port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RTP
Bit symbol
Address 03FF16
When reset 0016
Bit name
P00 to P03 real time port mode select bit P04 to P07 real time port mode select bit P10 to P13 real time port mode select bit P14 to P17 real time port mode select bit P20 to P23 real time port mode select bit P24 to P27 real time port mode select bit P120 to P123 real time port mode select bit
Function
0 : I/O port 1 : Real time port output (Note)
RW
RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7
P124 to P127 real time port mode select bit Note : The corresponding port direction register is invalidated.
Figure 1.14.2. Real time port control register
Counter content (hex)
Start count
Underflow
Underflow
Time
Real time port mode select bit Count start flag
"1" "0" "1" "0"
Timer Ai interrupt request bit (i=0, 1, 5, 6) Real time port output
"1" "0" 0016 5516 AA16
Writing to port Pm register (m=0, 1, 2, 12) Value to port Pm (example) AA16 5516 AA16
Figure 1.14.3. Timing in real time port output operation
86
Mitsubishi microcomputers
M30220 Group
Serial I/O Serial I/O
Serial I/O is configured as three channels: UART0, UART1, UART2.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.15.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.15.2 and 1.15.3 show the block diagram of the transmit/receive unit. UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions. UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if the TxD pin and the RxD pin are different in level. Table 1.15.1 shows the comparison of functions of UART0 through UART2, and Figures 1.15.4 to 1.15.8 show the registers related to UARTi. Note: SIM : Subscriber Identity Module
Table 1.15.1. Comparison of functions of UART0 through UART2
Function CLK polarity selection LSB first / MSB first selection Continuous receive mode selection Transfer clock output from multiple pins selection Serial data logic switch Sleep mode selection TxD, RxD I/O polarity switch TxD, RxD port output format Parity error signal output Bus collision detection UART0 Possible Possible Possible Impossible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) UART1 Possible Possible Possible Possible Impossible Possible Impossible CMOS output Impossible Impossible (Note 3) (Note 1) (Note 1) (Note 1) (Note 1) UART2 Possible Possible Possible Impossible Possible Impossible Possible N-channel open-drain output Possible Possible (Note 4) (Note 4) (Note 1) (Note 2) (Note 1)
Note 1: Only when clock synchronous serial I/O mode. Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode. Note 3: Only when UART mode. Note 4: Using for SIM interface.
87
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART0)
RxD0
UART reception
TxD0
1/16
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A116)
Clock synchronous type
1/16
Reception control circuit
Receive clock
Transmit/ receive unit
1 / (n0+1)
External
UART transmission
Clock synchronous type
Transmission control circuit
Transmit clock
Clock synchronous type
1/2
(when internal clock is selected)
Clock synchronous type (when internal clock is selected)
CLK0
CLK polarity reversing circuit CTS/RTS disabled CTS/RTS selected
Clock synchronous type (when external clock is selected)
CTS0 / RTS0
Vcc CTS/RTS disabled
RTS0
CTS0
(UART1)
RxD1
Clock source selection
f1 f8 f32 Bit rate generator Internal (address 03A916)
1/16
TxD1
UART reception Reception control circuit Receive clock Transmit/ receive unit
Clock synchronous type UART transmission
1/16
1 / (n1+1)
External
Clock synchronous type Clock synchronous type
1/2 (when internal clock is selected)
Transmission control circuit
Transmit clock
CLK1 CTS1 / RTS1/ CLKS1
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS disabled CTS/RTS selected Clock output pin select switch VCC CTS/RTS disabled
RTS1 CTS1
(UART2)
RxD2
RxD polarity reversing circuit
UART reception
1/16
Clock source selection f1 f8 f32 Bit rate generator Internal (address 037916)
Clock synchronous type UART transmission
1/16
Reception control circuit
Receive clock
TxD polarity reversing circuit Transmit/ receive unit
TxD2
1 / (n2+1)
External
Clock synchronous type Clock synchronous type
1/2
Transmission control circuit
Transmit clock
(when internal clock is selected)
CLK2
CLK polarity reversing circuit
Clock synchronous type (when internal clock is selected)
Clock synchronous type (when external clock is selected)
CTS/RTS selected
CTS/RTS disabled
CTS2 / RTS2
Vcc CTS/RTS disabled
RTS2
CTS2
n0 : Values set to UART0 bit rate generator (BRG0) n1 : Values set to UART1 bit rate generator (BRG1) n2 : Values set to UART2 bit rate generator (BRG2)
Figure 1.15.1. Block diagram of UARTi (i = 0 to 2)
88
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous type UART (7 bits) UART (8 bits)
1SP
PAR disabled
Clock synchronous type
UART (7 bits)
UARTi receive register
RxDi
SP 2SP
SP
PAR
PAR enabled
UART
UART (9 bits)
Clock synchronous type UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi receive buffer register Address 03A616 Address 03A716 Address 03AE16 Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UARTi transmit buffer register Address 03A216 Address 03A316 Address 03AA16 Address 03AB16
UART (8 bits) UART (9 bits)
UART (9 bits)
Clock synchronous type
2SP SP SP 1SP
PAR
PAR enabled
UART
TxDi
PAR disabled Clock synchronous type
UART (7 bits)
UART (7 bits) UART (8 bits) Clock synchronous type
UARTi transmit register
"0"
SP: Stop bit PAR: Parity bit
Figure 1.15.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
89
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
No reverse
RxD2
RxD data reverse circuit
Reverse
Clock synchronous type
1SP SP 2SP SP
PAR
PAR disabled
Clock synchronous type
UART (7 bits) UART (8 bits)
UART(7 bits)
UART2 receive register
PAR enabled
UART
UART (9 bits)
Clock synchronous type
UART (8 bits) UART (9 bits)
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 receive buffer register Address 037E16 Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
D8
D7
D6
D5
D4
D3
D2
D1
D0
UART2 transmit buffer register Address 037A16 Address 037B16
UART (8 bits) UART (9 bits)
PAR enabled
UART (9 bits) UART
Clock synchronous type
2SP SP SP 1SP
PAR
PAR disabled
Clock synchronous type
"0"
UART (7 bits) UART (8 bits)
Clock synchronous type
UART(7 bits)
UART2 transmit register
Error signal output disable
No reverse
Error signal output circuit
Error signal output enable Reverse
TxD data reverse circuit
TxD2
SP: Stop bit PAR: Parity bit
Figure 1.15.3. Block diagram of UART2 transmit/receive unit
90
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit buffer register (Note)
(b15) b7 (b8) b0 b7 b0
Symbol U0TB U1TB U2TB
Address 03A316, 03A216 03AB16, 03AA16 037B16, 037A16
When reset Indeterminate Indeterminate Indeterminate Function RW
Transmit data Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turn out to be indeterminate. Note: Use MOV instruction to write to this register.
UARTi receive buffer register
(b15) b7 (b8) b0 b7 b0
Symbol U0RB U1RB U2RB
Address 03A716, 03A616 03AF16, 03AE16 037F16, 037E16
When reset Indeterminate Indeterminate Indeterminate Function (During UART mode) Receive data
Bit symbol
Bit name
Function (During clock synchronous serial I/O mode) Receive data
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". ABT OER FER PER SUM Arbitration lost detecting flag (Note 2) 0 : Not detected 1 : Detected Invalid 0 : No overrun error 1 : Overrun error found 0 : No framing error 1 : Framing error found 0 : No parity error 1 : Parity error found 0 : No error 1 : Error found
Overrun error flag (Note 1) 0 : No overrun error 1 : Overrun error found Framing error flag (Note 1) Invalid Parity error flag (Note 1) Error sum flag (Note 1) Invalid Invalid
Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016, 03A816 and 037816) are set to "0002" or the receive enable bit is set to "0". (Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out. Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value of this bit is "0".
UARTi bit rate generator (Note 1, Note 2)
b7 b0
Symbol U0BRG U1BRG U2BRG
Address 03A116 03A916 037916 Function
When reset Indeterminate Indeterminate Indeterminate Values that can be set 0016 to FF16 RW
Assuming that set value = n, BRGi divides the count source by n+1 Note 1: Write a value to this register while transmit/receive halts. Note 2: Use MOV instruction to write to this register.
Figure 1.15.4. Serial I/O-related registers (1)
91
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name Serial I/O mode select bit
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set 0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
0 : Internal clock 1 : External clock (Note) Invalid
Odd/even parity select bit Invalid
PRYE SLEP
Parity enable bit Sleep select bit
Invalid Must always be "0"
Note : Set the corresponding port direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol SMD0 SMD1 SMD2
Bit name Serial I/O mode select bit
Function (During clock synchronous serial I/O mode) Must be fixed to 001
b2 b1 b0
Function (During UART mode)
b2 b1 b0
RW
0 0 0 : Serial I/O invalid 0 1 0 : (Note 1) 0 1 1 : Must not be set 1 1 1 : Must not be set
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Must not be set 0 1 1 : Must not be set 1 1 1 : Must not be set Must always be "0" 0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse Usually set to "0"
CKDIR Internal/external clock select bit STPS PRY Stop bit length select bit
0 : Internal clock 1 : External clock (Note 2) Invalid
Odd/even parity select bit Invalid
PRYE IOPOL
Parity enable bit TxD, RxD I/O polarity reverse bit
Invalid 0 : No reverse 1 : Reverse Usually set to "0"
Note 1: Bit 2 to bit 0 are set to "0102" when I2C mode is used. Note 2: Set the corresponding port direction register to "0".
Figure 1.15.5. Serial I/O-related registers (2)
92
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC0(i=0,1) Bit symbol CLK0 CLK1 CRS
Address When reset 03A416, 03AC16 0816 Function (During clock synchronous serial I/O mode)
b1 b0 b1 b0
Bit name BRG count source select bit
Function (During UART mode) 0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
RW
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
CTS/RTS function select bit
TXEPT
0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0: TXDi pin is CMOS output 1: TXDi pin is N-channel open-drain output
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P60 and P64 function as programmable I/O port) 0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
NCH
Data output select bit
CKPOL
CLK polarity select bit
Must always be "0"
UFORM Transfer format select bit 0 : LSB first 1 : MSB first
Must always be "0"
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C0 Bit symbol CLK0 CLK1 CRS CTS/RTS function select bit
Address 037C16
When reset 0816 Function (During clock synchronous serial I/O mode) Function (During UART mode)
b1 b0
Bit name BRG count source select bit
RW
b1 b0
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
0 0 : f1 is selected 0 1 : f8 is selected 1 0 : f32 is selected 1 1 : Must not be set
Valid when bit 4 = "0" 0 : CTS function is selected (Note 1) 1 : RTS function is selected (Note 2)
TXEPT
0 : Data present in transmit 0 : Data present in transmit register Transmit register empty register (during transmission) (during transmission) flag 1 : No data present in transmit 1 : No data present in transmit register (transmission completed) register (transmission completed) 0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0: TXDi pin is CMOS output open-drain output
CRD
CTS/RTS disable bit
0 : CTS/RTS function enabled 1 : CTS/RTS function disabled (P73 functions programmable I/O port) 0 : TXDi pin is CMOS output open-drain output 0 : Transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : Transmit data is output at rising edge of transfer clock and receive data is input at falling edge
Nothing is assigned.
CKPOL
: TXDi pin is N-channel 1: to be "0". In an attempt to write to this bit, write1"0". The value, if read, turns out TXDi pin is N-channel
CLK polarity select bit
Must always be "0"
UFORM Transfer format select bit 0 : LSB first 1 : MSB first (Note 3)
0 : LSB first 1 : MSB first
Note 1: Set the corresponding port direction register to "0". Note 2: The settings of the corresponding port register and port direction register are invalid. Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.15.6. Serial I/O-related registers (3)
93
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiC1(i=0,1)
Address 03A516,03AD16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register
RW
RE RI
Receive enable bit Receive complete flag
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2C1
Address 037D16
When reset 0216
Bit symbol TE TI
Bit name Transmit enable bit Transmit buffer empty flag
Function (During clock synchronous serial I/O mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled 0 : No reverse 1 : Reverse Must always be "0"
Function (During UART mode) 0 : Transmission disabled 1 : Transmission enabled 0 : Data present in transmit buffer register 1 : No data present in transmit buffer register 0 : Reception disabled 1 : Reception enabled 0 : No data present in receive buffer register 1 : Data present in receive buffer register 0 : Transmit buffer empty (TI = 1) 1 : Transmit is completed (TXEPT = 1) Must always be "0"
RW
RE RI
Receive enable bit Receive complete flag
U2IRS UART2 transmit interrupt cause select bit
U2RRM UART2 continuous receive mode enable bit
U2LCH Data logic select bit U2ERE Error signal output enable bit
0 : No reverse 1 : Reverse 0 : Output disabled 1 : Output enabled
Figure 1.15.7. Serial I/O-related registers (4)
94
Mitsubishi microcomputers
M30220 Group
Serial I/O
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol UCON
Address 03B016
When reset X00000002
Bit symbol U0IRS
Bit name UART0 transmit interrupt cause select bit UART1 transmit interrupt cause select bit
Function (During clock synchronous serial I/O mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
Function (During UART mode)
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1) 0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed (TXEPT = 1)
RW
U1IRS
0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed
(TXEPT = 1)
U0RRM UART0 continuous receive mode enable bit
0 : Continuous receive mode disabled 1 : Continuous receive mode enable 0 : Continuous receive mode disabled 1 : Continuous receive mode enabled Valid when bit 5 = "1" 0 : Clock output to CLK1 1 : Clock output to CLKS1 0 : Normal mode
(CLK output is CLK1 only)
Must always be "0"
U1RRM UART1 continuous receive mode enable bit
Must always be "0"
CLKMD0 CLK/CLKS select bit 0
Invalid
CLKMD1 CLK/CLKS select bit 1 (Note)
Must always be "0"
1 : Transfer clock output from multiple pins function selected Reserved bit Must always be set to "0"
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. Note: When using multiple pins to output the transfer clock, the following requirements must be met: * UART1 internal/external clock select bit (bit 3 at address 03A816) = "0".
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U2SMR
Address 037716
When reset 0016
Bit symbol IICM ABC BBS LSYN
Bit name IIC mode selection bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit
Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : IIC mode 0 : Update per bit 1 : Update per byte
0 : STOP condition detected 1 : START condition detected
Function (During UART mode) Must always be "0" Must always be "0" Must always be "0"
RW
(Note)
0 : Disabled 1 : Enabled Must always be "0"
Must always be "0" 0 : Rising edge of transfer clock 1 : Underflow signal of timer A0 0 : No auto clear function 1 : Auto clear at occurrence of bus collision 0 : Ordinary 1 : Falling edge of RxD2
ABSCS
ACSE
Must always be "0"
SSS
Must always be "0"
Reserved bit Note: Nothing but "0" may be written.
Must always be set to "0"
Figure 1.15.8. Serial I/O-related registers (5)
95
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode (1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.15.2 and 1.15.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.15.9 shows the UARTi transmit/receive mode register. Table 1.15.2. Specifications of clock synchronous serial I/O mode (1) Specification * Transfer data length: 8 bits * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/ 2(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "1") : Input from CLKi pin _______ _______ _______ _______ Transmission/reception control * CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition * To start transmission, the following requirements must be met: _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _______ _______ _ When CTS function selected, CTS input level = "L" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" Reception start condition * To start reception, the following requirements must be met: _ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" _ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" * Furthermore, if external clock is selected, the following requirements must also be met: _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "0": CLKi input level = "H" _ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = "1": CLKi input level = "L" * When transmitting Interrupt request _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at generation timing address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed _ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving _ Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 2) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change. Item Transfer data format Transfer clock
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
96
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.15.3. Specifications of clock synchronous serial I/O mode (2) Item Select function Specification * CLK polarity selection Whether transmit data is output/input timing at the rising edge or falling edge of thetransfer clock can be selected * LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected * Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register * Transfer clock output from multiple pins selection (UART1) UART1 transfer clock can be chosen by software to be output from one of the two pins set * Switching serial data logic (UART2) Whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. * TxD, RxD I/O polarity reverse (UART2) This function is reversing TxD port output and RxD port input. All I/O data level is reversed.
97
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol UiMR(i=0,1) Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE SLEP
Address 03A016, 03A816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode 0 (Must always be "0" in clock synchronous serial I/O mode)
Note : Set the corresponding port direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
001
Symbol U2MR Bit symbol SMD0 SMD1 SMD2 CKDIR STPS PRY PRYE IOPOL
Address 037816 Bit name
When reset 0016 Function
b2 b1 b0
RW
Serial I/O mode select bit
0 0 1 : Clock synchronous serial I/O mode 0 : Internal clock 1 : External clock (Note2)
Internal/external clock select bit
Invalid in clock synchronous serial I/O mode TxD, RxD I/O polarity reverse bit (Note1) 0 : No reverse 1 : Reverse
Note1 : Usually set to "0". Note2 : Set the corresponding port direction register to "0".
Figure 1.15.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
98
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.15.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This table shows the pin functions when the transfer clock output from multiple pins function is not selected. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this pin is in floating state.) Table 1.15.4. Input/output pin functions in clock synchronous serial I/O mode (when transfer clock output from multiple pins is not selected)
Pin name Function Method of selection (Outputs dummy data when performing reception only) Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "1" Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16, bit 2 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1" TxDi Serial data output (P63, P67, P70) Serial data input RxDi (P62, P66, P71) CLKi Transfer clock output (P61, P65, P72) Transfer clock input
CTSi/RTSi CTS input (P60, P64, P73)
RTS output Programmable I/O port
99
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1" "0" "1" "0" Transferred from UARTi transmit buffer register to UARTi transmit register "H" Data is set in UARTi transmit buffer register
Transmit enable bit (TE) Transmit buffer empty flag (Tl) CTSi
"L"
TCLK
Stopped pulsing because CTS = "H"
Stopped pulsing because transfer enable bit = "0"
CLKi
TxDi Transmit register empty flag (TXEPT)
"1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Transmit interrupt "1" request bit (IR) "0"
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * Internal clock is selected. * CTS function is selected. * CLK polarity select bit = "0". * Transmit interrupt cause select bit = "0". Tc = TCLK = 2(n + 1) / fi fi: frequency of BRGi count source (f1, f8, f32) n: value set to BRGi
* Example of receive timing (when external clock is selected)
"1" "0" "1" "0" "1" "0" "H"
Receive enable bit (RE) Transmit enable bit (TE) Transmit buffer empty flag (Tl) RTSi
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
"L"
1 / fEXT
Receive data is taken in
CLKi
RxDi Receive complete "1" flag (Rl) "0" Receive interrupt request bit (IR)
"1" "0"
D0 D1 D2 D3 D4 D5 D6 D7
Transferred from UARTi receive register to UARTi receive buffer register
D0 D1 D2
D3 D4 D5
Read out from UARTi receive buffer register
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings: * External clock is selected. * RTS function is selected. * CLK polarity select bit = "0". fEXT: frequency of external clock Meet the following conditions are met when the CLK input before data reception = "H" * Transmit enable bit "1" * Receive enable bit "1" * Dummy data write to UARTi transmit buffer register
Figure 1.15.10. Typical transmit/receive timings in clock synchronous serial I/O mode
100
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Polarity select function As shown in Figure 1.15.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) allows selection of the polarity of the transfer clock.
* When CLK polarity select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 1: The CLK pin level when not transferring data is "H".
* When CLK polarity select bit = "1"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7
Note 2: The CLK pin level when not transferring data is "L".
Figure 1.15.11. Polarity of transfer clock (b) LSB first/MSB first select function As shown in Figure 1.15.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16, 037C16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
* When transfer format select bit = "0"
CLKi TXDi RXDi D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7
LSB first
D7
* When transfer format select bit = "1"
CLKi TXDi RXDi D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0
MSB first
D0
Note: This applies when the CLK polarity select bit = "0".
Figure 1.15.12. Transfer format
101
Mitsubishi microcomputers
M30220 Group
Clock synchronous serial I/O mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(c) Transfer clock output from multiple pins function (UART1) This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.15.3.) The multiple pins function is valid only when the internal clock is selected for UART1. Note that when _______ _______ this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
TXD1 (P67)
CLKS1 (P64) CLK1 (P65) IN CLK IN CLK
Note: This applies when the internal clock is selected and transmission is performed only in clock synchronous serial I/O mode.
Figure 1.15.13. The transfer clock output from the multiple pins function usage (d) Continuous receive mode If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.
(e) Serial data logic switch function (UART2) When the data logic select bit (bit6 at address 037D16) = "1", and writing to transmit buffer register or reading from receive buffer register, data is reversed. Figure 1.15.14 shows the example of serial data logic switch timing.
*When LSB first
Transfer clock TxD2
"H" "L" "H"
(no reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
TxD2
"H"
(reverse) "L"
D0
D1
D2
D3
D4
D5
D6
D7
Figure 1.15.14. Serial data logic switch timing
102
Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode (2) Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Tables 1.15.5 and 1.15.6 list the specifications of the UART mode. Figure 1.15.15 shows the UARTi transmit/receive mode register. Table 1.15.5. Specifications of UART Mode (1) Item Transfer data format Specification * Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected * Start bit: 1 bit * Parity bit: Odd, even, or nothing as selected * Stop bit: 1 bit or 2 bits as selected * When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = "0") : fi/16(n+1) (Note 1) fi = f1, f8, f32 * When external clock is selected (bit 3 at addresses 03A016, 03A816 ="1") : fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
_______ _______ _______ _______
Transfer clock
Transmission/reception control * CTS function, RTS function, CTS and RTS function invalid: selectable Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = "1" - Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = "0" _______ _______ - When CTS function selected, CTS input level = "L" Reception start condition * To start reception, the following requirements must be met: - Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = "1" - Start bit detection Interrupt request * When transmitting generation timing - Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at address 037D16) = "0": Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed - Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at address 037D16) = "1": Interrupts requested when data transmission from UARTi transfer register is completed * When receiving - Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed Error detection * Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out * Framing error This error occurs when the number of stop bits set is not detected * Parity error This error occurs when if parity is enabled, the number of 1's in parity and character bits does not match the number of 1's set * Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered Note 1: `n' denotes the value 0016 to FF16 that is set to the UARTi bit rate generator. Note 2: fEXT is input from the CLKi pin. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that the UARTi receive interrupt request bit does not change.
103
Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
Table 1.15.6. Specifications of UART Mode (2) Item Select function
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Specification * Sleep mode selection (UART0, UART1) This mode is used to transfer data to and from one of multiple slave microcomputers * Serial data logic switch (UART2) This function is reversing logic value of transferring data. Start bit, parity bit and stop bit are not reversed. * TXD, RXD I/O polarity switch (UART2) This function is reversing TXD port output and RXD port input. All I/O data level is reversed.
104
Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol UiMR(i=0,1)
Address 03A016, 03A816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long
RW
CKDIR STPS PRY
Internal / external clock select bit Stop bit length select bit
Odd / even parity select bit Parity enable bit Sleep select bit
0 : Internal clock 1 : External clock (Note) 0 : One stop bit 1 : Two stop bits
Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : Sleep mode deselected 1 : Sleep mode selected
PRYE SLEP
Note : Set the corresponding port direction register to "0".
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2MR
Address 037816
When reset 0016
Bit symbol
SMD0 SMD1 SMD2
Bit name
Serial I/O mode select bit
b2 b1 b0
Function
1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long
RW
CKDIR STPS PRY
Internal / external clock select bit Stop bit length select bit
Odd / even parity select bit Parity enable bit TxD, RxD I/O polarity reverse bit (Note)
Must always be "0"
0 : One stop bit 1 : Two stop bits Valid when bit 6 = "1" 0 : Odd parity 1 : Even parity 0 : Parity disabled 1 : Parity enabled 0 : No reverse 1 : Reverse
PRYE IOPOL
Note : Usually set to "0".
Figure 1.15.15. UARTi transmit/receive mode register in UART mode
105
Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.15.7 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the Nchannel open-drain is selected, this pin is in floating state.) Table 1.15.7. Input/output pin functions in UART mode
Pin name Function TxDi Serial data output (P63, P67, P70) RxDi Serial data input (P62, P66, P71) CLKi Programmable I/O port (P61, P65, P72) Transfer clock input Method of selection
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16, bit 1 at address 03EF16)= "0" (Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = "0" Internal/external clock select bit (bit 3 at address 03A016, 03A816) = "1" Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = "0" (Do not set external clock for UART2) CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) ="0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "0" Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16, bit 3 at address 03EF16) = "0" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "0" CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = "1" CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = "1"
CTSi/RTSi CTS input (P60, P64, P73)
RTS output Programmable I/O port
106
Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTS changes to "L".
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register.
Transferred from UARTi transmit buffer register to UARTi transmit register
"H"
CTSi
"L"
Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Parity bit
P
Stop bit
SP
Stopped pulsing because transmit enable bit = "0"
ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * CTS function is selected. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
* Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register Start bit TxDi
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
Stop bit
Stop bit
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SPSP ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP
Transmit interrupt request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is disabled. * Two stop bits. * CTS function is disabled. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT fi : frequency of BRGi count source (f1, f8, f32) fEXT : frequency of BRGi count source (external clock) n : value set to BRGi
Figure 1.15.16. Typical transmit timings in UART mode (UART0,UART1)
107
Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0"
Data is set in UART2 transmit buffer register
Note
Transferred from UART2 transmit buffer register to UARTi transmit register Start bit
ST D0 D1
TxD2
Parity bit
D2 D3 D4 D5 D6 D7 P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P
SP
"1" Transmit register empty flag (TXEPT) "0"
Transmit interrupt request bit (IR)
"1" "0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 1.15.17. Typical transmit timings in UART mode (UART2)
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Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
* Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count source Receive enable bit RxDi "1" "0" Start bit Sampled "L" Receive data taken in Transfer clock Receive complete flag RTSi Receive interrupt request bit Reception triggered when transfer clock "1" is generated by falling edge of start bit "0" "H" "L" "1" "0" Cleared to "0" when interrupt request is accepted, or cleared by software The above timing applies to the following settings : *Parity is disabled. *One stop bit. *RTS function is selected. Transferred from UARTi receive register to UARTi receive buffer register
Stop bit
D0
D1
D7
Figure 1.15.18. Typical receive timing in UART mode
(a) Sleep mode (UART0, UART1) This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to "1" during reception. In this mode, the unit performs receive operation when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".
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Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(b) Function for switching serial data logic (UART2) When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. Figure 1.15.19 shows the example of timing for switching serial data logic.
* When LSB first, parity enabled, one stop bit
Transfer clock TxD2
(no reverse)
"H" "L" "H" "L" "H" "L"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
TxD2
(reverse)
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST : Start bit P : Even parity SP : Stop bit
Figure 1.15.19. Timing for switching serial data logic
(c) TxD, RxD I/O polarity reverse function (UART2) This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to "0" (not to reverse) for usual use.
(d) Bus collision detection function (UART2) This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.15.20 shows the example of detection timing of a bus collision (in UART mode).
Transfer clock
"H" "L"
TxD2
"H" "L"
ST
SP
RxD2 Bus collision detection interrupt request signal Bus collision detection interrupt request bit
"H" "L" "1" "0" "1" "0"
ST
SP
ST : Start bit SP : Stop bit
Figure 1.15.20. Detection timing of a bus collision (in UART mode)
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Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table 1.15.8 shows the specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface). Table 1.15.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface) Item Transfer data format Specification * Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = "1012") * One stop bit (bit 4 of address 037816 = "0") * With the direct format chosen Set parity to "even" (bit 5 and bit 6 of address 037816 = "1" and "1" respectively) Set data logic to "direct" (bit 6 of address 037D16 = "0"). Set transfer format to LSB (bit 7 of address 037C16 = "0"). * With the inverse format chosen Set parity to "odd" (bit 5 and bit 6 of address 037816 = "0" and "1" respectively) Set data logic to "inverse" (bit 6 of address 037D16 = "1") Set transfer format to MSB (bit 7 of address 037C16 = "1") * With the internal clock chosen (bit 3 of address 037816 = "0") : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32 (Do not set external clock)
_______ _______
Transfer clock
Transmission / reception control * Disable the CTS and RTS function (bit 4 of address 037C16 = "1") Other settings * The sleep mode select function is not available for UART2 * Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D16 = "1") Transmission start condition * To start transmission, the following requirements must be met: - Transmit enable bit (bit 0 of address 037D16) = "1" - Transmit buffer empty flag (bit 1 of address 037D16) = "0" Reception start condition * To start reception, the following requirements must be met: - Reception enable bit (bit 2 of address 037D16) = "1" - Detection of a start bit Interrupt request * When transmitting generation timing When data transmission from the UART2 transfer register is completed (bit 4 of address 037D16 = "1") * When receiving When data transfer from the UART2 receive register to the UART2 receive buffer register is completed Error detection * Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2) * Framing error (see the specifications of clock-asynchronous serial I/O) * Parity error (see the specifications of clock-asynchronous serial I/O) - On the reception side, an "L" level is output from the TXD2 pin by use of the parity error signal output function (bit 7 of address 037D16 = "1") when a parity error is detected - On the transmission side, a parity error is detected by the level of input to the RXD2 pin when a transmission interrupt occurs * The error sum flag (see the specifications of clock-asynchronous serial I/O) Note 1: `n' denotes the value 0016 to FF16 that is set to the UART2 bit rate generator. Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that the UART2 receive interrupt request bit does not change.
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M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Tc
Transfer clock Transmit enable bit(TE) Transmit buffer empty flag(TI)
"1" "0" "1" "0" Data is set in UART2 transmit buffer register Note 1
Transferred from UART2 transmit buffer register to UART2 transmit register Start bit Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TxD2 RxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD2 due to the occurrence of a parity error.
Signal conductor level (Note 2)
"1" Transmit register empty flag (TXEPT) "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7 The level is detected by the interrupt routine.
P
SP
The level is detected by the interrupt routine.
Transmit interrupt request bit (IR)
Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "1".
Cleared to "0" when interrupt request is accepted, or cleared by software Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Tc
Transfer clock Receive enable bit (RE)
"1" "0"
Start bit
Parity bit
P
Stop bit
SP ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
RxD2 TxD2
ST D0 D1 D2 D3 D4 D5 D6 D7
A "L" level returns from TxD2 due to the occurrence of a parity error.
Signal conductor level (Note 2) Receive complete flag (RI) Receive interrupt request bit (IR)
"1" "0" "1" "0"
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
Read to receive buffer
Read to receive buffer
Cleared to "0" when interrupt request is accepted, or cleared by software Shown in ( ) are bit symbols. The above timing applies to the following settings : * Parity is enabled. * One stop bit. * Transmit interrupt cause select bit = "0". Tc = 16 (n + 1) / fi fi : frequency of BRG2 count source (f1, f8, f32) n : value set to BRG2
Note 1 : The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing. Note 2 : Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.15.21. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
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Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(a) Function for outputting a parity error signal With the error signal output enable bit (bit 7 of address 037D16) assigned "1", you can output an "L" level from the TxD2 pin when a parity error is detected. In step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. Figure 1.15.22 shows the output timing of the parity error signal.
* LSB first
Transfer clock RxD2 TxD2 Receive complete flag
"H" "L" "H" "L" "H" "L" "1" "0"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
Hi-Z
ST : Start bit P : Even Parity SP : Stop bit
Figure 1.15.22. Output timing of the parity error signal
(b) Direct format/inverse format Connecting the SIM card allows you to switch between direct format and inverse format. If you choose the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted and output from TxD2. Figure 1.15.23 shows the SIM interface format.
Transfer clcck TxD2 (direct) TxD2 (inverse) D0 D1 D2 D3 D4 D5 D6 D7 P
D7
D6
D5
D4
D3
D2
D1
D0
P P : Even parity
Figure 1.15.23. SIM interface format
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Mitsubishi microcomputers
M30220 Group
Clock asynchronous serial I/O (UART) mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.15.24 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
SIM card TxD2 RxD2
Figure 1.15.24. Connecting the SIM interface
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways. Figure 1.15.25 shows the UART2 special mode register.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol U2SMR
Address 037716
When reset 0016
Bit symbol IICM ABC BBS LSYN ABSCS
Bit name I 2C mode selection bit Arbitration lost detecting flag control bit Bus busy flag SCLL sync output enable bit Bus collision detect sampling clock select bit Auto clear function select bit of transmit enable bit Transmit start condition select bit
Function (During clock synchronous serial I/O mode) 0 : Normal mode 1 : I2 C mode 0 : Update per bit 1 : Update per byte
0 : STOP condition detected 1 : START condition detected
Function (During UART mode)
Must always be "0" Must always be "0"
RW
Must always be "0"
(Note)
0 : Disabled 1 : Enabled
Must always be "0"
Must always be "0"
0 : Rising edge of transfer clock 1 : Underflow signal of timer A0
0 : No auto clear function 1 : Auto clear at occurrence of bus collision
ACSE
Must always be "0"
SSS
Must always be "0"
0 : Ordinary 1 : Falling edge of RxD2
Reserved bit
Must always be set to "0"
Note: Nothing but "0" may be written.
Figure 1.15.25. UART2 special mode register Table 1.15.9. Features in I2C mode
Function 1 2 3 4 5 6 7 8 9 Factor of interrupt number 10 (Note 2) Factor of interrupt number 15 (Note 2) Factor of interrupt number 16 (Note 2) UART2 transmission output delay P70 at the time when UART2 is in use P71 at the time when UART2 is in use P72 at the time when UART2 is in use DMA1 factor at the time when 1 1 0 1 is assigned to the DMA request factor selection bits Noise filter width Normal mode Bus collision detection UART2 transmission UART2 reception Not delayed TxD2 (output) RxD2 (input) CLK2 UART2 reception 15ns Reading the terminal when 0 is assigned to the direction register H level (when 0 is assigned to the CLK polarity select bit) I2C mode (Note 1) Start condition detection or stop condition detection No acknowledgment detection (NACK) Acknowledgment detection (ACK) Delayed SDA (input/output) (Note 3) SCL (input/output) P72 Must not be set 50ns Reading the terminal regardless of the value of the direction register The value set in latch P70 when the port is selected
10 Reading P71 11 Initial value of UART2 output
Note 1: Make the settings given below when I2C mode is in use. Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register. Disable the RTS/CTS function. Choose the MSB First function. Note 2: Follow the steps given below to switch from a factor to another. 1. Disable the interrupt of the corresponding number. 2. Switch from a factor to another. 3. Reset the interrupt request flag of the corresponding number. 4. Set an interrupt level of the corresponding number. Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In the first place, the control bits related to the I2C bus (simplified I2C bus) interface are explained. Bit 0 of the UART special mode register (037716) is used as the I2C mode selection bit. Setting "1" in the I2C mode select bit (bit 0) goes the circuit to achieve the I2C bus (simplified I2C bus) interface effective. Table 1.15.9 shows the relation between the I2C mode select bit and respective control workings. Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode.
P70 through P72 conforming to the simplified I 2C bus
P70/TxD2/SDA
Timer Selector
I/O UART2
D
To DMA0, DMA1
IICM=1 delay IICM=0
Transmission register
UART2
IICM=0 IICM=1
UART2 transmission/ NACK interrupt request To DMA0
Q T
Noize Filter
Arbitration
IICM=1 IICM=0 Reception register UART2 IICM=0 IICM=1
Timer
UART2 reception/ACK interrupt request DMA1 request
Start condition detection
S
Stop condition detection
Falling edge detection P71/RxD2/SCL I/O
Q
RQ
Bus busy
D T DQ
NACK
Q
L-synchronous output enabling bit
R
Data bus
T
ACK
Selector
(Port P71 output data latch) UART2 IICM=1
9th pulse IICM=1 CLK
Internal clock Bus collision detection
Bus collision/start, stop condition detection interrupt request
Noize Filter Noize Filter
IICM=1
IICM=0
External clock
IICM=0 UART2 IICM=0 UART2
P72/CLK2
Selector
I/O Timer
Port reading * With IICM set to 1, the port terminal is to be readable even if 1 is assigned to P71 of the direction register.
Figure 1.15.26. Functional block diagram for I2C mode Figure 1.15.26 shows the functional block diagram for I2C mode. Setting "1" in the I2C mode selection bit (IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock inputoutput terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output, so the SDA output changes after SCL fully goes to "L". An attempt to read Port P71 (SCL) results in getting the terminal's level regardless of the content of the port direction register. The initial value of SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment detection interrupt respectively. The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the start condition detection, and set to "0" by the stop condition detection.
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmission clock. Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit. Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the UART2 reception buffer register (037F16), and "1" is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock. If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after completing the first byte acknowledge detect and before starting the next one byte transmission. Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting this bit to "1" goes the P71 data register to "0" in synchronization with the SCL terminal level going to "L".
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Some other functions added are explained here. Figure 1.15.27 shows their workings. Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at the rising edge of the transfer clock. Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus collision detect interrupt request bit (nonconformity). Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK TxD/RxD Bus collision detect interrupt request bit Transmit enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK TxD
Enabling transmission With "1: falling edge of RxD2" selected
CLK TxD RxD
Figure 1.15.27. Some other functions added
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register 2 UART2 Special Mode Register 2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 special mode register 2 (address 037616) is used to further control UART2 in I2C mode. Figure 1.15.28 shows the UART2 special mode register 2.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol U2SMR2
Address 037616
When reset 0016
Bit symbol IICM2 CSC SWC ASL STAC SWC2 SDHI SHTC
Bit name I 2C mode selection bit 2 Clock-synchronous bit SCL wait output bit SDA output stop bit UART2 initialization bit SCL wait output bit 2 SDA output disable bit Start/stop condition control bit
Function Refer to Table 1.15.10 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0 : Disabled 1 : Enabled 0: UART2 clock 1: 0 output 0: Enabled 1: Disabled (high impedance) Set this bit to "1" in I2C mode (refer to Table 1.15.11)
RW
Figure 1.15.28. UART2 special mode register 2
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register 2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I2C mode selection bit 2. Table 1.15.10 shows the types of control to be changed by I2C mode selection bit 2 when the I2C mode selection bit is set to "1". Table 1.15.11 shows the timing characteristics of detecting the start condition and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I2C mode.
Table 1.15.10. Functions changed by I2C mode selection bit 2
Function 1 Factor of interrupt number 15 2 Factor of interrupt number 16 IICM2 = 0 No acknowledgment detection (NACK) Acknowledgment detection (ACK) IICM2 = 1 UART2 transmission (the rising edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) UART2 reception (the falling edge of the final bit of the clock) The falling edge of the final bit of the reception clock The falling edge of the final bit of the reception clock
3 DMA1 factor at the time when 1 1 0 1 Must not be set is assigned to the DMA request factor selection bits 4 Timing for transferring data from the UART2 reception shift register to the reception buffer. 5 Timing for generating a UART2 reception/ACK interrupt request The rising edge of the final bit of the reception clock The rising edge of the final bit of the reception clock
Table 1.15.11. Timing characteristics of detecting the start condition and the stop condition(Note1)
3 to 6 cycles < duration for setting-up (Note2)
3 to 6 cycles < duration for holding (Note2) Note 1 : When the start/stop condition count bit is "1" . Note 2 : "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock. Duration for setting up
SCL SDA
Duration for holding
(Start condition)
SDA
(Stop condition)
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Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register 2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P70/TXD2/SDA
Timer Selector
UART2
To DMA0, DMA1 IICM=0 or IICM2=1
delay
I/0
IICM=1 Transmission register UART2 IICM=0 SDHI ALS
D Q T
UART2 transmission/ NACK interrupt request
IICM=1 and IICM2=0 To DMA0 IICM=0 or IICM2=1
Arbitration
IICM=1 Reception register IICM=0 UART2 IICM=1 and IICM2=0
Noize Filter
UART2 reception/ACK interrupt request DMA1 request
Start condition detection
S R Q
Bus busy
NACK
Stop condition detection
Falling edge detection P71/RXD2/SCL I/0
L-synchronous output enabling bit
D T Q
D R
Q T
Data register Selector
UART2 IICM=1
Noize Filter Noize Filter
ACK IICM=1
9th pulse
Internal clock Bus collision SWC2 CLK detection External clock control UART2
R S
Bus collision/start, stop condition detection interrupt request
IICM=1
IICM=0
IICM=0
Falling of 9th pulse SWC
P72/CLK2
UART2 IICM=0
Port reading * With IICM set to 1, the port terminal is to be readable even if 1 is assigned to P71 of the direction register. I/0 Timer
Selector
Figure 1.15.29. Functional block diagram for I2C mode
Functions available in I2C mode are shown in Figure 1.15.29 -- a functional block diagram. Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the instant when the arbitration lost detectng flag is set to "1". Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit. With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this function, the UART2 transmission-reception clock becomes the logical product of the signal flowing through the internal SCL and that flowing through the SCL pin. This function operates over the period from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this function, choose the internal clock for the transfer clock. Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to "0" frees the output fixed to "L".
121
Mitsubishi microcomputers
M30220 Group
UART2 Special Mode Register 2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit. Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows. (1) The transmission shift register is initialized, and the content of the transmission register is transferred to the transmission shift register. This starts transmission by dealing with the clock entered next as the first bit. The UART2 output value, however, doesn't change until the first bit data is output after the entrance of the clock, and remains unchanged from the value at the moment when the microcomputer detected the start condition. (2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the clock entered next as the first bit. (3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of the clock. Starting to transmit/receive signals to/from UART2 using this function doesn't change the value of the transmission buffer empty flag. To use this function, choose the external clock for the transfer clock. Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL pin wait output bit 2. Setting this bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin even if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock is input/output. Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detectng flag is turned on.
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Mitsubishi microcomputers
M30220 Group
LCD Drive Control Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD Drive Control Circuit
The M30220 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following. * LCD display RAM * Segment output enable register * LCD mode register * Charge-pump * Selector * Timing controller * Common driver * Segment driver * Bias control circuit A maximum of 48 segment output pins and 4 common output pins can be used. Up to 192 pixels can be controlled for LCD display. When the LCD enable bit is set to "1" after data is set in the LCD mode register, the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, performs the bias control and the duty ratio control, and displays the data on the LCD panel. When using the output port function, write data into the LCD display RAM while the time division select bit are "00" and the LCD output enable bit is "0", and if the LCDRAM output bit is set to "1", the SEG0 - SEG15 pin and the pin which are selected as segment output by the segment output enable register will respectively output the contents of the bit corresponds to the COM0 of LCD display RAM. Table 1.16.1 shows maximum number of display pixels at each duty ratio. Figure 1.16.1 shows the block diagram of LCD controller / driver. Table 1.16.1. Maximum number of display pixels at each duty ratio Duty ratio 2 3 4 Maximum number of display pixel 96 dots or 8 segment LCD 12 digits 144 dots or 8 segment LCD 18 digits 192 dots or 8 segment LCD 24 digits
123
124
LCD enable bit
Data bus high-order bits
Data bus low-order bits
Reload register (8)
"0" LCD frame frequency control counter (8)
1/2
LCD Drive Control Circuit
Address 010016
Address 010116
Address 011716 LCD display RAM
Duty ratio select bits
f32 fC1
"1"
LCDCK count source select bit
2
Charge-pump control bit
Bias control bit
Selector Selector Selector Selector
Selector Selector
Timing controller
LCDCK
Figure 1.16.1. Block diagram of LCD controller/driver
1/8
Level shift Level shift
Bias control
VCC
Level shift
Level shift
Level shift
Level shift
Level Shift Level Shift
Level Shift
Level Shift
LCD output enable bit
Segment Segment driver driver
Common Common Common Common driver driver driver driver
Segment Segment Segment Segment driver driver driver driver
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
SEG0
SEG1
SEG2
SEG3
P06/SEG46 P07/SEG47
VSS VL1 VL2 VL3 C1 C2
COM0 COM1 COM2 COM3
Mitsubishi microcomputers
M30220 Group
LCD Drive Control Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
LCD mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol LCDM
Bit symbol
Address 012016
When reset 0X0000002
Bit name
Duty ratio select bit
b1 b0
Function
0 0 : Output port 0 1 : 2 duty (use COM0, COM1) 1 0 : 3 duty (use COM0-COM2) 1 1 : 4 duty (use COM0-COM3) 0 : 1/3 bias 1 : 1/2 bias
0 : LCD OFF 1 : LCD ON
0 : Charge-pump disable 1 : Charge-pump enable(Note2)
0 : LCD waveform output 1 : LCDRAM data output
RW
LCDT0 LCDT1 BIAS LCDEN PUMP
LRAMOUT
Bias control bit
LCD enable bit
Charge-pump control bit
LCDRAM output bit
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate. LCDCK count source 0 : f32 LSRC select bit (Note 1) 1 : fC1
Note 1: LCDCK is a clock for a LCD timing controller. Note 2: When the Charge-pump is enabled, set "0" to the bias control bit without fail.
Segment output enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol SEG
Bit symbol
Address 012216
When reset 0016
Bit name
Segment output enable bit 0 Segment output enable bit 1 Segment output enable bit 2 Segment output enable bit 3
Segment output enable bit 4 Segment output enable bit 5
Segment output enable bit 6
LCD output enable bit
Function
0 : I/O ports P100 to P107 1 : Segment output SEG16 to SEG23 0 : I/O ports P110 to P114 1 : Segment output SEG24 to SEG28 0 : I/O ports P115, P116 1 : Segment output SEG29, SEG30 0 : I/O ports P117 1 : Segment output SEG31
RW
SEGO0
SEGO1 SEGO2 SEGO3 SEGO4
SEGO5
SEGO6
SEGO7
0 : I/O ports P120 to P125 1 : Segment output SEG32 to SEG37 0 : I/O ports P126, P127 1 : Segment output SEG38, SEG39
0 : I/O ports P00 to P07 1 : Segment output SEG40 to SEG47
0 : disable 1 : enable
LCD frame frequency counter (Note)
b7 b0
Symbol LCDTIM
Address 012416
When reset XX16
Function
8 bits timer
Values that can be set
0016 to FF16
RW
Note: Set this register when LCD output enable bit is "0" (disable).
Figure 1.16.2. LCD-related registers
125
Mitsubishi microcomputers
M30220 Group
LCD Drive Control Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Charge-pump
The charge-pump performs threefold boosting. This circuit inputs a reference voltage for boosting from LCD power input pin VL1. To activate the charge-pump, by the segment output enable register and the LCD mode register, choose the segment/port, select the time division and the bias control, and set up the LCD frame frequency counter, and select the count source for LCDCK, then set the LCD output enable bit (bit 7 at the address 012216) to "enable", apply a voltage equal to or greater than 1.3 V but not exceeding 2.1 V to the VL1 pin, after that, set the charge-pump control bit (bit 4 at address 012016) to "step up enabled". However, set the bias control to "1/3 bias" without fail. When using the charge-pump, a voltage that is twice as large as VL1 occurs at VL2 pin, and a voltage that is three times as large as VL1 occurs at the VL3 pin. The charge-pump control bit (bit 4 of the address 012016) controls the charge-pump. When not using the charge-pump, enable the LCD output enable bit and apply an appropriate voltage to the LCD power supply input pins (VL1 to VL3). When the LCD output enable bit is disabled, the VL3 pin is connected to VCC internally.
Bias Control and Applied Voltage to LCD Power Input Pins
To the LCD power input pins (VL1 to VL3), apply the voltage shown in Table 1.16.2 according to the bias value. Select a bias value by the bias control bit (bit 2 of the address 012016).
Table 1.16.2. Bias control and applied voltage to VL1 to VL3 Bias value 1/3 bias 1/2 bias Voltage value VL3 = VLCD VL2 = 2/3 VLCD VL1 = 1/3 VLCD VL3 = VLCD VL2 = VL1 = 1/2 VLCD
Note : VLCD is the maximum value of supplied voltage for the LCD panel.
VLCD
VLCD VCC
Contrast control
Contrast control
VL3 VL2 C2 C1 VL1
VL3
R1
VL3
R4
VL3 VL2
Open Open
VL2 C2 C1 VL1
R3 Open R2 Open
VL2 C2 C1 VL1
R5
C1 C2
VL1
Open Open
R1=R2=R3
R4=R5
1/3 bias when using the charge-pump
1/3 bias when not using the charge-pump
1/2 bias When not using the charge-pump
When selecting output port function (not using LCD panel)
Figure 1.16.3. Example of circuit at each bias
126
Mitsubishi microcomputers
M30220 Group
LCD Drive Control Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Common Pin and Duty Ratio Control
The common pins (COM0 to COM3) to be used are determined by duty ratio. Select duty ratio by the duty ratio select bits (bits 0 and 1 of address 012016). Table 1.16.3. Duty ratio control and common pins used Duty Duty ratio select bit Common pins used ratio Bit 1 Bit 0 2 0 1 COM0, COM1 (Note 1) 3 1 0 COM0 to COM2 (Note 2) 4 1 1 COM0 to COM3 Note 1 : COM2 and COM3 are open. Note 2 : COM3 is open.
LCD Display RAM
Address 010016 to 011716 is the designated RAM for the LCD display. When "1" are written to these addresses, the corresponding segments of the LCD display panel are turned on. Figure 1.16.4 shows the LCD display RAM map.
Bit Address 010016 010116 010216 010316 010416 010516 010616 010716 010816 010916 010A16 010B16 010C16 010D16 010E16 010F16 011016 011116 011216 011316 011416 011516 011616 011716
7
6 SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG25 SEG27 SEG29 SEG31 SEG33 SEG35 SEG37 SEG39 SEG41 SEG43 SEG45 SEG47
5
4
3
2 SEG0 SEG2 SEG4 SEG6 SEG8
1
0
R
W
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 SEG24 SEG26 SEG28 SEG30 SEG32 SEG34 SEG36 SEG38 SEG40 SEG42 SEG44 SEG46
Figure 1.16.4. LCD display RAM map
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated internally and the frame frequency can be determined with the following equation. The LCDCK count source frequency is fC1 (same frequency as XCIN) or f32 (divide-by-32 of XIN frequency).
f(LCDCK)= (frequency of count source for LCDCK) 16 X (LCD frame frequency count value + 1) f(LCDCK) duty ratio
Frame frequency=
127
Mitsubishi microcomputers
M30220 Group
LCD Drive Control Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.16.5 shows the LCD drive waveform (1/2 bias), Figure 1.16.6 shows the LCD drive waveform (1/3 bias).
Internal logic LCDCK timing
1/4 duty
Voltage level VL3 VL2=VL1 VSS
COM0 COM1 COM2 COM3 SEG0
VL3 VSS
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2=VL1 VSS
SEG0
ON COM0 1/2 duty COM0 COM1 SEG0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
VL3 VL2=VL1 VSS
VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0
Figure 1.16.5. LCD drive waveform (1/2 bias)
128
Mitsubishi microcomputers
M30220 Group
LCD Drive Control Circuit
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Internal logic LCDCK timing
1/4 duty Voltage level COM0 VL3 VL2 VL1 VSS
COM1 COM2 COM3 SEG0 VL3 VSS
OFF COM3 COM2 COM1
ON COM0 COM3
OFF COM2 COM1
ON COM0
1/3 duty COM0 COM1 COM2 VL3 VSS VL3 VL2 VL1 VSS
SEG0
ON COM0 1/2 duty COM0 COM1 SEG0
OFF COM2 COM1
ON COM0
OFF COM2 COM1
ON COM0
OFF COM2
VL3 VL2 VL1 VSS
VL3 VSS ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0 ON COM1 OFF COM0
Figure 1.16.6. LCD drive waveform (1/3 bias)
129
Mitsubishi microcomputers
M30220 Group
A-D Converter A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P90 to P97 also function as the analog signal input pins. The direction registers of these pins for AD conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers. Table 1.17.1. Performance of A-D converter Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) 0V to AVCC (VCC) Operating clock AD (Note 2) VCC = 4.0 to 5.5V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) VCC = 2.7 to 4.0V divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN) Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 5V * Without sample and hold function 3LSB * With sample and hold function (8-bit resolution) 2LSB * With sample and hold function (10-bit resolution) 3LSB VCC = 3V * Without sample and hold function (8-bit resolution) 2LSB Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 Analog input pins 8pins (AN0 to AN7) A-D conversion start condition * Software trigger A-D conversion starts when the A-D conversion start flag changes to "1" * External trigger (can be retriggered) A-D conversion starts when the A-D conversion start flag is "1" and the ___________ ADTRG/P130 input changes from "H" to "L" Conversion speed per pin * Without sample and hold function 8-bit resolution: 49 AD cycles, 10-bit resolution: 59 AD cycles * With sample and hold function 8-bit resolution: 28 AD cycles, 10-bit resolution: 33 AD cycles Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the AD frequency to 250kHZ min. With the sample and hold function, set the AD frequency to 1MHZ min.
130
Mitsubishi microcomputers
M30220 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CKS1=1
fAD 1/2 1/2
CKS0=1 CKS1=0
AD
A-D conversion rate selection
CKS0=0
VREF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register A-D control register 1 (address 03D716)
A-D control register 0 (address 03D616)
Addresses
(03C116, 03C016) (03C316, 03C216) (03C516, 03C416) (03C716, 03C616) (03C916, 03C816) (03CB16, 03CA16) (03CD16, 03CC16) (03CF16, 03CE16)
A-D register 0(16) A-D register 1(16) A-D register 2(16) A-D register 3(16) A-D register 4(16) A-D register 5(16) A-D register 6(16) A-D register 7(16) VIN Comparator Vref Decoder
Data bus high-order Data bus low-order
P90/AN0 P91/AN1 P92/AN2 P93/AN3 P94/AN4 P95/AN5 P96/AN6 P97/AN7
CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111 ADGSEL0 = 0
Figure 1.17.1. Block diagram of A-D converter
131
Mitsubishi microcomputers
M30220 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1
CH2 MD0 MD1 TRG ADST CKS0 Trigger select bit A-D conversion start flag Frequency select bit 0 A-D operation mode select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2)
0 0 : One-shot mode 0 1 : Repeat mode 1 0 : Single sweep mode 1 1 : Repeat sweep mode 0 Repeat sweep mode 1 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
(Note 2)
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) SCAN1 When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins) MD2 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit 0 : Any mode other than repeat sweep mode 1 1 : Repeat sweep mode 1 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 0 : Vref not connected 1 : Vref connected
BITS CKS1 VCUT
Reserved bit
Must always be set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.17.2. A-D converter-related registers (1)
132
Mitsubishi microcomputers
M30220 Group
A-D Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
0000XXX02
000
Bit symbol
SMP Reserved bit
Bit name
A-D conversion method select bit
Function
0 : Without sample and hold 1 : With sample and hold Must always be set to "0"
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0". Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D register i
(b15) b7 (b8) b0 b7
Symbol
ADi(i=0 to 7)
Address When reset 03C016 to 03CF16 Indeterminate
b0
Function
Eight low-order bits of A-D conversion result * During 10-bit mode Two high-order bits of A-D conversion result * During 8-bit mode When read, the content is indeterminate Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
RW
Figure 1.17.3. A-D converter-related registers (2)
133
Mitsubishi microcomputers
M30220 Group
A-D Converter (1) One-shot mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control register in one-shot mode. Table 1.17.2. One-shot mode specifications Item Function Start condition Stop condition Specification The pin selected by the analog input pin select bit is used for one A-D conversion Writing "1" to A-D conversion start flag * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag End of A-D conversion One of AN0 to AN7, as selected Read A-D register corresponding to selected pin
Interrupt request generation timing Input pin Reading of result of A-D converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol ADCON0 Bit symbol
CH0
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH1 CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2) (Note 2)
0 0 : One-shot mode 0 : Software trigger 1 : ADTRG trigger
A-D conversion start flag 0 : A-D conversion disabled 1 : A-D conversion started 0: fAD/4 is selected Frequency select bit 0 1: fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT Reserved bit
Address 03D716 Bit name
When reset 0016 Function
Invalid in one-shot mode
RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit1 Vref connect bit
Set to "0" when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected Must always be set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.17.4. A-D conversion register in one-shot mode
134
Mitsubishi microcomputers
M30220 Group
A-D Converter (2) Repeat mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. Table 1.17.3 shows the specifications of repeat mode. Figure 1.17.5 shows the A-D control register in repeat mode. Table 1.17.3. Repeat mode specifications Item Function Star condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pin selected by the analog input pin select bit is used for repeated A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated One of AN0 to AN7, as selected Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
01
Symbol ADCON0 Bit symbol
CH0 CH1
Address 03D616 Bit name
When reset 00000XXX2 Function
b2 b1 b0
RW
Analog input pin select bit
CH2 MD0 MD1 TRG ADST CKS0 A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
0 0 0 : AN0 is selected 0 0 1 : AN1 is selected 0 1 0 : AN2 is selected 0 1 1 : AN3 is selected 1 0 0 : AN4 is selected 1 0 1 : AN5 is selected 1 1 0 : AN6 is selected 1 1 1 : AN7 is selected
b4 b3
(Note 2) (Note 2)
0 1 : Repeat mode 0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
0
Symbol ADCON1 Bit symbol
SCAN0 SCAN1 MD2 BITS CKS1 VCUT Reserved bit
Address 03D716 Bit name
When reset 0016 Function
Invalid in repeat mode RW
A-D sweep pin select bit
A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
Set to "0" when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected Must always be set to "0"
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.17.5. A-D conversion register in repeat mode
135
Mitsubishi microcomputers
M30220 Group
A-D Converter (3) Single sweep mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. Table 1.17.4 shows the specifications of single sweep mode. Figure 1.17.6 shows the A-D control register in single sweep mode. Table 1.17.4. Single sweep mode specifications Item Specification Function The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion Start condition Writing "1" to A-D converter start flag Stop condition * End of A-D conversion (A-D conversion start flag changes to "0", except when external trigger is selected) * Writing "0" to A-D conversion start flag Interrupt request generation timing End of A-D conversion Input pin AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Reading of result of A-D converter Read A-D register corresponding to selected pin
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in single sweep mode
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 0 : Single sweep mode
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
001
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Set to "0" when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected Must always be set to "0"
MD2 BITS CKS1 VCUT Reserved bit
Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.17.6. A-D conversion register in single sweep mode
136
Mitsubishi microcomputers
M30220 Group
A-D Converter (4) Repeat sweep mode 0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. Table 1.17.5 shows the specifications of repeat sweep mode 0. Figure 1.17.7 shows the A-D control register in repeat sweep mode 0. Table 1.17.5. Repeat sweep mode 0 specifications Item Function Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter Specification The pins selected by the A-D sweep pin select bit are used for repeat A-D conversion Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins) Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0 Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616 Bit name
When reset 00000XXX2 Function
Invalid in repeat sweep mode 0
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 0
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1
001
0
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When single sweep and repeat sweep mode 0 are selected
b1 b0
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit Frequency select bit 1 Vref connect bit
0 0 : AN0, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins) Set to "0" when this mode is selected 0 : 8-bit mode 1 : 10-bit mode 0 : fAD/2 or fAD/4 is selected 1 : fAD is selected 1 : Vref connected Must always be set to "0"
MD2 BITS CKS1 VCUT Reserved bit
Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.17.7. A-D conversion register in repeat sweep mode 0
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Mitsubishi microcomputers
M30220 Group
A-D Converter (5) Repeat sweep mode 1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. Table 1.17.6 shows the specifications of repeat sweep mode 1. Figure 1.17.8 shows the A-D control register in repeat sweep mode 1.
Table 1.17.6. Repeat sweep mode 1 specifications
Item Function
Start condition Stop condition Interrupt request generation timing Input pin Reading of result of A-D converter
Specification All pins perform repeat A-D conversion, with emphasis on the pin or pins selected by the A-D sweep pin select bit Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Writing "1" to A-D conversion start flag Writing "0" to A-D conversion start flag None generated With emphasis on these pins ; AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ADCON0
Bit symbol
CH0 CH1 CH2 MD0 MD1 TRG ADST CKS0
Address 03D616
Bit name
When reset 00000XXX2
Function
Invalid in repeat sweep mode 1
RW
Analog input pin select bit
A-D operation mode select bit 0 Trigger select bit A-D conversion start flag Frequency select bit 0
b4 b3
1 1 : Repeat sweep mode 1
0 : Software trigger 1 : ADTRG trigger 0 : A-D conversion disabled 1 : A-D conversion started 0 : fAD/4 is selected 1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
001
1
Symbol ADCON1 Bit symbol
SCAN0
Address 03D716 Bit name
When reset 0016 Function
When repeat sweep mode 1 is selected
b1 b0
RW
A-D sweep pin select bit
SCAN1 A-D operation mode select bit 1 8/10-bit mode select bit
Frequency select bit 1
0 0 : AN0 (1 pin) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins)
Set to "1" when this mode is selected
MD2 BITS
CKS1
0 : 8-bit mode 1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected 1 : fAD is selected
VCUT
Reserved bit
Vref connect bit
1 : Vref connected
Must always be set to "0"
Note : If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.
Figure 1.17.8. A-D conversion register in repeat sweep mode 1
138
Mitsubishi microcomputers
M30220 Group
A-D Converter Sample and hold
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used. When sample and hold is selected, apply a 4.0 V - 5.5 V voltage to Vcc.
139
Mitsubishi microcomputers .
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains three independent D-A converters of this type. D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 to 2 (D-A output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the target port to output mode if D-A conversion is to be performed. Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register. V = VREF X n/ 256 (n = 0 to 255) VREF : reference voltage Table 1.18.1 lists the performance of the D-A converter. Figure 1.18.1 shows the block diagram of the D-A converter. Figure 1.18.2 shows the D-A control register. Figure 1.18.3 shows the D-A converter equivalent circuit.
Table 1.18.1. Performance of D-A converter Item Conversion method Resolution Analog output pin Performance R-2R method 8 bits 3 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816) D-A0 output enable bit
R-2R resistor ladder
P130/DA0
D-A register1 (8)
(Address 03DA16) D-A1 output enable bit
R-2R resistor ladder
P131/DA1
D-A register2 (8)
(Address 03DE16) D-A2 output enable bit
R-2R resistor ladder
P132/DA2
Figure 1.18.1. Block diagram of D-A converter
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Mitsubishi microcomputers
M30220 Group
D-A Converter
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol DACON Bit symbol
DA0E DA1E DA2E
Address 03DC16 Bit name
D-A0 output enable bit D-A1 output enable bit D-A2 output enable bit
When reset 0016 Function
0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled 0 : Output disabled 1 : Output enabled
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
D-A register
b7 b0
Symbol DAi (i = 0 to 2)
Address 03D816, 03DA16, 03DE16
When reset Indeterminate
Function
Output value of D-A conversion
RW RW
Figure 1.18.2. D-A control register
D-A0 output enable bit "0" DA0 "1" 2R MSB D-A register0 "0" AVSS VREF "1" 2R 2R 2R 2R 2R 2R 2R LSB R R R R R R R 2R
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16. Note 2: The same circuit as this is also used for D-A1 and D-A2. Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 0016 so that no current flows in the resistors Rs and 2Rs.
Figure 1.18.3. D-A converter equivalent circuit
141
Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Ports
There are 104 programmable I/O ports: P0 to P13 (excluding P77). Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P77 is an input-only port and has no built-in pull-up resistance. Figures 1.19.1 to 1.19.4 show the programmable I/O ports. Figure 1.19.5 shows the I/O pins. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A converter), they function as outputs regardless of the contents of the direction registers. When pins are to be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.19.6 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin. Note: There is no direction register bit for P77.
(2) Port registers
Figure 1.19.7 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.19.8 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register. When pull-up is ON for ports P1 and P2, an intermittent pull-up that pulls up the port for only a set period of time, can be performed from the key input mode register.
(4) Key input mode register
Figure 1.19.9 shows the key input mode register. With bits 0 and 1 of this register, it is possible to select both edges or the fall edge of the key input for P1 and P2. Also, with bit 2, it is possible to make the pull-up for a port (P1 or P2), which is set for pull-up using the pull-up control register, automatically connect as an intermittent pull-up. And, using the significant 3 bits, the pull-up resistance can be connected to and disconnected from ports P12 and P13.
(5) Real-time port control register
Figure 1.19.10 shows the real-time port control register. The real-time port control register can be used to set the registers of ports P0, P1, P2 and P12 for real-time port output, whereby output is synchronized with timer overflow of timers A0, A1, A5 and A6 in the timer mode. For details, see "Real-time Port".
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Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P00 to P07, P120 to P127
VL3/VCC Direction register "1" "1" LCD drive timing
VL2/VCC
VL3/VCC
Interface logic level shift circuit
Data bus Port latch Segment output Port/segment D Timer A overflow CK Q Port ON/OFF VL1/VSS
P10 to P17, P20 to P27
Intermittent pull-up control Pull-up selection Direction register
"1" Port latch
Data bus
DQ
Timer A overflow
CK
QD P30 to P33, P41, P43, P45, P47, P50 to P56, P62, P66, P74 to P76, P81, P83, P85, P87
Pull-up selected Direction register
CK
Intermittent pull-up control
Data bus
Port latch
P34, P35
Pull-up selection Direction register
Data bus
Port latch
Figure 1.19.1. Programmable I/O ports (1)
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Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up selection
P40, P42, P44, P46, P60, P61, P64, P65, P72, P73, P80, P82, P84, P86
Direction register "1"
Output Data bus Port latch
Input respective peripheral functions
Pull-up selection
P57, P63, P67
Direction register "1"
Output Data bus Port latch
Direction register
P70, P71
"1"
Output Data bus Port latch
Input respective peripheral functions
P77
Data bus
NMI interrupt input
Figure 1.19.2. Programmable I/O ports (2)
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Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P90 to P97
Pull-up selection Direction register
Data bus
Port latch
Analog input
P100 to P107, P110 to P117
Direction register "1"
VL3/VCC LCD drive timing
VL2/VCC
VL3/VCC
Interface logic level shift circuit
Data bus Port latch Segment output Port/segment Port ON/OFF VL1/VSS
P130
Pull-up selection Direction register
Data bus
Port latch
Input respective peripheral functions Analog output
Figure 1.19.3. Programmable I/O ports (3)
145
Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P131, P132
Pull-up selection Direction register
Data bus
Port latch
Analog output
COM0 to COM3, SEG0 to SEG15
VL3
VL2 VL1
The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value.
VSS
Figure 1.19.4. Programmable I/O ports (4)
RESET RESET signal input
(Note)
Note :
symbolizes a parasitic diode. Do not apply a voltage higher than VCC to each pin.
Figure 1.19.5. I/O pins
146
Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi direction register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PDi ( i = 0 to 12 except 3 and 7)
Address 03E216, 03E316, 03E616, 03EA16, 03EB16, 03EE16, 03F216, 03F316, 03F616, 03F716, 03FA16
When reset 0016
Bit symbol
PDi_0 PDi_1 PDi_2 PDi_3 PDi_4 PDi_5 PDi_6 PDi_7
Bit name
Port Pi0 direction register Port Pi1 direction register Port Pi2 direction register Port Pi3 direction register Port Pi4 direction register Port Pi5 direction register Port Pi6 direction register Port Pi7 direction register
Function
0 : Input mode (Functions as an input port) 1 : Output mode (Functions as an output port) (i = 0 to 12 except 3 and 7)
RW
Note : Do not access the Port P12 direction register in words.
Port P3 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD3
Address 03E716
When reset XX0000002
Bit symbol
PD3_0 PD3_1 PD3_2 PD3_3 PD3_4 PD3_5
Bit name
Port P30 direction register Port P31 direction register Port P32 direction register Port P33 direction register Port P34 direction register Port P35 direction register
Function
0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port)
RW
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Port P7 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD7
Address 03EF16
When reset X00000002
Bit symbol
PD7_0 PD7_1 PD7_2 PD7_3 PD7_4 PD7_5
Bit name
Port P70 direction register Port P71 direction register Port P72 direction register Port P73 direction register Port P74 direction register Port P75 direction register
Function
0: Input mode (Functions as an input port) 1: Output mode (Functions as an output port)
RW
PD7_6
Port P76 direction register
Nothing is assigned. In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.
Port P13 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD13
Address 03FB16
When reset XXXXX0002
Bit symbol
PD13_0 PD13_1 PD13_2
Bit name
Function
RW
Port P130 direction register 0: Input mode (Functions as an input port) Port P131 direction register 1: Output mode (Functions as an output port) Port P132 direction register
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Figure 1.19.6. Direction register
147
Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Port Pi register (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address Pi ( i = 0 to 12 except 3 and 7) 03E016, 03E116, 03E416, 03E816, 03E916, 03EC16, 03F016, 03F116, 03F416, 03F516, 03F816
Bit symbol
When reset Indeterminate
Bit name
Port Pi0 register Port Pi1 register Port Pi2 register Port Pi3 register Port Pi4 register Port Pi5 register Port Pi6 register Port Pi7 register
Function
Data is input an atput to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data (i = 0 to 12 except 3 and 7)
RW
Pi_0 Pi_1 Pi_2 Pi_3 Pi_4 Pi_5 Pi_6 Pi_7
Note : Do not access the Port P12 register in words.
Port P3 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P3
Bit symbol
Address 03E516
When reset Indeterminate
Bit mame
Port P30 register Port P31 register Port P32 register Port P33 register Port P34 register Port P35 register
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data
RW
P3_0 P3_1 P3_2 P3_3 P3_4 P3_5
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Port P7 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P7
Address 03ED16
When reset Indeterminate
Bit symbol
Bit mame
Port P70 register Port P71 register Port P72 register Port P73 register Port P74 register Port P75 register Port P76 register Port P77 register
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for P77) 0 : "L" level data 1 : "H" level data (Note)
RW
P7_0 P7_1 P7_2 P7_3 P7_4 P7_5 P7_6 P7_7
Note : Since P70 and P71 are N-channel open drain ports, the data is high-impedance.
Port P13 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol P13
Address 03F916
When reset Indeterminate
Bit symbol
Bit mame
Port P130 register Port P131 register Port P132 register
Function
Data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : "L" level data 1 : "H" level data
RW
P13_0 P13_1 P13_2
Nothing is assigned. In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Figure 1.19.7. Port register
148
Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pull-up control register 0 (Note 1)(Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR0 Bit symbol
PU00 PU01 PU02 PU03 PU04 PU05 PU06 PU07
Address 03FC16 Bit name
P00 to P03 pull-up P04 to P07 pull-up P10 to P13 pull-up P14 to P17 pull-up P20 to P23 pull-up P24 to P27 pull-up P30 to P33 pull-up P34 to P37 pull-up
When reset 000000112 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Note 1 : The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register. Note 2 : Do not access this register in words.
Pull-up control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR1 Bit symbol
PU10 PU11 PU12 PU13 PU14 PU15 PU16 PU17
Address 03FD16 Bit name
P40 to P43 pull-up P44 to P47 pull-up P50 to P53 pull-up P54 to P57 pull-up P60 to P63 pull-up P64 to P67 pull-up P70 to P73 pull-up P74 to P77 pull-up
When reset 0016 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high RW
Note : The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register.
Pull-up control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol PUR2 Bit symbol
PU20 PU21 PU22 PU23 PU24 PU25 PU26 PU27
Address 03FE16 Bit name
P80 to P83 pull-up P84 to P87 pull-up P90 to P93 pull-up P94 to P97 pull-up P100 to P103 pull-up P104 to P107 pull-up P110 to P113 pull-up P114 to P117 pull-up
When reset 111100002 Function
The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
RW
Note : The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register.
Figure 1.19.8. Pull-up control register
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Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Key input mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol KUPM
Bit symbol
Address 012616
When reset 011000002
Bit name
P1 key input select bit (Note 1) P1 key input enable bit P2 key input select bit (Note 1) P2 key input enable bit P3 key input enable bit P120 to P123 pull-up (Note 3) P124 to P127 pull-up (Note 3) P130 to P132 pull-up (Note 3)
Function
0 : Falling edge 1 : Two edges (Note 2) 0 : Disable 1 : Enable
R
W
P1KIS
P1KIE P2KIS P2KIE P3KIE PUP12L PUP12H PUP13
0 : Falling edge 1 : Two edges (Note 2)
0 : Disable 1 : Enable 0 : Disable 1 : Enable The corresponding port is pulled high with a pull-up resistor 0 : Not pulled high 1 : Pulled high
Note 1 : If this bit is set for "Two edges" when the corresponding port has been specified to have a pullup, the port is automatically pulled high intermittently. Operating sub-clock. Note 2 : When this bit is set for "Two edges" and the input from either of the corresponding pin is "L", if the pullup control register 0 of the corresponding port (bit 2 to 5 at the address 03FC16) is changed, there may be the thing that the key input interruption request is set to "1". Note 3 : The pull-up resistance is not connected for pins that are set for output from peripheral functions, regardless of the setting in the pull-up control register.
Figure 1.19.9. Key input mode register
Real time port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol RTP
Bit symbol
Address 03FF16
When reset 0016
Bit name
P00 to P03 real time port mode select bit P04 to P07 real time port mode select bit P10 to P13 real time port mode select bit P14 to P17 real time port mode select bit P20 to P23 real time port mode select bit P24 to P27 real time port mode select bit P120 to P123 real time port mode select bit
Function
0 : I/O port 1 : Real time port output (Note)
RW
RTP0 RTP1 RTP2 RTP3 RTP4 RTP5 RTP6 RTP7
P124 to P127 real time port mode select bit Note : The corresponding port direction register is invalidated.
Figure 1.19.10. Realtime port control register
150
Mitsubishi microcomputers
M30220 Group
Programmable I/O Port
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.19.1. Example connection of unused pins in single-chip mode
Pin name Ports P0 to P13 (excluding P77) XOUT (Note 2), XCOUT XCIN NMI AVCC AVSS, VREF COM0 to COM3 SEG0 to SEG15 C1, C2 VL2, VL3 VL1 CNVSS Connection After setting for output mode, leave these pins open; or after setting for input mode, connect every pin to VSS via a resistor (Note 1, Note 3). Open Connect this pin to VSS via a resistor (pull-down) Connect this pin to VCC via a resistor (pull-up) Connect to VCC Connect to VSS Open Open Open Connect to VCC Connect to VSS Connect this pin to VSS via a resistor (pull-down)
Note 1: If setting these pins in output mode and opening them, ports are in input mode until switched into output mode by use of software after reset. Thus the voltage levels of the pins become unstable, and there can be instances in which the power source current increases while the ports are in input mode. In view of an instance in which the contents of the direction registers change due to a runaway generated by noise or other causes, setting the contents of the direction registers periodically by use of software increases program reliability. Note 2: When an external clock is input to the XIN pin. Note 3: Output "L" if port P70 and P71 are set to output mode. Port P70 and P71 are N channel open drain.
Microcomputer
Port P0 to P13 (except for P77) (Input mode) * * * (Input mode) (Output mode)
* * *
Open
NMI VCC Open Open Open XCOUT COM0 to COM3 SEG0 to SEG15 AVCC VL3 VL2 VL1 AVSS VREF XCIN CNVSS VSS
Figure 1.19.11. Example connection of unused pins
151
Mitsubishi microcomputers
M30220 Group
Usage precaution Usage Precaution Timer A (timer mode)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF16". Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer Ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. Reading the timer Ai register with the reload timing gets "FFFF16" by underflow or "000016" by overflow. Reading the timer Ai register after setting a value in the timer Ai register with a count halted but before the counter starts counting gets a proper value. (2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to "0" while a count is in progress causes as follows: * The counter stops counting and a content of reload register is reloaded. * The TAiOUT pin outputs "L" level. * The interrupt request generated and the timer Ai interrupt request bit goes to "1". (2) The timer Ai interrupt request bit goes to "1" if the timer's operation mode is set using any of the following procedures: * Selecting one-shot timer mode after reset. * Changing operation mode from timer mode to one-shot timer mode. * Changing operation mode from event counter mode to one-shot timer mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer Ai interrupt request bit becomes "1" if setting operation mode of the timer in compliance with any of the following procedures: * Selecting PWM mode after reset. * Changing operation mode from timer mode to PWM mode. * Changing operation mode from event counter mode to PWM mode. Therefore, to use timer Ai interrupt (interrupt request bit), set timer Ai interrupt request bit to "0" after the above listed changes have been made. (2) Setting the count start flag to "0" while PWM pulses are being output causes the counter to stop counting. If the TAiOUT pin is outputting an "H" level in this instance, the output level goes to "L", and the timer Ai interrupt request bit goes to "1". If the TAiOUT pin is outputting an "L" level in this instance, the level does not change, and the timer Ai interrupt request bit does not becomes "1".
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. Reading the timer Bi register with the reload timing gets "FFFF16". Reading the timer Bi register after setting a value in the timer Bi register with a count halted but before the counter starts counting gets a proper value.
152
Mitsubishi microcomputers
M30220 Group
Usage precaution
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt request bit goes to "1". (2) When the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. At this time, timer Bi interrupt request is not generated.
Real time port
(1) Make sure timer Ai for real time port output is set for timer mode, and is set to have "no gate function" using the gate function select bit. (2) Before setting the real time port mode select bit to "1", temporarily turn off the timer Ai used and write its set value to the timer Ai register.
Serial I/O
When the IIC mode select bit (bit 0 at address 037716) is set to "1"; (1) When setting up port P7 (address 03EF16), write immediate values. If you use Read/Modify/Write instructions (BSET, BCLR, AND, OR, etc..) on the port P7 direction register, the value of P71 direction register may change to unknown data. (2) Only for the mask ROM version, when the internal/external clock select bit (bit 3 of address 037816) is set to "1 (set to slave)", the SCL wait output bit (bit 2 of address 037616) and SCL wait output bit 2 (bit 5 of address 037616) do not function. (3) Only for the mask ROM version, when the internal/external clock select bit (bit 3 of address 037816) is set to "1 (set to slave)", the port P71 cannot be read unless the port P71 direction register (bit 1 of address 03EF16) is set to "0", although it is specified as follows; "When IICM=1, the port pin shall be able to be read even if the P71 direction register=1."
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit 0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs). In particular, when the Vref connection bit is changed from "0" to "1", start A-D conversion after an elapse of 1 s or longer. (2) When changing A-D operation mode, select analog input pin again. (3) Using one-shot mode or single sweep mode Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by AD conversion interrupt request bit.) (4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to "L" level until main clock oscillation is stabilized. (2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction or from the instruction that sets the every-clock stop bit to "1" within the instruction queue are prefetched and then the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that sets the every-clock stop bit to "1". (3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with WAIT peripheral function clock stop bit set to "1".
153
Mitsubishi microcomputers
M30220 Group
Usage precaution Interrupts
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Reading address 0000016 * When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0". Reading address 0000016 by software sets enabled highest priority interrupt source request bit to "0". Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software. (2) Setting the stack pointer * The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. Be sure to _______ set a value in the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Concerning the first instruction immedi_______ ately after reset, generating any interrupts including the NMI interrupt is prohibited. _______ (3) The NMI interrupt _______ _______ * The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a resistor (pull-up) if unused. Be sure to work on it. _______ * Do not get either into stop mode with the NMI pin set to "L". (4) External interrupt ________ ________ * When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1". After changing the polarity, set the interrupt request bit to "0". (5) Rewrite the interrupt control register * To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1: FCLR I AND.B #00h, 0055h NOP NOP FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Four NOP instructions are required when using HOLD function. ; Enable interrupts.
Example 2:
INT_SWITCH2: FCLR I AND.B #00h, 0055h MOV.W MEM, R0 FSET I ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Dummy read. ; Enable interrupts.
Example 3:
INT_SWITCH3: PUSHC FLG FCLR I AND.B #00h, 0055h POPC FLG ; Push Flag register onto stack ; Disable interrupts. ; Clear TA0IC int. priority level and int. request bit. ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.
* When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been generated. This will depend on the instruction. If this creates problems, use the below instructions to change the register. Instructions : AND, OR, BCLR, BSET
154
Mitsubishi microcomputers
M30220 Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.21.1. Absolute maximum ratings
Symbol
Vcc AVcc VI
Parameter
Supply voltage Analog supply voltage Input voltage RESET, VREF, XIN P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132 (Mask ROM version CNVss) VL1 VL2 VL3 P70, P71, C1, C2 (flash memory version CNVss) Output voltage
Condition
Vcc=AVcc Vcc=AVcc
Rated value
- 0.3 to 6.5 - 0.3 to 6.5
Unit
V V
- 0.3 to Vcc+0.3
V
- 0.3 to VL2 VL1 to VL3 VL2 to 6.5 - 0.3 to 6.5
VO
P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132, XOUT P00 to P07, P100 to P107, P110 to P117, P120 to P127, P70, P71 When output port
When segment output
- 0.3 to Vcc+0.3
V
- 0.3 to Vcc - 0.3 to VL3 - 0.3 to 6.5
Pd Topr Tstg
Power dissipation Operating ambient temperature Storage temperature
Ta = 25C
300 - 20 to 85 - 40 to 150
mW C C
155
Mitsubishi microcomputers
M30220 Group
Electrical characteristics
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.21.2. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V at Ta = - 20 to 85oC unless otherwise specified) Symbol
Vcc AVcc Vss AVss VIH
Parameter
Supply voltage Analog supply voltage Analog supply voltage Analog supply voltage
HIGH input voltage P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, 130 to P132, XIN, RESET, CNVSS P70, P71 P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, 130 to P132, XIN, RESET, CNVSS P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132 P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132 P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27,P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, P130 to P132 P00 to P07, P100 to P107, P110 to P117, P120 to P127 P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, P130 to P132 VCC=4.0V to 5.5V
Min
2.7
Standard Typ. Max.
5.0 Vcc 0 0 5.5
Unit
V V V V
0.8Vcc
Vcc
V
0.8Vcc 0
6.5 0.2Vcc V
VIL
LOW input voltage
IOH (peak) HIGH peak output current (Note 2)
-0.5 -10.0 -0.1
mA
IOH (avg)
HIGH average output current (Note 1) LOW peak output current (Note 2) LOW average output current (Note 1)
mA -5.0 5.0 10.0 mA
IOL (peak)
IOL (avg)
2.5 mA 5.0 0 0 0 0 32.768 10 5 X VCC -10.000 10 2.31 X VCC +0.760 50 MHz MHz MHz MHz kHz
No wait
f (XIN)
Main clock input oscillation frequency
(Note 3)
VCC=2.7V to 4.0V VCC=4.0V to 5.5V
With wait
VCC=2.7V to 4.0V
f (XcIN)
Subclock oscillation frequency
Note 1: The mean output current is the mean value within 100ms. Note 2: The total IOL (peak) for ports P0, P1, P2, P30 to P35, P4, P5, P6, P70 to P76 and P122 to P127 must be 80mA max. The total IOH (peak) for ports P0, P1, P2, P30 to P35, P4, P5, P6, P72 to P76 and P122 to P127 must be 80mA max. The total IOL (peak) for ports P8, P9, P10, P11, P120, P121 and P130 to P132 must be 80mA max. The total IOH (peak) for ports P8, P9, P10, P11, P120,P121 and P130 to P132 must be 80mA max. Note 3: Relationship between main clock oscillation frequency and supply voltage.
Operating maximum frequency [MHZ] Operating maximum frequency [MHZ]
Main clock input oscillation frequency (No wait)
Main clock input oscillation frequency (With wait)
10.0
5 X Vcc-10.000MHz
10.0 7.0
2.31 X VCC+0.760MHz
3.5
0.0 2.7 4.0 5.5
Supply voltage [V] (BCLK: no division)
0.0 2.7 4.0
Supply voltage [V] (BCLK: no division)
5.5
156
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.21.3. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN)=10MHZ unless otherwise specified)
Symbol
VOH VOH
Parameter
HIGH output P00 to P07, P100 to P107, voltage P110 to P117, P120 to P127 HIGH output P10 to P17, P20 to P27, P30 to P35, voltage P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132 HIGH output XOUT voltage HIGH output XCOUT voltage HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER
Measuring condition
IOH= -0.1mA IOH= -5mA IOH= -200A IOH= -1mA IOH= -0.5mA With no load applied With no load applied IOL=5mA
Standard Min Typ. Max.
3.0 3.0 4.7 3.0 3.0 3.0 1.6 2.0
Unit
V
V
VOH VOH VOL
V V V
LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132 LOW output XOUT voltage LOW output XCOUT voltage Hysteresis HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER
IOL=200A
0.45 2.0 2.0 0 0 0.2 0.8 V V
VOL
IOL=1mA IOL=0.5mA With no load applied With no load applied
V
VOL VT+-VT-
TA0IN to TA7IN, TB0IN to TB5IN, INT0 to INT5, ADTRG, CTS0, CTS1, CLK0, CLK1, NMI, TA2OUT to TA4OUT, TA7OUT, KI0 to KI15 (Note), KI16 to KI19 RESET P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132 XIN XCIN When clock is stopped VI=5V
VT+-VTIIH
Hysteresis HIGH input current
0.2
1.8
V A
5.0
IIL
LOW input current
VI=0V
-5.0
A
RPULLUP
Pull-up resistance
VI=0V
30.0
50.0
167.0
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM retention voltage
1.0 6.0 2.0
M M V
Note : Has no effect during intermittent pullup operation.
157
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Table 1.21.4. Electrical characteristics (referenced to VCC = 5V, VSS = 0V at Ta = 25oC, f(XIN)=10MHZ unless otherwise specified)
Symbol Parameter Measuring condition
Mask ROM, flash memory versions Mask ROM version
Min.
Standard Typ. Max. Unit
19.0 90.0 200.0 4.0 1.0 A 20.0 38.0 mA A A A
f(XIN)=10MHz
Square wave, no division
f(XCIN)=32kHz
Square wave
Flash memory version
f(XCIN)=32kHz
Square wave
Icc
Power supply current
I/o pin is no load applied
Mask ROM, flash memory versions
f(XCIN)=32kHz
When a WAIT instruction is executed
When clock is stopped Ta=25 C When clock is stopped Ta=85 C VL3 VL1 IL1 Supply voltage (VL3) (Note) Supply voltage (VL1) Power supply current (VL1) When charge-pump not used When charge-pump used VL1=1.7V, f(LCDCK) = 200Hz 2.7 1.3 1.7 3.0
6.5 2.1 6.0
V V A
Note: Rating: VL1=-0.3 V to VL2, VL2=VL1 to VL3, VL3=VL2 to 6.5V.
Table 1.21.5. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 5V, Vss = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol
- -
Parameter Resolution
Absolute accuracy
Sample & hold function not available Sample & hold function available(10bit) Sample & hold function available(8bit)
Measuring condition
VREF =VCC
VREF =VCC = 5V VREF =VCC= 5V VREF = VCC = 5V
Standard Min. Typ. Max.
10 3 3 2 10 3.3 2.8 0.3 2 0 VCC VREF 40
Unit
Bits LSB LSB LSB k s s s V V
RLADDER tCONV tCONV tSAMP VREF VIA
Ladder resistance Conversion time(10bit) Conversion time(8bit) Sampling time Reference voltage Analog input voltage
VREF =VCC
Table 1.21.6. D-A conversion characteristics (referenced to VCC = AVCC =VREF =5V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 10MHZ unless otherwise specified)
Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current Measuring condition
Min. Standard Typ. Max. 8 1.0 3 20 4 10 1.5
Unit
Bits % s k mA
tsu RO IVREF
(Note)
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
158
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.7. External clock input
Symbol
tc tw(H) tw(L) tr tf
Parameter
External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Standard Min. Max.
100 40 40 15 15
Unit
ns ns ns ns ns
Table 1.21.8. Timer A input (counter input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 40 40 Unit ns ns ns
Table 1.21.9. Timer A input (gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 400 200 200 Unit ns ns ns
Table 1.21.10. Timer A input (external trigger input in one-shot timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Min. Standard Max. Unit ns ns ns
200 100 100
Table 1.21.11. Timer A input (external trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 100 100 Unit ns ns
Table 1.21.12. Timer A input (up/down input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Max. Min. 2000 1000 1000 400 400 Unit ns ns ns ns ns
159
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.13. Timer B input (counter input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 100 40 40 200 80 80 Max. Unit ns ns ns ns ns ns
Table 1.21.14. Timer B input (pulse period measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns
Table 1.21.15. Timer B input (pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 400 200 200 Max. Unit ns ns ns
Table 1.21.16. A-D trigger input
Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. 1000 125 Max. Unit ns ns
Table 1.21.17. Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time
_______
Parameter
Standard Min. 200 100 100 80 0 30 90 Max.
Unit ns ns ns ns ns ns ns
Table 1.21.18. External interrupt INTi inputs
Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. Max. 250 250 Unit ns ns
160
Mitsubishi microcomputers
M30220 Group
Timing
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 30pF
Figure 1.21.1. Port P0 to P13 measurement circuit
161
Mitsubishi microcomputers
M30220 Group
Timing (VCC = 5V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input
(When count on falling edge is selected)
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When count on rising edge is selected)
tc(TB) tw(TBH)
TBiIN input tw(TBL) tc(AD) ADTRG input tw(ADL)
tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) INTi input tw(INH) tsu(D-C) th(C-D) th(C-Q)
162
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.21.19. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait) Standard Measuring condition Symbol Parameter Min Typ. Max. Unit
VOH VOH HIGH output P00 to P07, P100 to P107, voltage P110 to P117, P120 to P127 HIGH output P10 to P17, P20 to P27, P30 to P35, voltage P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132 HIGH output XOUT voltage HIGH output XCOUT voltage HIGHPOWER LOWPOWER HIGHPOWER LOWPOWER IOH= -20A IOH= -1mA 2.0 2.5 V V
VOH VOH VOL
IOH= -0.1mA IOH= -50A With no load applied With no load applied IOL=1mA
2.5 2.5 3.0 1.6 0.5
V V V
LOW output P00 to P07, P10 to P17, P20 to P27, voltage P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P76, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132 LOW output voltage LOW output voltage Hysteresis XOUT HIGHPOWER LOWPOWER XCOUT HIGHPOWER LOWPOWER TA0IN to TA7IN, TB0IN to TB5IN, INT0 to INT5, ADTRG, CTS0, CTS1, CLK0, CLK1, NMI, TA2OUT to TA4OUT, TA7OUT, KI0 to KI15 (Note), KI16 to KI19 RESET
VOL
IOL=0.1mA IOL=50A With no load applied With no load applied 0.2 0 0
0.5 V 0.5 V
VOL VT+-VT-
0.8
V
VT+-VTIIH
Hysteresis
0.2 VI=3V
1.8
V A
HIGH input P00 to P07, P10 to P17, P20 to P27, current P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132, XIN, RESET, CNVSS LOW input current P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132, XIN, RESET, CNVSS P00 to P07, P10 to P17, P20 to P27, P30 to P35, P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132 XIN XCIN
4.0
IIL
VI=0V
-4.0
A
RPULLUP
Pull-up resistance
VI=0V
66.0 120.0
500.0
k
RfXIN RfXCIN VRAM
Feedback resistance Feedback resistance RAM retention voltage
3.0 10.0 When clock is stopped 2.0
M M V
Note : Has no effect during intermittent pullup operation.
163
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Table 1.21.20. Electrical characteristics (referenced to VCC = 3V, VSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait)
Symbol Parameter Measuring condition
Mask ROM, flash memory versions Mask ROM version Flash memory version
Min.
Standard Typ. Max.
6.0 40.0 150.0 2.8 15.0
Unit
mA A A A
f(XIN)=7MHz
Square wave, no division
f(XCIN)=32kHz
Square wave
f(XCIN)=32kHz
Square wave
Icc
Power supply current
I/o pin is no load applied
Mask ROM, flash memory versions
f(XCIN)=32kHz
When a WAIT instruction is executed Oscillation capacity High (Note)
f(XCIN)=32kHz
When a WAIT instruction is executed Oscillation capacity Low (Note 1)
0.9 1.0
A
When clock is stopped Ta=25 C When clock is stopped Ta=85 C VL3 VL1 IL1 Supply voltage (VL3) (Note 2) Supply voltage (VL1) Power supply current (VL1) When charge-pump not used When charge-pump used VL1=1.7V, f(LCDCK)=200Hz 2.7 1.3 1.7 3.0
A 20.0 6.5 2.1 6.0 V V A
Note 1: With one timer operated using fC32. Note 2: Rating: VL1=-0.3 V to VL2, VL2=VL1 to VL3, VL3=VL2 to 6.5V.
Table 1.21.21. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 3V, VSS = AVSS = 0V at Ta = 25oC, f(XIN) = 7MHZ, with wait unless otherwise specified)
Symbol
- - RLADDER tCONV VREF VIA
Parameter Resolution
Absolute accuracy
Measuring condition
VREF =VCC
Standard Min. Typ. Max.
10 2 10 14.0 2.7 0 40 VCC VREF
Unit
Bits LSB k s V V
Sample & hold function not available(8bit) VREF =VCC = 3V, oAD=fAD/2
Ladder resistance Conversion time(8bit) Reference voltage Analog input voltage
VREF =VCC
Table 1.21.22. D-A conversion characteristics (referenced to VCC = AVCC= VREF= 3V, VSS = AVSS = 0V, at Ta = 25oC, f(XIN) = 7MHZ unless otherwise specified)
Symbol Parameter Resolution Absolute accuracy Setup time Output resistance Reference power supply input current
A-D converter's ladder resistance is not included. Also, when the Vref is unconnected at the A-D control register, IVREF is sent.
Measuring condition
Min.
tsu RO IVREF
(Note)
Standard Typ. Max. 8 1.0 3 20 4 10 1.0
Unit
Bits % s k mA
Note : This applies when using one D-A converter, with the D-A register for the unused D-A converter set to "0016". The
164
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.23. External clock input
Symbol
tc tw(H) tw(L) tr tf
Parameter
External clock input cycle time External clock input HIGH pulse width External clock input LOW pulse width External clock rise time External clock fall time
Standard Min. Max.
143 60 60 18 18
Unit
ns ns ns ns ns
Table 1.21.24. Timer A input (counter input in event counter mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 150 60 60 Unit ns ns ns
Table 1.21.25. Timer A input (gating input in timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Max. Min. 600 300 300 Unit ns ns ns
Table 1.21.26. Timer A input (external trigger input in one-shot timer mode)
Symbol tc(TA) tw(TAH) tw(TAL) TAiIN input cycle time TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 300 150 150 Unit ns ns ns
Table 1.21.27. Timer A input (external trigger input in pulse width modulation mode)
Symbol tw(TAH) tw(TAL) TAiIN input HIGH pulse width TAiIN input LOW pulse width Parameter Standard Min. Max. 150 150 Unit ns ns
Table 1.21.28. Timer A input (up/down input in event counter mode)
Symbol tc(UP) tw(UPH) tw(UPL) tsu(UP-TIN) th(TIN-UP) TAiOUT input cycle time TAiOUT input HIGH pulse width TAiOUT input LOW pulse width TAiOUT input setup time TAiOUT input hold time Parameter Standard Min. Max. 3000 1500 1500 600 600 Unit ns ns ns ns ns
165
Mitsubishi microcomputers
M30220 Group
Electrical characteristics (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = 25oC unless otherwise specified) Table 1.21.29. Timer B input (counter input in event counter mode)
Symbol tc(TB) tw(TBH) tw(TBL) tc(TB) tw(TBH) tw(TBL) Parameter TBiIN input cycle time (counted on one edge) TBiIN input HIGH pulse width (counted on one edge) TBiIN input LOW pulse width (counted on one edge) TBiIN input cycle time (counted on both edges) TBiIN input HIGH pulse width (counted on both edges) TBiIN input LOW pulse width (counted on both edges) Standard Min. 150 60 60 300 160 160 Max. Unit ns ns ns ns ns ns
Table 1.21.30. Timer B input (pulse period measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Max. Min. 600 300 300 Unit ns ns ns
Table 1.21.31. Timer B input (pulse width measurement mode)
Symbol tc(TB) tw(TBH) tw(TBL) TBiIN input cycle time TBiIN input HIGH pulse width TBiIN input LOW pulse width Parameter Standard Min. 600 300 300 Max. Unit ns ns ns
Table 1.21.32. A-D trigger input
Symbol tc(AD) tw(ADL) Parameter ADTRG input cycle time (trigger able minimum) ADTRG input LOW pulse width Standard Min. Max. 1500 200 Unit ns ns
Table 1.21.33. Serial I/O
Symbol tc(CK) tw(CKH) tw(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) CLKi input cycle time CLKi input HIGH pulse width CLKi input LOW pulse width TxDi output delay time TxDi hold time RxDi input setup time RxDi input hold time Parameter Standard Min. 300 150 150 160 0 50 90 Max. Unit ns ns ns ns ns ns ns
_______
Table 1.21.34. External interrupt INTi inputs
Symbol tw(INH) tw(INL) INTi input HIGH pulse width INTi input LOW pulse width Parameter Standard Min. Max. 380 380 Unit ns ns
166
Mitsubishi microcomputers
M30220 Group
Timing (Vcc = 3V)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
tc(TA) tw(TAH) TAiIN input tw(TAL) tc(UP) tw(UPH) TAiOUT input tw(UPL) TAiOUT input (Up/down input) During event counter mode TAiIN input
(When count on falling edge is selected)
th(TIN-UP)
tsu(UP-TIN)
TAiIN input
(When count on rising edge is selected)
tc(TB) tw(TBH) TBiIN input tw(TBL) tc(AD) tw(ADL) ADTRG input
tc(CK) tw(CKH) CLKi tw(CKL) TxDi td(C-Q) RxDi tw(INL) tw(INH) tsu(D-C) th(C-D) th(C-Q)
INTi input
167
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ
SH56
83B <97B0> Mask ROM number
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30220MA-XXXGP/RP MASK ROM CONFIRMATION FORM
Receipt
Date :
Section head signature Supervisor signature
Note : Please complete all items marked
.
)
Customer Date issued Date :
1. Check sheet Name the product you order, and choose which to give in, EPROMs or floppy disks. If you order by means of EPROMs, three sets of EPROMs are required per pattern. If you order by means of floppy disks, one floppy disk is required per pattern. In the case of EPROMs Mitsubishi will create the mask using the data on the EPROMs supplied, providing the data is the same on at least two of those sets. Mitsubishi will, therefore, only accept liability if there is any discrepancy between the data on the EPROM sets and the ROM data written to the product. Please carefully check the data on the EPROMs being submitted to Mitsubishi. Microcomputer type No. : M30220MA-XXXGP M30220MA-XXXRP (hex)
Checksum code for total EPROM area : EPROM type :
27C201
Address
0000016 Product : Area containing ASCII 0000F16 code for M30220MA 0001016 27FFF16 2800016 ROM(96K) 3FFFF16 7FFFF16
27C401
Address
0000016 Product : Area containing ASCII 0000F16 code for M30220MA 0001016 67FFF16 6800016 ROM(96K)
Issuance signature
Company name
TEL (
Submitted by
Supervisor
(1) Write "FF16" to the lined area. (2) The area from 0000016 to 0000F16 is for storing data on the product type name. The ASCII code for 'M30220MA-' is shown at right. The data in this table must be written to address 0000016 to 0000F16. Both address and data are shown in hex.
Address
0000016 0000116 0000216 0000316 0000416 0000516 0000616 0000716
Address 'M ' '3 ' '0 ' '2 ' '2 ' '0 ' 'M ' 'A '
= 4D16 = 3316 = 3016 = 3216 = 3216 = 3016 = 4D16 = 4116 0000816 ' -- ' = 2D16 0000916 FF16 0000A16 FF16 FF16 0000B16 FF16 0000C16 FF16 0000D16 FF16 0000E16 FF16 0000F16
168
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ
SH56
83B <97B0>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30220MA-XXXGP/RP MASK ROM CONFIRMATION FORM
Mask ROM number
The ASCII code for the type No. can be written to EPROM addresses 0000016 to 0000F16 by specifying the pseudo-instructions for the respective EPROM type shown in the following table at the beginning of the assembler source program.
27C401 .SECTION ASCIICODE, ROM DATA Code entered in .ORG 080000H source program .BYTE ' M30220MA- ' Note: The ROM cannot be processed if the type No. written to the EPROM does not match the type No. in the check sheet.
EPROM type
27C201 .SECTION ASCIICODE, ROM DATA .ORG 0C0000H .BYTE ' M30220MA- '
In the case of floppy disks Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that there is any discrepancy between the contents of these mask files and the ROM data to be burned into products we produce. Check thoroughly the contents of the mask files you give in. Prepare 3.5 inches 2HD(IBM format) floppy disks. And store only one mask file in a floppy disk.
Microcomputer type No. : File code : M30220MA-XXXGP
M30220MA-XXXRP
(hex)
Mask file name :
.MSK (alpha-numeric 8-digit)
2. Mark specification The mark specification differs according to the type of package. After entering the mark specification on the separate mark specification sheet (for each package), attach that sheet to this masking check sheet for submission to Mitsubishi. For the M30220MA-XXXRP, submit the 144PFB mark specification sheet. For the M30220MA-XXXGP, submit the 144P6Q mark specification sheet.
3. Usage Conditions
For our reference when of testing our products, please reply to the following questions about the usage of the products you ordered. (1) Which kind of XIN-XOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do you use? f(XIN) = MHZ Quartz-crystal oscillator Other ( )
169
Mitsubishi microcomputers
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
GZZ
SH56
83B <97B0>
MITSUBISHI ELECTRIC SINGLE-CHIP 16-BIT MICROCOMPUTER M30220MA-XXXGP/RP MASK ROM CONFIRMATION FORM
Mask ROM number
(2) Which kind of XCIN-XCOUT oscillation circuit is used? Ceramic resonator External clock input What frequency do you use? f(XCIN) = kHZ Quartz-crystal oscillator Other ( )
(3) Which operating ambient temperature do you use? -10 C to 75 C -10 C to 85 C -20 C to 75 C -20 C to 85 C -40 C to 75 C -40 C to 85 C
(4) Which operating supply voltage do you use? 2.7V to 3.2V 4.2V to 4.7V 3.2V to 3.7V 4.7V to 5.2V 3.7V to 4.2V 5.2V to 5.5V
(5) Do you use I2C (Inter IC) bus function? Not use Use
(6) Do you use IE (Inter Equipment) bus function? Not use Use
Thank you cooperation. 4. Special item (Indicate none if there is no specified item)
170
Mitsubishi microcomputers
M30220 Group
Description (Flash Memory Version) Outline Performance
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.22.1 shows the outline performance of the M30220 (flash memory version). Table 1.22.1. Outline performance of the M30220 (flash memory version)
Item Power supply voltage Program/erase voltage Flash memory operation mode Erase block division User ROM area Boot ROM area Performance VCC=2.7V to 5.5 V (Note 1) VCC=2.7V to 3.6 V (Note 2) VPP=5.0V 10% Three modes (parallel I/O, standard serial I/O, CPU rewrite) See Figure 1.22.1 No division (8 K bytes) (Note 3) In units of words Collective erase/block erase Program/erase control by software command 6 commands 100 times Parallel I/O and standard serial I/O modes are supported.
Program method Erase method Program/erase control method Number of commands Program/erase count ROM code protect
Note 1: Use a 4.5 - 5.5 V power supply voltage when program/erase. Note 2: Use a 3.0 - 3.6 V power supply voltage when program/erase. Note 3: The boot ROM area contains a standard serial I/O mode control program which is stored in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode.
171
Mitsubishi microcomputers
M30220 Group
Description (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash Memory
The M30220 (flash memory version) has an internal new DINOR (DIvided bit line NOR) flash memory that can be rewritten with a single power source when VCC is 4.5 to 5.5 V, and 2 power sources when VCC is 2.7 to 4.5V. For this flash memory, three flash memory modes are available in which to read, program, and erase: parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit (CPU). Each mode is detailed in the pages to follow. The flash memory is divided into several blocks as shown in Figure 1.22.1, so that memory can be erased one block at a time. In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. However, the user can write a rewrite control program in this area that suits the user's application system. This boot ROM area can be rewritten in only parallel I/O mode.
0DE00016 0DFFFF16 0E000016
Boot ROM area Block 3 : 32K byte Block 2 : 32K byte
8K byte
0E800016 0F000016
Flash memory size 128K Flash memory start address 0E000016
User ROM area Block 1 : 32K byte Block 0 : 32K byte Note 1: The boot ROM area can be rewritten in only parallel input/ output mode. (Access to any other areas is inhibited.) Note 2: To specify a block, use the optional even address in the block.
0F800016 0FFFFF16
byte
Figure 1.22.1. Block diagram of flash memory version
172
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the Central Processing Unit (CPU). In CPU rewrite mode, only the user ROM area shown in Figure 1.22.1 can be rewritten; the boot ROM area cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM area and each block area. The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard serial I/O mode becomes unusable.) See Figure 1.22.1 for details about the boot ROM area. Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case, the CPU starts operating using the control program in the user ROM area. _____ When the microcomputer is reset by pulling the P74 (CE) pin high, the CNVSS pin high, the CPU starts operating using the control program in the boot ROM area (program start address is DE00016 fixation). This mode is called the "boot" mode.
Block Address
Block addresses refer to the optional even address of each block. These addresses are used in the block erase command.
173
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software commands. This rewrite control program must be transferred to internal RAM before it can be excuted. The CPU rewrite mode is accessed by applying 5V 10% to the CNVSS pin and writing "1" for the CPU rewrite mode select bit (bit 1 in address 03B416). Software commands are accepted once the mode is accessed. In the CPU rewrite mode, write to and read from software commands and data into even-numbered address ("0" for byte address A0) in 16-bit units. Always write 8-bit software commands into even-numbered address. Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations. Whether a program or erase operation has terminated normally or in error can be verified by reading the status register. Figure 1.23.1 shows the flash memory control register. _____ Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1". Bit 1 is the CPU rewrite mode select bit. When this bit is set to "1" and 5V 10% are applied to the CNVSS pin, the M30220 accesses the CPU rewrite mode. Software commands are accepted once the mode is accessed. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly. Therefore, use the control program in RAM for write to bit 1. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. The bit can be set to "0" by only writing a "0" . Bit 2 is the CPU rewrite mode entry flag. This bit can be read to check whether the CPU rewrite mode has been entered or not. Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1", writing "1" for this bit resets the control circuit. To release the reset, it is necessary to set this bit to "0". If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Figure 1.23.2 shows a flowchart for setting/releasing the CPU rewrite mode.
174
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Flash memory control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMCR Bit symbol
Address
03B416
When reset
XXXX00012
Bit name RY/BY status flag CPU rewrite mode select bit (Note 1)
Function 0: Busy (being written or erased) 1: Ready 0: Normal mode (Software commands invalid) 1: CPU rewrite mode 0: Normal mode (Software commands invalid) 1: CPU rewrite mode (Software commands acceptable) 0: Normal operation 1: Reset
RW RW
FMCR0 FMCR1
FMCR2
CPU rewrite mode entry flag
FMCR3
Flash memory reset bit (Note 2)
Nothing is assigned. When write, set "0". When read, values are indeterminate. Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Use the control program in the RAM for write to this bit. Note 2: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently after setting it to 1 (reset).
Figure 1.23.1. Flash memory control registers
175
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Program in ROM
Start
Program in RAM
*1
Single-chip mode, or boot mode (Note 1)
Set CPU rewrite mode select bit to "1" (by writing "0" and then "1" in succession)(Note 3)
Set processor mode register (Note 2)
Check the CPU rewrite mode entry flag
Transfer CPU rewrite mode control program to internal RAM
Using software command execute erase, program, or other operation
Jump to transferred control program in RAM (Subsequent operations are executed by control program in this RAM)
Execute read array command or reset flash memory by setting flash memory reset bit (by writing "1" and then "0" in succession) (Note 4)
*1 Write "0" to CPU rewrite mode select bit
End
Note 1: Apply 5V 10 % to CNVSS pin by confirmation of CPU rewrite mode entry flag when started operation with single-chip mode. Note 2: During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 5.0 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state) Note 3: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed during the interval. Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory.
Figure 1.23.2. CPU rewrite mode set/reset flowchart
176
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode. (1) Operation speed During CPU rewrite mode, set the main clock frequency as shown below using the main clock divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716): 5.0 MHz or less when wait bit (bit 7 at address 000516) = 0 (without internal access wait state) 10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state) (2) Instructions inhibited against use The instructions listed below cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction (3) Interrupts inhibited against use _______ The NMI, address match, and watchdog timer interrupts cannot be used during CPU rewrite mode because they refer to the internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be used by transferring the vector into the RAM area. (4) Reset If the control circuit is reset while erasing is in progress, a 5 ms wait is needed so that the flash memory can restore normal operation. Set a 5 ms wait to release the reset operation. Also, when the reset has been released, the program execute start address is automatically set to 0DE00016, therefore program so that the execute start address of the boot ROM is 0DE00016. (5) Writing in the user ROM area If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or parallel I/O mode to rewrite these blocks.
177
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.23.1 lists the software commands available with the M30220 (flash memory version). After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored. The content of each software command is explained below. Table 1.23.1. List of software commands (CPU rewrite mode)
First bus cycle Command Read array Read status register Clear status register Program
(Note 3)
Second bus cycle Mode Address Data (D0 to D7)
Cycle number 1 2 1 2 2 2
Mode Write Write Write Write Write Write
Data Address (D0 to D7) X
(Note 5)
FF16 7016 5016 4016 2016 2016 Write Write Write BA WA
(Note 3)
X X X X X
Read
X
SRD
(Note 2)
WD 2016 D016
(Note 3)
Erase all block Block erase
X
(Note 4)
Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored. Note 2: SRD = Status Register Data Note 3: WA = Write Address, WD = Write Data Note 4: BA = Block Address (Enter the optional address of each block that is an even address.) Note 5: X denotes a given address in the user ROM area (that is an even address).
Read Array Command (FF16) The read array mode is entered by writing the command code "FF16" in the first bus cycle. When an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (D0-D15), 16 bits at a time. The read array mode is retained intact until another command is written. Read Status Register Command (7016) When the command code "7016" is written in the first bus cycle, the content of the status register is read out at the data bus (D0-D7) by a read in the second bus cycle. The status register is explained in the next section. Clear Status Register Command (5016) This command is used to clear the bits SR4 to SR5 of the status register after they have been set. These bits indicate that operation has ended in an error. To use this command, write the command code "5016" in the first bus cycle.
178
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Program Command (4016) Program operation starts when the command code "4016" is written in the first bus cycle. Then, if the address and data to program are written in the 2nd bus cycle, program operation (data programming and verification) will start. Whether the write operation is completed can be confirmed by reading the status register or the RY/ _____ BY status flag. When the program starts, the read status register mode is accessed automatically and the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written. ____ The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is the status register bit 7. At program end, program results can be checked by reading the status register. Erase All Blocks Command (2016/2016) By writing the command code "2016" in the first bus cycle and the confirmation command code "2016" in the second bus cycle that follows, the system starts erase all blocks( erase and erase verify). Whether the erase all blocks command is terminated can be confirmed by reading the status register ____ or the RY/BY status flag. When the erase all blocks operation starts, the read status register mode is accessed automatically and the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the erase operation starts and is returned to 1 upon completion of the erase operation. In this case, the read status register mode remains active until the Read Array command (FF16) is written.
Start Write 4016 Write Write address Write data Status register read
SR7=1? or RY/BY=1? YES
NO
NO SR4=0? YES Program completed
Program error
Figure 1.23.3. Program flowchart
179
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
____
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
The RY/BY status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7. At erase all blocks end, erase results can be checked by reading the status register. For details, refer to the section where the status register is detailed. Block Erase Command (2016/D016) By writing the command code "2016" in the first bus cycle and the confirmation command code "D016" in the second bus cycle that follows to the block address of a flash memory block, the system initiates a block erase (erase and erase verify) operation. Whether the block erase operation is completed can be confirmed by reading the status register or ____ the RY/BY status flag. At the same time the block erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. The status register bit 7 (SR7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. In this case, the read status register mode remains active until the Read Array command (FF16). ____ The RY/BY status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status register bit 7. After the block erase operation is completed, the status register can be read out to know the result of the block erase operation. For details, refer to the section where the status register is detailed.
Start
Write 2016
Write
2016/D016 Block address
2016:Erase all blocks D016:Block erase
Status register read
SR7=1? or RY/BY=1?
NO
YES SR5=0? YES Erase completed NO Erase error
Figure 1.23.4. Erase flowchart
180
Mitsubishi microcomputers
M30220 Group
CPU Rewrite Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register
The status register shows the operating state of the flash memory and whether erase operations and programs ended successfully or in error. It can be read in the following ways. (1) By reading an arbitrary address from the user ROM area after writing the read status register command (7016) (2) By reading an arbitrary address from the user ROM area in the period from when the program starts or erase operation starts to when the read array command (FF16) is input Table 1.23.2 shows the status register. Also, the status register can be cleared in the following way. (1) By writing the clear status register command (5016) After a reset, the status register is set to "8016". Each bit in this register is explained below. Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase status (SR5) The erase status informs the operating status of erase operation to the CPU. When an erase error occurs, it is set to 1. The erase status is reset to 0 when cleared. Program status (SR4) The program status informs the operating status of write operation to the CPU. When a write error occurs, it is set to 1. The program status is reset to 0 when cleared. If "1" is written for any of the SR5 or SR4 bits, the program, erase all blocks, and block erase commands are not accepted. Before executing these commands, execute the clear status register command (5016) and clear the status register. Also, any commands are not correct, both SR5 and SR4 are set to 1.
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CPU Rewrite Mode (Flash Memory Version)
Table 1.23.2. Definition of each bit in status register
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Each bit of SRD SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0)
Definition Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
Full Status Check By performing full status check, it is possible to know the execution results of erase and program operations. Figure 1.23.5 shows a full status check flowchart and the action to be taken when each error occurs.
Read status register
YES SR4=1 and SR5 =1 ? NO
Command sequence error (Note 1)
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used.
SR5=0? YES
NO
Block erase error
SR4=0? YES
NO
Program error
Should a program error occur, the block in error cannot be used.
End (block erase, program)
Note 1: Either SR5 or SR4 may become "0". Take care about it during program debugging. Note 2: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands.
Figure 1.23.5. Full status check flowchart and remedial procedure for errors
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Mitsubishi microcomputers
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Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version) Functions To Inhibit Rewriting Flash Memory Version
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
To prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for use in standard serial I/O mode.
ROM code protect function
The ROM code protect function is used to prohibit reading out or modifying the contents of the flash memory during parallel I/O mode and is set by using the ROM code protect control address register (0FFFFF16). Figure 1.23.6 shows the ROM code protect control address (0FFFFF16). (This address exists in the user ROM area.) If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. ROM code protect is implemented in two levels. If level 2 is selected, the flash memory is protected even against readout by a shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is selected by default. If both of the two ROM code protect reset bits are set to "00," ROM code protect is turned off, so that the contents of the flash memory version can be read out or modified. Once ROM code protect is turned on, the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/ O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
b7 b6 b5 b4 b3 b2 b1 b0
11
Symbol ROMCP
Address 0FFFFF16
When reset FF16
Bit symbol
Bit name
Function Always set this bit to 1.
b3 b2
Reserved bit
ROMCP2
ROM code protect level 2 set bit (Note 1, 2)
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
b5 b4
ROMCR
ROM code protect reset bit (Note 3)
00: Protect removed 01: Protect set bit effective 10: Protect set bit effective 11: Protect set bit effective
b7 b6
ROMCP1
ROM code protect level 1 set bit (Note 1)
00: Protect enabled 01: Protect enabled 10: Protect enabled 11: Protect disabled
Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection LSI tester, etc. also is inhibited. Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and ROM code protect level 2. However, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode.
Figure 1.23.6. ROM code protect control address
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Mitsubishi microcomputers
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Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had the ID code preset at these addresses to the flash memory.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector
4 bytes
Figure 1.23.7. ID code store addresses
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Mitsubishi microcomputers
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Appendix Parallel I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Parallel I/O Mode
The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is parallel. Use an exclusive programer supporting M30220 (flash memory version). Refer to the instruction manual of each programer maker for the details of use.
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.22.1 can be rewritten. Both areas of flash memory can be operated on in the same way. Program and block erase operations can be performed in the user ROM area. The user ROM area and its blocks are shown in Figure 1.22.1. The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0DE00016 through 0DFFFF16. Make sure program and block erase operations are always performed within this address range. (Access to any location outside this address range is prohibited.) In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory. Therefore, using the device in standard serial input/output mode, you do not need to write to the boot ROM area.
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Mitsubishi microcomputers .
M30220 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
Pin functions (Flash memory standard serial I/O mode) (Note 1)
Pin VCC,VSS CNVSS RESET XIN XOUT XCIN XCOUT AVCC, AVSS VREF P00 to P07 P10 to P17 P20 to P27 P30 to P35 P40 to P47 P50 to P57 P60 P61 P62 P63 P64 to P67 P70 to P73, P75, P76 P74 P77 P80 to P87 P90 to P97 P100 to P107 P110 to P117 P120 to P127 P130 to P132 SEG0 to SEG15 COM0 to COM3 VL3 to VL1 C1 to C2 Name Power input CNVSS Reset input I I I/O
Description Apply a 3.0 - 3.6 V (Note 2) or 4.5 - 5.5 V (Note 3) voltage on the Vcc pin, and 0 V voltage on the Vss pin. Connect to VCC when VCC = 4.5V to 5.5 V. Connect to Vpp (=4.5 V to 5.5 V) when VCC = 3.0V to 3.6 V. Reset input pin. While reset is "L" level, a 20 cycle or longer clock must be input to XIN pin. Connect a ceramic resonator or crystal oscillator between XIN and XOUT pins. To input an externally generated clock, input it to XIN pin and open XOUT pin. Connect a crystal oscillator between XCIN and XCOUT pins. To input an externally generated clock, input it to XCIN pin and open XCOUT pin. Connect AVSS to VSS and AVCC to VCC, respectively.
Clock input Clock output Sub-clock input Sub-clock output Analog power supply input Reference voltage input Input port P0 Input port P1 Input port P2 Input port P3 Input port P4 Input port P5 BUSY output SCLK input RxD input TxD output Input port P6 Input port P7 CE input NMI input Input port P8 Input port P9 Input port P10 Input port P11 Input port P12 Input port P13 Segment output Common output Power supply input for LCD Charge-pump capacitor pin
I O I O
I I I I I I I O I I O I I I I I I I I I I O O
Enter the reference voltage for AD from this pin. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Standard serial mode 1: BUSY signal output pin Standard serial mode 2: Monitors the program operation check Standard serial mode 1: Serial clock input pin Standard serial mode 2: Input "L". Serial data input pin Serial data output pin Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" level signal. Connect this pin to Vcc. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Input "H" or "L" level signal or open. Open when not used LCD control circuit. Open when not used LCD control circuit. Input LCD power source. However, do not input the power when the power supply voltages for VCC and LCD are different. Connect a condenser between C1 and C2 when used LCD chargepump.
Note 1: About the unused pins, see the example of processing for unused pins in the single-chip mode. Note 2: The power supply voltage is VCC=2.7 - 3.6 V in the single-chip mode. Note 3: The power supply voltage is VCC=2.7 - 5.5 V in the single-chip mode.
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Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
106
102
105
101
108
104
103
100
88
107
97
92
83
87
78
74
96
91
82
95
86
90
81
77
99
94
85
89
80
76
98
93
84
79
75
73
P103/SEG19 P104/SEG20 P105/SEG21 P106/SEG22 P107/SEG23 P110/SEG24 P111/SEG25 P112/SEG26 P113/SEG27 P114/SEG28 P115/SEG29 P116/SEG30 P117/SEG31 P120/SEG32 P121/SEG33 VSS P122/SEG34 VCC P123/SEG35 P124/SEG36 P125/SEG37 P126/SEG38 P127/SEG39 P00/SEG40 P01/SEG41 P02/SEG42 P03/SEG43 P04/SEG44 P05/SEG45 P06/SEG46 P07/SEG47 P10/KI0 P11/KI1 P12/KI2 P13/KI3 P14/KI4
P102/SEG18 P101/SEG17 P100/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 C2 C1 VL3 VL2 VL1 Vss P132/DA2 P131/DA1 AVSS P130/ADTRG/DA0 VREF AVCC P97/AN7
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
M30220 flash memory version (144P6Q-A, 144PFB-A)
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
P15/KI5 P16/KI6 P17/KI7 P20/KI8 P21/KI9 P22/KI10 P23/KI11 P24/KI12 P25/KI13 P26/KI14 P27/KI15 P30/KI16 P31/KI17 P32/KI18 P33/KI19 P34 P35 P40/TA0OUT P41/TA0IN P42/TA1OUT P43/TA1IN P44/TA2OUT P45/TA2IN P46/TA3OUT/INT4 P47/TA3IN/INT4 P50/TB0IN P51/TB1IN P52/TB2IN P53/TB3IN P54/TB4IN P55/TB5IN P56/INT3 P57/CKOUT P60/CTS0/RTS0 P61/CLK0 P62/RxD0
BUSY RxD
SCLK
14
23
10
19
15
24
28
32
11
20
16
25
29
33
12
21
17
26
30
34
13
22
18
27
31
35
5
P96/AN6 P95/AN5 P94/AN4 P93/AN3 P92/AN2 P91/AN1 P90/AN0 P87/TA7IN P86/TA7OUT P85/TA6IN P84/TA6OUT P83/TA5IN P82/TA5OUT P81/TA4IN/INT5 P80/TA4OUT/INT5 CNVSS XCIN XCOUT RESET XOUT VSS XIN VCC P77/NMI P76/INT2 P75/INT1 P74/INT0 P73/CTS2/RTS2 P72/CLK2 P71/RXD2/SCL P70/TXD2/SDA P67/T xD 1 P66/RxD1 P65/CLK1 P64/CTS1/RTS1/CLKS1 P63/TxD0
36
1
2
6
3
7
4
8
9
VCC VSS
Note 2
RESET
Note 1
VPP
Mode setup method Signal CNVss RESET CE Value 4.5 to 5.5V Vss Vcc Vcc
Note 1: Connect oscillator circuit. Note 2: Connect to VCC when VCC = 4.5V to 5.5 V. Connect to Vpp (=4.5V to 5.5 V) when VCC = 3.0V to 3.6 V.
Figure 1.25.1. Pin connections for serial I/O mode (1)
TxD
CE
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Mitsubishi microcomputers
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Appendix Standard Serial I/O Mode (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both modes require a purpose-specific peripheral unit. The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. The standard serial I/O mode is _____ started by connecting "H" to the P74 (CE) pin and "H" to the CNVSS pin (when VCC = 4.5 V to 5.5 V, connect to VCC; when VCC = 2.7 V to 4.5 V, supply 4.5 V to 5.5 V to Vpp from an external source), and releasing the reset operation. (In the ordinary command mode, set CNVss pin to "L" level.) This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accordingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is rewritten in the parallel I/O mode. Figure 1.25.1 shows the pin connections for the standard serial I/O mode. Serial data I/O uses UART0 and transfers the data serially in 8-bit units. Standard serial I/O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK0 pin when the reset is released. To use standard serial I/O mode 1 (clock synchronized), set the CLK0 pin to "H" level and release the reset. The operation uses the four UART0 pins CLK0, RxD0, TxD0 and RTS0 (BUSY). The CLK0 pin is the transfer clock input pin through which an external transfer clock is input. The TxD0 pin is for CMOS output. The RTS0 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts. To use standard serial I/O mode 2 (clock asynchronized), set the CLK0 pin to "L" level and release the reset. The operation uses the two UART0 pins RxD0 and TxD0. In the standard serial I/O mode, only the user ROM area indicated in Figure 1.22.1 can be rewritten. The boot ROM cannot. In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the ID code matches.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 1 (clock synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART0). Standard serial I/O mode 1 is engaged by releasing the reset with the P61 (CLK0) pin "H" level. In reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the CLK0 pin, and are then input to the MCU via the RxD0 pin. In transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the TxD0 pin. The TxD0 pin is for CMOS output. Transfer is in 8-bit units with LSB first. When busy, such as during transmission, reception, erasing or program execution, the RTS0 (BUSY) pin is "H" level. Accordingly, always start the next transfer after the RTS0 (BUSY) pin is "L" level. Also, data and status registers in memory can be read after inputting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained software commands, status registers, etc.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) Software Commands
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.25.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Software commands are explained here below. Table 1.25.1. Software commands (Standard serial I/O mode 1)
Control command 1 Page read
1st byte transfer
2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (low)
3rd byte Address (high) Address (high) Address (high) SRD1 output
4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte
FF16
When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable
2
Page program
4116
3 4 5 6 7 8
Block erase Erase all blocks Read status register Clear status register ID check function Download function
2016 A716 7016 5016
Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high)
Address (high) Checksum Version data output Data output
9
Version data output function
FB16
ID1 To Data required input number of times Version Version data data output output Data output Data output
ID size
To ID7
Acceptable Not acceptable
10 Boot ROM area output function 11 Read check data
FC16
Version data output to 9th byte Data output to 259th byte
Acceptable Not acceptable Not acceptable
Check FD16 data (low)
Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.
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Mitsubishi microcomputers
M30220 Group
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first in sync with the fall of the clock.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
FF16
A8 to A15
A16 to A23
data0
data255
Figure 1.25.2. Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
7016
SRD output
SRD1 output
Figure 1.25.3. Timing for reading the status register
191
Mitsubishi microcomputers
M30220 Group
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command This command clears the bits (SR4-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared. When the clear status register operation ends, the RTS0 (BUSY) signal changes from the "H" to the "L" level.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
5016
Figure 1.25.4. Timing for clearing the status register Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. When reception setup for the next 256 bytes ends, the RTS0 (BUSY) signal changes from the "H" to the "L" level. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
4116
A8 to A15
A16 to A23
data0
data255
Figure 1.25.5. Timing for the page program
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Mitsubishi microcomputers
M30220 Group
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the optional even address of the specified block for addresses A8 to A23. When block erasing ends, the RTS0 (BUSY) signal changes from the "H" to the "L" level. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
2016
A8 to A15
A16 to A23
D016
Figure 1.25.6. Timing for block erasing
193
Mitsubishi microcomputers
M30220 Group
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Erase All Blocks Command This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. When block erasing ends, the RTS0 (BUSY) signal changes from the "H" to the "L" level. The result of the erase operation can be known by reading the status register. CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
A716
D016
Figure 1.25.7. Timing for erasing all blocks Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
FA16
Data size (low)
Check sum
Program data
Program data
Data size (high)
Figure 1.25.8. Timing for download
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Mitsubishi microcomputers
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
FB16
'V'
'E'
'R'
'X'
Figure 1.25.9. Timing for version information output Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
FC16
A8 to A15
A16 to A23
data0
data255
Figure 1.25.10. Timing for boot ROM area output
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Mitsubishi microcomputers
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data) RTS0(BUSY)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 1.25.11. Timing for the ID check ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector
4 bytes
Figure 1.25.12. ID code storage addresses
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M30220 Group
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. Check data adds write data in 1 byte units and obtains the two's-compliment of the insignificant 2 bytes of the accumulated data.
CLK0
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FD16
Check data (low) RTS0(BUSY)
Check data (high)
Figure 1.25.13. Timing for the read check data
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. It can be read by writing the read status register command (7016). Also, the status register is cleared by writing the clear status register command (5016). Table 1.25.2 gives the definition of each status register bit. After clearing the reset, the status register outputs "8016". Table 1.25.2. Status register (SRD) SRD0 bits SR7 (bit7) SR6 (bit6) SR5 (bit5) SR4 (bit4) SR3 (bit3) SR2 (bit2) SR1 (bit1) SR0 (bit0) Status name Sequencer status Reserved Erase status Program status Reserved Reserved Reserved Reserved Definition "1" Ready Terminated in error Terminated in error "0" Busy Terminated normally Terminated normally -
Sequencer status (SR7) After power-on, the sequencer status is set to 1(ready). The sequencer status indicates the operating status of the device. This status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. Erase Status (SR5) The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is set to "1". When the erase status is cleared, it is set to "0". Program Status (SR4) The program status reports the operating status of the auto write operation. If a write error occurs, it is set to "1". When the program status is cleared, it is set to "0".
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from check sum comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status register 1 is cleared by writing the clear status register command (5016). Table 1.25.3 gives the definition of each status register 1 bit. "0016" is output when power is turned ON and the flag status is maintained even after the reset. Table 1.25.3. Status register 1 (SRD1) SRD1 bits SR15 (bit7) SR14 (bit6) SR13 (bit5) SR12 (bit4) SR11 (bit3) SR10 (bit2) Status name Boot update completed bit Reserved Reserved Check sum match bit ID check completed bits Definition "1"
Update completed
"0" Not update Mismatch Not verified Verification mismatch Reserved Verified Normal operation -
Match 00 01 10 11 Time out -
SR9 (bit1) SR8 (bit0)
Data receive time out Reserved
Boot Update Completed Bit (SR15) This flag indicates whether the control program was downloaded to the RAM or not, using the download function. Check Sum Match Bit (SR12) This flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download function. ID Check Completed Bits (SR11 and SR10) These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check. Data Receive Time Out (SR9) This flag indicates when a time out error is generated during data reception. If this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure 1.25.14 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
YES SR4=1 and SR5 =1 ? NO
SR5=0? YES
SR4=0? YES NO
Command sequence error (Note 1)
Execute the clear status register command (5016) to clear the status register. Try performing the operation one more time after confirming that the command is entered correctly. Should a block erase error occur, the block in error cannot be used.
NO
Block erase error
Program error
Should a program error occur, the block in error cannot be used.
End (block erase, program)
Note 1: Either SR5 or SR4 may become "0". Take care about it during program debugging. Note 2: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and block erase commands is accepted. Execute the clear status register command (5016) before executing these commands.
Figure 1.25.14. Full status check flowchart and remedial procedure for errors
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for The Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary according to programmer, therefore see the peripheral unit manual for more information.
Clock input BUSY output Data input Data output
CLK0 RTS0(BUSY) RXD0 TXD0
M30220 flash
VPP power source input CNVss NMI
P74(CE)
(1) Control pins and external circuitry will vary according to peripheral unit. For more information, see the peripheral unit manual. (2) In this example, the Vpp power supply is supplied from an external source (writer). To use the user's power source, connect to 4.5V to 5.5 V.
Figure 1.25.15. Example circuit application for the standard serial I/O mode 1
201
Mitsubishi microcomputers
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 2 (clock asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0). Standard serial I/O mode 2 is engaged by releasing the reset with the P61 (CLK0) pin "L" level. The TxD0 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF. After the reset is released, connections can be established at 9,600 bps when initial communications (Figure 1.25.16) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by executing software commands. However, communication errors may occur because of the oscillation frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate. After executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. Data and status registers in memory can be read after transmitting software commands. Status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. Here following are explained initial communications with peripheral units, how frequency is identified and software commands.
Initial communications with peripheral units
After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation frequency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (Figure 1.25.16). (1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz, the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is anything other than 10 MHz, the MCU does not output anything. (2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit rate generator so that "0016" can be successfully received.) (3) The MCU with internal flash memory outputs the "B016" check code and initial communications end successfully *1. Initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps. *1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock.
Peripheral unit
MCU with internal flash memory Reset
(1) Transfer "B016" (2) Transfer "0016" 16 times At least 15ms transfer interval 15 th 16th
"B016" "B016" 1st 2nd "0016" "0016" "0016" "0016" "B016" (3) Transfer check code "B016" If the oscillation frequency input by the main clock is 10 MHz, the MCU outputs "B016". If other than 10 MHz, the MCU does not output anything.
The bit rate generator setting completes (9600bps)
Figure 1.25.16. Peripheral unit and initial communication
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
How frequency is identified
When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. Baud rate cannot be attained with some operating frequencies. Table 1.25.4 gives the operation frequency and the baud rate that can be attained for.
Table 1.25.4 Operation frequency and the baud rate
Operation frequency (MHZ) 10MHZ 8MHZ 7.3728MHZ 6MHZ 5MHZ 4.5MHZ 4.194304MHZ 4MHZ 3.58MHZ 3MHZ 2MHZ
Baud rate 9,600bps

Baud rate 19,200bps

Baud rate 38,400bps - -

Baud rate 57,600bps

- -
- -
- -
-

- -
-
-
: Communications possible - : Communications not possible
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) Software Commands
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Table 1.25.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and reading are controlled by transferring software commands via the RxD0 pin. Standard serial I/O mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software commands of standard serial I/O mode 1. Software commands are explained here below. Table 1.25.5. Software commands (Standard serial I/O mode 2)
Control command 1 2 Page read Page program
1st byte transfer
2nd byte Address (middle) Address (middle) Address (middle) D016 SRD output Address (low)
3rd byte Address (high) Address (high) Address (high) SRD1 output
4th byte 5th byte 6th byte Data output Data input D016 Data output Data input Data output Data input Data output to 259th byte Data input to 259th byte
FF16 4116
When ID is not verified Not acceptable Not acceptable Not acceptable Not acceptable Acceptable Not acceptable
3 4 5 6 7 8
Block erase Erase all unlocked blocks Read status register Clear status register ID check function Download function
2016 A716 7016 5016
Address (middle) Size FA16 Size (low) (high) F516 Version data output Address (middle) Version data output Address (high) Check data (high)
Address (high) Checksum Version data output Data output
9
Version data output function
FB16
ID1 To Data required input number of times Version Version data data output output Data output Data output
ID size
To ID7
Acceptable Not acceptable
10 Boot ROM area output function 11 Read check data
FC16
Version data output to 9th byte Data output to 259th byte
Acceptable Not acceptable Not acceptable
Check FD16 data (low)
12 Baud rate 9600 13 Baud rate 19200 14 Baud rate 38400 15 Baud rate 57600
B016 B116 B216 B316
B016 B116 B216 B316
Acceptable Acceptable Acceptable Acceptable
Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is transferred from the peripheral unit to the flash memory microcomputer. Note 2: SRD refers to status register data. SRD1 refers to status register 1 data. Note 3: All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Page Read Command This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page read command as explained here following. (1) Transfer the "FF16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FF16
A8 to A15
A16 to A23
data0
data255
Figure 1.25.17. Timing for page read Read Status Register Command This command reads status information. When the "7016" command code is sent with the 1st byte, the contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1 (SRD1) specified with the 3rd byte are read.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
7016
SRD output
SRD1 output
Figure 1.25.18. Timing for reading the status register
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command This command clears the bits (SR4-SR5) which are set when the status register operation ends in error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
5016
Figure 1.25.19. Timing for clearing the status register
Page Program Command This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. Execute the page program command as explained here following. (1) Transfer the "4116" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, as write data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 is input sequentially from the smallest address first, that page is automatically written. The result of the page program can be known by reading the status register. For more information, see the section on the status register.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
4116
A8 to A15
A16 to A23
data0
data255
Figure 1.25.20. Timing for the page program
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M30220 Group
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Block Erase Command This command erases the data in the specified block. Execute the block erase command as explained here following. (1) Transfer the "2016" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the erase operation will start for the specified block in the flash memory. Write the optional even address of the specified block for addresses A8 to A23. After block erase ends, the result of the block erase operation can be known by reading the status register. For more information, see the section on the status register.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
2016
A8 to A15
A16 to A23
D016
Figure 1.25.21. Timing for block erasing
Erase All Blocks Command This command erases the content of all blocks. Execute the erase all blocks command as explained here following. (1) Transfer the "A716" command code with the 1st byte. (2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the erase operation will start and continue for all blocks in the flash memory. The result of the erase operation can be known by reading the status register.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
A716
D016
Figure 1.25.22. Timing for erasing all blocks
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Download Command This command downloads a program to the RAM for execution. Execute the download command as explained here following. (1) Transfer the "FA16" command code with the 1st byte. (2) Transfer the program size with the 2nd and 3rd bytes. (3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th byte onward. (4) The program to execute is sent with the 5th byte onward. When all data has been transmitted, if the check sum matches, the downloaded program is executed. The size of the program will vary according to the internal RAM.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FA16
Data size (low)
Check sum
Program data
Program data
Data size (high)
Figure 1.25.23. Timing for download
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Version Information Output Command This command outputs the version information of the control program stored in the boot area. Execute the version information output command as explained here following. (1) Transfer the "FB16" command code with the 1st byte. (2) The version information will be output from the 2nd byte onward. This data is composed of 8 ASCII code characters.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FB16
'V'
'E'
'R'
'X'
Figure 1.25.24. Timing for version information output
Boot ROM Area Output Command This command outputs the control program stored in the boot ROM area in one page blocks (256 bytes). Execute the boot ROM area output command as explained here following. (1) Transfer the "FC16" command code with the 1st byte. (2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively. (3) From the 4th byte onward, data (D0-D7) for the page (256 bytes) specified with addresses A8 to A23 will be output sequentially from the smallest address first.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FC16
A8 to A15
A16 to A23
data0
data255
Figure 1.25.25. Timing for boot ROM area output
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check This command checks the ID code. Execute the boot ID check command as explained here following. (1) Transfer the "F516" command code with the 1st byte. (2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd, 3rd and 4th bytes respectively. (3) Transfer the number of data sets of the ID code with the 5th byte. (4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
F516
DF16
FF16
0F16
ID size
ID1
ID7
Figure 1.25.26. Timing for the ID check
ID Code When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written in the flash memory are compared to see if they match. If the codes do not match, the command sent from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte, addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write a program into the flash memory, which already has the ID code set for these addresses.
Address 0FFFDC16 to 0FFFDF16 0FFFE016 to 0FFFE316 0FFFE416 to 0FFFE716 0FFFE816 to 0FFFEB16 0FFFEC16 to 0FFFEF16 0FFFF016 to 0FFFF316 0FFFF416 to 0FFFF716 0FFFF816 to 0FFFFB16 0FFFFC16 to 0FFFFF16 ID1 Undefined instruction vector ID2 Overflow vector BRK instruction vector ID3 Address match vector ID4 Single step vector ID5 Watchdog timer vector ID6 DBC vector ID7 NMI vector Reset vector
4 bytes
Figure 1.25.27. ID code storage addresses
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read Check Data This command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) Transfer the "FD16" command code with the 1st byte. (2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd. To use this read check data command, first execute the command and then initialize the check data. Next, execute the page program command the required number of times. After that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. Check data adds write data in 1 byte units and obtains the two's-compliment of the insignificant 2 bytes of the accumulated data.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
FD16
Check data (low)
Check data (high)
Figure 1.25.28. Timing for the read check data
Baud Rate 9600 This command changes baud rate to 9,600 bps. Execute it as follows. (1) Transfer the "B016" command code with the 1st byte. (2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B016
B016
Figure 1.25.29. Timing of baud rate 9600
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Mitsubishi microcomputers
M30220 Group
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Baud Rate 19200 This command changes baud rate to 19,200 bps. Execute it as follows. (1) Transfer the "B116" command code with the 1st byte. (2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B116
B116
Figure 1.25.30. Timing of baud rate 19200 Baud Rate 38400 This command changes baud rate to 38,400 bps. Execute it as follows. (1) Transfer the "B216" command code with the 1st byte. (2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B216
B216
Figure 1.25.31. Timing of baud rate 38400 Baud Rate 57600 This command changes baud rate to 57,600 bps. Execute it as follows. (1) Transfer the "B316" command code with the 1st byte. (2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
RxD0 (M16C reception data) TxD0 (M16C transmit data)
B316
B316
Figure 1.25.32. Timing of baud rate 57600
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Example Circuit Application for The Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
CLK0 Monitor output Data input Data output BUSY RXD0 TXD0
M30220 flash
VPP power source input CNVss NMI
P74(CE)
(1) In this example, the Vpp power supply is supplied from an external source (writer). To use the user's power source, connect to 4.5V to 5.5 V.
Figure 1.25.23. Example circuit application for the standard serial I/O mode 2
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Timing (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Absolute maximum ratings
Symbol
Vcc AVcc VI
Parameter
Supply voltage Analog supply voltage Input RESET, VREF, XIN voltage P00 to P07, P10 to P17, P20 to P27, P30 to P35,P40 to P47, P50 to P57, P60 to P67,P72 to P77, P80 to P87, P90 to P97, P100 to P107, P110 to P117, P120 to P127, P130 to P132 (Mask ROM version CNVss) VL1 VL2 VL3 P70, P71, C1, C2 (Flash memory version CNVss) Output P10 to P17, P20 to P27, P30 to P35, voltage P40 to P47, P50 to P57, P60 to P67, P72 to P76, P80 to P87, P90 to P97, P130 to P132, XOUT P00 to P07, P100 to P107, P110 to P117, P120 to P127, P70, P71
Condition
Vcc=AVcc Vcc=AVcc
Rated value
- 0.3 to 6.5 - 0.3 to 6.5
Unit
V V
-0.3 to Vcc+0.3
V
- 0.3 to VL2 VL1 to VL3 VL2 to 6.5 - 0.3 to 6.5
VO
- 0.3 to Vcc+0.3
V
When output port When segment otput
- 0.3 to Vcc - 0.3 to VL3 - 0.3 to 6.5
Pd Topr Tstg
Power dissipation Operating ambient temperature (Note) Storage temperature
Ta = 25 C
300 255 - 40 to 150
mW C C
Note: It is a value in flash memory mode. Other parameter becomes same as a value in microcomputer mode.
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Timing (Flash memory version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DC electrical characteristics (referenced to VCC = 4.5V to 5.5V at Ta = 25oC unless otherwise specified)
Symbol
IPP1 IPP2 IPP3 VPP
Parameter
VPP power supply current (at read) VPP power supply current (at program) VPP power supply current (at erase) VPP power supply voltage VPP =VCC VPP =VCC VPP =VCC
Condition
Rated value
Min. Typ. Max. 100 60 30 5.5
Unit
A mA mA V
4.5
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
144P6Q-A
MMP
JEDEC Code - HD Weight(g) 1.23 Lead Material Cu Alloy
Plastic 144pin 2020mm body LQFP
MD
e
EIAJ Package Code LQFP144-P-2020-0.50
144
109
1
108
b2
D
l2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
36
73
37
72
A F
L1
e
A2
A3
x y b2 I2 MD ME
y
b
x
M
L Detail F
Lp
Dimension in Millimeters Min Nom Max 1.7 - - 0.125 0.2 0.05 1.4 - - 0.17 0.22 0.27 0.105 0.125 0.175 19.9 20.0 20.1 19.9 20.0 20.1 0.5 - - 21.8 22.0 22.2 21.8 22.0 22.2 0.35 0.5 0.65 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.08 0.1 - - 0 8 - 0.225 - - 0.95 - - 20.4 - - 20.4 - -
HE
E
A1
144PFB-A
MMP
JEDEC Code - Weight(g) 0.62 Lead Material Cu Alloy
c
Plastic 144pin 1616mm body TQFP
MD
EIAJ Package Code TQFP144-P-1616-0.40
e
HD D
144 1 114 113
b2
I2 Recommended Mount Pad Symbol A A1 A2 b c D E e HD HE L L1 Lp
A3
36 37 77
78
A L1
e
F
x y b2 I2 MD ME
y
b
x
L Detail F Lp
M
Dimension in Millimeters Min Nom Max 1.2 - - 0.05 0.1 0.15 1.0 - - 0.13 0.18 0.23 0.105 0.125 0.175 15.9 16.0 16.1 15.9 16.0 16.1 0.4 - - 17.8 18.0 18.2 17.8 18.0 18.2 0.4 0.5 0.6 1.0 - - 0.45 0.6 0.75 - 0.25 - - - 0.07 0.08 - - 0 8 - 0.225 - - - - 1.0 16.4 - - - - 16.4
HE
E
A2
A1
216
c
A3
ME
ME
REVISION HISTORY
Rev. H Date Page 01/12/17 1 1 1 2 4 5 5 6 8 12 13 15 16 17 18 23 25 32 34 42 44 47 47 48 50 53 56 63 67 68 69 73 73 74 75 77 78 86 91 91 123 125 126 126 130 139 147 148 148
M30220 GROUP DATA SHEET
Description Summary
Features are partly revised. Applications is partly added. Page numbers of Table of Contents are partly revised. Figure 1.1.1 is partly revised. Table 1.1.1 is partly revised. Figure 1.1.3 is partly revised. Figure 1.1.4 is partly revised. Pin description is partly revised. Figure 1.4.1 is partly revised. Figure 1.6.1 is partly added. Figure 1.6.3 is partly revised. Figure 1.7.1 is partly revised. Note is added. Figure 1.7.2 is partly revised. Note 2 is added. Figure 1.7.3 is partly revised. Note is added. Processor mode register 0 in Figure 1.8.1 is partly revised. System clock control register in Figure 1.9.4 is partly revised. Note 8 is partly revised. Explanation of "Wait Mode" is partly revised. Explanation of "Hardware Interrupts" is partly revised. Table 1.10.2 is partly revised. Note 3 and note 4 are partly revised. Explanation of "Saving Registers is" partly revised. Note is partly revised. Figure 1.10.9 is partly revised. Explanation of "Key Input Interrupt" is partly revised. Figure 1.10.13 is partly revised. Figure 1.10.14 and 1.10.15 are partly revised. ______ Explanation of "(3) The NMI interrupt" is partly revised. Explanation of "Watchdog timer" is partly added. Table 1.12.1 is partly revised. Explanation of "(1) Interrupt factors" is partly revised. Figure 1.13.3 is partly revised. Timer Ai register in Figure 1.13.5 is partly revised. Up/down flag 0 and Up/down flag 1 in Figure 1.13.6 is partly revised. Note is added. Table 1.13.2 is partly revised. Figure 1.13.10 is partly revised. Table 1.13.3 is partly revised. Figure 1.13.11 is partly revised. Table 1.13.5 is partly revised. Figure 1.13.14 and Figure 1.13.15 are partly revised. Figure 1.14.2 and Figure 1.14.3 are partly revised. UARTi transmit buffer register in Figure1.15.4 is partly revised. Note is added. UARTi bit rate generator in Figure1.15.4 is partly revised. Note is added. Explanation of "LCD Drive Control Circuit" is partly revised. LCD mode register in Figure 1.16.2 is partly revised. Explanation of "Voltage Multiplier" is partly revised. Figure 1.16.3 is partly revised. Table 1.17.1 is partly revised. Explanation of "Sample and hold" is partly revised. Port P13 direction register in Figure 1.19.6 is partly revised. Note is deleted. Port P7 register in Figure 1.19.7 is partly revised. Note is added. Port P13 register in Figure 1.19.7 is partly revised. Note is deleted.
217
REVISION HISTORY
Rev. Date Page H 01/12/17 149 150 151 151 153 153 154 158 163 164 168-170 171 172 172 173 177 178 182 183 186 187 191 193 195 200 205 207 209 214-215 216
M30220 GROUP DATA SHEET
Description Summary
Figure 1.19.8 is partly revised. Note is added. Figure 1.19.9 and Figure 1.19.10 are partly revised. Table 1.19.1 is partly revised. Figure 1.19.8 is partly revised. Explanation of "Serial I/O usage precaution" is added. Explanation of "Stop Mode and Wait Mode usage precaution" is partly revised. ______ Explanation of "(3) The NMI interrupt" is partly revised. Table 1.21.4 is partly revised. Table 1.21.19 is partly revised. Table 1.21.20 is partly revised. MASK ROM CONFIRMATION FORM is added. Table 1.22.1 is partly revised. Explanation of "Flash Memory" is partly revised. Figure 1.22.1 is partly revised. Explanation of "Block Address" is partly revised. Explanation of "Writing in the user ROM area" is partly revised. Table 1.23.1 is partly revised. Note 4 is partly revised. Figure 1.23.5 is partly revised. Explanation of "ROM code protect function" is partly revised. Pin description (Flash memory standard serial I/O mode) is partly revised. Figure 1.25.1 is partly revised. Explanation of "Page Read Command" is partly revised. Explanation of "Block Erase Command" is partly revised. Explanation of "Boot ROM Area Output Command" is partly revised. Figure 1.25.14 is partly revised. Explanation of "Page Read Command" is partly revised. Explanation of "Block Erase Command" is partly revised. Explanation of "Boot ROM Area Output Command" is partly revised. Timing (Flash memory version) is added. Package is added.
218
Keep safety first in your circuit designs!
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Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http:// www.mitsubishichips.com). When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon ductor product distributor for further details on these materials or the products con tained therein.
MITSUBISHI SEMICONDUCTORS M30220 Group Specification REV.H Dec. First Edition 2001 Editioned by Committee of editing of Mitsubishi Semiconductor Published by Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation. (c)2001 MITSUBISHI ELECTRIC CORPORATION

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