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| SSM9915K N-CHANNEL ENHANCEMENT MODE POWER MOSFET Simple drive requirement Lower gate charge Fast switching characteristic D D S BVDSS RDS(ON) ID 20V 50m 6.2A SOT-223 G Description Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, low on-resistance and cost-effectiveness. D G S Absolute Maximum Ratings Symbol VDS VGS ID @ TA=25C ID @ TA=70C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current 1 3 3 Rating 20 12 6.2 5 30 3.2 0.025 -55 to 150 -55 to 150 Units V V A A A W W/C C C Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range Thermal Data Symbol Rthj-a Parameter Thermal Resistance Junction-ambient 3 Value Max. 40 Unit C/W Rev.1.01 4/06/2004 www.SiliconStandard.com 1 of 4 SSM9915K Electrical Characteristics @ T j=25oC (unless otherwise specified) Symbol BVDSS Parameter Drain-Source Breakdown Voltage Test Conditions VGS=0V, ID=250uA 2 Min. 20 0.5 - Typ. 0.03 13 5 1 2 8 55 10 3 360 70 50 0.78 Max. Units 50 80 1.2 1 25 100 8 580 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF BV DSS/ Tj RDS(ON) Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA Static Drain-Source On-Resistance VGS=4.5V, ID=6A VGS=2.5V, ID=4A VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg Gate Threshold Voltage Forward Transconductance Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C) o o VDS=VGS, ID=250uA VDS=10V, ID=5A VDS=20V, VGS=0V VDS=16V ,VGS=0V VGS=12V ID=10A VDS=16V VGS=4.5V VDS=10V ID=10A RG=3.3, VGS=5V RD=1 VGS=0V VDS=20V f=1.0MHz f=1.0MHz Gate-Source Leakage Total Gate Charge 2 Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance 2 Source-Drain Diode Symbol VSD Parameter Forward On Voltage 2 2 Test Conditions IS=2.5A, VGS=0V IS=10A, VGS=0V, dI/dt=100A/s Min. - Typ. 17 9 Max. Units 1.3 V ns nC trr Qrr Reverse Recovery Time Reverse Recovery Charge Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 2 3.t10sec , Surface mounted on 1 in copper pad of FR4 board. Rev.1.01 4/06/2004 www.SiliconStandard.com 2 of 4 SSM9915K 50 40 T A =25 C 40 o T A =150 o C 4.5V ID , Drain Current (A) 30 ID , Drain Current (A) 4.5V 30 3.5V 20 20 3.5V 10 2.5V V G =1.5V 10 2.5V V G =1.5V 0 0 1 2 3 4 5 0 0 1 2 3 4 5 6 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 80 1.8 ID=4A 70 I D =6A 1.6 T A =25 o C Normalized R DS(ON) V G =4.5V 1.4 R DS(ON) (m ) 60 1.2 50 1.0 40 0.8 30 1 2 3 4 5 6 0.6 -50 0 50 100 150 V GS , Gate-to-Source Voltage (V) T j , Junction Temperature ( C) o Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 1.2 100 10 0.95 VGS(th) (V) IS (A) 1 0.7 T j =150 o C 0.1 T j =25 C o 0.45 0.01 0 0.4 0.8 1.2 0.2 -50 0 50 100 150 V SD , Source -to-Drain Voltage (V) T j , Junction Temperature ( C ) o Fig 5. Forward Characteristic of Reverse Diode Rev.1.01 4/06/2004 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 4 SSM9915K f=1.0MHz 14 1000 VGS , Gate to Source Voltage (V) 12 I D =6A V DS =16V V DS =12V V DS =10V C (pF) 100 C iss 10 8 6 C oss C rss 4 2 0 0 2 4 6 8 10 12 14 10 1 5 9 13 17 21 25 29 Q G , Total Gate Charge (nC) V DS , Drain-to-Source Voltage (V) Fig 7. Gate Charge Characteristics 100 1 Fig 8. Typical Capacitance Characteristics Normalized Thermal Response (Rthja) Duty factor=0.5 0.2 10 0.1 0.1 0.05 1ms ID (A) 1 0.02 0.01 0.1 T A =25 C Single Pulse 0.01 0.1 1 10 o 10ms 100ms 1s 10s DC Single Pulse PDM 0.01 t T Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja=90oC/W Per Unit Base 0.001 100 0.0001 0.001 0.01 0.1 1 10 100 1000 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area VDS 90% Fig 10. Effective Transient Thermal Impedance VG QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Charge Q Fig 11. Switching Time Waveform Fig 12. Gate Charge Waveform Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. Rev.1.01 4/06/2004 www.SiliconStandard.com 4 of 4 |
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