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| TM Application Specific Crystal Oscillator 7.0 x 5.0mm 3.3V HCSL Low Jitter 100MHz PCIe(R) 2.0 XO SHPCIE100 7.0 x 5.0mm Ceramic SMD ASSP XOTM for Networking Package: Product Features * Provides 100 MHz HCSL output for interfacing to standard PCIe(R) devices * Very low PCIe 2.0 jitter - 1.8ps RMS (typ.) * Thicker crystal for improved reliability * Pb-free & RoHS compliant * Industrial temperature range Recommended Land Pattern: Product Description The SHPCIE100 3.3V crystal clock oscillator achieves superb jitter for PCIe(R) 1.0 & 2.0 applications. The output clock signal, generated internally with a patented oscillator design, is compatible with HCSL logic levels. The device, available on tape and reel, is contained in a 7.0 x 5.0mm surface-mount ceramic package. Pin Functions: Pin Function 1 2 3 4 5 6 OE Function N/C Ground OUT OUT VCC Applications * Server * Network Switch/Router * Telecom Switch * Media Box * Graphics Card * Host Bus Adapter *Extended high frequency power decoupling is recommended (see test circuit for minimum recommendation). To ensure optimal performance, do not route RF traces beneath the package. Part Ordering Information: SHPCIE100 SaRonix-eCeraTM is a Pericom(R) Semiconductor company * US: +1-408-435-0800 TW: +886-3-4518888 * www.pericom.com 04/07/10 B All specifications are subject to change without notice. SHPCIE100 Rev C 3.3V HCSL Low Jitter 100 MHz PCIe(R) 2.0 XO SHPCIE100 TM Application Specific Crystal Oscillator 7.0 x 5.0mm Electrical Performance Parameter Min. Typ. Max. Units Notes Output Frequency Supply Voltage Supply Current, Output Enabled Supply Current, Output Disabled Frequency Stability Operating Temperature Range Output Logic 0, VOL Output Logic 1, VOH Output Load Duty Cycle Rise and Fall Time Jitter, Phase RMS (1-) Jitter, pk-pk 45 -40 -0.15 0.66 2.97 100 3.30 3.63 40 10 50 +85 0.9 Rs = 33, Rp = 50, CL = 2pF 55 0.7 1.8 27 2.5 40 MHz V mA mA ppm C V V output requires termination % ns ps ps Measured 50% of waveform Maximum measured from VOL = 0.175V to VOH = 0.525V As defined by PCI-SIG for PCIe(R) 2.0 reference clock 100,000 random periods See Note 1 below Industrial Notes: 1. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25C), aging (5 year at 40C average effective ambient temperature), shock and vibration. 2. For specifications othere than those listed, please contact sales. Output Enable / Disable Function Parameter Min. Typ. Max. Units Notes Input Voltage (pin 1), Output Enable Input Voltage (pin 1), Output Disable (low power standby) Output Disable Delay Output Enable Delay 2.2 0.8 200 10 V V ns ms or open Outputs disabled to Hi-Z Absolute Maximum Ratings Parameter Min. Typ. Max. Units Notes Storage Temperature -55 +125 C For the latest product information visit: http://www.pericom.com/products/asspxo/SHPCIE100 For test circuit go to: http://www.pericom.com/pdf/sre/tc_hcsl.pdf For soldering reflow profile and reliability test ratings go to: http://www.pericom.com/pdf/sre/reflow.pdf For typical phase noise go to: http://www.pericom.com/pdf/sre/pn_SHPCIE100.pdf For tape and reel information go to: http://www.pericom.com/pdf/sre/tr_7050.pdf SaRonix-eCeraTM is a Pericom(R) Semiconductor company * US: +1-408-435-0800 TW: +886-3-4518888 * www.pericom.com 04/07/10 B All specifications are subject to change without notice. SHPCIE100 Rev C |
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