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GPIO ICs Series
GPIO Expander IC
BU8272GUW
No.09098EAT01
Description GPIO expander is useful especially for the application that is in short of IO ports. It can 2 1. Control GPIO output states by I C write protocol. 2 2. Know GPIO input states by I C read protocol. Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander. GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output. Features 1) 400Kbps, 2-Wire serial interface 2) Interrupt output 3) 20-bit General purpose input/output interface 8-bit and 12-bit IO groups are designed for different power supply voltages from the device core voltage supply Absolute Maximum Ratings (Ta=25) Item Symbol VDD Supply Voltage VDDI2C VDDIO Value -0.3 ~ +2.5 -0.3 ~ +3.5 -0.3 ~ +3.5 -0.3 ~ VDD +0.5 Input voltage VI -0.3 ~ VDDI2C +0.5 -0.3 ~ VDDIO +0.5 Storage temperature range Package power
*1 *2
Unit V V V
*1 *1 *1
comment CMOS Core CMOS I/O for 2-Wire CMOS I/O -
V V V
o
Tstg PD
-55 ~ +125 310
*2
C
mW
The input voltage range doesn't exceed absolute maximum ratings even including +0.5 V. Package dissipation will be reduced each 3.1mW/ oC when the ambient temperature increases beyond 25 oC. This IC is not designed to be X-ray proof.
Recommended Operating Conditions o o (Ta=-25 C ~+85 C) Limit Item Supply voltage (VDD Symbol Min VVDD VVDDI2C VVDDIO1 VVDDIO2 FI2C 1.65 1.65 1.65 1.65 Typ 1.80 Max 1.95 3.45 3.45 3.45 400 V V V V KHz Core 2-Wire,INT,ADR, XRST GPIO[7:0] GPIO[19:8] Slave Unit Condition
Supply voltageVDDI2C Supply voltageVDDIO1 Supply voltageVDDIO2 2-Wire operating Frequency
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Package SpecificationVBGA035W040
Technical Note
Fig.1 Package Specification
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Pin Diagram
Technical Note
F
VDD
GPIO0
GPIO1
GPIO3
GPIO5
VDDIO1
E
INT
GND
GPIO2
GPIO4
GPIO6
GPIO7
D
SCL
XRST
GND
GND
GPIO9
GPIO8
C
ADR
SDA
GND
GND
GPIO11
GPIO10
B
GPIO19
GPIO17
GPIO15
VDD
GPIO12
A
VDDI2C
GPIO18
GPIO16
GPIO14
GPIO13
VDDIO2
1
2
3
4
5
6
Fig.2 Pin DiagramBottom View
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Block Diagram
Technical Note
Functional Block Diagram
INT VDDI2C Interrupt Logic INT_MASK IN/OUT Control VDDIO1 ADR
8bit
GPIO [7:0]
8bit
GPIO[7:0]
SCL SDA
Input Filter
I2C Bus Control
Shift Register
12bit
XRST
Reset
GPIO [19:8]
12bit
GPIO[19:8] VDDIO2
VDD
Write Pulse Read Pulse
Fig.3 Functional Block Diagram
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Electrical Specification o VDD=1.8V, VDDIO=3.0V, VDDI2C=3.0V, Ta=25 Cwithout output load conditions Limit Item Input H Voltage Input L Voltage Input H Current Input L Current Output H Voltage Output L Voltage SCL clk frequency Bus free time repeatStart condition Setup Time repeatStart condition Hold Time SCL Low Time SCL High Time Data Setup Time Data Hold Time Stop condition Setup Time Interrupt Valid Interrupt Reset Output Data Valid Input Data Setup Time Input Data Hold Time Standby Current Symbol Min. VIH VIL IIH IIL VOH VOL fSCL tBUF tSU:STA tHD:STA tLOW tHIGH tSU:DAT tHD:DAT tSU:STO tIV tIR tDV tDS tDH ISTBY 0.75xVDDIO 0 -3 VDDIO0.2 1.3 0.6 0.6 1.3 0.6 100 0 0.6 100 0 Typ. Max. 0.25xVDDIO 3 0 0.2 400 0.1 1.0 0.8 3.0 V V A A V V KHz s s s s s ns ns s s s s ns s A Unit
Technical Note
comment IOH=-1.0mA IOL=1.0mA
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Pin-out Functional Descriptions 1. Pin table PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
*1 *2
Technical Note
Land number A1 (NC) C3 C1 C2 D1 D2 E1 E2 F1 F2 D3 F3 E3 F4 E4 F5 E5 F6 E6 D4 D6 D5 C6 C5 B6 B5 A6 A5 C4 A4 B4 A3 B3 A2 B2
PIN name VDDI2C GND ADR SDA SCL XRST INT GND VDD GPIO0 GND GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 VDDIO1 GPIO7 GND GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 VDD VDDIO2 GPIO13 GND GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19
I/O IN INOUT IN IN OUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT INOUT
Power source system VDDI2C VDDI2C VDDI2C VDDI2C VDDI2C VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO1 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2 VDDIO2
Function
Cell Type
XRST
Serial data inout for 2-Wire Clock for 2-Wire ResetLow Active Interrupt signal
*1
B A B B C
Hi-z L -*3
General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD
*2
A A A A A A A A A A A A A
Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z
*2 *2 *2 *2 *2 *2
*2
*2 *2 *2 *2 *2
General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD General purpose inout. Pull-up to VDD
*2
A A A A A A A
Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z
*2 *2 *2 *2 *2 *2
The Low Active or High Active of interrupt output level and specific bit mask control are decided by internal register value. When IOSEL register is set to "1", please pull-up IO output to the same value as VDDIO1 or VDDIO2 voltages respectively.
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2. Equivalent IO circuit diagram
Technical Note
A
B
C
Fig.4 Equivalent IO circuit diagram
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Functional Description
Technical Note
1 2-Wire Bus Interface 1.1 Slave address Please pull-up SDA and SCL to the same potential of voltage as DVDDI2C. BU8272GUW is controlled by using an on-chip 2-Wire slave interface. Two kinds of the device address, "0001111" at ADR="1" or "0001000" at ADR="0" can be used. The transfer bit rate supports Fast-mode up to max 400Kbps.
A7 ADR=0 ADR=1 0 0
A6 0 0
A5 0 0
A4 1
A3 0
A2 0
A1 0 1
W/R 0/1
1 1 1 2-Wire Slave address
Fig. 5 Slave address
1.2 Data transfer One bit of data is transferred during SCL = "1". During the bit transfer SCL = "1" cycle, the signal SDA should keep the value. If SDA changes during SCL = "1", a START condition or STOP condition occur and it is interpreted as a control signal.
SDA SCL
Data is valid when SDA is stable
SDA is variable
Fig. 6 Data transfer
1.3 START-STOP conditions When SDA and SCL are "1", the data isn't transferred on the 2-wire bus. If SCL remains "1" and SDA transfers from "1" to "0", it means a "Start condition" is occurred and access is started. If SCL remains "1" and SDA transfers from "0" to "1", it means a "Stop condition" is occurred and access is stopped.
SDA SCL
S START condition
P STOP condition
Fig. 7 START-STOP conditions
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Technical Note
1.4 Acknowledge After start condition is occurred, 8 bits data will be transferred. Then the "Master" opens SDA and "Slave" de-asserts SDA to "0" as an "Acknowledge" returned.
SDA output from "Master" Not acknowledge SDA output from "Slave" SCL 1 2 Acknowledg e S START condition 8
Clock pulse For Acknowledgs
9
Fig. 8 Acknowledge
1.5 Writing protocol A writing protocol is shown in Fig.8-5 below. GPIO register address in BU8272GUW is transferred after one byte of slave address with a write commend. The 3rd byte data is written to internal register which defined by the 2nd byte. After the each byte transfer, the register address will be automatically increased. However, when the register address increased to the final address (09h), it will be reset to (00h) after the byte transfer. GPIO register address (00h) is assigned to GPIO register[7:0], the register address (01h) is assigned to GPIO register[15:8], and the register address (02h) is assigned to GPIO register[19:16]. Only the 4 bits LSB data are valid in the register with GPIO register address (02h).
S X X X X X X X 0 A X X X X A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A
Slave address R/W=0(write) Register address data
D7 D6 D5 D4 D3 D2 D1 D0 A P
data
Register address increment A=acknowledge A=not acknowledge S=Start condition P=Stop condition
Register address increment
Transmit from master
Transmit from slave
Fig. 9 Writing protocol
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Technical Note
1.6 Reading protocol After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address is next of previous accessed address. Therefore, the data is read with address increment. When the address in increased to the last, the following read address will be reset to (00h). When the GPIO port [19:16] is read, 4 bits of "0" will be added from MSB, and the value of 4 bits from GPIO port [19:16] is read from 2-wire interface.
S X X X X X X X 1 A D7 D6 D5 D4 D3 D2 D1 D0 A
Salve address R/W=1(Read) data Register Address increment
D7 D6 D5 D4 D3 D2 D1 D0 A P
data Register address increment
Transmit fronm master
Transmit from slave
A=acknowledge A=not acknowledge S=Start condition P=Stop condition
Fig. 10 Readout protocol
1.7 Complex reading protocol After the specifying the internal register address, a resending start condition occurs and the direction of data transfer is changed then reading access is done. Therefore, the data is read followed by address increment. If the address is increased to the last, it will be reset to (00h).
S X X X X X X X 0 A X X X X A3 A2 A1 A0 A Sr X X X X X X X 1 A
Slave address R/W=0(write) Register address Slave address R/W=1(read)
D7 D6 D5 D4 D3 D2 D1 D0 A
data Register address increment
D7 D6 D5 D4 D3 D2 D1 D0 A P
data Register address increment
Transmit from master
Transmit from slave
A=acknowledge A=not aclnowledge S=Start condition P=Stop condition Sr=Start condition
Fig. 11 Complex reading protocol
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1.8 Timing Diagram
Technical Note
Transfer state
(Repeat) Start condition
BIT 7
BIT 6
Ack
Stop condition
tSU;STA SCL SDA tBUF tHD;STA
tLOW tHIGH
1/fSCLK
tSU;DAT tHD;DAT
tSU;STO
Fig. 12 Timing Diagram
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Technical Note
2. GPIOINT Interface The default mode of all GPIO [19:0] ports are input mode upon the power-on. By setting the specific bit of Interrupt Mask Sel register to "1", the corresponding bit of Interrupt will be masked. There are two kinds of ways to control input / output operations. The first way is to change read / write register value in each corresponding bit. Second way is to write each GPIO register a "0" value for `Output operation' and a "1" value for `input operation'. It is necessary to pull up the output to the same voltage value as the corresponding I/O power supply in the second way.
Interrupt Logic
Please pull up the output to the same voltage value as the corresponding I/O power supply
GPI Reg
Interrupt Mask Read Data Register
S
XRST Read Configuration Pulse 0 1 GPIO[19:0]
GPO Reg Data From Shift Register Write Configuration Pulse S
0 1
IOSEL Reg
R/W Reg Data From Shift Register S
Fig. 13 GPIOINT system
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2.1 Write to GPIO Port After setting the internal register address, the data from master is written from MSB. After Acknowledge is returned, the value of each GPIO port will be changed.
Technical Note
IOSEL=1 In the condition that IOSEL register is "1", after sending Acknowledge, a value "0" is output from the GPIO port which the corresponding bit is transferred as `0', and a input-mode(Hi-Z) is output from GPIO port which the corresponding bit is transferred as `1'.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
0
Ack
MSB
Reg Address
LSB
Ack
MSB
Data1 (GPIO[7:0])
LSB
Ack
MSB
Data2 (GPIO[15:8])
LSB
Ack
P
Acknowledge From Slave Start Condition GPIO [7:0] Write Acknowledge From Slave Acknowledge From Slave Stop Condition Data1 Valid
tDV
GPIO [15:8]
tDV
Data2 Valid
Fig. 14 Write to GPIO port Pull-up-mode
IOSEL=0 In the condition that IOSEL register is "0", data input or output is defined by the value of RWSEL register. Therefore, after "0" is written to each bit of RWSEL register, the data is output from GPIO port. If "0" is written to RWSEL register at first, the data will be output immediately from the GPIO port after the acknowledge signaling.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
0
Ack
MSB
Reg Address
LSB
Ack
MSB
Data1 (GPIO[7:0])
LSB
Ack
MSB
RWSEL = Write Mode
LSB
Ack
P
Acknowledge From Slave Start Condition GPIO [7:0] Write Acknowledge From Slave Acknowledge From Slave Stop Condition Data1 Valid
tDV
GPIO [15:8] Data2 Valid
tDV
Fig. 15 Write to GPIO port RWSEL-mode
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Technical Note
2.2 Read From GPIO Port After slave address and R/W bit is written, the GPIO ports value will be read into the GPIO registers. (refer to section 8.1.6 for 2-wire reading protocol.) The data fixed between tow consecutive acknowledges will be transferred to the Master.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
1
Ack
MSB
Data0
LSB
Ack
MSB
Data1
LSB
NA
P
Acknowledge From Master Start Condition Read Acknowledge From Slave No Acknowledge From Master GPIO Data0 Data1 Data2 Stop Condition
tDS
tDH
Fig. 16 Read from GPIO port
2.3 Interrupt Valid/Reset The transition of each GPIO port de-asserts the interrupt signal (INT), generates the interrupt signal by asserting the INT after each acknowledge signaling. Either a "High-Active" or a "Low-Active" interrupt signaling can be defined by changing the INTSEL register value beforehand.
SCL
1
2
3
4
5
6
7
8
9
SDA
S
X
X
X
X
X
X
X
1
Ack
MSB
Data2
LSB
Ack
MSB
Data3
LSB
NA
P
Acknowledge From Master Start Condition Read Acknowledge From Slave No Acknowledge From Master GPIO Data1 Data2 Data3 Stop Condition
INT
tIV
tIR
Fig. 17 Interrupt Valid/Reset
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The Setting Registers When setting address is written beyond 00h~09h, the register address will be forced to value 00h. When the final address is set to 09h, then the next address 00h will be written. By making XRST "Low", the setting register value will be initialed shown in following register map.
Technical Note
1. Register map Addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h Init ffh ffh 0fh 00h 00h 00h ffh ffh 0fh 03h Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W D7 GPIO7 GPIO15 MASK7 MASK15 RWSEL7 RWSEL1 5 D6 GPIO6 GPIO14 MASK6 MASK14 RWSEL6 RWSEL1 4 D5 GPIO5 GPIO13 MASK5 MASK13 RWSEL5 RWSEL1 3 D4 GPIO4 GPIO12 MASK4 MASK12 RWSEL4 RWSEL1 2 D3 GPIO3 GPIO11 GPIO19 MASK3 MASK11 MASK19 RWSEL3 RWSEL1 1 RWSEL1 9 D2 GPIO2 GPIO10 GPIO18 MASK2 MASK10 MASK18 RWSEL2 RWSEL1 0 RWSEL1 8 INTSEL D1 GPIO1 GPIO9 GPIO17 MASK1 MASK9 MASK17 RWSEL1 RWSEL9 RWSEL1 7 IOSEL2 D0 GPIO0 GPIO8 GPIO16 MASK0 MASK8 MASK16 RWSEL0 RWSEL8 RWSEL1 6 IOSEL1
2. Register functional explanations
Symbol GPIO7 GPIO0 GPIO15 GPIO8 GPIO19 GPIO16 MASK7 MASK0 MASK15 MASK8 MASK19 MASK16 RWSEL7 RWSEL0 RWSEL15 RWSEL8 RWSEL19 RWSEL16 IOSEL1 IOSEL2 INTSEL 09h Addr 00h Init ffh Description Read or write data of GPIO bit 0 to 7.
01h
ffh
Read or write data of GPIO bit 8 to 15. Read or write data of GPIO bit 16 to bit 19. In writing mode, 4 bits of MSB is ignored and in reading mode, 4 bits of "0" is filled up from MSB. 0: Interrupt is not masked when "0" is written to GPIO bit 0 to 7 1: Interrupt is masked when "0" is written to GPIO bit 0 to 7 0: Interrupt is not masked When "0" is written to GPIO bit 8 to 15 1: Interrupt is masked When "0" is written to GPIO bit 8 to 15 0: Interrupt is not masked when "0" is written to GPIO bit 16 to 19 1: Interrupt is masked when "0" is written to GPIO bit 16 to 19 In writing mode, 4 bit of MSB is ignored and in reading mode, 4 bits of "0" is filled up from MSB. 0: GPIO bit 0 through 7 becomes output mode. 1: GPIO bit 0 through 7 becomes input mode. 0: GPIO bit 8 through 15 becomes output mode. 1: GPIO bit 8 through 15 becomes input mode. 0: GPIO bit 16 through 19 becomes output mode. 1: GPIO bit 16 through 19 becomes input mode. 0: RWSEL bit 0 through 7 becomes available. 1: Change to pull-up mode. 0: RWSEL bit 8 through 19 becomes available. 1: Change to pull-up mode. 0: Make Interrupt "Low active". 1: Make Interrupt "High active".
02h
0fh
03h
00h
04h
00h
05h
00h
06h
ffh
07h
Ffh
08h
0fh 1h 1h 0h
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Technical Note
Appendix 1. About difference between I2C and 2-Wire 2-wire interface logic uses a normal IN/OUT cell (Hi-Z or only "0" output) instead of an Open-Drain cell in normal I2C interface. For this reason, the VDDI2C voltage level must be same as the connected other normal I2C masters'. Therefore, any other I2C slave with same bus level can be connected to the bus. 2 .In case of illegal access *1 during 2-Wire data transference The current data will be canceled and next access is necessary.
*1
In case of a consecutive Start-condition and Stop-condition occurred. In case of Resend-condition or Stop-condition occurred during a slave address or R/W bit witting cycles. In case of Resend-condition or Stop-condition occurred during data witting cycles.
3. About the handling of the no using GPIO port Any no using GPIO port must be pulled-up or connected to GND. In order to prevent from any unexpected interrupt happening when a no using GPIO is connected to GND, the corresponding bit of GPIO Mask register must be disabled by Mask register access, or simply read the GPIO value into corresponding internal GPIO port register. The no using GPIO port power supply (VDDIO1 or VDDIO2) must be connected to the voltage value defined in this specification, never left it open.
4. Caution of power on sequence The BU8272GUW can not works correctly even one of the power supply among the core power supply (VDD) and the I/O power supply ( VDDI2C, VDDIO1, VDDIO2) is not connected to specified conditions described in this specification. The power on sequence must be designed to give core power supply first then I/O power. Inversely, the I/O power supply must be switched off before the core power down in the device power down sequence.
5. Reset release timing Core power supply (VDD) and I/O power supply (VDDI2C, VDDIO1, VDDIO2) first. Afterwards, release XRST.
VD
VDDI2C , VDDIO1(2)
Release XRST
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Ordering part number
Technical Note
B
U
8
Part No.
2
7
2
G
U
W
-
E
2
Part No.
Package GUW: VBGA035W040
Packaging and forming specification E2: Embossed tape and reel
VBGA035W040
1PIN MARK 4.0 0.1

Tape
0.9MAX. 4.0 0.1
Embossed carrier tape (with dry pack) 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
Quantity Direction of feed
S
0.75 0.1 35- 0.2950.05 0.05 M S AB
A P=0.5x5 0.5 B
F E D C B A 123456
P=0.5x5
0.75 0.1
0.08 S
0.10
( reel on the left hand and you pull out the tape on the right hand
)
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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