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Rev PrB, 25-Feb-08 Advanced Product InformationAll Information Subject to Change
ACT8740
Six Channel Integrated Power Management IC for Handheld Portable Equipment FEATURES
* Multiple Patents Pending * Li+ Battery Charger with Integrated MOSFET
- Programmable Charge Current up to 1A - ON/OFF Control * Five Integrated Regulators - 350mA PWM Step-Down DC/DC - Step-Up DC/DC with OVP for WLED Bias - 350mA Low Noise LDO - 250mA Low Noise LDO - 250mA Low Noise LDO
GENERAL DESCRIPTION
The patent-pending ACT8740 is a complete, cost effective, highly-efficient ActivePMUTM power management solution that is ideal for a wide range of portable handheld equipment. This device integrates one PWM step-down DC/DC converter, one PWM step-up DC/DC converter with over-voltage protection (OVP), three low dropout linear regulators (LDOs) and a full-featured linear-mode Li+ battery charger into a single, thin, space-saving package. An I2C Serial Interface provides programmability for the DC/DC converters, LDOs and battery charger. REG1 is a fixed-frequency, current-mode PWM step -down DC/DC converter that is optimized for high efficiency and is capable of supplying up to 350mA output current. REG2 is a fixed-frequency, step-up DC/DC converter that safely and efficiently biases a string of up to seven white-LEDs for backlighting. REG3, REG4, and REG5 are low noise, high PSRR linear regulators that are capable of supplying up to 350mA, 250mA, and 250mA, respectively. The battery charger incorporates an internal power MOSFET for constant-current/constant-voltage, thermally regulated charging of a single-cell Li+ battery. All DC/DC converters and LDOs output voltages are programmable and controllable via the I2C interface. The ACT8740 is available in a tiny 4mm x 4mm 24-pin Thin-QFN package that is just 0.75mm thin.
* I2CTM Compatible Serial Interface
- Programmable Output Voltages - Configurable Operating Modes
* Minimal External Components * 4x4mm, Thin-QFN (TQFN44-24) Package
- Only 0.75mm Height - RoHS Compliant
APPLICATIONS
* Portable Devices and PDAs * Wireless Handhelds * DMB Enabled Devices * GPS Receivers, etc.
SYSTEM BLOCK DIAGRAM
VIN CHGLEV
Single-Cell Li+ Battery Charger
REG1
Step-Down DC/DC
Battery Programmable Up to 1A OUT1 1.1V to 4.4V Up to 350mA
nMSTR nIRQ SCL SDA ON1
REG2
System Control
Step-Up DC/DC
OUT2 WLED Bias OUT3 1.4 to 3.7V Up to 350mA OUT4 1.4 to 3.7V Up to 250mA OUT5 1.4 to 3.7V Up to 250mA
REG3
LDO
Pb-free
REG4
LDO
ACT8740
Active
PMU
TM
REG5
LDO
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ACT8740
TABLE OF CONTENTS
GENERAL INFORMATION ...................................................................................... P. 01
Functional Block Diagram ............................................................................................ p. 03 Ordering Information .................................................................................................... p. 04 Pin Configuration .......................................................................................................... p. 04 Pin Descriptions ........................................................................................................... p. 05 Absolute Maximum Ratings ......................................................................................... p. 07
Rev PrB, 25-Feb-08
SYSTEM MANAGEMENT ........................................................................................ P. 08
Register Descriptions ................................................................................................... p. 08 Electrical Characteristics .............................................................................................. p. 09 I2C Interface Electrical Characteristics ......................................................................... p. 10 Typical Performance Characteristics............................................................................ p. 11 Functional Description .................................................................................................. p. 12
STEP-DOWN DC/DC CONVERTERS ..................................................................... P. 14
Electrical Characteristics ............................................................................................. p. 14 Register Descriptions ................................................................................................... p. 15 Typical Performance Characteristics ........................................................................... p. 17 Functional Description .................................................................................................. p. 18
WLED BIAS DC/DC CONVERTER ......................................................................... P. 20
Electrical Characteristics ............................................................................................. p. 20 Register Descriptions ................................................................................................... p. 21 Typical Performance Characteristics ........................................................................... p. 23 Functional Description .................................................................................................. p. 24
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS....................................... P. 26
Electrical Characteristics ............................................................................................. p. 26 Register Descriptions ................................................................................................... p. 29 Typical Performance Characteristics............................................................................ p. 31 Functional Description .................................................................................................. p. 32
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) ................................................. P. 33
Electrical Characteristics .............................................................................................. p. 33 Register Descriptions ................................................................................................... p. 34 Typical Performance Characteristics ............................................................................ p. 36 Functional Description .................................................................................................. p. 37
PACKAGE INFORMATION ...................................................................................... P. 40
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ACT8740
FUNCTIONAL BLOCK DIAGRAM
VSYS
Rev PrB, 25-Feb-08
BODY AND VSYS CONTROL
ACT8740
BAT Li+ Battery +
CURRENT SENSE VOLTAGE SENSE
AC Adaptor or USB
4.3V to 6V
VIN
VINUVLO
4.0V Charge Control CHGLEV FLOAT
OUT3
PRECONDITION
2.9V
THERMAL REGULATION
110C
VP1 To Battery
SCL SDA Serial Interface REG1 SW1 OUT1 OUT1 GP1
VINUVLO
VSYS nMSTR PUSH BUTTON REG2 OUT3 nIRQ System Control
SW2 OVP2 FB2 GP2
To Battery OUT2
INL ON1 LDO REG3 REFBP OUT3 OUT3 To Battery
Reference
LDO REG4
OUT4 OUT4
GA LDO REG5 OUT5 OUT5
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ACT8740
ORDERING INFORMATION
PART NUMBER
ACT8740QLEGA-T
Rev PrB, 25-Feb-08
VOUT1
1.8V
VOUT3
3.0V
VOUT4
2.5V
VOUT5
3.0V
PACKAGE
TQFN44-24
PINS
24
TEMPERATURE RANGE
-40C to +85C
OUTPUT VOLTAGE CODES
C 1.2V D 1.5V E 1.8V F 2.5V G 3.0V H 3.3V
: Output voltage options detailed in this table represent standard voltage options, and are available for samples or production orders. Additional output voltage options, as detailed in the Output Voltage Codes table, are available for production subject to minimum order quantities. Contact Active-Semi for more information regarding semi-custom output voltage combinations. : All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
PIN CONFIGURATION
TOP VIEW
CHGLEV 23 OVP2
SW2
GP2
24 VIN SCL SDA nIRQ nMSTR OUT3 1 2 3 4 5 6 7 INL
BAT
FB2
22
21
20
19 18 REFBP 17 GA 16 VSYS
ACT8740
EP 8 OUT5 9 OUT4 10 GP1 11 SW1 12 VP1
15 ON1 14 GA 13 OUT1
Thin - QFN (TQFN44-24)
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ACT8740
PIN DESCRIPTIONS
PIN
1 2 3 4 5 6 7 8 9 10 11 12 13 14,17 15 16
Rev PrB, 25-Feb-08
NAME
VIN SCL SDA nIRQ nMSTR OUT3 INL OUT5 OUT4 GP1 SW1 VP1 OUT1 GA ON1 VSYS
DESCRIPTION
Power Input for the Battery Charger. The Battery Charger, REG1 and REG3 are automatically enabled whenever a valid voltage is present on VIN. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. Clock Input for I2C Serial Interface. Data is read on the rising edge of the clock. Data Input for I2C Serial Interface. Data is read on the rising edge of the clock. Open-Drain Push-Button Status Output. nIRQ is an open-drain output which sinks current when nMSTR is asserted or when a fault-condition occurs. If interrupts are not masked. Master Enable Input. Drive nMSTR to GA or to a logic low to enable the IC. Output voltage for REG3. Capable of delivering up to 350mA of output current. Output has high impedance when disabled. Power input for REG3, REG4 and REG5. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. Output voltage for REG5. Capable of delivering up to 250mA of output current. Output has high impedance when disabled. Output voltage for REG4. Capable of delivering up to 250mA of output current. Output has high impedance when disabled. Power Ground for REG1. Connect GA, GP1 and GP2 together at a single point as close to the IC as possible. Switching Node Output for REG1. Connect this pin to the switching end of the inductor. Power Input for REG1. Bypass to GP1 with a high quality ceramic capacitor placed as close as possible to the IC. Output Feedback Sense for REG1. Connect this pin directly to the output node to connect the internal feedback network to the output voltage. Analog Ground. Connect GA directly to a quiet ground node. Connect GA, GP1 and GP2 together at a single point as close to the IC as possible. Enable Control Input for REG1 and REG3. Drive ON1 to VSYS or to a logic high for normal operation, drive to GA or a logic low to disable REG1 and REG3. Power Bypass for System Management Circuitry. Bypass to GA with a high quality ceramic capacitor placed as close as possible to the IC. VSYS is internally connected to the higher voltage of either VVIN or VBAT. Do not load VSYS with more than 100A.
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ACT8740
PIN DESCRIPTIONS CONT'D
PIN
18 19 20 21 22 23
Rev PrB, 25-Feb-08
NAME
REFBP FB2 OVP2 GP2 SW2
DESCRIPTION
Reference Noise Bypass. Connect a 0.01F ceramic capacitor from REFBP to GA. This pin is discharged to GA in shutdown. Feedback Sense for REG2. Connect this pin to the LED string current sense resistor to sense the LED current. Over-Voltage Protection Input for REG2. Connect this pin directly to the output node to sense and prevent over-voltage conditions. Power Ground for REG2. Connect GP2 directly to a power ground plane. Connect GA, GP1 and GP2 together at a single point as close to the IC as possible. Switching Node Output for REG2. Connect this pin to the switching end of the inductor.
Tri-State Charging State Select Input. When ISET1[ ] = [0000], drive CHGLEV to VSYS or to a CHGLEV logic high for high-current charging mode (450mA), and drive to GA or a logic low for lowcurrent charging mode (90mA). Allow CHGLEV to float (|ICHGLEV| < 2A) to disable the charger. BAT EP Output Voltage for the Battery Charger. Connect this pin directly to the battery anode (+ terminal) to sense the battery voltage. Exposed Pad. Must be soldered to ground on PCB.
24 EP
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ACT8740
ABSOLUTE MAXIMUM RATINGS
PARAMETER
VP1, SW1 to GP1, VSYS, SCL, SDA, INL, OUT1, OUT2, OUT3, OUT4, OUT5, FB2, BAT, CHGLEV, ON1, nMSTR, nIRQ to GA SW1 to VP1 OVP2, SW2 to GP2 VIN to GA t <1ms and duty cycle <1% Steady State GP1, GP2 to GA RMS Power Dissipation (TA = 70C) Operating Temperature Range Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec)
Rev PrB, 25-Feb-08
VALUE
-0.3 to +6 -6 to +0.3 -0.3 to +30 -0.3 to +7 -0.3 to +6 -0.3 to +0.3 1.8 -40 to 85 125 -55 to 150 300
UNIT
V V V V V V W C C C C
: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect device reliability.
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ACT8740
SYSTEM MANAGEMENT REGISTER DESCRIPTIONS
Table 1: Global Register Map ADDRESS HEX A7
08h 09h 0Ah 0Bh 10h 11h 12h 13h 20h 21h 22h 23h 40h 41h 42h 43h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rev PrB, 25-Feb-08
OUTPUT CHGR CHGR CHGR CHGR REG1 REG1 REG1 REG1 REG2 REG2 REG2 REG2 REG3 REG4 REG5 REG345CFG
KEY:
DATA (DEFAULT VALUE) A2
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A6
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
A5
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
A4
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
A3
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
A1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 R R R R R R R R 0 R R R R 0 1 0 R V R R R R R R 0 R R R R 0 R 0 R V R R R V R 0 0 1 0 0 R 0 R 0 R V R R R V R 0 0 V V V 0 R R R 1 V R R R V R 0 R V V V 0 R R R 0 V R R 0 V R 0 0 V V V 0 R R R R V R R R V R 0 R V V V 0 R R R 0 V 0 R 1 V 0 0 0 V V V R
R: Read-Only bit. No Default Assigned. V: Default Values Depend on Voltage Option. Default Values May Vary. Note: Addresses other than those specified in Table 1 may be used for factory settings. Do not access any registers other than those specified in Table 1.
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ACT8740
SYSTEM MANAGEMENT ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
PARAMETER
VSYS Operating Voltage Range VSYS UVLO Threshold VSYS UVLO Hysteresis VSYS Output Resistance Oscillator Frequency VSYS Supply Current nMSTR Internal Pull-Up Resistance Logic High Input Voltage Logic Low Input Voltage Logic Low Output Voltage Leakage Current Thermal Shutdown Temperature Thermal Shutdown Hysteresis
TEST CONDITIONS
VSYS Voltage Rising VSYS Voltage Falling
MIN
2.6 2.25
TYP
2.4 80 10
MAX
5.5 2.55
UNIT
V V mV
1.35 ON1 = GA, CHGLEV = floating 250 ON1, nMSTR ON1, nMSTR nIRQ, ISINK = 5mA nIRQ, VnIRQ = 4.2V Temperature rising Temperature falling 1.4
1.6 1.5 500
1.85
MHz A k V
0.4 0.3 1 160 20
V V A C C
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ACT8740
SYSTEM MANAGEMENT I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
PARAMETER
SCL, SDA Low Input Voltage SCL, SDA High Input Voltage SCL, SDA Leakage Current SDA Low Output Voltage SCL Clock Period, tSCL SDA Data In Setup Time to SCL High, tSU SDA Data Out Hold Time after SCL Low, tHD SDA Data Low Setup Time to SCL Low, tST SDA Data High Hold Time after Clock High, tHP
TEST CONDITIONS
MIN
1.4
TYP
MAX
0.4
UNIT
V V
1 IOL = 5mA fSCL clock freq = 400kHz 2.5 100 300 Start Condition Stop Condition 100 100 0.3
A V s ns ns ns ns
Figure 1: I2C Serial Bus Timing tSCL SCL tST SDA IN tSU tSP
tHD
SDA OUT
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ACT8740
SYSTEM MANAGEMENT TYPICAL PERFORMANCE CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
Oscillator Frequency vs. Temperature
1.71 1.68 3 ACT8740-001
VSYS Current vs. Temperature
ACT8740-002 ON1 = GA
Supply Current (A)
Frequency (MHz)
1.65 1.62 1.59 1.56 1.53 1.50 -40 -20 0 20 40 60
VVSYS = 4.2V
2
VVSYS = 3.6V
1
VVSYS = 3.2V
85
0 -40
-20
0
20
40
60
85
Temperature (C)
Temperature (C)
Startup Sequence
ACT8740-003
Startup Sequence
ACT8740-004
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH1: VnMSTR, 5V/div CH2: Power-On Reset (External Signal), 2V/div CH3: VON1, 5V/div CH4: VOUT1, 2V/div
TIME: 100ms/div
CH1: VnMSTR, 5V/div CH2: Power-On Reset (External Signal), 2V/div CH3: VON1, 5V/div CH4: VOUT1, 2V/div
TIME: 100ms/div
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ACT8740
SYSTEM MANAGEMENT FUNTIONAL DESCRIPTION
General Description
The ACT8740 offers an array of system management functions that allow it to provide optimal performance in a wide range of applications.
Rev PrB, 25-Feb-08
Automatic Enable Due to Valid VIN Supply The ACT8740 battery charger, REG1, and REG3 are automatically enabled when a valid input supply is applied to VIN. Automatically enabling these functions simplifies system design and eliminates the need for external input supply-detection circuitry. Manual Enable Due to Asserting nMSTR Low System startup is initiated when the user presses the push-button, asserting nMSTR low. When this occurs, both REG1 and REG3 are enabled. Once the power-up routine is successfully completed, the microprocessor must assert ON1 so that the ACT8740 remains enabled after the push-button is released by the user. Upon completion of the startup sequence the processor assumes control of the power system and all further operation is softwarecontrolled. Manual Enable Due to Asserting ON1 High The ACT8740 is compatible with applications that do not utilize its push-button control function, and may be enabled by simply driving ON1 to a logichigh. In this case, the signal driving ON1 controls enable/disable timing, although software-controlled enable/disable sequences are still supported if the processor assumes control of the power system once the startup sequence is completed. Shutdown Sequence Once a successful power-up routine is completed, the system processor controls the operation of the power system, including the system shutdown timing and sequence. The ACT8740 asserts nIRQ low when nMSTR is asserted low, providing a simple means of alerting the system processor when the user wishes to shut the system down. Asserting nIRQ interrupts the system processor, initiating an interrupt service routine in the processor which will reveal that the user pressed the push-button. The microprocessor may validate the input, such as by ensuring that the push-button is asserted for a minimum amount of time, then initiates a softwarecontrolled power-down routine, the final step of which is to de-assert the ON1 input, disabling REG1 and REG3 and shutting the system down.
I2C Serial Interface
At the core of the ACT8740's flexible architecture is an I2C interface that permits optional programming capability to enhance overall system performance. To ensure compatibility with a wide range of system processors, the ACT8740 uses standard I2C commands, I2C write-byte commands are used to program the ACT8740 and I2C read-byte commands are used to read the ACT8740's internal registers. The ACT8740 always operates as a slave device, and is addressed using a 7-bit slave address followed by an eighth bit, which indicates whether the transaction is a read-operation or a write-operation, [1011110x]. SDA is a bi-directional data line and SCL is a clock input. The master initiates a transaction by issuing a START condition, defined by SDA transitioning from high to low while SCL is high. Data is transferred in 8-bit packets, beginning with the MSB, and is clocked-in on the rising edge of SCL. Each packet of data is followed by an "Acknowledge" (ACK) bit, used to confirm that the data was transmitted successfully. For more information regarding the I2C 2-wire serial interface, go to the NXP website: http://www.nxp.com
System Startup and Shutdown
The ACT8740 features a flexible control architecture that supports a variety of software-controlled enable/disable functions that make it a simple yet flexible and highly configurable solution. The ACT8740 is automatically enabled when any of the following conditions exists: 1) A valid supply voltage is present at VIN, 2) nMSTR is asserted low, or 3) ON1 is asserted high. If any of these conditions is true, the ACT8740 enables REG1 and REG3, powering up the system processor so that the startup and shutdown sequences may be controlled via software. Each of these startup conditions are described in detail below.
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ACT8740
SYSTEM MANAGEMENT
nMSTR Enable Input In most applications, connect nMSTR to an active low, momentary push-button switch to utilize the ACT8740's closed-loop enable/disable functionality. If a momentary-on switch is not used, drive nMSTR to GA or to a logic low to initiate a startup sequence. nIRQ Output The ACT8740 provides an active-low, open-drain push-button status output that sinks current when nMSTR is driven to a logic-low. Connect a pull-up resistor from nIRQ to an appropriate voltage supply. nIRQ is typically used to drive the interrupt input of the system processor, and is useful in a variety of software-controlled enable/disable control routines. Thermal Shutdown The ACT8740 integrates thermal shutdown protection circuitry to prevent damage resulting from excessive thermal stress, as may be encountered under fault conditions. This circuitry disables all regulators if the ACT8740 die temperature exceeds 160C, and prevents the regulators from being enabled until the IC temperature drops by 20C (typ).
Rev PrB, 25-Feb-08
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ACT8740
STEP-DOWN DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
(VVP1 = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
PARAMETER
VP1 Operating Voltage Range VP1 UVLO Threshold VP1 UVLO Hysteresis Standby Supply Current Shutdown Supply Current Output Voltage Regulation Accuracy Line Regulation Load Regulation Current Limit Oscillator Frequency PMOS On-Resistance NMOS On-Resistance SW1 Leakage Current Power Good Threshold Minimum On-Time
TEST CONDITIONS
Input Voltage Rising Input Voltage Falling
MIN
3.1 2.9
TYP
3 80 130
MAX
5.5 3.1
UNIT
V V mV
200 1 +1.8% +1.8%
A A V %/V %/mA A
ON1 = GA, VVP1 = 4.2V VNOM1 < 1.3V, IOUT1 = 10mA VNOM1 1.3V, IOUT1 = 10mA VVP1 = Max(VNOM1 + 1V, 3.2V) to 5.5V IOUT1 = 10mA to 350mA 0.45 VOUT1 20% of VNOM1 VOUT1 = 0V ISW1 = -100mA ISW1 = 100mA VVP1 = 5.5V, VSW1 = 5.5V or 0V 1.35 -2.4% -1.2%
0.1 VNOM1 VNOM1 0.15 0.0017 0.6 1.6 530 0.45 0.3
1.85
MHz kHz
0.75 0.5 1
A %VNOM1 ns
94 70
: VNOM1 refers to the nominal output voltage level for VOUT1 as defined by the Ordering Information section.
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ACT8740
STEP-DOWN DC/DC CONVERTER REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev PrB, 25-Feb-08
Table 2: REG1 Control Register Map ADDRESS
10h 11h 12h 13h
DATA D7
R R R R
D6
VRANGE R R R
D5
R R R
D4
R R R
D3
VSET R R R
D2
R R W/E
D1
R R OK
D0
MODE R W/E
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1 .
Table 3: REG1 Control Register Bit Descriptions ADDRESS
10h 10h 10h 11h 11h 12h 13h 13h 13h 13h OK MODE
NAME
VSET VRANGE
BIT
[5:0] [6] [7] [0] [7:1] [7:0] [0] [1] [2] [7:3]
ACCESS
R/W R/W R R/W R R W/E R W/E R
FUNCTION
REG1 Output Voltage Selection REG1 Voltage Range Selection 0 1 0 1
DESCRIPTION
See Table 4 Min VOUT = 1.1V Min VOUT = 1.25V READ ONLY PWM/PFM Forced PWM READ ONLY READ ONLY WRITE-EXACT 0 1 Output is not OK Output is OK WRITE-EXACT READ ONLY
Mode Selection
REG1 Power-OK
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ACT8740
STEP-DOWN DC/DC CONVERTER REGISTER DESCRIPTIONS CONT'D
Table 4: REG1/VSET[ ] Output Voltage Setting REG1/VSET[5:4] REG1/VSET [3:0] 00
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
(N/A): Not Available
Rev PrB, 25-Feb-08
REG1/VRANGE[ ] = [0] 01
N/A N/A 1.100 1.125 1.150 1.175 1.200 1.225 1.255 1.280 1.305 1.330 1.355 1.380 1.405 1.430
REG1/VRANGE[ ] = [1] 11
1.860 1.890 1.915 1.940 1.965 1.990 2.015 2.040 2.065 2.090 2.115 2.140 2.165 2.190 2.200 2.245
10
1.455 1.480 1.505 1.530 1.555 1.585 1.610 1.635 1.660 1.685 1.710 1.735 1.760 1.785 1.810 1.835
00
1.250 1.300 1.350 1.400 1.450 1.500 1.550 1.600 1.650 1.700 1.750 1.800 1.850 1.900 1.950 2.000
01
2.050 2.100 2.150 2.200 2.250 2.300 2.350 2.400 2.450 2.500 2.550 2.600 2.650 2.700 2.750 2.800
10
2.850 2.900 2.950 3.000 3.050 3.100 3.150 3.200 3.250 3.300 3.350 3.400 3.450 3.500 3.550 3.600
11
3.650 3.700 3.750 3.800 3.850 3.900 3.950 4.000 4.050 4.100 4.150 4.200 4.250 4.300 4.350 4.400
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
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ACT8740
STEP-DOWN DC/DC CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8740QLEGA, VVP1 = VVP2 = 3.6V, L = 3.3H, CVP1 = CVP2 = 2.2F, COUT1 = COUT2 = 10F, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
REG1 Efficiency vs. Load Current
100
REG1 Transient Peak Inductor Current
650 ACT8740-006 ACT8740-005
Peak Inductor Current (mA)
VOUT1 = 1.8V
3.2V
90
630
Efficiency (%)
80
3.6V
4.2V
610
70
590
60
570 550
50 0.1
1
10
100
1000
3.0
3.5
4.0
4.5
5.0
5.5
Output Current (mA)
VP1 Voltage (V)
REG1 MOSFET Resistance
600 500 PMOS 0.2
REG1 Load Regulation
ACT8740-008
Load Regulation Error (%)
ACT8740-007
0.0 -0.2 -0.4 -0.6 -0.8 -1.0 4.2V
RDSON (m)
400 300 200 100 0 2.5 NMOS
3.6V
3.0
3.5
4.0
4.5
5.0
5.5
0
50
100
150
200
250
300
350
400
VP1 Voltage (V)
Output Current (mA)
OUT1 Regulation Voltage
1.812 1.808 ACT8740-009 IOUT1 = 35mA
OUT1 Voltage (V)
1.804 1.800 1.796 1.792 1.788 -40 -20 0 20 40 60
85
Temperature (C)
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ACT8740
STEP-DOWN DC/DC CONVERTER FUNCTIONAL DESCRIPTION
General Description
REG1 is a fixed-frequency, current-mode, synchronous PWM step-down converters that achieves a peak efficiency of up to 97%. REG1 is capable of supplying up to 350mA of output current and operates with a fixed frequency of 1.6MHz, minimizing noise in sensitive applications and allowing the use of small external components. REG1 is available with a variety of standard and custom output voltages, and may be software-controlled via the I2C interface by systems that require advanced power management functions.
Rev PrB, 25-Feb-08
Programmable Operating Mode
By default, REG1 operates in fixed-frequency PWM mode at medium to heavy loads, then transitions to a proprietary power-saving mode at light loads in order to save power. In applications where low noise is critical, force fixed-frequency PWM operation across the entire load current range, at the expense of light-load efficiency, by setting the REG1/MODE[ ] bit to [1].
Power-OK
REG1 features a power-OK status bit that can be read by the system microprocessor. If the output voltage is lower than the power-OK threshold, typically 6% below the programmed regulation voltage, REG1/OK[ ] will clear to 0.
100% Duty Cycle Operation
REG1 is capable of operating at up to 100% duty cycle. During 100% duty-cycle operation, the highside power MOSFET is held on continuously, providing a direct connection from the input to the output (through the inductor), ensuring the lowest possible dropout voltage in battery-powered applications.
Soft-Start
REG1 includes internal soft-start circuitry, and enabled its output voltage tracks an internal 80s softstart ramp so that it powers up in a monotonic manner that is independent of loading.
Synchronous Rectification
REG1 features an integrated n-channel synchronous rectifier, which maximizes efficiency and minimizes the total solution size and cost by eliminating the need for an external rectifier.
Compensation
REG1 utilizes current-mode control and a proprietary internal compensation scheme to simultaneously simplify external component selection and optimize transient performance over its full operating range. No compensation design is required, simply follow a few simple guidelines described below when choosing external components.
Enabling and Disabling REG1
Enable/disable functionality is typically implemented as part of a controlled enable/disable scheme utilizing nMSTR and other system control features of the ACT8740. REG1 is automatically enabled whenever either of the following conditions are met: 1) nMSTR is driven low, or 2) ON1 is asserted high. When none of these conditions are true, REG1 is disabled, and its quiescent supply current drops to less than 1A.
Input Capacitor Selection
The input capacitor reduces peak currents and noise induced upon the voltage source. A 2.2F ceramic input capacitor is recommended for most applications.
Output Capacitor Selection
For most applications, a 10F ceramic output capacitor is recommended. Although REG1 was designed to take advantage of the benefits of ceramic capacitors, namely small size and very-low ESR, low-ESR tantalum capacitors can provide acceptable results as well.
Programming the Output Voltage
By default, REG1 powers up and regulates to its default output voltage. Once the system is enabled, REG1's output voltage may be programmed to a different value, typically in order to reduce the power consumption of a microprocessor in standby mode. Program the output voltage via the I2C serial interface by writing to the REG1/VSET1[ ] register.
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Inductor Selection
REG1 utilizes current-mode control and a proprietary internal compensation scheme to simultaneously
- 18 www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
STEP-DOWN DC/DC CONVERTER
simplify external component selection and optimize transient performance over its full operating range. REG1 was optimized for operation with a 3.3H inductor, although inductors in the 2.2H to 4.7H range can be used. Choose an inductor with a low DC-resistance, and avoid inductor saturation by choosing inductors with DC ratings that exceed the maximum output current of the application by at least 30%.
Rev PrB, 25-Feb-08
PCB Layout Considerations
High switching frequencies and large peak currents make PC board layout an important part of stepdown DC/DC converter design. A good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Stepdown DC/DCs exhibit discontinuous input current, so the input capacitors should be placed as close as possible to the IC, and avoiding the use of vias if possible. The inductor, input filter capacitor, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. The ground nodes for each regulator's power loop should be connected at a single point in a star-ground configuration, and this point should be connected to the backside ground plane with multiple vias. The output node should be connected to the OUT1 pin through the shortest possible route, while keeping sufficient distance from switching nodes to prevent noise injection. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance.
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
WLED BIAS DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
(VVSYS = 3.6V, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
PARAMETER
Input Voltage Range UVLO Voltage Threshold UVLO Voltage Hysteresis Supply Current FB2 Feedback Voltage FB2 Input Current Oscillator Frequency Minimum On-Time Maximum Duty Cycle Switch Current Limit Switch On-Resistance Switch Leakage Current Over Voltage Threshold
TEST CONDITIONS
VSYS Voltage Rising VSYS Voltage Falling REG2/ON[ ] = [1], VFB2 = 0.3V REG2/ON[ ] = [0], ILOAD = 0mA
MIN
2 2.9
TYP
3 80 75 0.1
MAX
5.5 3.1
UNIT
V V mV
150 1 275
A mV nA
235
255 50
1.35
1.6 100
1.85
MHz ns % mA
85 Duty = 83%, L = 22H, COUT2 = 4.7F ISW2 = 100mA VSW2 = 30V, Regulator Disabled VSET[ ] = [111111] 27.5 500
90 750 0.67 1.1 10 28.5 29.5
A V
: As long as VSYS is within the VSYS operating range, this spec refers to the voltage range of the input that the inductor is connected to.
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
WLED BIAS DC/DC CONVERTER REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev PrB, 25-Feb-08
Table 5: REG2 Control Register Map ADDRESS
20h 21h 22h 23h
DATA D7
R R R W/E
D6
R R R W/E
D5
R W/E W/E
D4
R W/E W/E
D3
VSET R W/E R
D2
R W/E W/E
D1
R W/E OK
D0
W/E W/E ON
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 6: REG2 Control Register Bit Descriptions ADDRESS
20h 20h 21h 21h 22h 22h 23h ON
NAME
VSET
BIT
[5:0] [7:6] [0] [7:1] [5:0] [7:6] [0]
ACCESS
R/W R W/E R W/E R R/W
FUNCTION
REG2 Over Voltage Threshold Selection
DESCRIPTION
See Table 7 READ ONLY WRITE-EXACT READ ONLY WRITE-EXACT READ ONLY
REG2 Enable
0 1 0 1
REG2 Disable REG2 Enable Output is not OK Output is OK WRITE-EXACT READ ONLY WRITE-EXACT
23h 23h 23h 23h
OK
[1] [2] [3] [7:4]
R W/E R W/E
REG2 Power-OK
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
WLED BIAS DC/DC CONVERTER REGISTER DESCRIPTIONS CONT'D
Table 7: REG2/VSET[ ] Over Voltage Threshold Setting REG2/VSET [2:0]
000 001 010 011 100 101 110 111
Rev PrB, 25-Feb-08
REG2/VSET[5:3] 000
5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75
001
7.00 7.25 7.50 7.75 8.00 8.25 8.50 8.75
010
9.000 9.250 9.500 9.750 10.00 10.25 10.50 10.75
011
11.00 11.25 11.50 11.75 12.00 12.25 12.50 12.75
100
13.00 13.50 14.00 14.50 15.00 15.50 16.00 16.50
101
17.00 17.50 18.00 18.50 19.00 19.50 20.00 20.50
110
21.00 21.50 22.00 22.50 23.00 23.50 24.00 24.50
111
25.00 25.50 26.00 26.50 27.00 27.50 28.00 28.50
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ACT8740
WLED BIAS DC/DC CONVERTER TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8740QLEHA, VVSYS = 3.6V, L = 22H, COUT = 2.2F, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
REG2 Efficiency vs. Output Current
100 4 LEDs 90 900 800 700 ACT8740-010
REG2 RDSON
ACT8740-011
Efficiency (%)
80
RDSON (m)
6 LEDs
600 500 400
70
60
300 200 1 5 9 13 17 21 25 31 2.5 3.0 3.5 4.0 4.5 5.0 5.5
50
Output Current (mA)
VSYS Voltage (V)
REG2 Over-Voltage Protection
ACT8740-012
REG2 Startup Waveform
ACT8740-013
CH1
CH1 0V
REG2/ON[ ] = 1 CH2 0V REG2/ON[ ] = 0 CH1: VOUT3, 10V/div CH2: VFB3, 200mV/div TIME: 2ms/div
CH1: VOUT2, 10V/div TIME: 100s/div
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
WLED BIAS DC/DC CONVERTER FUNCTIONAL DESCRIPTION
General Description
REG2 is a highly efficient step-up DC/DC converter that employs a fixed frequency, current-mode, PWM architecture. This regulator is optimized for white-LED bias applications consisting of up to seven white-LEDs.
Rev PrB, 25-Feb-08
Inductor Selection
REG2 was designed to provide excellent performance across a wide range of applications, but was optimized for operation with inductors in the 10H to 22H range, although larger inductor values of up to 68H can be used to achieve the highest possible efficiency.
Enabling and Disabling REG2
Enable/disable control of REG2 is achieved through the ACT8740's I2C serial interface. Enable REG2 by setting REG2/ON[ ] to [1], disable REG2 by clearing REG2/ON[ ] to [0]. When disabled, REG2's quiescent supply current drops to just 1A. As with all non-synchronous step-up DC/DC converters, REG2's application circuit produces a DC current path between the input and the output in shutdown mode. Although the forward drop of the WLEDs makes this leakage current very small in most applications, it is important to consider the effect that this may have in your application particularly when using fewer than three WLEDs.
Optimizing for Smallest Footprint
REG2 is capable of operating with very low inductor values in order to achieve the smallest possible footprint. When solution size is of primary concern, best results are achieved when using an inductor that ensures discontinuous conduction mode (DCM) operation over the full load current range.
Optimizing for Highest Efficiency
REG2 achieves excellent efficiency in applications that demand the longest possible battery life. When efficiency is the primary design consideration, best results are achieved when using an inductor that results in continuous conduction mode (CCM) operation and achieves very small inductor ripple current.
Over-Voltage Protection
REG2 features internal over-voltage protection (OVP) circuitry which protects the system from LED open-circuit fault conditions. If the voltage at OV ever reaches the over-voltage threshold, REG2 will regulate the top of the LED strong to the OVP threshold voltage. By default, the ACT8740's OVP threshold is set at 28.5V, although it may be programmed to a lower value by writing to the REG2/VSET[ ] register.
Output Capacitor Selection
REG2 was designed to operate with output capacitors ranging from 0.47F to 10F, providing design flexibility. A 1F output capacitor is suitable for most applications, although larger output capacitors may be used to minimize output voltage ripple, if needed. Ceramic capacitors are recommended for most applications.
Power-OK Bit
REG2 features a Power-OK status bit that can be read by the system microprocessor via the I2C interface. If the voltage at OV is greater than the OVP threshold, REG2/OK[ ] will clear to 0.
Rectifier Selection
REG2 requires a Schottky diode to rectify the inductor current. Select a low forward voltage drop Schottky diode with a forward current (IF) rating that is sufficient to support the maximum switch current and a sufficient peak repetitive reverse voltage (VRRM) to support the output voltage.
Compensation and Stability
REG2 utilizes current-mode control and an internal compensation network to optimize transient performance, ease compensation, and improve stability over a wide range of operating conditions. REG2 is a flexible regulator, and its external components can be chosen to achieve the smallest possible footprint or to achieve the highest possible efficiency.
Setting the LED Bias Current
The LED bias current is set by a resistor connected from FB2 and ground, and the regulator is satisfied when the LED current is sufficient to generate 250mV across this resistor. Once the bias current is programmed, the LED current can be
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- 24 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
WLED BIAS DC/DC CONVERTER
adjusted using the ACT8740's Direct-PWM feature. REG2 is also compatible with a variety of well-known LED dimming circuits, such as with a DC control voltage and a filtered PWM signal.
Rev PrB, 25-Feb-08
PCB Layout Considerations
High switching frequencies and large peak currents make PC board layout a very important part of the design. Good design minimizes excessive EMI on the feedback paths and voltage gradients in the ground plane, both of which can result in instability or regulation errors. Step-up DC/DCs exhibit continuous input current, so there is some amount of flexibility in placing vias in the input capacitor circuit. The inductor, input filter capacitor, rectifier, and output filter capacitor should be connected as close together as possible, with short, direct, and wide traces. Connect the ground nodes together in a star configuration, with a direct connection to the exposed pad. Finally, the exposed pad should be directly connected to the backside ground plane using multiple vias to achieve low electrical and thermal resistance. Note that since the LED string is a low, DC-current path, it does not generally require special layout consideration.
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ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 25 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT3 = 1F, TA = 25C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VINL Input Rising VINL Input Falling TA = 25C TA = -40C to 85C VINL = Max(VOUT3 + 0.5V, 3.6V) to 5.5V IOUT3 = 1mA to 350mA f = 1kHz, IOUT3 = 350mA, COUT3 = 1F f = 10kHz, IOUT3 = 350mA, COUT3 = 1F Regulator Enabled Regulator Disabled IOUT3 = 160mA, VOUT3 > 3.1V
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
VNOM3 VNOM3 0 -0.004 70 60 40 0 100
+2 +3
% mV %/mA dB
Supply Current per Output Dropout Voltage Output Current Current Limit Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT3 Range Discharge Resistor in Shutdown
A 200 350 mV mA s % VRMS 20 F
VOUT3 = 95% of regulation voltage
400 100
VOUT3, hysteresis = -4% COUT3 = 10F, f = 10Hz to 100kHz 1 LDO Disabled, DIS3[ ] = [1]
89 40
650
: VNOM3 refers to the nominal output voltage level for VOUT3 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage. : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 30% (typ)
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ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT4 = 1F, TA = 25C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VINL Input Rising VINL Input Falling TA = 25C TA = -40C to 85C VINL = Max(VOUT4 + 0.5V, 3.6V) to 5.5V IOUT4 = 1mA to 250mA f = 1kHz, IOUT4 = 250mA, COUT4 = 1F f = 10kHz, IOUT4 = 250mA, COUT4 = 1F Regulator Enabled Regulator Disabled IOUT4 = 120mA, VOUT4 > 3.1V
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
VNOM4 VNOM4 0 -0.004 70 60 40 0 100
+2 +3
% mV %/mA dB
Supply Current per Output Dropout Voltage Output Current Current Limit Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT4 Range Discharge Resistor in Shutdown
A 200 250 mV mA mA
VOUT4 = 95% of regulation voltage
280 100
s % VRMS 20 F
VOUT4, hysteresis = -4% COUT4 = 10F, f = 10Hz to 100kHz 1 LDO Disabled, DIS4[ ] = [1]
89 40
650
: VNOM4 refers to the nominal output voltage level for VOUT4 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage. : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 30% (typ)
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- 27 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS ELECTRICAL CHARACTERISTICS
(VINL = 3.6V, COUT5 = 1F, TA = 25C, unless otherwise specified.)
PARAMETER
INL Operating Voltage Range INL UVLO Threshold UVLO Hysteresis Output Voltage Accuracy Line Regulation Error Load Regulation Error Power Supply Rejection Ratio
TEST CONDITIONS
VINL Input Rising VINL Input Falling TA = 25C TA = -40C to 85C VINL = Max(VOUT5 + 0.5V, 3.6V) to 5.5V IOUT5 = 1mA to 250mA f = 1kHz, IOUT5 = 250mA, COUT5 = 1F f = 10kHz, IOUT5 = 250mA, COUT5 = 1F Regulator Enabled Regulator Disabled IOUT5 = 120mA, VOUT5 > 3.1V
MIN
3.1 2.9
TYP
3 0.1
MAX
5.5 3.1
UNIT
V V V
-1.2 -2.5
VNOM5 VNOM5 0 -0.004 70 60 40 0 100
+2 +3
% mV %/mA dB
Supply Current per Output Dropout Voltage Output Current Current Limit Internal Soft-Start Power Good Flag High Threshold Output Noise Stable COUT5 Range Discharge Resistor in Shutdown
A 200 250 mV mA mA
VOUT5 = 95% of regulation voltage
280 100
s % VRMS 20 F
VOUT5, hysteresis = -4% COUT5 = 10F, f = 10Hz to 100kHz 1 LDO Disabled, DIS5[ ] = [1]
89 40
650
: VNOM5 refers to the nominal output voltage level for VOUT5 as defined by the Ordering Information section. : Dropout Voltage is defined as the differential voltage between input and output when the output voltage drops 100mV below the regulation voltage at 1V differential voltage. : LDO current limit is defined as the output current at which the output voltage drops to 95% of the respective regulation voltage. Under heavy overload conditions the output current limit folds back by 30% (typ)
Innovative Products. Active Solutions.
ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 28 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Table 8: CFG Control Register Map ADDRESS
40h 41h 42h 43h
DATA D7
R R R OK5
D6
R R R OK4
D5
ON3 ON4 ON5 OK3
D4
D3
D2
VSET3 VSET4 VSET5
D1
D0
DIS5
DIS4
DIS3
W/E
R
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 9: REG345 Control Register Bit Descriptions ADDRESS
40h 40h 40h 41h 41h 41h 42h 42h 42h 43h 43h 43h DIS3 VSET5 ON5 VSET4 ON4
NAME
VSET3 ON3
BIT
[4:0] [5] [7:6] [4:0] [5] [7:6] [4:0] [5] [7:6] [0] [1] [2]
ACCESS
R/W R/W R R/W R/W R R/W R/W R R W/E R/W
FUNCTION
REG3 Output Voltage Selection REG3 Enable 0 1
DESCRIPTION
See Table 10 REG3 Disable REG3 Enable READ ONLY
REG4 Output Voltage Selection REG4 Enable 0 1
See Table 10 REG4 Disable REG4 Enable READ ONLY
REG5 Output Voltage Selection REG5 Enable 0 1
See Table 10 REG5 Disable REG5 Enable READ ONLY READ ONLY WRITE-EXACT
REG3 Discharge Enable
0 1 0 1
Discharge Disable Discharge Enable Discharge Disable Discharge Enable
43h
DIS4
[3]
R/W
REG4 Discharge Enable
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www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS REGISTER DESCRIPTIONS CONT'D
Table 9: Control Register Bit Descriptions (Cont'd) ADDRESS
43h
NAME
DIS5
BIT
[4]
ACCESS
R/W
FUNCTION
REG5 Discharge Enable 0 1 0 1 0 1 0 1
DESCRIPTION
Discharge Disable Discharge Enable Output is not OK Output is OK Output is not OK Output is OK Output is not OK Output is OK
43h
OK3
[5]
R
REG3 Power-OK
43h
OK4
[6]
R
REG4 Power-OK
43h
OK5
[7]
R
REG5 Power-OK
Table 10: REG345CFG/VSETx[ ] Output Voltage Setting REG345CFG/VSETx[4:3] 00
1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1
REG345CFG/VSETx[2:0]
000 001 010 011 100 101 110 111
01
2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
10
2.55 2.60 2.65 2.70 2.75 2.80 2.85 2.90
11
3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
Innovative Products. Active Solutions.
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- 30 -
www.active-semi.com Copyright (c) 2008 Active-Semi, Inc.
ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8740QLEGA, VVIN = 5V, TA = 25C, unless otherwise specified.) Dropout Voltage vs. Output Current
225 200 ACT8740-015 ACT8740-014
Load Regulation
0.5 0.4
Output Voltage (%)
0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0 25 50 75
Dropout Voltage (mV)
175 150 125 100 75 50 25 0
REG4, REG5
REG3
3.1V 3.3V 3.6V 0 50 100 150 200 250 300 350
100 125 150 175 200 225 250
Load Current (mA)
Output Current (mA)
Output Voltage Deviation vs. Temperature Output Voltage Deviation (%)
0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -40 -15 10 35 60 85 ACT8740-016 ILOAD = 0mA
LDO Output Voltage Noise
ACT8740-017
CH1
CREF = 10nF
Temperature (C)
CH1: VOUTx, 200V/div (AC COUPLED) TIME: 200ms/div
Region of Stable COUT ESR vs. Output Current
ACT8740-018 1
ESR ()
0.1 Stable ESR
0.01 0 50 100 150 200 250 300 350
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ACT8740
Rev PrB, 25-Feb-08
LOW-NOISE, LOW-DROPOUT, LINEAR REGULATORS FUNCTIONAL DESCRIPTION
General Description
REG3, REG4, and REG5 are low-noise, lowdropout linear regulators (LDOs) that are optimized for low-noise and high-PSRR operation, achieving more than 60dB PSRR at frequencies up to 10kHz.
Optional LDO Output Discharge
Each of the ACT8740's LDOs features an optional, independent output voltage discharge feature. When this feature is enabled, the LDO output is discharged to ground through a 1k resistance when the LDO is shutdown. This feature may be enabled or disabled via the I2C interface by writing to the REG345CFG/DISx[ ] bits.
LDO Output Voltage Programming
All LDOs feature independently-programmable output voltages that are set via the I2C serial interface, increasing the ACT8740's flexibility while reducing total solution size and cost. Set the output voltage by writing to the REG345CFG/VSETx[ ] registers.
Output Capacitor Selection
REG3, REG4, and REG5 each require only a small ceramic capacitor for stability. For best performance, each output capacitor should be connected directly between the OUTx and G pins as possible, with a short and direct connection. To ensure best performance for the device, the output capacitor should have a minimum capacitance of 1F, and ESR value between 10m and 200m. High quality ceramic capacitors such as X7R and X5R dielectric types are strongly recommended.
Output Current Capability
REG3, REG4, and REG5 each supply 250mA of load current. Excellent performance is achieved over each regulator's entire load current ranges.
Output Current Limit
In order to ensure safe operation under over-load conditions, each LDO features current-limit circuitry with current fold-back. The current-limit circuitry limits the current that can be drawn from the output, providing protection in over-load conditions. For additional protection under extreme over current conditions, current-fold-back protection reduces the current-limit by approximately 30% under extreme overload conditions.
PCB Layout Considerations
The ACT8740's LDOs provide good DC, AC, and noise performance over a wide range of operating conditions, and are relatively insensitive to layout considerations. When designing a PCB, however, careful layout is necessary to prevent other circuitry from degrading LDO performance. A good design places input and output capacitors as close to the LDO inputs and output as possible, and utilizes a star-ground configuration for all regulators to prevent noise-coupling through ground. Output traces should be routed to avoid close proximity to noisy nodes, particularly the SW nodes of the DC/DCs. REFBP is a filtered reference noise, and internally has a direct connection to the linear regulator controller. Any noise injected onto REFBP will directly affect the outputs of the linear regulators, and therefore special care should be taken to ensure that no noise is injected to the outputs via REFBP. As with the LDO output capacitors, the REFBP bypass capacitor should be placed as close to the IC as possible, with short, direct connections to the star-ground. Avoid the use of vias whenever possible. Noisy nodes, such as from the DC/DCs, should be routed as far away from REFBP as possible.
Enabling and Disabling the LDOs
All LDOs feature independent enable/disable control via the I2C serial interface. Independently enable or disable each output by writing to the appropriate REG345CFG/ONx[ ] bit.
Power-OK
Each of the LDOs features Power-OK status bit that can be read by the system microprocessor via the I2C interface. If an output voltage is lower than the power-OK threshold, typically 6% below the programmed regulation voltage, the corresponding REG345CFG/OKx[ ] will clear to 0.
Reference Bypass Pin
The ACT8740 contains a reference bypass pin which filters noise from the reference, providing a low-noise voltage reference to the LDOs. Bypass REF to G with a 0.01F ceramic capacitor.
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) ELECTRICAL CHARACTERISTICS
(VVIN = 5V, VBAT = 3.6V, ISET1[ ] = [0000], TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
PARAMETER
VIN Operating Voltage Range VIN UVLO Threshold VIN UVLO Hysteresis On-Resistance Battery Termination Voltage Line Regulation Load Regulation Charge Current Precondition Charge Current Precondition Threshold Voltage Precondition Threshold Hysteresis End-of-Charge Current Threshold End-of-Charge Delay Charge Restart Threshold Thermal Regulation Threshold BAT Reverse Leakage Current
TEST CONDITIONS
VIN Voltage Rising VIN Voltage Falling TA = 25C VVIN = 4.5V to 5.5V, TA = 0C to 85C VVIN = 4.5V to 5.5V, IBAT = 10mA IBAT = 50mA to 500mA VBAT = 4V, CHGLEV = GA VBAT = 4V, CHGLEV = VSYS VBAT = 2.7V, CHGLEV = GA or VSYS VBAT Voltage Rising VBAT Voltage Falling VBAT = 4.2V, CHGLEV = VSYS
MIN
4.3 3.75
TYP
4 500 300
MAX
6 4.25 500 4.221 4.242
UNIT
V V mV m V V %/V %/mA
4.179 4.158
4.200 4.200 0.2 0.001 90
100 500 60 3.05
mA mA mA V mV
400 30 2.75
450 45 2.9 150
20
38 4
56
mA min mV C
VSET[ ] - VBAT, VBAT Falling VBAT = 4.2V, VIN = GA or BAT VVIN < UVLO Voltage SLEEP, SUSPEND or TIMEOUT-FAULT state PRECONDITION, FAST-CHARGE, or TOP-OFF state
200 110 0.4 50 200 700 90 4 1.4 -2 2 0.4 2
A A A A min hr V A V
VIN Supply Current
Precondition Timeout Period Total Timeout Period CHGLEV Logic High Input Voltage CHGLEV Tri-state Current Threshold CHGLEV Logic Low Input Voltage
TIMOSET[ ] = [10] TIMOSET[ ] = [10] ICHGLEV 15A ICHGLEV -15A
: Charger is suspended when CHGLEV pin current is within this range
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) REGISTER DESCRIPTIONS
Note: See Table 1 for default register settings.
Rev PrB, 25-Feb-08
Table 11: Battery Charger (CHGR) Control Register Map ADDRESS
08h 09h 0Ah 0Bh TIMOSET LDOMODE R R
DATA D7 D6
ISET1 R ISET2 R R BATFLT
D5
D4
D3
R TIMOFLT R W/E
D2
R TEMPFLT R ICHGSET
D1
R CHGSTAT R CHGROK
D0
R VINPOK R SUSCHG
R: Read-Only bits. Default Values May Vary. W/E: Write-Exact bits. Read/Write bits which must be written exactly as specified in Table 1.
Table 12: Battery Charger (CHGR) Control Register Bit Descriptions ADDRESS
08h 08h 09h ISET1 VINPOK
NAME
BIT
[3:0] [7:4] [0]
ACCESS
R R/W R
FUNCTION
ISET1 Charge Current Selection Input Supply Power-OK 0 1 0 1 0 1 0 1 0 1
DESCRIPTION
READ ONLY See Table 13 Input Power is not OK Input Power is OK Not Charging Charging No Temperature Fault Temperature Fault No Timeout Fault Timeout Fault Battery Not Removed Battery Removed READ ONLY 00 60 mins 90 mins 120 mins No Timeout READ ONLY
09h
CHGSTAT
[1]
R
Charging Status
09h
TEMPFLT
[2]
R
Temperature Status
09h
TIMOFLT
[3]
R
Timeout Fault
09h 09h
BATFLT
[4] [5]
R R
Battery Removed Fault
09h
TIMOSET
[7:6]
R/W
Charge Timeout Select
01 10 11
0Ah 0Ah ISET2
[3:0] [6:4]
R R/W ISET2 Charger Current Selection
See Table 14
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) REGISTER DESCRIPTIONS CONT'D
Table 12: Battery Charger (CHGR) Control Register Bit Descriptions (Cont'd) ADDRESS
0Ah 0Bh 0Bh 0Bh 0Bh 0Bh
Rev PrB, 25-Feb-08
NAME
LDOMODE SUSCHG CHGROK ICHGSET
BIT
[7] [0] [1] [2] [3] [7:4]
ACCESS
R/W R/W R R/W W/E R
FUNCTION
LDO Mode Enable Suspend Charging Charge Status USB Charge Current Selection 0 1 0 1 0 1 0 1
DESCRIPTION
Charger in Normal Mode Charger in LDO Mode Charging Enable Charging Disable Charging Error Occurred Charging OK 90mA 450mA WRITE-EXACT READ ONLY
Table 13: ISET1[ ] Charge Current Setting CHGR/ISET1 [3:0]
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table 14: ISET2[ ] Charge Current Setting CHGR/ISET2[2:0]
000 001 010 011 100 101 110 111
FAST CHARGE CURRENT SETTING (mA)
CHGLEV = 1 CHGLEV = 0 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 450 90
ISET2 CURRENT SETTING (mA)
300 400 500 600 700 800 900 1000
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) TYPICAL PERFORMANCE CHARACTERISTICS
(ACT8740QLEGA, VVIN = 5V, TA = 25C, unless otherwise specified.)
Rev PrB, 25-Feb-08
Charge Termination Voltage
4.210 3.0
Trickle-Charge Threshold Trickle-Charge Threshold (V)
ACT8740-019 ACT8740-020
VBAT Voltage Accuracy (V)
4.208 4.206 4.204 4.202 4.200 4.198 4.196 4.194 4.192 4.190 0 10 20 30 40 50 60 70
2.9 VBAT RISING 2.8 VBAT FALLING
2.7
2.6
2.5 0 10 20 30 40 50 60 70
Temperature (C)
Temperature (C)
SUSPEND Mode Battery Current
5 4 6
CHGLEV Drive Current Threshold
ACT8740-022
CHGLEV Drive Current (A)
ACT8740-021
LOGIC HIGH INPUT 3 FLOATING INPUT 0
BAT Current (A)
VIN = GA 3
VIN FLOATING
2
VVIN = 5V
1
-3 LOGIC LOW INPUT -20 0 20 40 60 85
0 0 10 20 30 40 50 60 70
-6 -40
Temperature (C)
Temperature (C)
MOSFET Resistance
350 300 250 600
Maximum Charge Current Max. Charge Current (mA)
ACT8740-023 ACT8740-024
500
CHGLEV = VSYS
RDSON (m)
400
CHARGE CURRENT LIMITED BY THERMAL CONTROL CIRCUITRY
200 150 100 50 0 0 10 20 30 40 50 60 70
300 200
CHGLEV = GA
100 0 -40
-25
5
35
65
95
125
Temperature (C)
Temperature (C)
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTION
General Description
The ACT8740's internal battery charger is a fullfeatured, intelligent, linear-mode, single-cell charger for Lithium-based cells. This charger provides a complete selection of advanced functions and requires minimum system design effort. The core of the charger is a CC/CV (Constant- Current/Constant-Voltage), linear-mode charge controller with a highly-accurate charge termination threshold. This controller incorporates current and voltage sense circuitry, an internal power MOSFET, a fullfeatured state-machine that implements charge control and safety features, and circuitry that eliminates the reverse-blocking diode required by conventional charger designs. The ACT8740's charger also features thermal-regulation circuitry that protects it against excessive junction temperature, allowing the fastest possible charging times, as well as proprietary input protection circuitry that makes the charger robust against input voltage transients that can damage other chargers.
Rev PrB, 25-Feb-08
Charger Status
During normal operation, the processor can read the status of the input supply by reading CHGR/VINPOK[ ], which is set to [1] when the following conditions are true: 1) The voltage at VIN is greater than the voltage at BAT, and 2) The voltage at VIN is greater than the VIN UVLO threshold. Alternatively, the processor can read the status of the charger by reading the CHGR/CHGROK[ ] bit, which is set to [1] when the following conditions are true: 1) The voltage at VIN is greater than the voltage at BAT, and 2) The voltage at VIN is greater than the VIN UVLO threshold, and 3) No fault has occurred. Finally, the status of a charge cycle can be determine by reading the CHGR/CHGSTAT[ ] bit or by evaluating the state of the nSTAT output. nSTAT is an open-drain output that has an internal 8mA current limit, and is capable of directly driving LEDs for a visual charge-status indication without the need of current-limiting resistors or other external circuitry. To drive an LED, simply connect the LED between an appropriate supply, typically VIN, and nSTAT. When a logic-level charge status indicator is desired, simply connect a pull-up resistor of 10k or more from nSTAT to OUT2 or another suitable supply. CHGR/CHGSTAT[ ] is set to [1] and nSTAT sinks current when any of the following conditions are true: 1) The charger is operating in the PRECONDITION state, or 2) The charger is operating in the FAST-CHARGE state, or 3) The charger is operating in the TOP-OFF state. When none of these conditions are true, CHGR/ CHGSTAT[ ] is cleared to [0] and nSTAT goes into a high-Z state.
CC/CV Regulation Loop
At the core of the ACT8740's battery charger is a CC/CV regulation loop, which regulates either current or voltage as necessary to ensure fast and safe charging of the battery. In a normal charge cycle, this loop regulates the charge current to the programmed charge current level and continues charging at this current until the battery cell voltage reaches the charge termination voltage. Once the cell reaches the Charge-Termination Threshold Voltage, the CV loop takes over and charge current is allowed to decrease as necessary to keep the cell voltage at the charge termination voltage.
Charger Enable/Disable
When a valid input voltage is applied to VIN, the battery charger is automatically enabled in order to simplify system design and eliminate the need for external input supply detection circuitry. Once the charger is enabled, a charge cycle automatically begins unless CHGLEV is floating, CHGR/SUSCHG[ ] is set to [1], or a fault condition has occurred.
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTION CONT'D
Input Capacitor Selection
VIN is the power input pin for the ACT8740 battery charger. The battery charger is automatically enabled whenever a valid voltage is present on VIN. In most applications, VIN is connected to either a wall adapter or a USB port. Under normal operation, the input of the charger will often be "hot-plugged" directly to a powered USB or a wall adapter cable, and supply voltage ringing and overshoot may appear at the VIN pin and can potentially be large enough to damage the charger input. In most applications, a capacitor connected from VIN to GA, placed as close as possible to the IC, is sufficient to absorb the energy. The VIN pin is designed for enhanced robustness and has an absolute maximum transient voltage rating of +7V, and attention must be given to bypass techniques to ensure operation within this limit.
Rev PrB, 25-Feb-08
CHGR/ISET1[ ] to select the desired charge current, then select this charge current by driving CHGLEV to a logic low or clear CHGR/ICHGSET[ ] to [0].
Charge Safety Timer
The ACT8740 features a programmable charge safety timer that is utilized during operation in the PRECONDITION state. The safety timer has a default timeout period of 60 minutes, although it may be programmed to either 90 minutes or 120 minutes by writing to the CHGR/TIMOSET[ ] register. This register also provides a timer-disable function, for applications that do not require a charge safety timer function.
Thermal Regulation
The ACT8740 features an internal thermal feedback loop that reduces the charging current as necessary to ensure that the die temperature does not exceed the thermal regulation threshold of 110C. This feature protects the ACT8740 against excessive junction temperature and makes the ACT8740 more accommodating of aggressive thermal designs without risk of damage. Note, however, that attention to good thermal design is required to achieve the shortest possible charge time.
Charge Current Programming
The charger was designed for maximum flexibility, and charge current programming is performed using the CHGR/ISET1[ ] and CHGR/ISET2[ ] registers and (optionally) the multifunction CHGLEV input. For applications that desire a combination of pin-control and I2C control, the CHGLEV input provides charge current selection between the current settings defined by CHGR/ISET1[ ] and CHGR/ISET2[ ]. Alternatively, when complete I2C control is desired, simply connect CHGLEV to G and utilize the CHGR/ICHGSET[ ] bit. The two methods are functionally equivalent, select the charge current programmed by CHGR/ISET1[ ] by driving CHGLEV to a logic low or by clearing CHGR/ICHGSET[ ] to [0], and select the charge current programmed by CHGR/ISET2[ ] by driving CHGLEV to a logic high or by setting CHGR/ICHGSET[ ] to [1]. The charger's default settings of CHGR/ISET1[ ] =[0000] and CHGR/ISET2[ ]=[0000] ensure compatibility with lower-current input supplies, such as USB ports. In the default configuration, drive CHGLEV to a logic-low for a 90mA charge current, and drive CHGLEV to a logic-high for 450mA charge current. If different charge current settings are desired, the charge current associated with either CHGLEV state is easily modified via the I2C serial interface. For example, in order to maintain compatibility with USB's high-current mode as well as charge at a higher current if an AC adapter is available, simply reprogram
Reverse Leakage Current
The ACT8740 includes internal circuitry that eliminates the need for series blocking diodes, reducing solution size and cost as well as dropout voltage relative to conventional battery chargers. When the input supply is removed, when VVIN goes below its under-voltage-lockout (UVLO) voltage, or when VVIN drops below VBAT, the ACT8740 automatically goes into SUSPEND mode and reconfigures its power switch to minimize current drain from the battery.
Charger State Machine
PRECONDITION State A new charging cycle begins in the PRECONDITION state. In this state, the cell is charged at a reduced current of either 45mA or 10% of the selected maximum fast-charge current, whichever is greater. During a normal charge cycle, charging continues at this rate until VBAT reaches the Precondition Threshold Voltage, at which point the state machine jumps to the FAST-CHARGE state. If VBAT
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ACT8740
SINGLE-CELL Li+ BATTERY CHARGER (CHGR) FUNCTIONAL DESCRIPTION CONT'D
does not reach the Precondition Threshold Voltage before the Precondition Charge Timeout period expires, then a damaged cell is detected and the state machine jumps to the TIMEOUT-FAULT state. FAST-CHARGE State In the FAST-CHARGE state the charger operates in Constant-Current (CC) mode and charges the cell at the programmed charge current. During a normal charge cycle, constant-current charging continues until VBAT reaches the charge termination voltage, at which point the state machine jumps to the TOPOFF state. TOP-OFF State In the TOP-OFF state the cell is charged in Constant-Voltage (CV) mode with the charge current limited by the internal chemistry of the cell, decreasing as the cell charges. A normal charging cycle continues until the charge current decreases to below the End-Of-Charge (EOC) threshold. In order to improve immunity to conditions that can result in false-EOC detection, the charging continues until the EOC condition persists for 4 consecutive minutes. Once this condition is met, the charge cycle is terminated and the state machine jumps to the SLEEP state. SLEEP State In the SLEEP state the ACT8740 presents a highimpedance to the battery, allowing the cell to "relax" and minimizing battery leakage current. The ACT8740 continues to monitor the cell voltage, however, so that it can reinitiate a charging cycle as necessary to ensure that the cell remains fully charged. Charge Restart After a charge cycle successfully terminates, the ACT8740 jumps to its SLEEP state to minimize battery drain, but continues to actively monitor the cell voltage. A new charging cycle begins when the cell voltage has dropped by 200mV (typ), keeping the cell fully charged. This charge restart process minimizes cycle-life degradation of the cell by allowing it to "relax" between charges, while ensuring that the cell remains fully-charged while connected to a power source. SUSPEND State
Rev PrB, 25-Feb-08
When in the SUSPEND state, the charger is disabled and the charger presents a high-impedance to the battery, but the charge-control circuitry remains functional. When exiting the SUSPEND state, the charge timer is reset and the state machine jumps to the PRECONDITION state. TIMEOUT-FAULT State When a TIMEOUT-FAULT occurs, charging is suspended, CHGR/TIMOFLT[ ] is set to [1], and the charger presents a high-impedance to the battery. To maximize safety, there is no direct path to resume charging from the TIMEOUT-FAULT state. A new charging cycle may only be initiated if the state machine first jumps to the SUSPEND state then each of the conditions necessary to enter the PRECONDITION state are satisfied.
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ACT8740
PACKAGE INFORMATION PACKAGE OUTLINE
TQFN44-24 PACKAGE OUTLINE AND DIMENSIONS
D D/2
Rev PrB, 25-Feb-08
SYMBOL
A A1
DIMENSION IN MILLIMETERS MIN MAX
0.800 0.050 0.700 0.000
DIMENSION IN INCHES MIN
0.028 0.000
MAX
0.031 0.002
E/2
PIN #1 INDEX AREA D/2 x E/2
E
A3 b D E D2
0.200 REF 0.180 3.850 3.850 2.500 2.500 0.300 4.150 4.150 2.800 2.800
0.008 REF 0.007 0.152 0.152 0.098 0.098 0.012 0.163 0.163 0.110 0.110
A A3 D2 L b A1
E2 e L R
0.500 BSC 0.350 0.450
0.020 BSC 0.014 0.018
0.200 TYP 0.200 ---
0.008 TYP 0.008 ---
e E2
PIN #1 INDEX AREA D/2 x E/2
K
R
K
Active-Semi, Inc. reserves the right to modify the circuitry or specifications without notice. Users should evaluate each product to make sure that it is suitable for their applications. Active-Semi products are not intended or authorized for use as critical components in lifesupport devices or systems. Active-Semi, Inc. does not assume any liability arising out of the use of any product or circuit described in this datasheet, nor does it convey any patent license. Active-Semi and its logo are trademarks of Active-Semi, Inc. For more information on this and other products, contact sales@activesemi.com or visit http://www.active-semi.com. For other inquiries, please send to: 1270 Oakmead Parkway, Suite 310, Sunnyvale, California 94085-4044, USA
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ActivePMUTM is a trademark of Active-Semi. I2CTM is a trademark of Philips Electronics.
- 40 -
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