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Datasheet File OCR Text:

M29DW323DT M29DW323DB
32 Mbit (4Mb x8 or 2Mb x16, Dual Bank 8:24, Boot Block) 3V Supply Flash Memory
FEATURES SUMMARY s SUPPLY VOLTAGE - VCC = 2.7V to 3.6V for Program, Erase and Read
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Figure 1. Packages
- VPP =12V for Fast Program (optional) ACCESS TIME: 70, 90ns PROGRAMMING TIME - 10s per Byte/Word typical - Double Word/ Quadruple Byte Program
TSOP48 (N) 12 x 20mm
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MEMORY BLOCKS - Dual Bank Memory Array: 8Mbit+24Mbit - Parameter Blocks (Top or Bottom Location)
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DUAL OPERATIONS - Read in one bank while Program or Erase in other
FBGA
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ERASE SUSPEND and RESUME MODES - Read and Program another Block during Erase Suspend
TFBGA63 (ZA) 7 x 11mm
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UNLOCK BYPASS PROGRAM COMMAND - Faster Production/Batch Programming VPP/WP PIN for FAST PROGRAM and WRITE PROTECT TEMPORARY BLOCK UNPROTECTION MODE COMMON FLASH INTERFACE - 64 bit Security Code EXTENDED MEMORY BLOCK - Extra block used as security block or to store additional information
FBGA
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TFBGA48 (ZE) 6 x 8mm
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LOW POWER CONSUMPTION - Standby and Automatic Standby 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Top Device Code M29DW323DT: 225Eh - Bottom Device Code M29DW323DB: 225Fh
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June 2003
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M29DW323DT, M29DW323DB
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. TFBGA63 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. TFBGA48 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7. Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Input/Output or Address Input (DQ15A-1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VPP/Write Protect (VPP/WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCC Supply Voltage (2.7V to 3.6V).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protect and Chip Unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 3. Bus Operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4. Bus Operations, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read/Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Fast Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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Quadruple Byte Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Double Word Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unlock Bypass Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unlock Bypass Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Unlock Bypass Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chip Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Enter Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Exit Extended Block Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5. Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 6. Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 7. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 19 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 9. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 12. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 14. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 15. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 16. Accelerated Program Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline . 29
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Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data . . . . . 29 Figure 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline . . . . 30 Table 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . 30 Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline . . . . . 31 Table 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data. . . . . . . . . 31 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 APPENDIX A. BLOCK ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 21. Top Boot Block Addresses, M29DW323DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22. Bottom Boot Block Addresses, M29DW323DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 23. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 25. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 26. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 27. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 28. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 APPENDIX C. EXTENDED MEMORY BLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 29. Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 APPENDIX D. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 30. Programmer Technique Bus Operations, BYTE = V IH or VIL . . . . . . . . . . . . . . . . . . . . . 43 Figure 20. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 21. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 22. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 23. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 31. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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SUMMARY DESCRIPTION The M29DW323D is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The device features an asymmetrical block architecture. The M29DW323D has an array of 8 parameter and 63 main blocks and is divided into two Banks, A and B, providing Dual Bank operations. While programming or erasing in Bank A, read operations are possible in Bank B and vice versa. Only one bank at a time is allowed to be in program or erase mode. The bank architecture is summarized in Table 2. M29DW323DT locates the Parameter Blocks at the top of the memory address space while the M29DW323DB locates the Parameter Blocks starting from the bottom. M29DW323D has an extra 32 KWord (x16 mode) or 64 KByte (x8 mode) block, the Extended Block, that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. How-
ever the protection is irreversible, once protected the protection cannot be undone. Each block can be erased independently so it is possible to preserve valid data while old data is erased. The blocks can be protected to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP48 (12x20mm), TFBGA63 (7x11mm, 0.8mm pitch) and TFBGA48 (6x8mm, 0.8mm pitch) packages. The memory is supplied with all the bits erased (set to '1').
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A20 DQ0-DQ7 Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select Supply Voltage VPP/Write Protect Ground Not Connected Internally
VCC VPP/WP
DQ8-DQ14 DQ15A-1
21 A0-A20 W E G RP M29DW323DT M29DW323DB
15 DQ0-DQ14 DQ15A-1
W E G
BYTE
RP
RB
RB BYTE VCC
VSS
AI05523
VPP/WP
VSS NC
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Figure 3. TSOP Connections
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP NC VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1
1
48
M29DW323DT M29DW323DB 12 13 37 36
24
25
A16 BYTE VSS DQ15A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0
AI05524
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Figure 4. TFBGA63 Connections (Top view through package)
1 2 3 4 5 6 7 8
A
NC(1)
NC(1)
NC(1)
NC(1)
B
NC(1)
NC(1)
NC(1)
C
A3
A7
RB
W
A9
A13
D
A4
A17
VPP/WP
RP
A8
A12
E
A2
A6
A18
NC
A10
A14
F
A1
A5
A20
A19
A11
A15
G
A0
DQ0
DQ2
DQ5
DQ7
A16
H
E
DQ8
DQ10
DQ12
DQ14
BYTE
J
G
DQ9
DQ11
VCC
DQ13
DQ15 A-1
K
VSS
DQ1
DQ3
DQ4
DQ6
VSS
L
NC(1)
NC(1)
NC(1)
NC(1)
M
NC(1)
NC(1)
NC(1)
NC(1)
AI05525B
Note: 1. Balls are shorted together via the substrate but not connected to the die.
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Figure 5. TFBGA48 Connections (Top view through package)
1 2 3 4 5 6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/WP
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15 A-1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI08084
Table 2. Bank Architecture
Parameter Blocks Bank Bank Size No. of Blocks 8 Block Size 8KByte/ 4 KWord Main Blocks No. of Blocks 15 48 Block Size 64KByte/ 32 KWord 64KByte/ 32 KWord
A B
8 Mbit 24 Mbit
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Figure 6. Block Addresses (x8)
Top Boot Block (x8) Address lines A20-A0, DQ15A-1 000000h 00FFFFh Bank B 64 KByte or 32 KWord Total of 48 Main Blocks
Bottom Boot Block (x8) Address lines A20-A0, DQ15A-1 000000h 001FFFh 8 KByte or 4 KWord Total of 8 Parameter Blocks (1) 00E000h Bank A 00FFFFh 010000h 01FFFFh Total of 15 Main Blocks 8 KByte or 4 KWord 64 KByte or 32 KWord Total of 15 Main Blocks
2F0000h 2FFFFFh 300000h 30FFFFh
64 KByte or 32 KWord 64 KByte or 32 KWord
3E0000h Bank A 3EFFFFh 3F0000h 3F1FFFh
64 KByte or 32 KWord 8 KByte or 4 KWord Total of 8 Parameter Blocks (1)
0F0000h 0FFFFFh 100000h 10FFFFh Bank B
64 KByte or 32 KWord 64 KByte or 32 KWord Total of 48 Main Blocks
3FE000h 3FFFFFh
8 KByte or 4 KWord
3F0000h 3FFFFFh
64 KByte or 32 KWord
Note 1. Used as Extended Block Addresses in Extended Block mode.
Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.
AI05556
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Figure 7. Block Addresses (x16)
Top Boot Block (x16) Address lines A20-A0 000000h 007FFFh Bank B 64 KByte or 32 KWord Total of 48 Main Blocks 000000h 000FFFh
Bottom Boot Block (x16) Address lines A20-A0 8 KByte or 4 KWord Total of 8 Parameter Blocks (1) 007000h Bank A 007FFFh 008000h 00FFFFh Total of 15 Main Blocks 8 KByte or 4 KWord 64 KByte or 32 KWord Total of 15 Main Blocks
178000h 17FFFFh 180000h 187FFFh
64 KByte or 32 KWord 64 KByte or 32 KWord
1F0000h Bank A 1F7FFFh 1F8000h 1F8FFFh
64 KByte or 32 KWord 8 KByte or 4 KWord Total of 8 Parameter Blocks (1)
078000h 07FFFFh 080000h 087FFFh Bank B
64 KByte or 32 KWord 64 KByte or 32 KWord Total of 48 Main Blocks
1FF000h 1FFFFFh
8 KByte or 4 KWord
1F8000h 1FFFFFh
64 KByte or 32 KWord
Note 1. Used as Extended Block Addresses in Extended Block mode.
Note: Also see Appendix A, Tables 21 and 22 for a full listing of the Block Addresses.
AI05555
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SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the Program/Erase Controller. Data Inputs/Outputs (DQ8-DQ14). The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. Data Input/Output or Address Input (DQ15A-1). When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A-1 Low will select the LSB of the addressed Word, DQ15A-1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, V IH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. VPP/Write VPP/Write Protect (VPP/WP). The Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by bypassing the unlock cycles and/or using the Double Word or Quadruple Byte Program commands. The Write Protect function provides a hardware method of protecting the two outermost boot blocks. When V PP/Write Protect is Low, VIL, the memory protects the two outermost boot blocks; Program
and Erase operations in these blocks are ignored while V PP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the two outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. When V PP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When V PP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to V PP and from V PP to VIH must be slower than tVHVPP, see Figure 16. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreliable. A 0.1F capacitor should be connected between the V PP/Write Protect pin and the V SS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, I PP. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. Note that if V PP/WP is at VIL, then the two outermost boot blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, V IL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 16 and Figure 15, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at V ID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations
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Ready/Busy is Low, V OL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 16 and Figure 15, Reset/Temporary Unprotect AC Characteristics. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. Byte/Word Organization Select (BYTE). The Byte/Word Organization Select pin is used to switch between the x8 and x16 Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, V IH, the memory is in x16 mode. VCC Supply Voltage (2.7V to 3.6V). VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1F capacitor should be connected between the V CC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and Erase operations, ICC3. VSS Ground. VSS is the reference for all voltage measurements. The device features two V SS pins which must be both connected to the system ground.
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BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. The Dual Bank architecture of the M29DW323 allows read/write operations in Bank A, while read operations are being executed in Bank B or vice versa. Write operations are only allowed in one bank at a time. See Tables 3 and 4, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 12, Read Mode AC Waveforms, and Table 13, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 13 and 14, Write AC Waveforms, and Tables 14 and 15, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, V IH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-imped-
ance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC 0.2V. For the Standby current level see Table 12, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 3 and 4, Bus Operations. Block Protect and Chip Unprotect. Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A, Tables 21 and 22, Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed. The VPP/Write Protect pin can be used to protect the two outermost boot blocks. When VPP/Write Protect is at VIL the two outermost boot blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin status. Block Protect and Chip Unprotect operations are described in Appendix D.
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Table 3. Bus Operations, BYTE = V IL
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code Extended Memory Block Verify Code
Note: X = VIL or VIH.
E VIL VIL X VIH VIL VIL VIL
G VIL VIH VIH X VIL VIL VIL
W VIH VIL VIH X VIH VIH VIH
Address Inputs DQ15A-1, A0-A20 Cell Address Command Address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIH, A6 = VIL, A9 = VID, Others VIL or VIH
Data Inputs/Outputs DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z 20h 5Eh (M29DW323DT) 5Fh (M29DW323DB) 81h (factory locked) 01h (not factory locked)
Table 4. Bus Operations, BYTE = V IH
Operation Bus Read Bus Write Output Disable Standby Read Manufacturer Code Read Device Code Extended Memory Block Verify Code
Note: X = VIL or VIH.
E VIL VIL X VIH VIL VIL VIL
G VIL VIH VIH X VIL VIL VIL
W VIH VIL VIH X VIH VIH VIH
Address Inputs A0-A20 Cell Address Command Address X X A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH A0 = VIH, A1 = VIH, A6 = VIL, A9 = VID, Others VIL or VIH
Data Inputs/Outputs DQ15A-1, DQ14-DQ0 Data Output Data Input Hi-Z Hi-Z 0020h 225Eh (M29DW323DT) 225Fh (M29DW323DB) 81h (factory locked) 01h (not factory locked)
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16-bit or 8bit mode. See either Table 5, or 6, depending on the configuration that is being used, for a summary of the commands. Read/Reset Command The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. If the Read/Reset command is issued during the timeout of a Block erase operation then the memory will take up to 10s to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. Auto Select Command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Block Protection Status and the Extended Memory Block Verify Code. It can be addressed to either Bank. Three consecutive Bus Write operations are required to issue the Auto Select command. The final Write cycle must be addressed to one of the Banks. Once the Auto Select command is issued Bus Read operations to the Bank where the command was issued output the Auto Select data. Bus Read operations to the other Bank will output the contents of the memory array. The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued. In Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = V IL and A1 = V IL and A19-A20 = Bank Address. The other address bits may be set to either V IL or VIH. The Device Code can be read using a Bus Read operation with A0 = V IH and A1 = VIL and A19-A20 = Bank Address. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = V IH, A19-A20 = Bank Address and A12-A17 specifying the address of the block inside the Bank. The other address bits may be set to either
VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. Read CFI Query Command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode. See Appendix B, Tables 23, 24, 25, 26, 27 and 28 for details on the information contained in the Common Flash Interface (CFI) memory area. Program Command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. See the section on the Status Register for more details. Typical program times are given in Table 7. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'.
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Fast Program Commands There are two Fast Program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. The Quadruple Byte Program command is available for x8 operations, while the Double Word Program command is available for x16 operations. Quadruple Byte Program Command. The Quadruple Byte Program command is used to write a page of four adjacent Bytes in parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles are necessary to issue the Quadruple Byte Program command. s The first bus cycle sets up the Quadruple Byte Program Command. s The second bus cycle latches the Address and the Data of the first byte to be written. s The third bus cycle latches the Address and the Data of the second byte to be written. s The fourth bus cycle latches the Address and the Data of the third byte to be written. s The fifth bus cycle latches the Address and the Data of the fourth byte to be written and starts the Program/Erase Controller. Double Word Program Command. The Double Word Program command is used to write a page of two adjacent words in parallel. The two words must differ only for the address A0. Three bus write cycles are necessary to issue the Double Word Program command. s The first bus cycle sets up the Double Word Program Command. s The second bus cycle latches the Address and the Data of the first word to be written. s The third bus cycle latches the Address and the Data of the second word to be written and starts the Program/Erase Controller. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. Programming should not be attempted when VPP is not at V PPH. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Fast Program commands cannot change a bit set at '0' back to '1'. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Typical Program times are given in Table 7, Program, Erase Times and Program/Erase Endurance Cycles. Unlock Bypass Command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. The Unlock Bypass Program command can then be issued to program addresses within the bank, or the Unlock Bypass Reset command can be issued to return the bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. When VPP is applied to the VPP/Write Protect pin the memory automatically enters the Unlock Bypass mode and the Unlock Bypass Program command can be issued immediately. Unlock Bypass Program Command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data, and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted, a Bus Read operation to the Bank where the command was issued outputs the Status Register. See the Program command for details on the behavior. Unlock Bypass Reset Command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/ Reset command does not exit from Unlock Bypass Mode. Chip Erase Command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the
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blocks are protected the Chip Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 7. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to '1'. All previous data is lost. Block Erase Command The Block Erase command can be used to erase a list of one or more blocks in a Bank. It sets all of the bits in the unprotected selected blocks to '1'. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. All blocks must belong to the same Bank; if a block belonging to the other Bank is given it will not be erased. The Block Erase operation starts the Program/Erase Controller after a time-out period of 50s after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50s of the last block. The 50s timer restarts when an additional block is selected. After the sixth Bus Write operation a Bus Read operation within the same Bank will output the Status Register. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100s, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the 50s time-out period. Typical block erase times are given in Table 7. After the Erase operation has started all Bus Read operations to the Bank being erased will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Erase Suspend Command The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency time of the Erase Suspend Command being issued. Once the Program/ Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read operation to the Extended Block will output the Extended Block data. Erase Resume Command The Erase Resume command must be used to restart the Program/Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once.
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Enter Extended Block Command The M29DW323D has an extra 64KByte block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus write cycles are required to issue the Extended Block command. Once the command has been issued the device enters Extended Block mode where all Bus Read or Program operations to the Boot Block addresses access the Extended Block. The Extended Block (with the same address as the boot block) cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode the Boot Blocks are not accessible. In Extended Block mode dual operations are possible, with the Extended Block mapped in Bank A. When in Extended Block mode, Erase Commands in Bank A are not allowed. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected, however once protected the protection cannot be undone. Exit Extended Block Command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. Block Protect and Chip Unprotect Commands Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A, Tables 21 and 22, Block Addresses. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix D.
Table 5. Commands, 16-bit mode, BYTE = VIH
Command Length Bus Write Operations 1st Addr X 555 555 555 555 555 X X 555 555 BKA BKA 55 555 555 Data F0 AA AA AA 50 AA A0 90 AA AA B0 30 98 AA AA 2AA 2AA 55 55 555 555 88 90 X 00 2AA 2AA 2AA PA0 2AA PA X 2AA 2AA 55 55 55 PD0 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 X (BKA) 555 555 PA1 555 F0 90 A0 PD1 20 PA PD 2nd Addr Data 3rd Addr Data 4th Addr Data 5th Addr Data 6th Addr Data
1 Read/Reset 3 Auto Select Program Double Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 3 3 2 2 6 6+ 1 1 1 3 4
Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in hexadecimal. The Command Interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is V IL or DQ15 when BYTE is VIH.
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Table 6. Commands, 8-bit mode, BYTE = VIL
Command Length Bus Write Operations 1st Add X AAA AAA AAA AAA AAA X X AAA AAA BKA BKA AA AAA AAA Data F0 AA AA AA 55 AA A0 90 AA AA B0 30 98 AA AA 555 555 55 55 AAA AAA 88 90 X 00 555 555 555 PA0 555 PA X 555 555 55 55 55 PD0 55 PD 00 55 55 AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA BA 10 30 X (BKA) AAA AAA PA1 AAA F0 90 A0 PD1 20 PA PA2 PD PD2 PA3 PD3 2nd Add Data 3rd Add Data 4th Add Data 5th Add Data 6th Add Data
1 Read/Reset 3 Auto Select Program Quadruple Byte Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume Read CFI Query Enter Extended Block Exit Extended Block 3 4 5 3 2 2 6 6+ 1 1 1 3 4
Note: X Don't Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A-1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15 are Don't Care. DQ15A-1 is A-1 when BYTE is V IL or DQ15 when BYTE is VIH.
Table 7. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Chip Erase Block Erase (64 KBytes) Erase Suspend Latency Time Program (Byte or Word) Double Word Program (Byte or Word) Chip Program (Byte by Byte) Chip Program (Word by Word) Chip Program (Quadruple Byte or Double Word) Program/Erase Cycles (per Block) Data Retention
Note: 1. 2. 3. 4.
Min
Typ (1, 2) 40 0.8
Max(2) 200(3) 6(3) 50(4)
Unit s s s s s s s s cycles years
10 10 40 20 10 100,000 20
200(4) 200(3) 200(3) 100(3) 100(3)
Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VCC.
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STATUS REGISTER The M29DW323D has two Status Registers, one for each bank. The Status Registers provide information on the current or previous Program or Erase operations executed in each bank. The various bits convey information and errors on the operation. Bus Read operations from any address within the Bank, always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 8, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs '0', the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a '1' during a Bus Read operation within a block being erased. The Data Polling Bit will change from a '0' to a '1' when the Program/Erase Controller has suspended the Erase operation. Figure 8, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.
Figure 9, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to '1' when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to '0' back to '1' and attempting to do so will set DQ5 to `1'. A Bus Read operation to that address will show the bit is still `0'. One of the Erase commands must be used to set all the bits in a block or in the whole memory from '0' to '1'. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to '1'. Before the Program/Erase Controller starts the Erase Timer Bit is set to '0' and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from '0' to '1' to '0', etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from '0' to '1' to '0', etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
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Table 8. Status Register Bits
Operation Program Program During Erase Suspend Program Error Chip Erase Block Erase before timeout Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address
Note: Unspecified data bits should be ignored.
Address Bank Address Bank Address Bank Address Any Address Erasing Block Non-Erasing Block Erasing Block
DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1
DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle
DQ5 0 0 1 0 0 0 0 0 0
DQ3 - - - 1 0 0 1 1 -
DQ2 - - - Toggle Toggle No Toggle Toggle No Toggle Toggle
RB 0 0 0 0 0 0 0 0 1 1
Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle
0 0
Figure 8. Data Polling Flowchart
START
Figure 9. Data Toggle Flowchart
START READ DQ6
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ5 & DQ6
DQ7 = DATA NO NO YES
DQ6 = TOGGLE YES
NO
DQ5 =1 YES
NO
DQ5 =1 YES READ DQ6 TWICE
READ DQ7 at VALID ADDRESS
DQ7 = DATA NO FAIL
YES
DQ6 = TOGGLE
PASS
NO
YES FAIL PASS
AI90195B
AI90194
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MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at Table 9. Absolute Maximum Ratings
Symbol TBIAS TSTG VIO VCC VID VPP(3) Temperature Under Bias Storage Temperature Input or Output Voltage (1,2) Supply Voltage Identification Voltage Program Voltage Parameter Min -50 -65 -0.6 -0.6 -0.6 -0.6 Max 125 150 VCC +0.6 4 13.5 13.5 Unit C C V V V V
these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs.
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DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 10, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 10. Operating and AC Measurement Conditions
M29DW323D Parameter Min VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 0 to VCC VCC/2 3.0 -40 30 10 0 to VCC VCC/2 70 Max 3.6 85 Min 2.7 -40 30 10 90 Max 3.6 85 V C pF ns V V Unit
Figure 10. AC Measurement I/O Waveform
Figure 11. AC Measurement Load Circuit
VPP VCC VCC/2 0V
AI05557
VCC
VCC
25k DEVICE UNDER TEST 25k
CL 0.1F 0.1F
CL includes JIG capacitance
AI05558
Table 11. Device Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: Sampled only, not 100% tested.
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Table 12. DC Characteristics
Symbol ILI ILO ICC1(2) ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, G = VIH, f = 6MHz E = VCC 0.2V, RP = VCC 0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPP VIL VIH VPP IPP VOL VOH VID VLKO Input Low Voltage Input High Voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low Voltage Output High Voltage Identification Voltage Program/Erase Lockout Supply Voltage VCC = 3.0V 10% VCC = 3.0V 10% IOL = 1.8mA IOH = -100A VCC -0.4 11.5 1.8 12.5 2.3 -0.5 0.7VCC 11.5 Min Max 1 1 10 100 20 20 0.8 VCC +0.3 12.5 15 0.45 Unit
A A
mA
A
mA mA V V V mA V V V V
ICC3 (1,2)
Supply Current (Program/ Erase)
Note: 1. Sampled only, not 100% tested. 2. In Dual operations the Supply Current will be the sum of I CC1(read) and I CC3 (program/erase).
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Figure 12. Read Mode AC Waveforms
tAVAV A0-A20/ A-1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ
AI05559
VALID tAXQX
tEHQX tEHQZ
tGHQX tGHQZ VALID
Table 13. Read AC Characteristics
M29DW323D Symbol Alt Parameter Test Condition 70 tAVAV tAVQV tELQX (1) tELQV tGLQX (1) tGLQV tEHQZ (1) tGHQZ (1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV tRC tACC tLZ tCE tOLZ tOE tHZ tDF tOH tELFL tELFH tFLQZ tFHQV Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Chip Enable to BYTE Low or High BYTE Low to Output Hi-Z BYTE High to Output Valid E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Min Max Min Max Min Max Max Max Min 70 70 0 70 0 30 25 25 0 90 90 90 0 90 0 35 30 30 0 ns ns ns ns ns ns ns ns ns Unit
Max Max Max
5 25 30
5 30 40
ns ns ns
Note: 1. Sampled only, not 100% tested.
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M29DW323DT, M29DW323DB
Figure 13. Write AC Waveforms, Write Enable Controlled
tAVAV A0-A20/ A-1 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX tWLWH tWHGL tWHEH
VCC tVCHEL RB tWHRL
AI05560
Table 14. Write AC Characteristics, Write Enable Controlled
M29DW323D Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL (1) tVCHEL tOEH tBUSY tVCS Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 70 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 30 50 90 90 0 50 50 0 0 30 0 50 0 0 35 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
Note: 1. Sampled only, not 100% tested.
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Figure 14. Write AC Waveforms, Chip Enable Controlled
tAVAV A0-A20/ A-1 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH
VCC tVCHWL RB tEHRL
AI05561
Table 15. Write AC Characteristics, Chip Enable Controlled
M29DW323D Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL (1) tVCHWL tOEH tBUSY tVCS Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 70 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 70 0 45 45 0 0 30 0 45 0 0 30 50 90 90 0 50 50 0 0 30 0 50 0 0 35 50 ns ns ns ns ns ns ns ns ns ns ns ns s Unit
Note: 1. Sampled only, not 100% tested.
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Figure 15. Reset/Block Temporary Unprotect AC Waveforms
W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH
AI02931B
Table 16. Reset/Block Temporary Unprotect AC Characteristics
M29DW323D Symbol tPHWL (1) tPHEL tPHGL (1) tRHWL (1) tRHEL (1) tRHGL
(1)
Alt
Parameter 70 RP High to Write Enable Low, Chip Enable Low, Output Enable Low 90
Unit
tRH
Min
50
50
ns
tRB
RB High to Write Enable Low, Chip Enable Low, Output Enable Low RP Pulse Width RP Low to Read Mode RP Rise Time to VID VPP Rise and Fall Time
Min
0
0
ns
tPLPX tPLYH tPHPHH (1) tVHVPP (1)
tRP tREADY tVIDR
Min Max Min Min
500 50 500 250
500 50 500 250
ns s ns ns
Note: 1. Sampled only, not 100% tested.
Figure 16. Accelerated Program Timing Waveforms
VPP VPP/WP VIL or VIH tVHVPP
tVHVPP
AI05563
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PACKAGE MECHANICAL Figure 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline
1 48
e
D1
B
24
25
L1 A2 A
E1 E
DIE
A1 C CP
L
TSOP-G
Note: Drawing not to scale.
Table 17. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data
millimeters Symbol Typ A A1 A2 B C CP D1 E E1 e L L1 12.000 20.000 18.400 0.500 0.600 0.800 3 0 5 11.900 19.800 18.300 - 0.500 0.100 1.000 0.220 0.050 0.950 0.170 0.100 Min Max 1.200 0.150 1.050 0.270 0.210 0.080 12.100 20.200 18.500 - 0.700 0.4724 0.7874 0.7244 0.0197 0.0236 0.0315 3 0 5 0.4685 0.7795 0.7205 - 0.0197 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0031 0.4764 0.7953 0.7283 - 0.0276 inches
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Figure 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline
D D1 FD SD
e
E
E1
SE
ddd
BALL "A1"
FE A e b A1 A2
BGA-Z33
Note: Drawing not to scale.
Table 18. TFBGA63 7x11mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 7.000 5.600 - 11.000 8.800 0.800 0.700 1.100 0.400 0.400 0.350 6.900 - - 10.900 - - - - - - 0.250 0.900 0.450 7.100 - 0.100 11.100 - - - - - - 0.2756 0.2205 - 0.4331 0.3465 0.0315 0.0276 0.0433 0.0157 0.0157 0.0138 0.2717 - - 0.4291 - - - - - - Min Max 1.200 0.0098 0.0354 0.0177 0.2795 - 0.0039 0.4370 - - - - - - Typ Min Max 0.0472 inches
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Figure 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Bottom View Package Outline
D FD FE SD D1
SE E E1 BALL "A1" ddd
e e A A1 b A2
BGA-Z32
Note: Drawing not to scale.
Table 19. TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SD SE 8.000 5.600 0.800 1.000 1.200 0.400 0.400 7.900 - - - - - - 6.000 4.000 0.350 5.900 - 0.260 0.900 0.450 6.100 - 0.100 8.100 - - - - - - 0.3150 0.2205 0.0315 0.0394 0.0472 0.0157 0.0157 0.3110 - - - - - - 0.2362 0.1575 0.0138 0.2323 - Min Max 1.200 0.0102 0.0354 0.0177 0.2402 - 0.0039 0.3189 - - - - - - Typ Min Max 0.0472 inches
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M29DW323DT, M29DW323DB
PART NUMBERING Table 20. Ordering Information Scheme
Example: Device Type M29 Architecture D = Dual Bank Operating Voltage W = VCC = 2.7 to 3.6V Device Function 323D = 32 Mbit (x8/x16), Boot Block, 1/4-3/4 partitioning Array Matrix T = Top Boot B = Bottom Boot Speed 70 = 70 ns 90 = 90 ns Package N = TSOP48: 12 x 20 mm ZA = TFBGA63: 7 x 11mm, 0.80 mm pitch ZE = TFBGA48: 6 x 8mm, 0.8mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing
M29DW323DB
70
N
1
T
Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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APPENDIX A. BLOCK ADDRESSES Table 21. Top Boot Block Addresses, M29DW323DT
Bank Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Bank B 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (Kbytes/ Kwords) 64/32 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 1E0000h-1EFFFFh 1F0000h-1FFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection Group Protection Block Group Protection Group (x8) 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x16) 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh
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M29DW323DT, M29DW323DB
Bank (Kbytes/ Kwords) 64/32 64/32 Protection Group 34 35 36 37 38 Bank B 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Bank A 54 55 56 57 58 59 60 61 62 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 64/32 Protection Group 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh Protection Block Group
Block 32 33
(x8) 200000h-20FFFFh 210000h-21FFFFh
(x16) 100000h-107FFFh 108000h-10FFFFh
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Bank (Kbytes/ Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 Protection Block Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group
Block 63 64 65
(x8) 3F0000h-3F1FFFh(1) 3F2000h-3F3FFFh(1) 3F4000h-3F5FFFh(1) 3F6000h-3F7FFFh(1) 3F8000h-3F9FFFh(1) 3FA000h-3FBFFFh(1) 3FC000h-3FDFFFh(1) 3FE000h-3FFFFFh(1)
(x16) 1F8000h-1F8FFFh(1) 1F9000h-1F9FFFh(1) 1FA000h-1FAFFFh(1) 1FB000h-1FBFFFh(1) 1FC000h-1FCFFFh(1) 1FD000h-1FDFFFh(1) 1FE000h-1FEFFFh(1) 1FF000h-1FFFFFh(1)
Bank A
66 67 68 69 70
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
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Table 22. Bottom Boot Block Addresses, M29DW323DB
Bank Block 0 1 2 3 4 5 6 7 8 9 Bank A 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Bank B 26 27 28 29 30 (Kbytes/ Kwords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 160000h-16FFFFh 170000h-17FFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh Protection Group Protection Block Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group (x8) 000000h-001FFFh(1) 002000h-003FFFh(1) 004000h-005FFFh(1) 006000h-007FFFh(1) 008000h-009FFFh(1) 00A000h-00BFFFh(1) 00C000h-00DFFFh(1) 00E000h-00FFFFh(1) 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x16) 000000h-000FFFh(1) 001000h-001FFFh(1) 002000h-002FFFh(1) 003000h-003FFFh(1) 004000h-004FFFh(1) 005000h-005FFFh(1) 006000h-006FFFh(1) 007000h-007FFFh(1) 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh
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Bank (Kbytes/ Kwords) 64/32 64/32 Protection Group 33 34 35 36 37 38 39 40 41 42 43 44 45 Bank B 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 360000h-36FFFFh 370000h-37FFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh Protection Block Group
Block 31 32
(x8) 180000h-18FFFFh 190000h-19FFFFh
(x16) 0C0000h-0C7FFFh 0C8000h-0CFFFFh
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Bank (Kbytes/ Kwords) 64/32 64/32 Protection Group 65 Bank B 66 67 68 69 70 64/32 64/32 64/32 64/32 64/32 64/32 Protection Group Protection Group 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh Protection Block Group
Block 63 64
(x8) 380000h-38FFFFh 390000h-39FFFFh
(x16) 1C0000h-1C7FFFh 1C8000h-1CFFFFh
Note: 1. Used as the Extended Block Addresses in Extended Block mode.
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APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure Table 23. Query Structure Overview
Address Sub-section Name x16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number Description
is read from the memory. Tables 23, 24, 25, 26, 27 and 28 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 28, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST.
Note: Query data are always presented on the lowest order data outputs.
Table 24. CFI Query Identification String
Address Data x16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h Address for Primary Algorithm extended Query table (see Table 27) 0000h 0000h 0000h 0000h 0000h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported Address for Alternate Algorithm extended Query table NA P = 40h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Query Unique ASCII String "QRY" "Q" "R" "Y" AMD Compatible Description Value
NA
Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are `0'.
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Table 25. CFI Query System Interface Information
Address Data x16 1Bh x8 36h 0027h VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Typical timeout per single byte/word program = 2n s Typical timeout for minimum size write buffer program = 2n s Typical timeout per individual block erase = 2n ms Typical timeout for full chip erase = 2n ms Maximum timeout for byte/word program = 2n times typical Maximum timeout for write buffer program = 2n times typical Maximum timeout per individual block erase = 2n times typical Maximum timeout for chip erase = 2n times typical 2.7V Description Value
1Ch
38h
0036h
3.6V
1Dh
3Ah
00B5h
11.5V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch
00C5h 0004h 0000h 000Ah 0000h 0004h 0000h 0003h 0000h
12.5V 16s NA 1s NA 256 s NA 8s NA
Table 26. Device Geometry Definition
Address Data x16 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h x8 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 0016h 0002h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 003Eh 0000h 0000h 0001h Device Size = 2n in number of bytes Flash Device Interface Code description Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions. It specifies the number of regions containing contiguous Erase Blocks of the same size. Region 1 Information Number of identical size erase block = 0007h+1 Region 1 Information Block size in Region 1 = 0020h * 256 byte Region 2 Information Number of identical size erase block = 003Eh+1 Region 2 Information Block size in Region 2 = 0100h * 256 byte 4 MByte x8, x16 Async. NA 2 8 8Kbyte 63 64Kbyte Description Value
Note: The region information contained in addresses 2Dh to 34h (or 5Ah to 68h) is correct for the M29DW323DB. For the M29DW323DT the regions must be reversed.
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Table 27. Primary Algorithm-Specific Extended Query Table
Address Data x16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h 0052h 0049h 0031h 0030h 0000h Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of blocks in per group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 04 = M29W400B Simultaneous Operations, x = number of blocks in Bank B Burst Mode, 00 = not supported, 01 = supported Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Top/Bottom Boot Block Flag 02h = Bottom Boot device, 03h = Top Boot device Primary Algorithm extended Query table unique ASCII string "PRI" "P" "R" "I" "1" "0" Yes Description Value
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh
8Ch 8Eh 90h 92h 94h 96h 98h 9Ah
0002h 0001h 0001h 0004h 0030h 0000h 0000h 00B5h
2 1 Yes 4 48 No No 11.5V
4Eh
9Ch
00C5h
12.5V
4Fh
9Eh
000xh
-
Table 28. Security Code Area
Address x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h Data XXXX XXXX XXXX XXXX 64 bit: unique device number Description
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APPENDIX C. EXTENDED MEMORY BLOCK The M29DW323D has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 32 KWords in x16 mode and 64 KBytes in x8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Block is either Factory Locked or Customer Lockable, its status is indicated by bit DQ7. This bit is permanently set to either `1' or `0' at the factory and cannot be changed. When set to `1', it indicates that the device is factory locked and the Extended Block is protected. When set to `0', it indicates that the device is customer lockable and the Extended Block is unprotected. Bit DQ7 being permanently locked to either `1' or `0' is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bit DQ7 is the most significant bit in the Extended Block Verify Code and a specific procedure must be followed to read it. See "Extended Memory Block Verify Code" in Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH, respectively, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Enter Extended Block Command and Exit Extended Block Command paragraphs, and to Tables 5 and 6, "Commands, 16-bit mode, BYTE = VIH" and "Commands, 8-bit mode, BYTE = VIL", respectively. Table 29. Extended Block Address and Data
Device x8 3F0000h-3F000Fh M29DW323DT 3F0010h-3FFFFFh 000000h-00000Fh M29DW323DB 000010h-00FFFFh 000008h-007FFFh 1F8008h-1FFFFFh 000000h-000007h Address(1) x16 1F8000h-1F8007h Factory Locked Security Identification Number Unavailable Security Identification Number Unavailable Determined by Customer Data Customer Lockable Determined by Customer
Factory Locked Extended Block In devices where the Extended Block is factory locked, the Security Identification Number is written to the Extended Block address space (see Table 29, Extended Block Address and Data) in the factory. The DQ7 bit is set to `1' and the Extended Block cannot be unprotected. Customer Lockable Extended Block A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to `0' and the Extended Block unprotected. It is up to the customer to program and protect the Extended Block but care must be taken because the protection of the Extended Block is not reversible. There are two ways of protecting the Extended Block: s Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique (refer to Appendix D, In-System Technique and to the corresponding flowcharts, Figures 22 and 23, for a detailed explanation of the technique). s Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique (refer to Appendix D, Programmer Technique and to the corresponding flowcharts, Figures 20 and 21, for a detailed explanation of the technique). Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode.
Note: 1. See Tables 21 and 22, Top and Bottom Boot Block Addresses.
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APPENDIX D. BLOCK PROTECTION Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A, Tables 21 and 22 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Programmer Technique The Programmer technique uses high (V ID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 20, Programmer Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 21, Programmer Equipment Chip Unprotect Flowchart. Table 30, Programmer Technique Bus Operations, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 22, In-System Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 23, In-System Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
Table 30. Programmer Technique Bus Operations, BYTE = V IH or VIL
Operation Block (Group) Protect(1) Chip Unprotect Block (Group) Protection Verify Block (Group) Unprotection Verify E VIL VID G VID VID W VIL Pulse VIL Pulse Address Inputs A0-A20 A9 = VID, A12-A20 Block Address Others = X A9 = VID, A12 = VIH, A15 = VIH Others = X A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A20 Block Address Others = X A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A20 Block Address Others = X Data Inputs/Outputs DQ15A-1, DQ14-DQ0 X X Pass = XX01h Retry = XX00h Retry = XX01h Pass = XX00h
VIL
VIL
VIH
VIL
VIL
VIH
Note: 1. Block Protection Groups are shown in Appendix A, Tables 21 and 22.
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Figure 20. Programmer Equipment Group Protect Flowchart
START
ADDRESS = GROUP ADDRESS Set-up W = VIH n=0
G, A9 = VID, E = VIL
Wait 4s Protect W = VIL Wait 100s W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Wait 4s G = VIL Wait 60ns Read DATA
Verify
DATA NO = 01h YES A9 = VIH E, G = VIH End PASS ++n = 25 YES A9 = VIH E, G = VIH FAIL
AI05574
NO
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
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Figure 21. Programmer Equipment Chip Unprotect Flowchart
START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0
A6, A12, A15 = VIH(1) E, G, A9 = VID
Wait 4s Unprotect W = VIL Wait 10ms W = VIH E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1, A6 = VIH
E = VIL Wait 4s G = VIL Verify Wait 60ns Read DATA
INCREMENT CURRENT GROUP
NO
DATA = 00h
YES
NO
++n = 1000 YES
LAST GROUP YES A9 = VIH E, G = VIH PASS
NO
End
A9 = VIH E, G = VIH FAIL
AI05575
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
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Figure 22. In-System Equipment Group Protect Flowchart
START Set-up n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Protect
WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
Wait 100s WRITE 40h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Verify
Wait 4s READ DATA ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL
DATA NO = 01h YES RP = VIH End ISSUE READ/RESET COMMAND ++n = 25 YES RP = VIH ISSUE READ/RESET COMMAND NO
PASS
FAIL
AI05576
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
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Figure 23. In-System Equipment Chip Unprotect Flowchart
START PROTECT ALL GROUPS Set-up n=0 CURRENT GROUP = 0
RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Verify
Wait 4s READ DATA ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH INCREMENT CURRENT GROUP
NO
DATA = 00h
YES
NO
++n = 1000 YES RP = VIH
LAST GROUP YES RP = VIH
NO
End
ISSUE READ/RESET COMMAND
ISSUE READ/RESET COMMAND
FAIL
PASS
AI05577
Note: Block Protection Groups are shown in Appendix D, Tables 21 and 22.
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REVISION HISTORY Table 31. Document Revision History
Date 20-Sep-2001 26-Oct-2001 16-Jan-2002 Version -01 -02 -03 First Issue (Target Specification) Document expanded to full Product Preview Corrections made in "Primary Algorithm-Specific Extended Query" Table in Appendix-B Description of Ready/Busy signal clarified (and Figure 15 modified) Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section tPLYH (time to reset device) re-specified. Values for addresses 23h and 25h corrected in CFI Query System Interface Information table in Appendix B When in Extended Block mode, the block at the boot block address can be used as OTP. Data Toggle Flow chart corrected. Document promoted from "Product Preview" to "Preliminary Data". Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 06 equals 6.0). Revision History moved to end of document. TFBGA48, 6 x 8mm, 0.80mm pitch package added. Identification Current IID removed from Table 12, DC Characteristics. Erase Suspend Latency time and Data Retention parameters and notes added to Table 7, Program, Erase Times and Program, Erase Endurance Cycles. Appendix C, EXTENDED MEMORY BLOCK, added. Auto Select Command sued to read the Extended Memory Block. Extended Memory Block Verify Code row added to Tables 3 and 4, Bus Operations, BYTE = VIL and Bus Operations, BYTE = VIH. Bank Address modified in Auto Select Command. Chip Erase Address modified in Table 8, Status Register Bits. VSS pin connection to ground clarified. Note added to Table 20, Ordering Information Scheme. Table 17, TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Package Mechanical Data and Figure 17, TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, Bottom View Package Outline, corrected. Document promoted from Preliminary Data to full Datasheet status. Packing option added to Table 20, Ordering Information Scheme. Revision Details
19-Apr-2002
-04
24-Apr-2002
-05
19-Jul-2002
-06
08-Apr-2003
6.1
07-May-2003
6.2
25-Jun-2003
7.0
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
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