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May 2008 rev 0.3
PCS3P73Z01AW
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
General Features
* *
input from an external reference, and locks on to it delivering a 1x Timing-SafeTM clock. PCS3P73Z01AW has a Frequency Selection (FS) control that facilitates selecting one of the two frequency ranges within the operating frequency range. Refer to the frequency Selection table for details. The device has an SSEXTR pin to select different deviation and associated Input-Output Skew (TSKEW), depending upon the value of an external resistor connected between SSEXTR and GND. PCS3P73Z01AW has a DLY_CTRL for adjusting the Input-Output clock delay, depending upon the value of capacitor connected at this pin to GND. PD#/OE provides the Power Down option. Outputs will be tri-stated when power down is active. PCS3P73Z01AW operates from a 2.5V/3.3V supply and is available in an 8 Pin TSSOP, and TDFN (2X2) COL Packages, over Commercial temperature range.
1x , LVCMOS Timing-SafeTM Peak EMI Reduction Input frequency: 2MHz - 16MHz @ 2.5V 2MHz - 20MHz @ 3.3V Output frequency ( Timing-SafeTM): 2MHz - 16MHz @ 2.5V 2MHz - 20MHz @ 3.3V Analog Spread Selection up to 1.5% External Input-Output Delay Control option Power Down option for Power Save mode Supply Voltage: 2.5V0.2V 3.3V 0.3V Commercial temperature range 8 pin, TSSOP, and TDFN(2X2) COL packages The First True Drop-in Solution
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* * * * * * *
Functional Description
PCS3P73Z01AW is a 2.5V/3.3V versatile EMI reduction IC based on PulseCore Semiconductor's patent pending Timing-SafeTM technology. PCS3P73Z01AW accepts one
Application
PCS3P73Z01AW is targeted for use in Displays, Camera modules and SDRAM memory interface systems.
Block Diagram
DLY_CTRL
VDD
SSEXTR
CLKIN
PLL ModOUT (Timing-SafeTM)
PD#/OE GND
FS
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
May 2008 rev 0.3
Pin Configuration
VDD SSEXTR DLY_CTRL ModOUT
PCS3P73Z01AW
CLKIN 1 PD#/OE 2 PCS3P73Z01AW FS 3 GND 4
8 7 6 5
Pin Description Pin #
1 2 3 4 5 6 7 8
Type
I I I P O O I P
Pin Name
CLKIN PD#/OE FS GND ModOUT DLY_CTRL SSEXTR VDD External reference Clock input.
Description
Power Down. Pull LOW to enable Power Down. Outputs will be tri-stated when power down is enabled. Pull HIGH to disable power down and enable output. Frequency Select (see Frequency Selection table for details). Ground Buffered modulated Timing-SafeTM clock output External Input-Output Delay control Analog Spread Selection through external resistor to GND. 2.5V / 3.3V supply Voltage
Frequency Selection Table VDD
2.5V 3.3V
FS
0 1 0 1
Frequency(MHz)
2-6 6-16 2-6 6-20
Absolute Maximum Rating Symbol
VDD TSTG Ts TJ TDV Storage temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6 -65 to +125 260 150 2
Unit
V C C C KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Operating Conditions Parameter
VDD(3.3V) VDD(2.5V) TA CL CIN Supply Voltage Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance Input Capacitance
PCS3P73Z01AW
Description
Min
3.0 2.3 0
Max
3.6 2.7 +70 10 7
Unit
V V C pF pF
Electrical Characteristics for 2.5V Supply Parameter
VDD VIL VIH IIL IIH VOL VOH ICC IDD Zo
Description
Supply Voltage Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Static Supply Current Dynamic Supply Current Output Impedance VIN = 0V VIN = VDD IOL = 8mA IOH = -8mA
Test Conditions
Min
2.3 1.7
Typ
2.5
Max
2.7 0.7 50 50 0.6
Unit
V V V A A V V A mA
1.8 2 2 5 6 36 2MHz
CLKIN & PD#/OE pins pulled to GND Unloaded Output 6MHz 16MHz
Electrical Characteristics for 3.3V Supply Parameter
VDD VIH VIL IIH IIL VOH VOL ICC IDD Zo
Description
Supply Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Static Supply Current Dynamic Supply Current Output Impedance VIN = VDD VIN = 0V IOH = -8mA IOL =8mA
Test Conditions
Min
3.0 2.0
Typ
3.3
Max
3.6 0.8 50 50
Unit
V V V A A V V A mA
2.4 0.4 2 4 7 9 27 2MHz
CLKIN pulled Low, PD#/OE pulled Low Unloaded outputs 6MHz 20MHz
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Switching Characteristics for 2.5V Parameter
Input Frequency ModOUT Duty Cycle Rise Time Fall Time
1, 2
PCS3P73Z01AW
Test Conditions
FS=0 FS=1 FS=0 FS=1 Measured at VDD /2 Measured between 20% to 80% Measured between 80% to 20% Unloaded outputs Unloaded outputs with FS=0; @ 5 MHz FS=1; @ 15 MHz FS=0; @ 6 MHz FS=1; @ 12 MHz
Min
2 6 2 6 45
Typ
Max
6 16 6 16
Unit
MHz
50 1.7 0.9 225 150 175
55
% nS nS pS
1, 2
1, 2
Cycle-to-Cycle Jitter2
Input-to-Output propagation Delay
2
SSEXTR pin OPEN, No load on DLY_CTRL 75 3 Stable power supply, valid clock presented on CLKIN pin
pS
PLL Lock Time 2
mS
Notes: 1. All parameters are specified with 10 pF loaded outputs 2. Parameter is guaranteed by design and characterization. Not 100% tested in production
Switching Characteristics for 3.3V Parameter
Input Frequency ModOUT Duty Cycle Rise Time Fall Time
3,4
Test Conditions
FS=0 FS=1 FS=0 FS=1 Measured at VDD /2 Measured between 20% to 80% Measured between 80% to 20% FS=0; @ 5 MHz Unloaded outputs FS=1; @ 15 MHz Unloaded outputs with FS=0; @ 6 MHz FS=1; @ 12 MHz
Min
2 6 2 6 45
Typ
Max
6 20 6 20
Unit
MHz
50 1.2 0.8 200 125 -75 125
55
% nS nS pS
3,4
3,4
Cycle-to-Cycle Jitter 4
Input-to-Output propagation Delay PLL Lock Time
4
4
SSEXTR pin OPEN, No load on DLY_CTRL CLKIN pin
pS
Stable power supply, valid clock presented on
3
mS
Notes: 3. All parameters are specified with 10 pF loaded outputs 4. Parameter is guaranteed by design and characterization. Not 100% tested in production
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Switching Waveforms
PCS3P73Z01AW
Duty Cycle Timing
t1 t2
VDD/2 OUTPUT
VDD/2
VDD/2
All Outputs Rise/Fall Time
80% 20%
80% 20%
3.3V
OUTPUT t3 t4
0V
Input - Output Propagation Delay
VDD/2 INPUT VDD/2 OUTPUT
t6
Input-Output Skew
Input
Timing-SafeTM Output
TSKEW -
TSKEW+
One clock cycle N=1
when spread spectrum is ON For example, TSKEW = 0.20 for an Input clock of 12MHz, translates in to (1/12MHz) * 0.20=16.66nS Note: Tskew is measured in units of Clock Period
TSKEW represents input-output skew
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Typical example of Timing-SafeTM waveform
Input
PCS3P73Z01AW
Input
ModOUT with SSOFF
Timing-SafeTM ModOUT
Typical Application Schematic
VDD VDD 0 VDD 0 0 3 FS DLY_CTRL 6 0 2 PD#/OE SSEXTR 7 External Input-Output Delay Control C 4 GND ModOUT 5
SSEXTR can be Pulled HIGH to turn OFF SS
CLKIN
1
CLKIN
VDD 8
0.01uF External Spread Control R
Note: Refer to Pin Description table for Functionality details
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Charts (for VDD=2.5V0.2V and 3.3V0.3V)
Deviation Vs Resistance 2.25 2 1.75 Deviation (+/-%) 1.5 Tskew 1.25 1 0.75 0.5 0.25 0 0 100 200 300 400 Resistance (KOhms) 0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 100
PCS3P73Z01AW
Tskew Vs Resistance
2MHz
2MHz
200
300
400
Resistance (KOhms)
Fig1: Deviation Vs Resistance (2MHz, FS=0)
Deviation Vs Resistance 2.25 2 1.75 Deviation (+/-%) 1.5 Tskew 1.25 1 0.75 0.5 0.25 0 0 20 40 60 80 100 120 140 160 180 200 220 Resistance (KOhms)
4MHz
Fig2: Tskew Vs Resistance (2MHz, FS=0)
Tskew Vs Resistance 0.11 0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 20 40 60 80 100 120 140 160 180 200 220 Resistance (KOhms)
4MHz
Fig3: Deviation Vs Resistance (4MHz, FS=0)
Fig4: Tskew Vs Resistance (4MHz, FS=0)
Tskew Vs Resistance
Deviation Vs Resistance 2.25 2 1.75 Deviation (+/-%) Tskew 1.5 1.25 1 0.75 0.5 0.25 0 0 10 20 30 40 50 60 70 80 90 100 110 120 Resistance (KOhms)
0.11
6MHz
6MHz
0.1 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 0 10 20 30 40 50 60 70 80 90 100 110 120 Resistance (KOhms)
Fig5: Deviation Vs Resistance (6MHz, FS=0)
Fig6: Tskew Vs Resistance (6MHz, FS=0)
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Deviation Vs Resistance 1.5 1.25 Deviation (+/-%) 1 0.75 0.5 0.25 0 0 50 100 150 200 250 300 Resistance (KOhms) Tskew 6MHz
0.225 0.2 0.175 0.15 0.125 0.1 0.075 0.05 0.025 0 0 50 100
PCS3P73Z01AW
Tskew Vs Resistance
6MHz
150
200
250
300
Resistance (KOhms)
Fig7: Deviation Vs Resistance (6MHz, FS=1)
Fig8: Tskew Vs Resistance (6MHz, FS=1)
Deviation Vs Resistance
Tskew Vs Resistance
12.5MHz
1.5 1.25 1 0.75 0.5 0.25 0 0 20 40 60 80 100 120
0.225 0.2 0.175
12.5MHz
Deviation (+/-%)
0.15 Tskew
140
0.125 0.1 0.075 0.05 0.025 0 0 20 40 60 80 100 120 140 160
Resistance (KOhms)
Resistance (KOhms)
Fig9: Deviation Vs Resistance (12.5MHz, FS=1)
Fig10: Tskew Vs Resistance (12.5MHz, FS=1)
Deviation Vs Resistance
1.5 1.25 0.2 0.175 0.15
Tskew Vs Resistance
16MHz
16MHz
Deviation (+/-%)
1
0.125
Tskew
0.75 0.5 0.25 0 0 10 20 30 40 50 60 70 80 90 100 110 120
0.1 0.075 0.05 0.025 0 0 10 20 30 40 50 60 70 80 90 100 110 120
Resistance (KOhms)
Resistance (KOhms)
Fig11: Deviation Vs Resistance (16MHz, FS=1)
Fig12: Tskew Vs Resistance (16MHz, FS=1)
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
I/O Delay Vs Load (DLY_CTRL)
400 200 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 200 0 0 -200 1 2 3 4 5 6
PCS3P73Z01AW
I/O Delay Vs Load (DLY_CTRL)
7
8
9
10 11 12 13 14 15
I/O Delay (nS)
-200 -400 -600 -800 -1000 -1200 2.3V 2.5V 2.7V 3.0V 3.3V 3.6V
I/O Delay (nS)
-400 -600 -800 -1000 -1200 2.3V 2.5V 2.7V 3.0V 3.3V 3.6V
Capacitace (pF)
Capacitace (pF)
Fig13: I/O Delay Vs Load (DLY_CTRL) (For 2MHz, FS=0)
Fig14: I/O Delay Vs Load (DLY_CTRL) (For 4MHz, FS=0)
I/O Delay Vs Load (DLY_CTRL)
400 200 0 400 200 0
I/O Delay Vs Load (DLY_CTRL)
I/O Delay (nS)
I/O Delay (nS)
0 -200 -400 -600 -800 -1000
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0 -200 -400 -600 -800 -1000
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
2.3V 2.5V 2.7V 3.0V 3.3V 3.6V
2.3V 2.5V 2.7V 3.0V 3.3V 3.6V
Capacitace (pF)
Capacitace (pF)
Fig15: I/O Delay Vs Load (DLY_CTRL) (For 6MHz, FS=0)
Fig16: I/O Delay Vs Load (DLY_CTRL) (For 6MHz, FS=1)
I/O Delay Vs Load (DLY_CTRL)
400 200 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 200 0 0 -200 1 2 3
I/O Delay Vs Load (DLY_CTRL)
4
5
6
7
8
9
10 11 12 13 14 15
I/O Delay (nS)
-200 -400 -600 -800 -1000 -1200 2.3V 2.5V 2.7V 3.0V 3.3V 3.6V
I/O Delay (nS)
-400 -600 -800 -1000 -1200 2.3V 2.5V 2.7V 3.0V 3.3V 3.6V
Capacitace (pF)
Capacitace (pF)
Fig17: I/O Delay Vs Load (DLY_CTRL) (For 12.5MHz, FS=1)
Note: Device to Device variation of Deviation and I/O delay is 10%
Fig18: I/O Delay Vs Load (DLY_CTRL) (For 16MHz, FS=1)
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Package Information
PCS3P73Z01AW
8-lead TSSOP Package (4.40-MM Body)
H
E D A2 A e B A1 L C
Dimensions Symbol Min
A A1 A2 B c D E e H L 0.020 0 0.002 0.033 0.008 0.004 0.114 0.169 0.026 BSC 0.252 BSC 0.028 8 0.50 0
Inches Max
0.043 0.006 0.037 0.012 0.008 0.122 0.177
Millimeters Min Max
1.10 0.05 0.85 0.19 0.09 2.90 4.30 0.65 BSC 6.40 BSC 0.70 8 0.15 0.95 0.30 0.20 3.10 4.50
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
TDFN COL 2x2 8L package Outline drawing
PCS3P73Z01AW
Dimensions Symbol
A A3 b D E e L
Inches Min Max
0.027 0.008 0.0315 0.012 0.008 BSC
Millimeters Min Max
0.70 0.20 0.80 0.203 BSC 0.30 2.00 BSC 2.00 BSC 0.50 BSC 0.50 0.60
0.079 BSC 0.078 BSC 0.020 BSC 0.020 0.024
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
Ordering Codes Ordering Code
PCS3P73Z01AWG-08-TT PCS3P73Z01AWG-08-TR PCS3P73Z01AWG-08-CR
LL = 2 Character LOT #
PCS3P73Z01AW
Marking
3P73Z01AWG 3P73Z01AWG AE1LL
Package Type
8-pin 4.4-mm TSSOP - TUBE, Green 8- pin 4.4-mm TSSOP - TAPE & REEL, Green 8- pin 2-mm TDFN COL - TAPE & REEL, Green
Temperature
Commercial Commercial Commercial
Device Ordering Information
PCS3P73Z01AWG-08-TR
R = Tape & Reel, T = Tube or Tray O = TSOT23 S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 J=TSOT26 C=TDFN (2X2) COL
DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved
PulseCore Semiconductor Mixed Signal Product
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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May 2008 rev 0.3
PCS3P73Z01AW
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Part Number: PCS3P73Z01AW Document Version: 0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 Many PulseCore Semiconductor products are protected by issued patents or by applications for patent
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
Wide Frequency range Timing-SafeTM Peak EMI reduction IC
Notice: The information in this document is subject to change without notice.
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