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19-0363; Rev 1; 3/10
KIT ATION EVALU BLE AVAILA
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Features
2.4GHz to 2.5GHz ISM Band Operation IEEE 802.11g/b Compatible (54Mbps OFDM and 11Mbps CCK) Complete RF Transceiver, PA, and Crystal Oscillator (MAX2831) Best-in-Class Transceiver Performance 62mA Receiver Current 2.6dB Rx Noise Figure -76dBm Rx Sensitivity (54Mbps OFDM) No I/Q Calibration Required 0.1dB/0.35 Rx I/Q Gain/Phase Imbalance 33dB RF and 62dB Baseband Gain Control Range 60dB Range Analog RSSI per RF Gain Setting Fast Rx I/Q DC-Offset Settling Programmable Baseband Lowpass Filter 20-Bit Sigma-Delta Fractional-N PLL with < 20Hz Step Size Digitally Tuned Crystal Oscillator +18.5dBm Transmit Power (5.6% EVM with 54Mbps OFDM) 31dB Tx Gain Control Range Integrated Power Detector (MAX2831) Serial or Parallel Gain-Control Interface > 40dB Tx Sideband Suppression without Calibration Tx/Rx I/Q Error Detection Transceiver Operates from +2.7V to +3.6V PA Operates from +2.7V to +4.2V (MAX2831) Low-Power Shutdown Mode Small 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm)
General Description
The MAX2831/MAX2832 direct conversion, zero-IF, RF transceivers are designed specifically for 2.4GHz to 2.5GHz 802.11g/b WLAN applications. The MAX2831 completely integrates all circuitry required to implement the RF transceiver function, providing an RF power amplifier (PA), RF-to-baseband receive path, basebandto-RF transmit path, VCO, frequency synthesizer, crystal oscillator, and baseband/control interface. The MAX2832 integrates the same functional blocks except for the PA. Both devices include a fast-settling sigma-delta RF synthesizer with smaller than 20Hz frequency steps and a digitally tuned crystal oscillator allowing use of a low-cost crystal. The devices also integrate on-chip DC-offset cancellation and I/Q errors and carrier leakage-detection circuits. Only an RF bandpass filter (BPF), crystal, RF switch, and a small number of passive components are needed to form a complete 802.11g/b WLAN RF frontend solution. The MAX2831/MAX2832 completely eliminate the need for an external SAW filter by implementing on-chip monolithic filters for both the receiver and transmitter. The baseband filters are optimized to meet the IEEE 802.11g standard and proprietary turbo modes up to 40MHz channel bandwidth. These devices are suitable for the full range of 802.11g OFDM data rates (6Mbps to 54Mbps) and 802.11b QPSK and CCK data rates (1Mbps to 11Mbps). The ICs are available in a small, 48-pin thin QFN package measuring only 7mm x 7mm x 0.8mm.
MAX2831/MAX2832
Applications
Wi-Fi, PDA, VOIP, and Cellular Handsets Wireless Speakers and Headphones General 2.4GHz ISM Radios
Ordering Information
PART MAX2831ETM+T MAX2832ETM+T TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 48 Thin QFN-EP* 48 Thin QFN-EP*
*EP = Exposed pad. +Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
ABSOLUTE MAXIMUM RATINGS
VCCTXPA, VCCPA and TXRF_ to GND ....................-0.3V to +4.5V VCCLNA, VCCTXMX, VCCPLL, VCCCP, VCCXTAL, VCCVCO, VCCRXVGA, VCCRXFL, and VCCRXMX_ to GND....-0.3V to +3.9V B6, B7, B3, B2, SHDN, B5, CS, SCLK, DIN, B1, TUNE, B4, TXBBI_, TXBBQ_, RXHP, RXTX, RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT, XTAL, CTUNE, RXRF_ to GND .......................................-0.3V to (Operating VCC + 0.3V) RXBBI_, RXBBQ_, RSSI, BYPASS, CPOUT, LD, CLOCKOUT Short-Circuit Duration ..........................................................10s RF Input Power ...............................................................+10dBm Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN (derates 27.8mW/C above +70C).....2.22W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10s) .................................+260C Soldering Temperature (reflow) .......................................+260C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2831 EV kit: VCC_ = 2.7V to 3.6V, VCCPA = VCCTXPA = 2.7V to 4.2V, TA = -40C to +85C, Rx set to the maximum gain. CS = high, RXHP = SCLK = DIN = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs terminated into 50, receiver baseband outputs are open. 100mVRMS differential I and Q signals (54Mbps IEEE 802.11g OFDM) applied to I/Q baseband inputs of transmitter in transmit mode, fREF = 40MHz, and registers set to recommended settings and corresponding test mode, unless otherwise noted. Typical values are at VCC = 2.8V, VCCPA = 3.3V, and TA = +25C, LO frequency = 2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETERS Supply Voltage VCC_ VCCPA, VCCTXPA Shutdown mode, B7: B1 = 0000000, reference oscillator not applied Standby mode Supply Current Rx mode Tx mode, TA = +25C, VCC = 2.8V, VCCPA = 3.3V, (Note 2) Rx calibration mode Tx calibration mode Rx I/Q Output Common-Mode Voltage Rx I/Q Output Common-Mode Voltage Variation Tx Baseband Input CommonMode Voltage Operating Range Tx Baseband Input Bias Current TA = +25C TA = -40C (relative to TA = +25C) TA = +85C (relative to TA = +25C) DC-coupled Source current 0.9 CONDITIONS MIN 2.7 2.7 TYP MAX 3.6 4.2 UNITS V
TA = +25C
20
A
TA = +25C TA = -40C to +85C TA = +25C TA = -40C to +85C MAX2831, transmit section MAX2831, PA, POUT = +18.2dBm MAX2832 TA = +25C TA = +25C 0.98
28 62 82 209 86 101 78 1.2 -17 15
35 35 78 82 104 258 mA
1.33
V mV
1.3 22
V A
2
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
DC ELECTRICAL CHARACTERISTICS (continued)
(MAX2831 EV kit: VCC_ = 2.7V to 3.6V, VCCPA = VCCTXPA = 2.7V to 4.2V, TA = -40C to +85C, Rx set to the maximum gain. CS = high, RXHP = SCLK = DIN = low, RSSI and clock output buffer are off, no signal at RF inputs, all RF inputs and outputs terminated into 50, receiver baseband outputs are open. 100mVRMS differential I and Q signals (54Mbps IEEE 802.11g OFDM) applied to I/Q baseband inputs of transmitter in transmit mode, fREF = 40MHz, and registers set to recommended settings and corresponding test mode, unless otherwise noted. Typical values are at VCC = 2.8V, VCCPA = 3.3V, and TA = +25C, LO frequency = 2.437GHz, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETERS CONDITIONS MIN VCC 0.4 0.4 -1 -1 VCC 0.4 0.4 +1 +1 TYP MAX UNITS LOGIC INPUTS: SHDN, RXTX, SCLK, DIN, CS, B7:B1, RXHP Digital Input-Voltage High, VIH Digital Input-Voltage Low, VIL Digital Input-Current High, IIH Digital Input-Current Low, IIL LOGIC OUTPUTS: LD, CLOCKOUT Digital Output-Voltage High, VOH Digital Output-Voltage Low, VOL Sourcing 100A Sinking 100A V V V V A A
MAX2831/MAX2832
AC ELECTRICAL CHARACTERISTICS--Rx Mode
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications which normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETER RF Input Frequency Range High RF gain RF Input Return Loss Mid RF gain Low RF gain Maximum gain, B7:B1 = 1111111 Total Voltage Gain Minimum gain, B7:B1 = 0000000 TA = +25C TA = -40C to +85C TA = +25C 86 83 3 -16 dB From high-gain mode (B7:B6 = 11) to low-gain mode (B7:B6 = 0X) RF Gain-Change Settling Time Gain change from high gain to medium gain, high gain to low, or medium gain to low gain; gain settling to within 2dB of steady state; RXHP = 1 -33 8 CONDITIONS MIN 2.4 18 11 14 98 dB dB TYP MAX 2.5 UNITS GHz
RECEIVER SECTION: LNA RF INPUT-TO-BASEBAND I/Q OUTPUTS
From high-gain mode (B7:B6 = 11) to medium-gain mode (B7:B6 = 10) RF Gain Steps (Note 3)
0.2
s
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3
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
AC ELECTRICAL CHARACTERISTICS--Rx Mode (continued)
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications which normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETER Baseband Gain Range CONDITIONS From maximum baseband gain (B5:B1 = 11111) to minimum baseband gain (B5:B1 = 00000) Voltage gain = maximum with B7:B6 = 11 DSB Noise Figure Voltage gain = 50dB with B7:B6 = 11 Voltage gain = 45dB with B7:B6 = 10 Voltage gain = 15dB with B7:B6 = 0X In-Band Compression Point Based on EVM In-Band Output P-1dB Out-of-Band Input IP3 (Note 4) I/Q Phase Error I/Q Gain Imbalance RX I/Q Output Load Impedance (R || C) Tx-to-Rx Conversion Gain for Rx I/Q Calibration Baseband VGA Settling Time I/Q Output DC Step when RXHP Transitions from 1 to 0 in Presence of 802.11g Short Sequence I/Q Output DC Droop I/Q Static DC Offset Spurious Signal Emissions from LNA input RECEIVER BASEBAND FILTERS Gain Ripple in Passband Group-Delay Ripple in Passband 10kHz to 8.5MHz at baseband 10kHz to 8.5MHz at baseband 1.3 45 DBP-P nsP-P -19dBVRMS baseband output EVM degrades to 9% B7:B6 = 11 B7:B6 = 10 B7:B6 = 0X MIN 55 TYP 62 2.6 3.2 16 34 -41 -24 -6 2.5 -12 -4 24 0.35 0.1 10 10 0.5 0.1 Degrees dB k pF dB s dBm VP-P dBm dB MAX 67 UNITS dB
Voltage gain = 90dB, with B7:B6 = 11 B7:B6 = 11 B7:B6 = 10 B7:B6 = 0X 1 variation (without calibration) 1 variation (without calibration) Minimum differential resistance Maximum differential capacitance For receiver gain, B7:B1 = 1101111 (Note 5) Gain change from B5:B1 = 10111 to B5:B1 = 00111; gain settling to within 2dB of steady state After switching RXHP to logic 0 from initial logic 1, during ideal short sequence data at -55dBm input in AWGN channel, for -19dBV output; normalized to RMS signal on I and Q outputs; transition point varied from 0 to 0.8s in steps of 0.1s After switching RXHP to 0, D13:D12, Register 7 (A3:A0 = 0111) RXHP = 1, B7:B1 = 1101110, 1 variation RF = 1GHz to 26.5GHz
-5
dBc
1 1 -51
V/s mV dBm
4
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
AC ELECTRICAL CHARACTERISTICS--Rx Mode (continued)
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fRF = 2.439GHz, fLO = 2.437GHz; receiver baseband I/Q outputs at 112 mVRMS (-19dBV), fREF = 40MHz, SHDN = CS = high, RXTX = SCLK = DIN = low, with power matching for the differential RF pins using the typical applications and registers set to default settings and corresponding test mode, unless otherwise noted. Unmodulated single-tone RF input signal is used with specifications which normally apply over the entire operating conditions, unless otherwise indicated. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETER At 8.5MHz Baseband Filter Rejection (Nominal Mode) RSSI RSSI Minimum Output Voltage RSSI Maximum Output Voltage RSSI Slope RSSI Output Settling Time To within 3dB of steady state +32dB signal step -32dB signal step RLOAD 10k || 5pF RLOAD 10k || 5pF 0.4 2.4 30 200 600 V V mV/dB ns At 15MHz At 20MHz At > 40MHz CONDITIONS MIN TYP 3.2 27 50 80 dB MAX UNITS
MAX2831/MAX2832
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5
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
AC ELECTRICAL CHARACTERISTICS--Tx Mode
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fRF = 2.439GHz , fLO = 2.437GHz. fREF = 40MHz, SHDN = RXTX = CS = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications circuit. 100mVRMS sine and cosine signal (or 100mVRMS 54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETER RF Output Frequency Range 54Mbps 802.11g OFDM signal MAX2831 Output Power 802.11b signal, 141mVRMS, IEEE802.11b I/Q signals MAX2832 Unwanted Sideband Suppression Carrier Leakage at Center Frequency of Channel -3dB VGA back off B6:B1 = 000000 dBm Output power adjusted to meet spectral mask 21 Output power adjusted to meet 5.6% EVM, and spectral mask B6:B1 = 000000 CONDITIONS MIN 2.4 18.5 -7.5 TYP MAX 2.5 UNITS GHz
TRANSMIT SECTION: Tx BASEBAND I/Q INPUTS TO RF OUTPUTS
-5.3 -31.5 -42 -30 -67 -36 -47 -64 -42 -65 -51 -33 -54 -78 -65 -72 -78 -46 -72 -46 -60 -75 dBm/ MHz dBm/ MHz dBc dBc
Without I/Q calibration, B6:B1 = 100001 Without DC offset correction 1/3 x fLO < 1GHz > 1GHz 2/3 x fLO 4/3 x fLO 5/3 x fLO 8/3 x fLO 2 x fLO 3 x fLO 1/3 x fLO < 1GHz > 1GHz 2/3 x fLO 4/3 x fLO 5/3 x fLO 8/3 x fLO 2 x fLO 3 x fLO
Transmitter Spurious Signal Emissions (MAX2831)
B6:B1 = 111000, OFDM signal
Transmitter Spurious Signal Emissions (MAX2832)
B6:B1 = 111111, OFDM signal
6
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
AC ELECTRICAL CHARACTERISTICS--Tx Mode (continued)
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fRF = 2.439GHz , fLO = 2.437GHz. fREF = 40MHz, SHDN = RXTX = CS = high, and SCLK = DIN = low, with power matching for the differential RF pins using the typical applications circuit. 100mVRMS sine and cosine signal (or 100mVRMS 54Mbps IEEE 802.11g I/Q signals wherever OFDM is mentioned) applied to baseband I/Q inputs of transmitter (differential DC-coupled). Registers set to recommend settings and corresponding test mode, unless otherwise noted. RF inputs/outputs specifications are referenced to device pins and do not include 1dB loss from EV kit PCB, balun, and SMA connectors.) (Note 1)
PARAMETER RF Output Return Loss Tx I/Q Input Load Impedance (R || C) Baseband -3dB Corner Frequency Baseband Filter Rejection Minimum Power Detector Output Voltage Maximum Power Detector Output Voltage RF Power Detector Response Time CONDITIONS Off-chip balun + match, singleended Minimum differential resistance Maximum differential capacitance D1:D0 = 01, Register 8 (A3:A0 = 1000) At 30MHz, in nominal mode Short sequence transmitter power = +9dBm Short sequence transmitter power = +19dBm Nominal mode MAX2831 MAX2832 MIN TYP -20 -10 20 0.7 11 62 0.3 1.2 0.3 MAX UNITS dB k pF MHz dB V V s
MAX2831/MAX2832
TRANSMITTER LO LEAKAGE AND I/Q CALIBRATION USING LO LEAKAGE AND SIDEBAND DETECTOR (see the Tx/Rx Calibration Mode section) Tx BASEBAND I/Q INPUTS TO RECEIVER OUTPUTS Output at 1 x fTONE (for LO leakage = -29dBc), fTONE = 2MHz, 100mVRMS Output at 2 x fTONE (for LO leakage = -240dBc), fTONE = 2MHz, 100mVRMS -34 dBVRMS -44 30 1 dB MHz
LO Leakage and Sideband Detector Output
Calibration register, D12:D11 = 00, A3:A0 = 0110
Amplifier Gain Range Lower -3dB Corner Frequency
D12:D11 = 00 to D12:D11 = 11, A3:A0 = 0110
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7
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
AC ELECTRICAL CHARACTERISTICS--Frequency Synthesis
(MAX2831 EV kit: VCC_ = 2.7V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER FREQUENCY SYNTHESIZER RF Channel Center Frequency Channel Center Frequency Programming Minimum Step Size Charge-Pump Comparison Frequency Reference Frequency Range Reference Frequency Input Levels Reference Frequency Input Impedance (R || C) AC-coupled to XTAL pin Resistance (XTAL) Capacitance (XTAL) fOFFSET = 1kHz fOFFSET = 10kHz Closed-Loop Phase Noise fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET = 10MHz Closed-Loop Integrated Phase Noise Charge-Pump Output Current Reference Spurs VCO Frequency Error 20MHz offset Measured from Tx-Rx or Rx-Tx transition 3s to 9s > 9s RMS phase jitter; integrate from 10kHz to 10MHz offset 20 800 5 4 -86 -94 -94 -110 -120 0.9 1 -55 50 1 210 0.5 VTUNE = 0.5V VTUNE = 2.2V 103 86 2.2 Degrees mA dBc kHz dBc/Hz 2.4 20 2.5 GHz Hz CONDITIONS MIN TYP MAX UNITS
20 44
MHz MHz mVP-P k pF
VOLTAGE-CONTROLLED OSCILLATOR Pushing VCO Tuning Voltage Range LO Tuning Gain Referred to 2400MHz LO, VCC varies by 0.3V kHz V MHz/V
8
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
AC ELECTRICAL CHARACTERISTICS--Miscellaneous Blocks
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, fLO = 2.437GHZ, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER CRYSTAL OSCILLATOR On-Chip Tuning Capacitance Range On-Chip Tuning Capacitance Step Size ON-CHIP TEMPERATURE SENSOR TA = -40C Output Voltage A3:A0 = 1000, D9:D8 = 01 TA = +25C TA = +85C 0.35 1 1.6 V Maximum capacitance, A3:A0 = 1110, D6:D0 = 1111111 Minimum capacitance, A3:A0 = 1110, D6:D0 = 0000000 15.4 0.5 0.12 pF pF CONDITIONS MIN TYP MAX UNITS
MAX2831/MAX2832
AC ELECTRICAL CHARACTERISTICS--Timing
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SYSTEM TIMING (See Figure 3) Turn-On Time Crystal Oscillator Turn-On Time Channel Switching Time From SHDN rising edge to LO settled within 1kHz using external reference frequency input 90% of final output amplitude level Loop BW = 150kHz, fRF = 2.5GHz to 2.4GHz Measured from Tx or Rx enable rising edge; signal settling to within 2dB of steady state Rx to Tx Tx to Rx, RXHP = 1 60 1 25 2 s 2 1.5 1 1.9 0.1 s s s s s ms s CONDITIONS MIN TYP MAX UNITS
Rx/Tx Turnaround Time
Tx Turn-On Time (from Standby Mode) Tx Turn-Off Time (from Standby Mode) Rx Turn-On Time (from Standby Mode) Rx Turn-Off Time (from Standby Mode)
From Tx-enable active rising edge; signal settling to within 2dB of steady state From Tx-enable inactive rising edge From Rx-enable active rising edge; signal settling to within 2dB of steady state From Rx-enable inactive rising edge
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9
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
AC ELECTRICAL CHARACTERISTICS--Timing (continued)
(MAX2831 EV kit: VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA =+25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, SCLK = DIN = low, PLL loop bandwidth = 150kHz, and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER 3-WIRE SERIAL-INTERFACE TIMING (See Figure 2) SCLK Rising Edge to CS Falling Edge Wait Time, tCSO Falling Edge of CS to Rising Edge of First SCLK Time, tCSS DIN to SCLK Setup Time, tDS DIN to SCLK Hold Time, tDH SCLK Pulse-Width High, tCH SCLK Pulse-Width Low, tCL Last Rising Edge of SCLK to Rising Edge of CS or Clock to Load Enable Setup Time, tCSH CS High Pulse Width, tCSW Time Between the Rising Edge of CS and the Next Rising Edge of SCLK, tCS1 Clock Frequency, fCLK Rise Time, tR Fall Time, tF 6 6 6 6 6 6 6 20 6 20 2 2 ns ns ns ns ns ns ns ns ns MHz ns ns CONDITIONS MIN TYP MAX UNITS
Note 1: Min and max limits are guaranteed by test at TA = +25C and +85C and guaranteed by design and characterization at TA = -40C. The power-on register settings are not production tested. Recommended register setting must be loaded after VCC is supplied. Note 2: Guaranteed by design and characterization. Note 3: The nominal part-to-part variation of the RF gain step is 1dB. Note 4: Two tones at +25MHz and +48MHz offset with -35dBm/tone. Measure IM3 at 2MHz. Note 5: Tx I/Q inputs = 100mVRMS.
10
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Typical Operating Characteristics
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
Rx ICC vs. VCC
MAX2831/32 toc01
MAX2831/MAX2832
NOISE FIGURE vs. BASEBAND GAIN SETTINGS
MAX2831/32 toc02
Rx VOLTAGE GAIN vs. BASEBAND GAIN SETTING
90 80 70 LNA = HIGH GAIN
MAX2831/32 toc03
67 66 TA = +85C 65 ICC (mA)
45 40 35 30 NF (dB) 25 20 15 10 LNA = HIGH GAIN LNA = MEDIUM GAIN LNA = LOW GAIN
100
GAIN (dB)
60 50 40 30 20 10 0 LNA = LOW GAIN 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 BASEBAND GAIN SETTINGS LNA = MEDIUM GAIN
64 63 62 61 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V) TA = -40C TA = +25C
5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 BASEBAND GAIN SETTINGS
Rx IN-BAND OUTPUT P-1dB vs. GAIN
MAX2831/32 toc04
Rx EVM vs. PIN
20 18 16 14 EVM (%) 12 10 8 6 4 2 0 0 -80 -70 -60 -50 -40 -30 PIN (dBm) -20 -10 0 0.5 EVM (%) 2.0 1.5 1.0 LNA = HIGH GAIN LNA = MEDIUM GAIN LNA = LOW GAIN
MAX2831/32 toc05
Rx EVM vs. VOUT
PIN = -50dBm LNA = HIGH GAIN
MAX2831/32 toc06
0 -1 OUTPUT P-1dB (dBVRMS) -2 -3 -4 -5 -6 -7 15 25 35 45 55 GAIN (dB) 75 85 LNA MEDIUM/LOWGAIN SWITCH POINT LNA MEDIUM/HIGHGAIN SWITCH POINT
22
3.0 2.5
95
-29 -27 -25 -23 -21 -19 -17 -15 -13 -11 -9 VOUT (dBVRMS)
OFDM EVM WITH OFDM JAMMER vs. OFFSET FREQUENCY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -65
MAX2831/32 toc07
Rx EMISSION SPECTRUM, LNA INPUT
1.5 VCO LEAKAGE -40 VCO LEAKAGE -50 -60 -70 dBM
MAX2831/32 toc08
LNA INPUT RETURN LOSS vs. RF FREQUENCY
MID GAIN -10 INPUT RETURN LOSS (dB)
MAX2831/32 toc09
-5
fOFFSET = 20MHz
EVM (%)
fOFFSET = 25MHz
-80 -90 -100 -110 -120 fOFFSET = 40MHz -130 -140
4x VCO
PIN = -62dBm
2x VCO LEAKAGE 3x VCO
RBW = 300kHz LNA = LOW GAIN
-15
-20 LOW GAIN -25 HIGH GAIN
-30 DC 26.5GHz 2300 2350 2400 2450 2500 RF FREQUENCY (MHz) 2550 2600
-55
-45 PJAMMER (dBm)
-35
-25
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11
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Typical Operating Characteristics (continued)
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
Rx RSSI STEP RESPONSE (+32dB LNA GAIN STEP)
MAX2831/32 toc11 MAX2831/32 toc10
Rx RSSI OUTPUT vs. INPUT POWER
3.0 LNA = HIGH GAIN 2.5 RSSI OUTPUT (V) 2.0 1.5 1.0 0.5 0 -120 -100 -80 -60 -40 PIN (dBm) -20 0 20 LNA = LOW GAIN LNA = MEDIUM GAIN 0 1.45V 3V
Rx RSSI STEP RESPONSE (-32dB LNA GAIN STEP)
MAX2831/32 toc12
3V
0V 1.5V
0.45 0V 200ns/div 200ns/div
Rx I/Q DC OFFSET SETTLING RESPONSE (+8dB BB VGA GAIN STEP)
MAX2831/32 toc13
Rx I/Q DC OFFSET SETTLING RESPONSE (-8dB BB VGA GAIN STEP)
MAX2831/32 toc14
Rx I/Q DC OFFSET SETTLING RESPONSE (-16dB BB VGA GAIN STEP)
MAX2831/32 toc15
3V
2.0V
2.5V 0V
0V 10mV 5mV 0V 40ns/div
0V 10mV 5mV 0mV 40ns/div 10mV 5mV 0V 400ns/div
Rx I/Q DC OFFSET SETTLING RESPONSE (-32dB BB VGA GAIN STEP)
MAX2831/32 toc16
I/Q OUTPUT DC ERROR DROOP (RxHP = 10; 100Hz MODE)
MAX2831/32 toc17
Rx BB VGA SETTLING RESPONSE (+8 GAIN STEP)
MAX2831/32 toc18
3V
3V 3V
0V
0V 0V 0V 500mV 0V -500mV
10mV 5mV 0V 400ns/div
-5mV -10mV
20ms/div
40ns/div
12
______________________________________________________________________________________
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Typical Operating Characteristics (continued)
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
Rx BB VGA SETTLING RESPONSE (-8 GAIN STEP)
MAX2831/32 toc19
MAX2831/MAX2832
Rx BB VGA SETTLING RESPONSE (-16 GAIN STEP)
MAX2831/32 toc20
Rx BB VGA SETTLING RESPONSE (-32 GAIN STEP)
MAX2831/32 toc21
3V
3V
3V
0V 500mV 0V -500mV
0V 500mV 0V -500mV
0V 500mV 0V -500mV
40ns/div
40ns/div
40ns/div
RF LNA SETTLING RESPONSE (HIGH TO MEDIUM)
MAX2831/32 toc22
RF LNA SETTLING RESPONSE (HIGH TO LOW)
MAX2831/32 toc23
Rx BB FREQUENCY RESPONSE vs. FINE SETTING (COARSE SETTING = 8.5MHz)
MAX2831/32 toc24
20 0 -20 dB
3V
3V
0V 500mV 0V -500mV 100ns/div
0V 500mV 0V
-40 -60 -80
-500mV -100 100ns/div 1 10 FREQUENCY (MHz) 100
Rx BB FREQUENCY RESPONSE vs. COARSE SETTING (FINE SETTING = 010)
MAX2831/32 toc25
RX BASEBAND FILTER GROUP DELAY
MAX2831/32 toc26
HISTOGRAM: Rx STATIC DC OFFSET
MEAN: 0mV STD: 0.977mV SAMPLE SIZE: 1006
MAX2831/32 toc27
20 0 -20
78 65 52
20ns/div
-40 dB -60 -80 -100 -120 1 10 FREQUENCY (MHz) 100
39 26 13 0 1 FREQUENCY (MHz) 12 1/div
______________________________________________________________________________________
13
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Typical Operating Characteristics (continued)
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
HISTOGRAM: Rx GAIN IMBALANCE
MAX2831/32 toc28
HISTOGRAM: Rx PHASE IMBALANCE
MAX2831/32 toc29
Tx ICC vs. VCC
TA = +85C 86 TA = +25C
MAX2831/32 toc30
138 115 92 69 46 23 0 1/div MEAN: 0dB STD: 0.064dB SAMPLE SIZE: 951
114 95 76 57 38 19 0 1/div MEAN: 0.3 STD: 0.314 SAMPLE SIZE: 1013
88
ICC (mA)
84
82
80
TA = -40C
78 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC (V)
HISTOGRAM: Tx LO LEAKAGE
MAX2831/32 toc31
HISTOGRAM: Tx SIDEBAND SUPPRESSION
MAX2831/32 toc32
HISTOGRAM: Tx OUTPUT POWER VARIATION
MEAN: 18.5dBm GAIN ADJUSTED TO ACHIEVE 5.6% EVM
MAX2831/32 toc33 MAX2831/32 toc36
48 40 32 24 16 8 0 1/div MEAN: -33.45dBc STD: 6.31dB SAMPLE SIZE: 999
72 60 48 36 24 12 0 1/div MEAN: -42dBc STD: 1.9dB SAMPLE SIZE: 1000
12 10 8 6 4 2 0
0.1dB/div
Tx BASEBAND FREQUENCY RESPONSE
MAX2831/32 toc34
Tx OUTPUT POWER vs. FREQUENCY (B6:B1 = 111111) (MAX2832 ONLY)
MAX2831/32 toc35
Tx OUTPUT POWER vs. GAIN SETTING (MAX2832 ONLY)
0 -5 -10 POUT (dBm) -15 -20 -25 -30 -35 -40 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 GAIN SETTINGS
0 -10 FILTER RESPONSE (dB) -20 -30 -40 -50 -60 -70 -80 -90 0.1 1 10
0 -0.5 -1.0 TA = -40C POUT (dBm) -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 2.40 2.42 2.44 2.46 FREQUENCY (GHz) 2.48 TA = +85C TA = +25C
100
2.50
BASEBAND FREQUENCY (MHz)
14
______________________________________________________________________________________
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Typical Operating Characteristics (continued)
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
EVM vs. Tx OUTPUT POWER (MAX2832 ONLY)
MAX2831/32 toc36a
MAX2831/MAX2832
11g SPECTRAL MASK (MAX2832 ONLY)
-19 -29 -39 -49 dBm -59 -69 -79 dBm POUT = -2.17dBm EVM = 2.12%
MAX2831/32 toc37
Tx OUTPUT SPURS (MAX2832 ONLY)
-10 -20 2x VCO -30 -40 -50 -60 -70 -80 -90 -100 RF VCO
MAX2831/32 toc38
3.00 2.75 2.50 2.25 EVM (%) 2.00 1.75 1.50 1.25 1.00 -30 -24 -18 -12 -6 OUTPUT POWER (dBm) 0
-9
RBW = 1MHz 802.11g SIGNAL 3x VCO 4x VCO
-89 -99 -109 2387 2407 2427 2447 2467 2487 FREQUENCY (MHz)
-110 DC 26.5GHz
Tx EVM vs. POUT
VCCPA = 4.2V 7 6 EVM (%) 5 4 3 2 0 2 4 6 8 10 12 14 16 18 20 22 POUT (dBm) VCCPA = 3.3V VCCPA = 3.0V VCCPA = 2.7V
MAX2831/32 toc39a
PA SUPPLY CURRENT vs. POUT
MAX2831/32 toc40
Tx GAIN VARIATION vs. FREQUENCY (B6:B1 = 101001)
TA = -40C
MAX2831/32 toc41
8
280
PA SUPPLY CURRENT (mA)
250
2x RF
1dB/div
220
TA = +25C
190 VCCPA = 4.2V 160 VCCPA = 2.7V, 3.0V, 3.3V 0 2 4 6 8 10 12 14 16 18 20 22 24 POUT (dBm) 2.40
TA = +85C
130
2.42
2.44 2.46 FREQUENCY (GHz)
2.48
2.50
Tx OUTPUT POWER vs. FREQUENCY
MAX2831/32 toc42
11g SPECTRAL MASK
MAX2831/32 toc43
802.11g POUT vs. GAIN SETTING (UPPER GAIN CONTROL RANGE)
MAX2831/32 toc44
20 GAIN ADJUSTED TO ACHIEVE 5.6% EVM 19 POUT (dBm) TA = +25C
-9 -19 -29 -39 POUT = 18.64dBm EVM = 5.6%
22
20
18
-59 -69 -79
POUT (dBm) 2407 2427 2447 2467 2487
dBm
-49
18
16
17 TA = +85C 16 2.40 2.42 2.44 2.46 FREQUENCY (GHz) 2.48 2.50 TA = -40C
-89 -99 -109 2387
14
12 40 44 FREQUENCY (MHz) 48 52 56 GAIN SETTINGS 60 64
______________________________________________________________________________________
15
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Typical Operating Characteristics (continued)
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
POWER DETECTOR OVER FREQUENCY
MAX2831/32 toc45
POWER DETECTOR OVER SUPPLY VOLTAGE
MAX2831/32 toc46
POWER DETECTOR OVER TEMPERATURE
1.8 1.6 POWER DETECTOR (V) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 TA = -40C, +25C TA = +85C
MAX2831/32 toc47
2.0 1.8 1.6 POWER DETECTOR (V) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 fRF = 2.5GHz fRF = 2.4GHz
2.0 1.8 1.6 POWER DETECTOR (V) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 VCCPA = 3.3V, 4.2V VCCPA = 2.7V, 3.0V
2.0
6 8 10 12 14 16 18 20 22 OUTPUT POWER (dBm)
0
2
4
6 8 10 12 14 16 18 20 22 OUTPUT POWER (dBm)
0
2
4
6
8 10 12 14 16 18 20 22 POUT (dBm)
POWER-DETECTOR OUTPUT
MAX2831/32 toc48
PA OUTPUT ENVELOPE RESPONSE
MAX2831/32 toc49
PA OUTPUT POWER HISTORGRAM FOR 1.1V POWER DETECTOR OUTPUT
MEAN = 18.5dBm
MAX2831/32 toc50
12 10 8
300mV
20dB GAIN STEP
PA ENVELOPE
50mV
-50mV -300mV 1V POWER DETECTOR 0V 20dBm 0 -20dBm 100ns/div PA ENVELOPE TX I/Q INPUT
6 4 2 0
1s/div
0.1dB/div
PA OUTPUT RETURN LOSS vs. RF FREQUENCY
MAX2831/32 toc51
Tx OUTPUT SPURS
10 RF 0 -10 VCO 2x RF 2x VCO 3x RF 4x RF -20 -30
MAX2831/32 toc52
-10
RBW = 1MHz 802.11g SIGNAL
OUTPUT RETURN LOSS (dB)
-15
-20
-40 -50
-25
-60 -70 -80
-30 2300 2350 2400 2450 2500 RF FREQUENCY (MHz) 2550 2600
-90 DC 26.5GHz
16
______________________________________________________________________________________
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Typical Operating Characteristics (continued)
(MAX2831 EV kit, VCC_ = 2.8V, VCCPA = VCCTXPA = 3.3V, TA = +25C, fLO = 2.437GHz, fREF = 40MHz, SHDN = CS = high, RXHP = SCLK = DIN = low.)
LO FREQUENCY vs. VTUNE
MAX2831/32 toc53
MAX2831/MAX2832
LO PHASE NOISE vs. OFFSET FREQUENCY
-60 -70 PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 -140 10kHz/ div
MAX2831/32 toc54
CHANNEL SWITCHING FREQUENCY SETTLING (FROM 2500MHz TO 2400MHz)
50kHz
MAX2831/32 toc55
2600 2550 LO FREQUENCY (MHz) 2500 2450 2400 2350 2300
-50
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 VTUNE (V)
-150 0.001
-50kHz 0.01 0.1 1 OFFSET FREQUENCY (MHz) 10 0 250s
PLL SETTLING TIME FROM SHUTDOWN TO STANDBY MODE
50kHz
MAX2831/32 toc56
PLL SETTLING TIME FROM STANDBY TO Tx
50kHz
MAX2831/32 toc57
Rx TO Tx TURNAROUND PLL SETTLING TIME
25kHz
MAX2831/32 toc58
10kHz/ div
10kHz/ div
5kHz/ div
-50kHz 0 2ms
-50kHz 0 30s
-25kHz 0 50s
Tx-Rx TURNAROUND PLL SETTLING TIME
25kHz
MAX2831/32 toc59
CLOCK OUTPUT
MAX2831/32 toc60
CRYSTAL-OSCILLATOR OFFSET FREQUENCY vs. CRYSTAL-OSCILLATOR TUNING BITS
800 700 600 500 400 300 200 100 0 -100 -200 -300 -400 -500 -600 -700 -800 KYOCERA (CX-3225SB)
MAX2831/32 toc61
3V 5kHz/div 0V
-25kHz 0 50s 10ns/div
CRYSTAL OFFSET FREQUENCY (Hz)
fCLOCK = 40MHz CLOAD = 5pF
0 10 20 30 40 50 60 70 80 90 100110120130 CTUNE (DIGITAL BITS)
______________________________________________________________________________________
17
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Block Diagrams/Typical Operating Circuits
MODE CONTROL
TX INPUT
RX BASEBAND HPF CORNER FREQUENCY CONTROL
RX I OUTPUTS
VCCRXFL
TXBBQ-
VCCRXVGA
GNDTEST
VCCRXMX
TXBBQ+
RXBBI+
38 MUX
TXBBI+
48 VCCLNA GNDRXLNA 1 2 3 4 5 6 7 8 9 10
47
46
45
44
43
42
41
40
39
RXBBI37 36 35 MUX 34 33 32 31 RXBBQ+ RXBBQB4 BYPASS TUNE GNDVCO VCCVCO CTUNE XTAL VCCXTAL GNDCP VCCCP RX Q OUTPUTS RX/TX GAIN CONTROL
TXBBI-
MAX2831
RSSI
RXHP
RXTX
RX INPUT
RX/TX GAIN CONTROL
B6 RXRF+ RXRF-
TO RSSI MUX
90 IMUX QMUX 0 PLL AM DETECTOR
RX GAIN CONTROL
B7 VCCPA
30 29 28 27 26
TX OUTPUT
RX/TX GAIN CONTROL
B3 TXRF+ TXRF-
/
TEMP SENSOR TO RSSI MUX POWER DETECTOR TEMP SENSOR RSSI 13 14 SERIAL INTERFACE
CRYSTAL OSCILLATOR/ BUFFER
RX/TX GAIN CONTROL MODE CONTROL
B2 11 SHDN 12
RSSI MUX 15 16 17
/
19 20 21 22 23 24
25
18
B1
CLOCKOUT
VCCTXMX
VCCTXPA
RX/TX GAIN CONTROL
SERIAL INPUTS
REFERENCE CLOCK BUFFER OUTPUT
RX/TX GAIN CONTROL
NOTE: ALL GROUND (PINS 2, 26, AND 31) AND BYPASS CAPACITORS' GROUND REQUIRE THEIR OWN VIAS TO GROUND. DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND.
18
______________________________________________________________________________________
CPOUT
CS
SCLK
RSSI
DIN
VCCPLL
LD
B5
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Block Diagrams/Typical Operating Circuits (continued)
MAX2831/MAX2832
MODE CONTROL
TX INPUT
RX BASEBAND HPF CORNER FREQUENCY CONTROL
RX I OUTPUTS
VCCRXVGA
GNDTEST
VCCRXMX
VCCRXFL
TXBBQ+
TXBBQ-
RXBBI+
38 MUX
TXBBI+
48 VCCLNA GNDRXLNA 1 2 3 4 5 6
47
46
45
44
43
42
41
40
39
RXBBI37 36 35 MUX 34 33 32 31 RXBBQ+ RXBBQB4 BYPASS TUNE GNDVCO VCCVCO CTUNE XTAL VCCXTAL GNDCP VCCCP RX Q OUTPUTS RX/TX GAIN CONTROL
TXBBI-
MAX2832
RSSI
RXHP
RXTX
RX INPUT
RX/TX GAIN CONTROL
B6 RXRF+ RXRF-
TO RSSI MUX
90 0 PLL AM DETECTOR
RX GAIN CONTROL
B7 VCCPA
IMUX QMUX 7 8 9 10 11 SHDN 12
30 29 28 27 26
TX OUTPUT
RX/TX GAIN CONTROL
B3 TXRF+ TXRF-
/
TEMP SENSOR TO RSSI MUX
CRYSTAL OSCILLATOR/ BUFFER
RX/TX GAIN CONTROL MODE CONTROL
B2 TEMP SENSOR RSSI 13 14 RSSI MUX 15 16 17
SERIAL INTERFACE
/
19 20 21 22 23 24
25
18
CS
B1
CLOCKOUT
VCCTXMX
VCCTXPA
RX/TX GAIN CONTROL
SERIAL INPUTS
REFERENCE CLOCK BUFFER OUTPUT
RX/TX GAIN CONTROL
NOTE: ALL GROUND (PINS 2, 26, AND 31) AND BYPASS CAPACITORS' GROUND REQUIRE THEIR OWN VIAS TO GROUND. DO NOT CONNECT THEM TO THE EXPOSED PADDLE GROUND.
______________________________________________________________________________________
CPOUT
SCLK
RSSI
DIN
VCCPLL
LD
B5
19
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 NAME VCCLNA GNDRXLNA B6 RXRF+ RXRFB7 VCCPA B3 TXRF+ TXRFB2 SHDN VCCTXPA B5 CS RSSI VCCTXMX SCLK DIN VCCPLL CLOCKOUT LD B1 CPOUT VCCCP GNDCP VCCXTAL XTAL CTUNE VCCVCO GNDVCO TUNE BYPASS B4 LNA Supply Voltage LNA Ground Receiver and Transmitter Gain-Control Logic-Input Bit 6 LNA Differential Input. Input is internally AC-coupled and matched to 100 differential. Connect directly to a 2:1 balun. Receiver Gain-Control Logic-Input Bit 7 Supply Voltage for Second Stage of Power Amplifier Receiver and Transmitter Gain-Control Logic-Input Bit 3 Power-Amplifier Differential Output for the MAX2831. PA output must be AC-coupled. PA driver internally AC-coupled differential outputs and matched to 100 differential for the MAX2832. Connect directly to a 2:1 balun. Receiver and Transmitter Gain-Control Logic-Input Bit 2 Active-Low Shutdown and Standby Logic Input. See Table 31 for operating modes. Supply Voltage for First-Stage of PA and PA Driver Receiver and Transmitter Gain-Control Logic-Input Bit 5 Active-Low Chip-Select Logic Input of 3-Wire Serial Interface (See Figure 2) RSSI, PA Power Detector (MAX2831 Only) or Temperature-Sensor Multiplexed Analog Output Transmitter Upconverter Supply Voltage Serial-Clock Logic Input of 3-Wire Serial Interface (See Figure 2) Data Logic Input of 3-Wire Serial Interface (See Figure 2) PLL and Registers Supply Voltage. Connect to the supply voltage to retain the register settings. Reference Clock Buffer Output Lock-Detect Logic Output of Frequency Synthesizer. Output high indicates that the frequency synthesizer is locked. Output programmable as CMOS or open-drain output. (See Tables 16 and 20.) Receiver and Transmitter Gain-Control Logic-Input Bit 1 Charge-Pump Output. Connect the frequency synthesizer's loop filter between CPOUT and TUNE (see the Block Diagrams/Typical Operating Circuits). PLL Charge-Pump Supply Voltage Charge-Pump Circuit Ground Crystal Oscillator Supply Voltage Crystal or Reference Clock Input. AC-couple a crystal or a reference clock to this analog input. Connection for Crystal Oscillator Off-Chip Capacitors. When using an external reference clock input, leave CTUNE unconnected. VCO Supply Voltage VCO Ground VCO TUNE Input (see the Block Diagrams/Typical Operating Circuits) On-Chip VCO Regulator Output Bypass. Bypass with a 0.1F to 1F capacitor to GND. Do not connect other circuitry to this point. Receiver and Transmitter Gain-Control Logic-Input Bit 4 FUNCTION
20
______________________________________________________________________________________
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Pin Description (continued)
PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME RXBBQRXBBQ+ RXBBIRXBBI+ VCCRXVGA RXHP VCCRXFL TXBBQTXBBQ+ TXBBITXBBI+ VCCRXMX GNDTEST RXTX EP FUNCTION Receiver Baseband Q-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage and sideband detector outputs. Receiver Baseband I-Channel Differential Outputs. In TX calibration mode, these pins are the LO leakage and sideband detector outputs. Receiver VGA Supply Voltage Receiver Baseband AC-Coupling High-Pass Corner Frequency Control Logic Input Receiver Baseband Filter Supply Voltage Transmitter Baseband I-Channel Differential Inputs Transmitter Baseband Q-Channel Differential Inputs Receiver Downconverters Supply Voltage Connect to Ground RX/TX Mode Control Logic Input. See Table 31 for operating modes. Exposed Paddle. Connect to the ground plane with multiple vias for proper operation and heat
MAX2831/MAX2832
Detailed Description
The MAX2831/MAX2832 single-chip, low-power, direct conversion, zero-IF transceivers are designed to support 802.11g/b applications operating in the 2.4GHz to 2.5GHz band. The fully integrated transceivers include a receive path, transmit path, voltage-controlled oscillator (VCO), sigma-delta fractional-N synthesizer, crystal oscillator, RSSI, PA power detector (MAX2831), temperature sensor, Rx and Tx I/Q error-detection circuitry, basebandcontrol interface and linear power amplifier (MAX2831). The only additional components required to implement a complete radio front-end solution are a crystal, a pair of baluns, a BPF, a switch, and a small number of passive components (RCs, no inductors required).
LNA Input Matching The LNA features a differential input that is internally AC-coupled and internally matched to 100. Connect a 2:1 balun transformer directly to the RXRF+ (pin 4) and RXRF- (pin 5) ports to convert the differential 100 input impedance to a single-ended 50 input. Provide electrically symmetrical input traces from the LNA input to the balun to maintain IP2 performance and RF common-mode noise rejection. LNA Gain Control The LNA has three gain modes: max gain, max gain 16dB, and max gain - 33dB. The three LNA gain modes can be serially programmed through the SPITM interface by programming bits D6:D5 in Register 11 (A3:A0 = 1011) or programmed in parallel through the digital logic gain-control pins, B7 (pin 6) and B6 (pin 3). Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable programming through the SPI interface, or set bit D12 = 0 to enable parallel programming. See Table 1 for LNA gain-control settings.
Receiver
The fully integrated receiver achieves a noise figure of 2.6dB in high-gain mode, and an input compression point of -6dBm in low-gain mode, while consuming only 62mA of supply current. The receiver integrates an LNA and VGA with a 95dB digitally programmable gain control range, direct-conversion downconverters, I/Q baseband lowpass filters with programmable LPF corner frequencies, analog RSSI and integrated DC-offset correction circuitry. A logic-low on the RXTX input (pin 48) and a logic-high on the SHDN input (pin 12) enable the receiver.
Table 1. LNA Gain-Control Settings (Pins B7:B6 or Register A3:A0 = 1011, D6:D5)
B7 OR D6 1 1 0 B6 OR D5 1 0 X NAME High Medium Low DESCRIPTION Max gain Max gain - 16dB (typ) Max gain - 33dB (typ)
SPI is a trademark of Motorola, Inc. ______________________________________________________________________________________ 21
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Baseband Variable-Gain Amplifier The receiver baseband variable-gain amplifiers provide 62dB of gain control range programmable in 2dB steps. The VGA gain can be serially programmed through the SPI interface by setting bits D4:D0 in Register 11 (A3:A0 = 1011) or programmed in parallel through the digital logic gain-control pins, B5 (pin 14), B4 (pin 34), B3 (pin 8), B2 (pin 11), and B1 (pin 23). Set bit D12 = 1 in Register 8 (A3:A0 = 1000) to enable serial programming through the serial interface or set bit D12 = 0 to enable parallel programming through the external logic pins. See Table 2 for the gain-step value and Table 3 for baseband VGA gain-control settings. Receiver Baseband Lowpass Filter The receiver integrates lowpass filters that provide an upper -3dB corner frequency of 8.5MHz (nominal mode) with 50dB of attenuation at 20MHz, and 45ns of group delay ripple in the passband (10kHz to 8.5MHz). The upper -3dB corner frequency is tightly controlled on-chip and does not require user adjustment. However, provisions are made to allow fine tuning of the upper -3dB corner frequency. In addition, coarse frequency tuning allows the -3dB corner frequency to be set to 7.5MHz (11b mode), 8.5MHz (11g mode), 15MHz (turbo 1 mode), and 18MHz (turbo 2 mode) by programming bits D1:D0 in Register 8 (A3:A0 = 1000). See Table 4. The coarse corner frequency can be fine-tuned approximately 10% in 5% steps by programming bits D2:D0 in Register 7 (A3:A0 = 0111). See Table 5 for receiver LPF fine -3dB corner frequency adjustment. Baseband Highpass Filter and DC Offset Correction The receiver implements programmable AC and nearDC coupling of I/Q baseband signals. Temporary ACcoupling is used to quickly remove LO leakage and other DC offsets that could saturate the receiver outputs. When DC offsets have settled, near DC-coupling is enabled to avoid attenuation of the received signal. AC-coupling is set (-3dB highpass corner frequency of 600kHz) when a logic-high is applied to RXHP (pin 40). Near DC-coupling is set (-3dB highpass corner frequency of 100Hz nominal) when a logic-low is applied to RXHP. Bits D13:D12 in Register 7 (A3:A0 = 0111) allow the near DC-coupling -3B highpass corner frequency to be set to 100Hz (D13:D12 = 00), 4kHz (D13:D12 = X1), or 30kHz (D13:D12 = 10). See Table 6.
Table 4. Receiver LPF Coarse -3dB Corner Frequency Settings in Register (A3:A0 = 1000)
BITS (D1:D0) 00 01 10 11 -3dB CORNER FREQUENCY (MHz) 7.5 8.5 15 18 MODE 11b 11g Turbo 1 Turbo 2
Table 2. Receiver Baseband VGA GainStep Value (Pins B5:B1 or Register D4:D0, A3:A0 = 1011)
PIN/BIT B1/D0 B2/D1 B3/D2 B4/D3 B5/D4 GAIN STEP (dB) 2 4 8 16 32
Table 5. Receiver LPF Fine -3dB Corner Frequency Adjustment in Register (A3:A0 = 0111)
BITS (D2:D0) 000 001 010 011 100 % ADJUSTMENT RELATIVE TO COARSE SETTING 90 95 100 105 110
Table 3. Baseband VGA Gain-Control Settings in Receiver Gain-Control Register (Pin B5:B1 or Register D4:D0, A3:A0 = 1011)
B5:B1 OR D4:D0 11111 11110 11101 : 00000 GAIN Max Max - 2dB Max - 4dB : Min
Table 6. Receiver Highpass Filter -3dB Corner Frequency Programming
RXHP 1 0 0 0 A3:A0 = 0111, D13:D12 XX 00 X1 10 -3dB HIGHPASS CORNER FREQUENCY (Hz) 600k 100 (recommended) 4k 30k
X = Don't care.
22
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Receiver I/Q Baseband Outputs The differential outputs (RXBBI+, RXBBI-, RXBBQ+, RXBBQ-) of the baseband amplifiers have a differential output impedance of ~300, and are capable of driving differential loads up to 10k || 10pF. The outputs are internally biased to a common-mode voltage of 1.1V and are intended to be DC-coupled to the inphase (I) and quadrature (Q) analog-to-digital data converter inputs of the accompanying baseband IC. Additionally, the common-mode output voltage can be adjusted from 1.1V to 1.4V through programming bits D11:D10 in Register 15 (A3:A0 = 1111). Received Signal-Strength Indicator (RSSI) The RSSI output (pin 16) can be programmed to multiplex an analog output voltage proportional to the received signal strength, the PA output power (MAX2831), or the die temperature. Set bits D9:D8 = 00 in Register 8 (A3:A0 = 1000) to enable the RSSI output in receive mode (off in transmit mode). Set bit D10 = 1 to enables the RSSI output when RXHP = 1, and disable the RSSI output when RXHP = 0. Set bit D10 = 0 to enable the RSSI output independent of RXHP. See Table 7 for a summary of the RSSI output versus register programming and RXHP. The received signal strength indicator provides an analog voltage proportional to the log of the sum of the squares of the I and Q channels, measured after the receive baseband filters and before the variable-gain amplifiers. The RSSI analog output voltage is proportional to the RF input signal level and LNA gain state over a 60dB range, and is not dependent upon VGA gain. See the graph RX RSSI Output vs. Input Power in the Typical Operating Characteristics for further details. Register 8 (A3:A0 = 1000) and bit D5:D3 in Register 7 (A3:A0 = 0111). The -3dB corner-frequency is tightly controlled on-chip and does not require user adjustment. Additionally, provisions are made to fine tune the -3dB corner frequency through bits D5:D3 in the Filter Programming register (A3:A0 = 0111). See Tables 8 and 9.
MAX2831/MAX2832
Table 7. RSSI Pin Truth Table
INPUT CONDITIONS A3:A0 = 1000, D9:D8 X 00 01 10 00 01 10 A3:A0 = 1000, D10 0 0 0 0 1 1 1 RXHP 0 1 1 1 X X X RSSI OUTPUT No signal RSSI Temperature sensor Power detector (MAX2831) RSSI Temperature sensor Power detector (MAX2831)
X = Don't care.
Table 8. Transmitter LPF Coarse -3dB Corner Frequency Settings in Register (A3:A0 = 1000)
BITS (D1:D0) 00 01 10 11 -3dB CORNER FREQUENCY (MHz) 8 11 16.5 22.5 MODE 11b 11g Turbo 1 Turbo 2
Transmitter
The transmitter integrates baseband lowpass filters, direct-upconversion mixers, a VGA, a PA driver, and a linear RF PA with a power detector (MAX2831). A logic-high on the RXTX input (pin 48) and a logic-high on the SHDN input (pin 12) enable the transmitter. Transmitter I/Q Baseband Inputs The differential analog inputs of the transmitter baseband amplifier I/Q inputs (TXBBI+, TXBBI-, TXBBQ+, TXBBQ-) have a differential impedance of 20k || 1pF. The inputs require an input common-mode voltage of 0.9V to 1.3V, which is provided by the DC-coupled I and Q DAC outputs of the accompanying baseband IC. Transmitter Baseband Lowpass Filtering The transmitter integrates lowpass filters that can be tuned to -3dB corner frequencies of 8MHz (11b), 11MHz (11g), 16.5MHz (turbo 1 mode), and 22.5MHz (turbo 2 mode) through programming bits D1:D0 in
Table 9. Transmitter LPF Fine -3dB Corner Frequency Adjustment in Register (A3:A0 = 0111)
BITS (D5:D3) 000 001 010 011 100 101 101-111 % ADJUSTMENT RELATIVE TO COARSE SETTING 90 95 100 105 110 (11g) 115 Not used
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23
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Transmitter Variable-Gain Amplifier The variable-gain amplifier of the transmitter provides 31dB of gain control range programmable in 0.5dB steps over the top 8dB of the gain control range and in 1dB steps below that. The transmitter gain can be programmed serially through the SPI interface by setting bits D5:D0 in Register 12 (A3:A0 = 1100) or in parallel through the digital logic gain-control pins B6:B1 (pins 3, 6, 8, 11, 14, 23, and 34, respectively). Set bit D10 = 0 in Register 9 (A3:A0 = 1001) to enable parallel programming, and set bit D10 = 1 to enable programming through the 3-wire serial interface. See Table 10 for the transmitter VGA gain-control settings. Power-Amplifier Bias, Enable Delay and Output Matching (MAX2831) The MAX2831 integrates a 2-stage PA, providing +18.5dBm of output power at 5.6% EVM (54Mbps OFDM signal) in 802.11g mode while exceeding the 802.11g spectral mask requirements. The first and second stage PA bias currents are set through programming bits D2:D0 and bits D6:D3 in Register 10 (A3:A0 = 1010), respectively. An adjustable PA enable delay, relative to the transmitter enable (RXTX low-to-high transition), can be set from 200ns to 7s through programming bits D13:D10 in Register 10 (A3:A0 = 1010). The PA of the MAX2831 has a 100 differential output that is internally matched. The output has to be AC-coupled using two off-chip 1.5pF capacitors to a 100:50 balun. Provide electrically symmetrical traces from the PA output to the balun to present a balanced load and to reduce out-of-band spurs. Power Detector (MAX2831) The MAX2831 integrates a voltage-peak detector at the PA output and provides an analog voltage proportional to PA output power. See the Power Detector Over Frequency and Power Detector Over Supply Voltage graphs in the Typical Operating Characteristics. Set bits D9:D8 = 10 in Register 8 (A3:A0 = 1000) to multiplex the power-detector analog output voltage to the RSSI output (pin 16).
Table 10. Transmitter VGA Gain-Control Settings
NUMBER 63 62 61 : 49 48 47 46 45 44 : 5 4 3 2 1 0 D5:D0 Or B6:B1 111111 111110 111101 : 110001 110000 101111 101110 101101 101100 : 000101 000100 000011 000010 000001 000000 OUTPUT SIGNAL POWER Max Max - 0.5dB Max - 1.0dB : Max - 7dB Max - 7.5dB Max - 8dB Max - 8dB Max - 9dB Max - 9dB : Max - 29dB Max - 29dB Max - 30dB Max - 30dB Max - 31dB Max - 31dB
Synthesizer Programming
The MAX2831/MAX2832 integrate a 20-bit sigma-delta fractional-N synthesizer, allowing the device to achieve excellent phase-noise performance (0.9 RMS from 10kHz to 10MHz), fast PLL settling times, and an RF frequency step-size of 20Hz. The synthesizer includes a divide-by-1 or a divide-by-2 reference frequency divider, an 8-bit integer portion main divider with a divisor range programmable from 64 to 255, and a 20-bit fractional portion main-divider. Bit D2 in Register 5 (A3:A0 = 0101) sets the reference oscillator divider ratio to 1 or 2. Bits D7:D0 in Register 3 (A3:A0 = 0011) set the integer portion of the main divider. The 20-bit fractional portion of the main-divider is split between two registers. The 14 MSBs of the fractional portion are set in Register 4 (A3:A0 = 0100), and the 6 LSBs of the fractional portion of the main divider are set in Register 3 (A3:A0 = 0011). See Tables 11 and 12.
Power-Amplifier Driver Output Matching (MAX2832) The PA driver of the MAX2832 has a 100 differential output with on-chip AC-coupling capacitors. Provide electrically symmetrical traces to present a balanced load to the PA driver output to help maintain driver linearity and RF common-mode rejection.
24
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Calculating Integer and Fractional Divider Ratios The desired integer and fractional divider ratios can be calculated by dividing the RF frequency (fRF) by fCOMP. For nominal 802.11g/b operation, a 40MHz reference oscillator is divided by 2 to generate a 20MHz comparison frequency (fCOMP). The following method can be used when calculating divider ratios supporting various reference and comparison frequencies: LO Frequency Divider = fRF / fCOMP = 2437MHz / 20MHz = 121.85 Integer Divider = 121 (d) = 0111 1001 (binary) Fractional Divider = 0.85 x (220 - 1) = 891289 (decimal) = 1101 1001 1001 1001 1001 See Table 13 for integer and fractional divider ratios for 802.11g/b systems using a 20MHz comparison frequency.
MAX2831/MAX2832
Table 11. Integer Divider Register (A3:A0 = 0011)
BIT D13:D8 D7:D0 RECOMMENDED 00000 01111001 DESCRIPTION 6 LSBs of 20-Bit Fractional Portion of Main Divider 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.
Table 12. Fractional Divider Register (A3:A0 = 0100)
BIT D13:D0 RECOMMENDED 11011001100110 DESCRIPTION 14 MSBs of 20-Bit Fractional Portion of Main Divider
Table 13. IEEE 802.11g/b Divider-Ratio Programming Words
fRF (MHz) 2412 2417 2422 2427 2432 2437 2442 2447 2452 2457 2462 2467 2472 2484 (fRF / fCOMP) 120.6 120.85 121.1 121.35 121.6 121.85 122.1 122.35 122.6 122.85 123.1 123.35 123.6 124.2 INTEGER DIVIDER A3:A0 = 0011, D7:D0 0111 1000b 0111 1000b 0111 1001b 0111 1001b 0111 1001b 0111 1001b 0111 1010b 0111 1010b 0111 1010b 0111 1010b 0111 1011b 0111 1011b 0111 1011b 0111 1100b 2666h 3666h 0666h 1666h 2666h 3666h 0666h 1666h 2666h 3666h 0666h 1666h 2666h 0CCCh FRACTIONAL DIVIDER A3:A0 = 0100, D13:D0 A3:A0 = 0011, D13:D8 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 1Ah 33h
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25
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Crystal Oscillator The crystal oscillator has been optimized to work with low-cost crystals (e.g., Kyocera CX-3225SB). See Figure 1. The crystal oscillator frequency can be fine tuned through bits D6:D0 in Register 14 (A3:A0 = 1110), which control the value of C TUNE from 0.5pF to 15.4pF in 0.12pF steps. See the Crystal-Oscillator Offset Frequency vs. Crystal-Oscillator Tuning Bits graph in the Typical Operating Characteristics. The crystal oscillator can be used as a buffer for an external reference frequency source. In this case, the reference signal is ACcoupled to the XTAL pin, and capacitors C1 and C2 are not connected. When used as a buffer, the XTAL input pin has to be AC-coupled. The XTAL pin has an input impedance of 5k || 4pF, (set D6:D0 = 0000000 in Register 14 A3:A0 = 1110). Reference Clock Output Divider/Buffer The reference oscillator of the MAX2831/MAX2832 has a divider and a buffered output for routing the reference clock to the accompanying baseband IC. Bit D10 in Register 14 (A3:A0 = 1110) sets the buffer divider to divide by 1 or 2, independent of the divide ratio for the reference frequency provided to the PLL. Bit B9 in the same register enables or disables the reference buffer output. See the Clock Output waveform in the Typical Operating Characteristics. Loop Filter The PLL charge-pump output, CPOUT (pin 24), connects to an external third-order, lowpass RC loop-filter, which in turn connects to the voltage tuning input, TUNE (pin 32), of the VCO, completing the PLL loop. The charge-pump output sink and source current is 1mA, and the VCO tuning gain is 103MHz/V at 0.5V tune voltage and 86MHz/V at 2.2V tune voltage. The RC loop-filter values have been optimized for a loop bandwidth of 150kHz, to achieve the desired Tx/Rx turnaround settling time, while maintaining loop stability and good phase noise. Refer to the MAX2831 EV kit schematic for the recommended loop-filter component values. Keep the line from this pinto the tune input as short as possible to prevent spurious pickup. Lock-Detector Output The PLL features a logic lock-detect output. A logic-high indicates the PLL is locked, and a logic-low indicates the PLL is not locked. Bit D5 in Register 5 (A3:A0 = 0101) enables or disables the lock-detect output. Bit D12 in Register 1 (A3:A0 = 0001) configures the lockdetect output as a CMOS or open-drain output. In opendrain output mode, bit D9 in Register 5 (A3:A0 = 0101) enables or disables an internal 30k pullup resistor from the open-drain output.
MAX2831 MAX2832 XTAL C1 CTUNE
28
29 CTUNE 1.35k 5.9k
C2
FOR EXTERNAL REFERENCE CLOCK SET, C1 = C2 = OPEN
Figure 1. Crystal Oscillator Schematic
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA
Programmable Registers and 3-Wire SPI-Interface
The MAX2831/MAX2832 include 16 programmable, 18bit registers. The 14 most significant bits (MSBs) are used for register data. The 4 least significant bits (LSBs) of each register contain the register address. See Table 14 for a summary of the registers and recommended register settings. Register data is loaded through the 3-wire SPI/ MICROWIRETM-compatible serial interface. Data is
MICROWIRE is a trademark of National Semiconductor Corp.
shifted in MSB first and is framed by CS. When CS is low, the clock is active, and data is shifted with the rising edge of the clock. When CS transitions high, the shift register is latched into the register selected by the contents of the address bits. See Figure 2. Only the last 18 bits shifted into the device are retained in the shift register. No check is made on the number of clock pulses. For programming data words less than 14 bits long, only the required data bits and the address bits need to be shifted, resulting in faster Rx and Tx gain control where only the LSBs need to be programmed.
MAX2831/MAX2832
Table 14. Recommended Register Settings*
REGISTER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DATA D13 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 D12 0 1 1 0 1 0 0 1 0 0 1 0 0 0 0 0 D11 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 D10 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 D9 1 0 0 0 1 0 0 0 0 1 0 0 0 1 1 0 D8 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 1 D7 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 D6 1 0 0 1 1 0 1 0 0 0 0 1 1 0 0 1 D5 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 0 D4 0 1 0 1 0 0 0 0 0 1 0 1 0 1 1 0 D3 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 D2 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 D1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 0 D0 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 ADDRESS (A3:A0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TABLE 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
*The power-on register settings are not production tested. Recommended register settings must be loaded after VCC is supplied.
DIN
BIT 1
BIT 2
BIT 15
BIT 16
BIT 23
BIT 24
SCLK tCH tCL
tCS1
tDS CS tCSO tCSS tDH
tCSH
tCSW
Figure 2. 3-Wire SPI Serial-Interface Timing Diagram ______________________________________________________________________________________ 27
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Table 15. Register 0 (A3:A0 = 0000)
DATA BITS D13:D11 D10 D9:D0 RECOMMENDED 000 1 1101000000 Set to recommended value. Fractional-N PLL Mode Enable. Set 1 to enable the fractional-N PLL or set 0 to enable the integer-N PLL. Set to recommended value. DESCRIPTION
Table 16. Register 1 (A3:A0 = 0001)
DATA BITS D13 D12 D11:D0 RECOMMENDED 0 1 000110011010 Set to recommended value. Lock-Detector Output Select. Set to 1 for CMOS Output. Set to 0 for open-drain output. Bit D9 in register (A3:A0 = 0101) enables or disables an internal 30k pullup resistor in open-drain output mode. Set to recommended value. DESCRIPTION
Table 17. Register 2 (A3:A0 = 0010)
DATA BITS D13:D0 RECOMMENDED 00000001111001 Set to recommended value. DESCRIPTION
This register contains the 8-bit integer portion and 6 LSBs of the fractional portion of the divider ratio of the synthesizer.
Table 18. Register 3 (A3:A0 = 0011)
BIT D13:D8 D7:D0 RECOMMENDED 00000 01111001 DESCRIPTION 6 LSBs of 20-Bit Fractional Portion of Main Divider 8-Bit Integer Portion of Main Divider. Programmable from 64 to 255.
Table 19. Register 4 (A3:A0 = 0100)
BIT D13:D0 RECOMMENDED 11011001100110 DESCRIPTION 14 MSBs of 20-Bit Fractional Portion of Main Divider
Table 20. Register 5 (A3:A0 = 0101)
BIT D13:D10 D9 D8:D6 D5 D4:D3 D2 D1:D0 RECOMMENDED 0000 0 010 1 00 1 00 Set to recommended value. Lock-Detect Output Internal Pullup Resistor Enable. Set to 1 to enable internal 30k pullup resistor or set to 0 to disable the resistor. Only available when lock-detect, open-drain output is selected (A3:A0 = 0010, D12 = 1). Set to recommended value. Lock-Detect Output Enable. Set to 1 to enable the lock-detect output or set to 0 to disable the output. The output is high impedance when disabled. Set to recommended value. Reference Frequency Divider Ratio to PLL. Set to 0 to divide by 1. Set to 1 to divide by 2. Set to recommended value. DESCRIPTION
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Table 21. Register 6 (A3:A0 = 0110)
DATA BIT D13 D12:D11 D10:D7 D6 D5:D2 D1 D0 RECOMMENDED 0 00 0000 1 1000 0 0 Set to recommended value. Tx I/Q Calibration LO Leakage and Sideband Detector Gain-Control Bits. D12:D11 = 00: 9dB; 01 19dB; 10: 29dB; 11: 39dB. Set to recommended value. Power-Detector Enable in Tx Mode. Set to 1 to enable the power detector or set to 0 to disable the detector. Set to recommended value. Tx Calibration Mode. Set to 1 to place the device in Tx calibration mode or 0 to place the device in normal Tx mode when RXTX is set to 1 (see Table 31). Rx Calibration Mode. Set to 1 to place the device in Rx calibration mode or 0 to place the device in normal Rx mode when RXTX is set to 0 (see Table 31). DESCRIPTION
Table 22. Register 7 (A3:A0 = 0111)
BIT D13:D12 D11:D6 D5:D3 D2:D0 RECOMMENDED 01 000000 100 010 DESCRIPTION Receiver Highpass Corner Frequency Setting for RXHP = 0. Set to 00 for 100Hz, X1 for 4kHz, and 10 for 30kHz. Set to recommended value. Transmitter Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See Table 8. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment. Receiver Lowpass Filter Corner Frequency Fine Adjustment (Relative to Coarse Setting). See Table 5. Bits D1:D0 in A3:A0 = 1000 provide the lowpass filter corner coarse adjustment.
Table 23. Register 8 (A3:A0 = 1000)
BIT D13 D12 D11 D10 RECOMMENDED 1 0 0 0 Set to recommended value. Enable Receiver Gain Programming Through the Serial Interface. Set to 1 to enable programming through the 3-wire serial interface (D6:D0 in Register A3:A0 = 1011). Set to 0 to enable programming in parallel through external digital pins (B7:B1). Set to recommended value. RSSI Operating Mode. Set to 1 to enable RSSI output independent of RXHP. Set to 0 to disable RSSI output if RXHP = 0, and enable the RSSI output if RXHP = 1. RSSI, Power Detector or Temperature Sensor Output Select. Set to 00 to enable the RSSI output in receive mode. Set to 01 to enable the temperature sensor output in receive and transmit modes. Set to 10 to enable the power-detector output in transmit mode. See Table 7. Set to recommended value. Receiver and Transmitter Lowpass Filter Corner Frequency Coarse Adjustment. See Tables 4 and 7. DESCRIPTION
D9:D8 D7:D2 D1:D0
00 001000 01
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Table 24. Register 9 (A3:A0 = 1001)
BIT D13:D11 D10 D9:D0 RECOMMENDED 000 0 1110110101 Set to recommended value. Enable Transmitter Gain Programming Through the Serial or Parallel Interface. Set to 1 to enable programming through the 3-wire serial interface (D5:D0 in Register A3:A0 = 1011). Set to 0 to enable programming in parallel through external digital pins (B6:B1). Set to recommended value. DESCRIPTION
Table 25. Register 10 (A3:A0 = 1010)
BIT D13:D10 D9:D7 D6:D3 D2:D0 RECOMMENDED 0111 011 0100 100 DESCRIPTION Power-Amplifier Enable Delay. Sets a delay between RXTX low-to-high transition and internal PA enable. Programmable in 0.5s steps. D13:D10 = 0001 (0.2s) and D13:D10 = 1111 (7s). Set to recommended value. Second-Stage Power-Amplifier Bias Current Adjustment. Set to XXXX for 802.11g/b. First-Stage Power-Amplifier Bias Current Adjustment. Set to XXX for 802.11g/b.
Table 26. Register 11 (A3:A0 = 1011)
BIT D13:D7 D6:D5 D4:D0 RECOMMENDED 0000000 11 11111 Set to recommended value. LNA Gain Control. Set to 11 for high-gain mode. Set to 10 for medium-gain mode, reducing LNA gain by 16dB. Set to 0X for low-gain mode, reducing LNA gain by 33dB. Receiver VGA Control. Set D4:D0 = 00000 for minimum gain and D4:D0 = 11111 for maximum gain. DESCRIPTION
Table 27. Register 12 (A3:A0 = 1100)
BIT D13:D6 D5:D0 RECOMMENDED 00111010 010010 Set to recommended value. Transmitter VGA Gain Control. Set D5:D0 = 000000 for minimum gain, and set D5:D0 = 111111 for maximum gain. DESCRIPTION
Table 28. Register 13 (A3:A0 = 1101)
BIT D13:D10 D9:D6 D5:D0 RECOMMENDED 0011 1010 010010 Set to recommended value. Set to recommended value. Set to recommended value. DESCRIPTION
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Table 29. Register 14 (A3:A0 = 1110)
BIT D13:D11 D10 D9 D8:D7 D6:D0 RECOMMENDED 000 0 1 10 XXXXXXX Set to recommended value. Reference Clock Output Divider Ratio. Set 1 to divide by 2 or set 0 to divide by 1. Reference Clock Output Enable. Set 1 to enable the reference clock output or set 0 to disable. Set to recommended value. Crystal-Oscillator Fine Tune. Tunes crystal oscillator over 20ppm to within 1ppm. DESCRIPTION
X = Don't care.
Table 30. Register 15 (A3:A0 = 1111)
BIT D13:D12 D11:D10 D9:D0 RECOMMENDED 00 00 0101000101 Set to recommended value. Receiver I/Q Output Common-Mode Voltage Adjustment. Set D11:D10 = 00: 1.1V, 01: 1.2V, 10: 1.3V, 11: 1.45V. Set to recommended value. DESCRIPTION
Table 31. Operating Mode Table
LOGIC PINS MODE SHDN Shutdown Standby Rx Tx Rx Calibration Tx Calibration 0 0 1 1 1 1 RXTX 0 1 0 1 0 1 D1:D0 (A3:A0 = 0110) 00 00 X0 0X X1 1X Rx PATH Off Off On Off On (except LNA) Off Tx PATH Off Off Off On Upconverters On (except PA driver and PA) REGISTER SETTINGS CIRCUIT BLOCK STATES PLL, VCO, LO GEN, AUTO-TUNER Off On On On On On CALIBRATION SECTIONS ON None None None None Cal tone, RF phase shift, Tx filter AM detector, Rx I/Q buffers
X = Don't care.
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31
2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Modes of Operation
The modes of operation for the MAX2831/MAX2832 are shutdown, standby, transmit, receive, transmitter calibration, and receiver calibration. See Table 31 for a summary of the modes of operation. The logic-input pins, SHDN (pin 12) and RXTX (pin 48), control the various modes. Shutdown Mode The MAX2831/MAX2832 feature a low-power shutdown mode that disables all circuit blocks, except the serialinterface and internal registers, allowing the registers to be loaded and values maintained, as long as VCC is applied. Set SHDN and RXTX logic-low to place the device in shutdown mode. Standby Mode The standby mode is used to enable the frequency synthesizer block while the rest of the device is powered down. In this mode, the PLL, VCO, and LO generators are on, so that Tx or Rx modes can be quickly enabled from this mode. Set SHDN to a logic-low and RXTX to a logic-high to place the device in standby mode. Receive (Rx) Mode The complete receive signal path is enabled in this mode. Set SHDN to logic-high and RXTX to logic-low to place the device in Rx mode. Transmit (Tx) Mode The complete transmitter signal path is enabled in this mode. Set SHDN and RXTX to logic-high to place the device in Tx mode. Tx/Rx Calibration Mode The MAX2831/MAX2832 feature Rx/Tx calibration modes to detect I/Q imbalances and transmit LO leakage. In the Tx calibration mode, all Tx circuit blocks, except the PA driver and external PA, are powered on and active. The AM detector and receiver I and Q channel buffers are also on, along with multiplexers in the receiver side to route this AM detector's signal. In this mode, the LO leakage calibration is done only for the LO leakage signal that is present at the center frequency of the channel (i.e., in the middle of the OFDM or QPSK spectrum). The LO leakage calibration includes the effect of all DC offsets in the entire baseband paths of the I/Q modulator and direct leakage of the LO to the I/Q modulator output. The LO leakage and sideband detector output are taken at the receiver I and Q channel outputs during this calibration phase. During Tx LO leakage and I/Q imbalance calibration, a sine and cosine signal (f = fTONE) is input to the baseband I/Q Tx pins from the baseband IC. At the LO leakage and sideband-detector output, the LO leakage corresponds to the signal at fTONE and the sideband suppression corresponds to the signal at 2 x fTONE. The output power of these signals vary 1dB for 1dB of variation in the LO leakage and sideband suppression. To calibrate the Tx path, first set the power-detector gain to 9dB using D12:D11 in Register 5 (see Table 21). Adjust the DC offset of the baseband inputs to minimize the signal at fTONE (LO leakage). Then, adjust the baseband input relative magnitude and phase offsets to reduce the signal at 2 x fTONE. In Rx calibration mode, the calibrated Tx RF signal is internally routed to the Rx inputs. In this mode, the VCO/LO generator/PLL blocks are powered on and active except for the low-noise amplifier (LNA).
Applications Information
Layout Issues
The MAX2831 EV kit can be used as a starting point for layout. For best performance, take into consideration grounding and RF, baseband, and power-supply routing. Make connections from vias to the ground plane as short as possible. Do not connect the device ground pin to the exposed paddle ground. Keep the buffered clock output trace as short as possible. Do not share the trace with the RF input layer, especially on or inter-layer or back side of the board. On the high-impedance ports, keep traces short to minimize shunt capacitance. EV kit Gerber files can be requested at www.maxim-ic.com.
Power-Supply Layout
To minimize coupling between different sections of the IC, a star power-supply routing configuration with a large decoupling capacitor at a central VCC node is recommended. The VCC traces branch out from this node, each going to a separate VCC node in the circuit. Place a bypass capacitor as close as possible to each supply pin. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Do not share the capacitor ground vias with any other branch and the exposed paddle ground.
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
POWER SUPPLY ON POWER 3-WIRE SERIAL INTERFACE AVAILABLE
IREF
SHDN MAC
SHUTDOWN
MAX2831/MAX2832
RXTX
CS MAC SPI SCLK DIN
CS (SELECT) SCLK (CLOCK) DIN (DATA) SPI: CHANNEL FREQUENCY, PA BIAS, TRANSMITTER LINEARITY, RECEIVER RSSI OPERATION, CALIBRATION MODE, ETC. INTERNAL PA ENABLED 0 TO 7s RECEIVE MODE
(DRIVES POWER RAMP CONTROL) SHUTDOWN MODE STANDBY MODE
PA ENABLE TRANSMIT MODE
Figure 3. Timing Diagram
Pin Configuration
VCCRXVGA GNDTEST VCCRXMX VCCRXFL TXBBQ+ TXBBQRXBBI+
Chip Information
PROCESS: BiCMOS
TXBBI+
RXHP
RXTX
TOP VIEW
RXBBI-
TXBBI-
48 47 46 45 44 43 42 41 40 39 38 37 VCCLNA GNDRXLNA B6 RXRF+ RXRFB7 VCCPA B3 TXRF+ TXRFB2 SHDN 1 2 3 4 5 6 7 8 9 10 11 12
EP
Package Information
36 RXBBQ+ 35 RXBBQ34 B4 33 BYPASS 32 TUNE
+
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 48 TQFN PACKAGE CODE T4877+4 DOCUMENT NO. 21-0144
MAX2831 MAX2832
31 GNDVCO 30 VCCVCO 29 CTUNE 28 XTAL 27 VCCXTAL 26 GNDCP 25 VCCCP
13 14 15 16 17 18 19 20 21 22 23 24 VCCPLL RSSI CS CLOCKOUT LD B5 B1 VCCTXMX VCCTXPA CPOUT SCLK DIN
TQFN
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2.4GHz to 2.5GHz 802.11g/b RF Transceivers with Integrated PA MAX2831/MAX2832
Revision History
REVISION NUMBER 0 1 REVISION DATE 10/06 3/10 Initial release Removed MAX2832 future product reference and made minor corrections DESCRIPTION PAGES CHANGED -- 1, 2, 10, 18, 19, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
34 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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