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Austin Semiconductor, Inc. 1M x 1 SRAM
SRAM MEMORY ARRAY
AVAILABLE AS MILITARY SPECIFICATIONS
* SMD 5962-92316 * MIL-STD-883
MT5C1001 Limited Availability
PIN ASSIGNMENT (Top View)
SRAM
28-Pin DIP (C) (400 MIL)
A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19 Q WE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 D CE\
32-Pin LCC (EC) 32-Pin SOJ (DCJ)
A10 A11 A12 NC A13 A14 A15 NC A16 A17 A18 A19 NC Q WE\ Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc NC A9 A8 A7 A6 A5 A4 A3 NC A2 NC A1 A0 D CE\
FEATURES
* * * * * * * High Speed: 20, 25, 35, and 45 Battery Backup: 2V data retention Low power standby Single +5V (+10%) Power Supply Easy memory expansion with CE\ and OE\ options. All inputs and outputs are TTL compatible Three-state output
32-Pin Flat Pack (F)
OPTIONS
* Timing 20ns access 25ns access 35ns access 45ns access 55ns access 70ns access * Package(s) Ceramic DIP (400 mil) Ceramic LCC Ceramic Flatpack Ceramic SOJ
MARKING
-20 -25 -35 -45 -55* -70*
A10 A11 A12 NC A13 A14 A15 NC A16 A17 A18 A19 NC Q WE\ Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
Vcc NC A9 A8 A7 A6 A5 A4 A3 NC A2 NC A1 A0 D CE\
C EC F DCJ
No. 109 No. 207 No. 303 No. 501
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance silicon-gate CMOS technology. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. For flexibility in high-speed memory applications, ASI offers chip enable (CE\) and output enable (OE\) capability. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is accomplished when write enable (WE|) and CE\ inputs are both LOW. Reading is accomplished when WE\ remains HIGH while CE\ and OE\ go LOW. The devices offer a reduced power standby mode when disabled. This allows system designs to achieve low standby power requirements. The "L" version provides an approximate 50 percent reduction in CMOS standby current (ISBC2) over the standard version. All devices operation from a single +5V power supply and all inputs and outputs are fully TTL compatible.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
* Operating Temperature Ranges Industrial (-40oC to +85oC) IT Military (-55oC to +125oC) XT * 2V data retention/low power L
*Electrical characteristics identical to those provided for the 45ns access devices.
For more products and information please visit our web site at www.austinsemiconductor.com
MT5C1001 Rev. 2.1 06/05
1
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
FUNCTIONAL BLOCK DIAGRAM
VCC Vss
A6 A5
ROW DECODER
1,048,576-BIT MEMORY ARRAY 512 rows x 2048 columns
D
A3 A15 A14 A13 A8 A7
I/O CONTROL
A4
Q CE\
WE\ POWER DOWN
COLUMN DECODER
A2 A1 A16 A0 A17 A18 A19 A10 A9 A12 A11
TRUTH TABLE
MODE STANDBY READ WRITE CE\ H L L WE\ X H L OUTPUT HIGH-Z Q HIGH-Z POWER STANDBY ACTIVE ACTIVE
PIN ASSIGNMENTS
PIN A0-A19 WE\ CE\ D Q NC VCC VSS ASSIGNMENT Address Inputs Write Enable Chip Enable Data Input Data Output No Connection +5V Power Supply Ground
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Input Relative to Vss................................-.5V to +7V Voltage on Vcc Supply Relative to Vss...............................-.5V to +7V Voltage Applied to Q............................................................-.5V to +6V Storage Temperature......................................................-65oC to +150oC Power Dissipation..............................................................................1W Short Circuit Output Current.........................................................20mA Lead Temperature (soldering 10 seconds)....................................+260oC Junction Temperature..................................................................+175oC
MT5C1001 Limited Availability
SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage CONDITIONS SYMBOL VIH VIL ILI ILO VOH VOL MIN 2.2 -0.5 -5 -5 2.4 MAX VCC+0.5 0.8 5 5 0.4 UNITS V V A A V V 1 1 NOTES 1 1, 2
0V VIN VCC Output(s) disabled 0V < VOUT < VCC IOH = -4.0mA IOL = 8.0mA
PARAMETER Power Supply Current: Operating
CONDITIONS CE\ < VIL; VCC = MAX f = MAX = 1/tRC (MIN) Output Open CE\ > VIH; VCC = MAX f = MAX = 1/tRC (MIN) Output Open CE\ > VIH; All Other Inputs < VIH or > VIH, VCC = MAX f = 0 Hz CE\ > VCC -0.2V; VCC = MAX VIL < VSS +0.2V VIH > VCC -0.2V; f = 0 Hz "L" Version Only
SYM Icc
-20 125
MAX -25 -35 120 115
-45 110
UNITS NOTES mA 3
Power Supply Current: Standby
ISBT1
50
45
40
35
mA
ISBT2
25
25
25
25
mA
ISBC2 ISBC2
10 5
10 5
10 5
10 5
mA mA
CAPACITANCE
PARAMETER Input Capacitance (A3-A5, A15 -A17) Output Capactiance (Q) Input Capacitance: (All Other Inputs) TA = 25 C, f = 1MHz VCC = 5V
o
CONDITIONS
SYMBOL CI Co CI
MAXIMUM 10 8 8
UNITS pF pF pF
NOTES 4 4 4
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION READ CYCLE READ cycle time Address access time Chip Enable access time Output hold from address change Chip Enable to output in Low-Z Chip disable to output in High-Z Chip Enable to power-up time Chip disable to power-down time WRITE CYCLE WRITE cycle time Chip Enable to end of write Address valid to end of write Address setup time Address hold from end of write WRITE pulse width Data setup time Data hold time Write disable to output in Low-Z Write Enable to output in High-Z -20 -25 -35 -45 SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES tRC tAA tACE tOH tLZCE tHZCE tPU tPD tWC tCW tAW tAS tAH tWP tDS tDH tLZWE tHZWE 20 15 15 0 1 15 8 0 3 0 9 0 20 25 16 16 0 1 16 10 0 3 0 10 3 3 8 0 25 35 20 20 0 1 20 13 0 3 0 13 20 20 20 3 3 10 0 35 45 25 25 0 1 25 15 0 3 0 13 25 25 25 3 3 15 0 45 35 35 35 3 3 15 45 45 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 4, 6, 7 4, 6, 7 4, 6, 7 4 4
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
AC TEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V Input rise and fall times ....................................... 5ns Input timing reference levels ............................. 1.5V Output reference levels ..................................... 1.5V Output load .............................. See Figures 1 and 2
MT5C1001 Limited Availability
SRAM
167 Q 30pF VTH = 1.73V Q
167 5pF VTH = 1.73V
Fig. 1 Output Load Equivalent
Fig. 2 Output Load Equivalent
NOTES
1. 2. 3. All voltages referenced to VSS (GND). -3V for pulse width < 20ns ICC is dependent on output loading and cycle rates. The specified value applies with the outputs unloaded, and f = 1 Hz. t RC (MIN) This parameter is guaranteed but not tested. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. tLZCE, tLZWE, tLZOE, t HZCE, tHZOE and tHZWE are specified with CL = 5pF as in Fig. 2. Transition is measured 200mV typical from steady state voltage,
4. 5. 6.
allowing for actual tester RC time constant. At any given temperature and voltage condition, tHZCE is less than tLZCE, and tHZWE is less than tLZWE and tHZOE is less than tLZOE. 8. WE\ is HIGH for READ cycle. 9. Device is continuously selected. Chip enables and output enables are held in their active state. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip enable (CE\) and write enable (WE\) can initiate and terminate a WRITE cycle. 7.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION VCC for Retention Data CONDITIONS CE\ > (VCC - 0.2V) and VIN > (VCC - 0.2V) or < 0.2V SYMBOL VDR ICCDR VCC = 2V VCC = 3V
t
MIN 2
MAX -1.0 1.5
UNITS V mA mA ns
NOTES
Data Retention Current
Chip Deselect to Data Retention Time Operation Recovery Time
CDR
t
0 -t
4 4, 11
R
RC
ns
LOW Vcc DATA RETENTION WAVEFORM
VCC
t CDR DATA RETENTION MODE 4.5V VDR > 2V 4.5V tR V DR
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
432 4321 4321 1 4321
321 321 321 321
CE\
VIH VIL
4216 3326 32 87 421154321 332154321 87 421154321 321154321 87 3326 4876
987654321 4321 321 987654321 4321 987654321 987654321 321
DON'T CARE UNDEFINED
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
READ CYCLE NO. 1 8, 9
ttRC RC
ADDRESS
VALID
ttAA AA t OH tOH
DQ
PREVIOUS DATA VALID DATA VALID
READ CYCLE NO. 2
ttRC RC
CE\
7, 8, 10
ttLZCE LZCE tACE tACE
DQ
DATA VALID
HZCE tHZCE
t
t PU tPU
Icc
ttPD PD
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1 12 (Chip Enabled Controlled)
WC tWC
MT5C1001 Limited Availability
SRAM
t
ADDRESS
tAW tAW tAS tAS
CE\ WE\
tCW tCW t WP tWP1 tDS tDS
AH tAH
t
D Q
DATA VAILD
HIGH Z
WRITE CYCLE NO. 2 7, 12 (Write Enabled Controlled)
tWC tWC
ADDRESS
tAW tAW tCW tCW t AH tAH
CE\
tAS tAS
t WP tWP1 tDS t DH tDH
WE\
Q
HIGH-Z
DON'T CARE UNDEFINED
NOTE: Output enable (OE\) is inactive (HIGH).
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
65432111 1 422 3 65432111 1 422 3 65432111 1 422 3 65432111 1 422 3
432 4321 4321 1 4321
321 321 321
6 431113210987654321 254 436113210987654321 154 2 436113210987654321 154 2 431113210987654321 254 6
D
tHZWE
DATA VALID
321098765432109876543211 1 2 32109876543210987654321 1 32109876543210987654321
098765432121098765432109876543210987654321 098765432121098765432109876543210987654321
t DH tDH tLZWE
109876543210987654321 109876543210987654321 987654321 987654321 987654321 116543210987654321 27 1 2765432109876543 1 21 1 276543210987654321 2
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
MECHANICAL DEFINITIONS* ASI Case #109 (Package Designator C) SMD #5962-92316, Case Outline T
D
A Q Pin 1 b b1 E L e
NOTE
0o to 15o
c E1
SYMBOL A b b1 c D E E1 e L Q
SMD SPECIFICATIONS MIN MAX 0.075 0.095 0.016 0.020 0.040 0.060 0.008 0.012 1.386 1.414 0.385 0.405 0.390 0.410 0.100 BSC 0.125 0.175 0.040 0.060
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
MECHANICAL DEFINITIONS* ASI Case #207 (Package Designator EC) SMD# 5962-92316, Case Outline Y
A
D1
L1 D
L e E b1
b
b2
SYMBOL A b b1 b2 D D1 E e L L1
SMD SPECIFICATIONS MIN MAX 0.080 0.100 0.022 0.028 0.004 0.014 0.054 0.066 0.815 0.835 0.740 0.760 0.392 0.408 0.050 BSC 0.070 0.080 0.090 0.110
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
MECHANICAL DEFINITIONS* ASI Case #303 (Package Designator F) SMD #5962-92316, Case Outline Z
L E1
Pin 1 Index e 32 1
b D1
D
17
16
Bottom View Top View
c Q E
A
SYMBOL A b c D D1 E E1 e L Q
SMD SPECIFICATIONS MIN MAX 0.097 0.117 0.015 0.019 0.004 0.006 0.812 0.828 0.745 0.755 0.324 0.336 0.405 0.415 0.050 BSC 0.290 0.310 0.032 0.038
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
MECHANICAL DEFINITIONS* ASI Case #501 (Package Designator DCJ) SMD #5962-92316, Case Outline U
A
e
D D1
B1 b
E2 E1
E A2
SYMBOL A A2 B1 b D D1 E E1 E2 e
SMD SPECIFICATIONS MIN MAX 0.135 0.153 0.026 0.036 0.030 0.040 0.015 0.019 0.812 0.828 0.745 0.760 0.405 0.415 0.435 0.445 0.360 0.380 0.050 BSC
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
*All measurements are in inches.
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
ORDERING INFORMATION
EXAMPLE: MT5C1001C-20L/IT
Device Package Speed Options** Number Type ns MT5C1001 C -20 L MT5C1001 C -25 L MT5C1001 C -35 L MT5C1001 C -40 L MT5C1001 C -55 L MT5C1001 C -70 L Process /* /* /* /* /* /*
EXAMPLE: MT5C1001EC-45/XT
Device Package Speed Options** Process Number Type ns MT5C1001 EC -20 L /* MT5C1001 EC -25 L /* MT5C1001 EC -35 L /* MT5C1001 EC -40 L /* MT5C1001 EC -55 L /* MT5C1001 EC -70 L /*
EXAMPLE: MT5C1001F-25L/883C
Device Package Speed Options** ns Number Type MT5C1001 F -20 L MT5C1001 F -25 L MT5C1001 F -35 L MT5C1001 F -40 L MT5C1001 F -55 L MT5C1001 F -70 L Process /* /* /* /* /* /*
EXAMPLE: MT5C1001DCJ-70/XT
Device Package Speed Options** Process Number Type ns MT5C1001 DCJ -20 L /* MT5C1001 DCJ -25 L /* MT5C1001 DCJ -35 L /* MT5C1001 DCJ -40 L /* MT5C1001 DCJ -55 L /* MT5C1001 DCJ -70 L /*
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing ** OPTIONS L = 2V Data Retention/Low Power
-40oC to +85oC -55oC to +125oC -55oC to +125oC
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
Austin Semiconductor, Inc.
MT5C1001 Limited Availability
SRAM
ASI TO DSCC PART NUMBER CROSS REFERENCE*
ASI Package Designator C
ASI Part # MT5C1001C-20L/883C MT5C1001C-20/883C MT5C1001C-25L/883C MT5C1001C-25/883C MT5C1001C-35L/883C MT5C1001C-35/883C MT5C1001C-45L/883C MT5C1001C-45/883C SMD Part # 5962-9231608MTA 5962-9231604MTA 5962-9231607MTA 5962-9231603MTA 5962-9231606MTA 5962-9231602MTA 5962-9231605MTA 5962-9231601MTA
ASI Package Designator EC
ASI Part # MT5C1001EC-20L/883C MT5C1001EC-20/883C MT5C1001EC-25L/883C MT5C1001EC-25/883C MT5C1001EC-35L/883C MT5C1001EC-35/883C MT5C1001EC-45L/883C MT5C1001EC-45/883C SMD Part # 5962-9231608MYA 5962-9231604MYA 5962-9231607MYA 5962-9231603MYA 5962-9231606MYA 5962-9231602MYA 5962-9231605MYA 5962-9231601MYA
ASI Package Designator F
ASI Part # MT5C1001F-20L/883C MT5C1001F-20/883C MT5C1001F-25L/883C MT5C1001F-25/883C MT5C1001F-35L/883C MT5C1001F-35/883C MT5C1001F-45L/883C MT5C1001F-45/883C SMD Part # 5962-9231608MZA 5962-9231604MZA 5962-9231607MZA 5962-9231603MZA 5962-9231606MZA 5962-9231602MZA 5962-9231605MZA 5962-9231601MZA
ASI Package Designator DCJ
ASI Part # MT5C1001DCJ-20L/883C MT5C1001DCJ-20/883C MT5C1001DCJ-25L/883C MT5C1001DCJ-25/883C MT5C1001DCJ-35L/883C MT5C1001DCJ-35/883C MT5C1001DCJ-45L/883C MT5C1001DCJ-45/883C SMD Part # 5962-9231608MUA 5962-9231604MUA 5962-9231607MUA 5962-9231603MUA 5962-9231606MUA 5962-9231602MUA 5962-9231605MUA 5962-9231601MUA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
MT5C1001 Rev. 2.1 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
13

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