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19-0588; Rev 2; 7/09
KIT ATION EVALU E AILABL AV
12V, 8A 1.2MHz Step-Down Regulator
General Description Features
o o o o o o o o Internal 26m RDS(ON) MOSFETs Guaranteed 8A Output Current Adjustable Overcurrent Protection 1% Output Accuracy Over Temperature Operates from 4.5V to 14V Supply Adjustable Output from 0.6V to 0.85 x VIN Soft-Start Reduces Inrush Supply Current 250kHz to 1.2MHz Adjustable Switching or SYNC Input o Compatible with Ceramic, Polymer, and Electrolytic Output Capacitors o SYNCOUT Synchronizes 2nd Regulator 180 Out-of-Phase o 36-Pin, Lead-Free, 6mm x 6mm Thin QFN Package
MAX8654
The MAX8654 high-efficiency switching regulator delivers up to 8A of load current at output voltages from 0.6V to 0.85 x VIN. The IC operates from 4.5V to 14V, making it ideal for on-board point-of-load and postregulation applications, with total output error less than 1% over load, line, and temperature ranges. The MAX8654 is a fixed-frequency PWM mode regulator with a switching frequency range of 250kHz to 1.2MHz set by an external resistor or SYNC input. High-frequency operation allows for an all-ceramic-capacitor solution. A SYNCOUT output is provided to synchronize a second regulator switching 180 out-of-phase with the first to reduce the input ripple current and consequently reduce the required input capacitance. The high operating frequency minimizes the size of external components. The on-board low RDS(ON) dual-nMOS design keeps the board cooler at heavy loads while minimizing the critical inductances, making the layout a much simpler task with respect to the discrete solutions. The MAX8654 comes with a high-bandwidth (20MHz) voltage-error amplifier. The voltage-mode control architecture and the op-amp voltage-error amplifier permit a type 3 compensation scheme to be utilized to achieve maximum loop bandwidth, up to 20% of the switching frequency. High loop bandwidth achieves fast transient response resulting in less output capacitance required. The MAX8654 offers programmable soft-start to accommodate different types of output capacitors and reduce input inrush current. The MAX8654 is available in a 36lead thin QFN package.
Ordering Information
PART MAX8654ETX+ TEMP RANGE -40C to +85C PINPACKAGE 36 Thin QFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Typical Operating Circuit
INPUT 4.5V TO 14V IN VP VL VL VDL LX BST OUTPUT UP TO 8A
Applications
POL Power Supplies Servers DDR Memory RAID Power Supplies Network Power Supplies Graphic Cards
PGND
MAX8654
FREQ ILIM REFIN SS
FB
COMP SYNC VL
SYNCOUT IN
EN GND
PWRGD
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
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12V, 8A 1.2MHz Step-Down Regulator MAX8654
ABSOLUTE MAXIMUM RATINGS
SYNC, VL, PWRGD to GND...................................-0.3V to +4.5V SYNCOUT, COMP, SS, FB, REFIN, ILIM, FREQ to GND .....................-0.3V to (VVL + 0.3V) VDL to PGND............................................................-0.3V to +6V VP, IN, EN to GND..................................................-0.3V to +16V LX Current (Note 1: -12A to +12A) BST to LX .......................................................-0.3V to +6V BST to GND ............................................-0.3V to (VIN + 6V) PGND to GND .......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 36-Pin Thin QFN (derate 35.7mW/C above +70C) ...2857.1mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ..............................................+150C Storage Temperature Range .............................-65C to +150C Thermal Resistance Junction to Exposed Pad (EP)...........3C/W Lead Temperature (soldering, 10s) .................................+300C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed the IC's package power-dissipation limits.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VEN = VVP = 12V, VVDL = 5V, VVL = 3.3V, VSYNC = 0V, VFB = 0.5V, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER IN/VP IN and VP Voltage Range VDL Voltage Range VL Output Voltage VDL Output Voltage IN + VP Supply Current VL Supply Current VDL Supply Current IN + VP Shutdown Current VL Undervoltage Lockout Threshold VDL and IN Undervoltage Lockout Threshold BST BST Shutdown Supply Current PWM COMPARATOR PWM Comparator Propagation Delay COMP COMP Clamp Voltage, High COMP Slew Rate COMP Shutdown Resistance From COMP to GND, VEN = 0V 1.8 7 7 V V/s 5mV overdrive 16 ns VEN = 0V, VIN = VVP = VBST = VVDL = 5V 10 A VP = VDL IVL = 5mA IVDL = 50mA Not switching, no load fS = 500kHz, no load, L = 1.5H VIN = 12V VIN = 4.5V 4.5 4.5 3.3 5 2.7 45 28 1.6 25 10 3 2.8 3.8 2.9 4.4 20 3.1 mA mA A V V mA 14 5.5 V V V V CONDITIONS MIN TYP MAX UNITS
fS = 500kHz, VVL = 3.8V from separate supply fS = 500kHz, VVDL = 5.5V from separate supply VP = VIN = 13.2V, VEN = VVDL = VVL = unconnected LX starts/stops switching, 2s rising/falling edge deglitch LX starts/stops switching, 3s rising/falling edge deglitch VVL rising VVL falling VIN rising VIN falling
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12V, 8A 1.2MHz Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = VVP = 12V, VVDL = 5V, VVL = 3.3V, VSYNC = 0V, VFB = 0.5V, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER ERROR-AMPLIFIER FB Regulation Voltage Open-Loop Voltage Gain Error-Amplifier Unity-Gain Bandwidth Error-Amplifier Common-Mode Input Range Error-Amplifier Maximum Output Current FB Input Bias Current REFIN REFIN Input Bias Current REFIN Common-Mode Range LX (All Pins Combined) LX On-Resistance, High Side LX On-Resistance, Low Side LX Current-Limit Threshold RILIM Range LX Leakage Current LX Switching Frequency RFREQ Range LX Minimum On-Time Maximum RMS LX Output Current EN/SS EN Input Logic-Low Threshold EN Input Logic-High Threshold EN Input Current SS Charging Current REFIN Discharge Resistance Current-Limit Startup Blanking Restart Time VEN = 0V VEN = 14V VSS = 0.45V 6 7 8 500 110 900 10 1.2 1 0.6 V V A A Clock cycles Clock cycles (Note 1) 10.5 VEN = 0V VLX = 14V = VIN VLX = 0V, VIN = 14V RFREQ = 50k RFREQ = 100k 0.85 0.45 50 80 1 0.5 ILX = -180mA ILX = 180mA RILIM = 100k Sourcing Sinking 7 7 40 VBST - VLX = 5V 36 25 8 8 64 40 10 10 200 +50 -50 1.1 0.55 200 m m A k A MHz k ns A VREFIN = 0.6V 0 -60 1.5 nA V VCOMP = 1V VFB = 0.6V VP = VIN = 4.5V to 14V 1k from COMP to GND Parallel 10k, 160pF from COMP to GND 0 1 -35 0.594 0.6 95 20 1.5 0.606 V dB MHz V mA nA CONDITIONS MIN TYP MAX UNITS
MAX8654
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3
12V, 8A 1.2MHz Step-Down Regulator MAX8654
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = VVP = 12V, VVDL = 5V, VVL = 3.3V, VSYNC = 0V, VFB = 0.5V, TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.)
PARAMETER SYNC SYNC Capture Range SYNC Pulse Width SYNC Input Threshold SYNC Input Current SYNCOUT SYNCOUT Frequency Range SYNCOUT Phase Shift from SYNCIN or Internal Oscillator SYNCOUT Output Voltage THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis POWER-GOOD PWRGD Threshold Voltage PWRGD Falling Edge Deglitch PWRGD Output Voltage Low PWRGD Leakage Current IPWRGD = 4mA VPWRGD = 5.5V, VFB = 0.9V VFB falling, 30mV hysteresis, VREFIN > 540mV 90 48 0.03 0.01 0.06 1 % of REFIN Clock cycles V A When LX stops switching +165 20 C C Frequency = 1MHz ISYNCOUT = 1mA VOH VOL 0.25 170 VVL - 0.4 0.2 180 1.2 190 MHz Degrees V tLO tHI VIL VIH VSYNC = 0V or 3.6V IIL IIH 10 7 0.25 100 100 0.4 1.6 1.20 MHz ns V nA A CONDITIONS MIN TYP MAX UNITS
Note 1: All devices are production tested at TA = +25C. Limits over the operating range are guaranteed by design.
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12V, 8A 1.2MHz Step-Down Regulator MAX8654
Typical Operating Characteristics
(Typical values are: VIN = VVP = 12V, VOUT = 3.3V, RFREQ = 100k, and TA = +25C, circuit of Figure 1.)
EFFICIENCY vs. LOAD CURRENT
MAX8654 toc01
EFFICIENCY vs. LOAD CURRENT
MAX8654 toc02
EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 VOUT = 3.3V VOUT = 1.8V VOUT = 5V
MAX8654 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.1 VIN = 12V, VVDL = VVP = 5V, fS = 500kHz 1 OUTPUT CURRENT (A) VOUT = 1.8V VOUT = 5V VOUT = 3.3V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VIN = VVP = 5V, fS = 500kHz 0.1 1 OUTPUT CURRENT (A) VOUT = 1.8V VOUT = 3.3V
100
10 0 10
VIN = VVP = 12V, fS = 500kHz 0.1 1 OUTPUT CURRENT (A) 10
10
REFERENCE VOLTAGE vs. TEMPERATURE
MAX8654 toc04
SWITCHING FREQUENCY vs. INPUT VOLTAGE
MAX8654 toc05
SWITCHING FREQUENCY vs. RFREQ
MAX8654 toc06
0.610
1200 1000 800 600 400 200
1400 1200 1000 800 600 400 200 0
SWITCHING FREQUENCY (kHz)
0.605
0.600
0.595
0.590 -50 -25 0 25 50 75 100 125 TEMPERATURE (C)
0 5 7 9 11 13 15 INPUT VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
REFERENCE VOLTAGE (V)
0
50
100
150
200
250
RFREQ (k)
LOAD REGULATION
MAX8654 toc07
SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE
MAX8654 toc08
CURRENT LIMIT vs. OUTPUT VOLTAGE
8.8 8.6 CURRENT LIMIT (A) 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0
MAX8654 toc09
0 VOUT = 3.3V OUTPUT VOLTAGE CHANGE (%) -0.05 -0.10 -0.15 VOUT = 1.8V -0.20 -0.25 -0.30 -0.35 0 1 2 3 4 5 6 7 8 LOAD CURRENT (A)
10 SHUTDOWN SUPPLY CURRENT (A) 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12
9.0
14
1.5
.2.0
2.5
3.0
3.5
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
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12V, 8A 1.2MHz Step-Down Regulator MAX8654
Typical Operating Characteristics (continued)
(Typical values are: VIN = VVP = 12V, VOUT = 3.3V, RFREQ = 100k, and TA = +25C, circuit of Figure 1.)
EXPOSED PADDLE TEMPERATURE vs. LOAD CURRENT
EXPOSED PADDLE TEMPERATURE (C) 120 100 80 60 40 20 0 -20 -40 -60 0 TA = -40C, 200LFM 2 4 LOAD CURRENT (A) 6 8 -0.4 5 7 9 11 13 15 INPUT VOLTAGE (V) TA = +25C, 200LFM TA = -40C, NO AIR FLOW TA = +25C, NO AIR FLOW TA = +85C, 200LFM TA = +85C, NO AIR FLOW
MAX8654 toc10
LINE REGULATION
MAX8654 toc11
140
0.2 OUTPUT VOLTAGE CHANGE (%) 0.1 0 -0.1 -0.2 ILOAD = 6A -0.3 ILOAD = 0A ILOAD = 3A
SHORT-CIRCUIT RESPONSE
MAX8654 toc12
RMS INPUT CURRENT DURING OUTPUT SHORT CIRCUIT
0.45 RMS INPUT CURRENT (A) 2V/div 0V 0.40 0.35 0.30 0.25 0.20 0.15 0.10 CSS = 22,000pF CSS = 10,000pF VOUT = 3.3V CSS = 1000pF
MAX8654 toc13
CSS = 1000pF VOUT
0.50
IOUT
5A/div 0
IIN 400s/div
1A/div 0
0.05 0 5 7 9 INPUT VOLTAGE (V) 11 13
RMS OUTPUT CURRENT DURING OUTPUT SHORT CIRCUIT
MAX8654 toc14
OPEN-LOOP FREQUENCY RESPONSE
40 GAIN (dB) 20 0 -20 -40 IOUT = 6A 0.1 1 10 100 1000 106.57946 kHz CPI
MAX8654 toc15
4.0 3.5 RMS OUTPUT CURRENT (A) 3.0 2.5 2.0 1.5 1.0 5
VOUT = 3.3V
CSS = 22,000pF
PHASE (DEG)
CSS = 1000pF
CSS = 10,000pF
166.6 83.3 0 -83.3 -166.6 0.1 1 10 FREQUENCY (kHz) 106.57946 kHz CPI 100 1000
7
9 INPUT VOLTAGE (V)
11
13
6
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12V, 8A 1.2MHz Step-Down Regulator
Typical Operating Characteristics (continued)
(Typical values are: VIN = VVP = 12V, VOUT = 3.3V, RFREQ = 100k, and TA = +25C, circuit of Figure 1.)
SOFT-START TIME vs. CSS
9 SOFT-START TIME (ms) VOUT AC-COUPLED 100mV/div 8 7 6 5 4 3 2 0A 20s/div 1 0 0 0.025 0.050 0.075 CSS (F) 0.100 0.125 0.150
MAX8654 toc17 MAX8654 toc16
MAX8654
LOAD TRANSIENT
10
IOUT 2A/div
STARTUP INTO A 0.5 LOAD
MAX8654 toc18
10V/div VEN 0V IIN 2A/div 0 2V/div VOUT 0V VPWRGD 200s/div 2V/div 0V
SOFT-START WITH REFIN INTO A 0.5 LOAD
MAX8654 toc19
SYNCHRONIZED OPERATION (NO LOAD)
MAX8654 toc20
VREFIN
500mV/div 0V 2A/div 10mV/div VLX1 0V VLX2 ILX1 2A/div 2V/div 0V 40s/div ILX2 400ns/div 2A/div 10V/div 0V
IIN 0 2V/div VOUT 0V VPWRGD
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12V, 8A 1.2MHz Step-Down Regulator MAX8654
Pin Description
PIN 1, 2, 3, 34, 35, 36 4 5-8 9 10 11 12 13, 32 14 NAME PGND VDL IN VP VL ILIM FREQ GND REFIN FUNCTION Power Ground. All PGND pins are internally connected. Connect all PGND pins externally to the power ground plane. 5V LDO Output. VDL supplies the gate-drive current to the internal MOSFETS, and charges the BST capacitor. VDL requires at least a 2.2F ceramic bypass capacitor to PGND. Power-Supply Input. Input supply range is from 4.5V to 14V. Bypass with two 10F and a 0.1F ceramic capacitors to PGND. See Figure 1. Input of the Internal 5V LDO Regulator. Connect to IN if a 5V supply is not available. Connect to an external 5V supply to disable the internal 5V regulator. 3.3V LDO for Internal Chip Supply. Bypass with a 1F ceramic capacitor to GND. Current-Limit Adjust. Connect a resistor, RILIM, from ILIM to GND. IILIM = 1V / RILIM. IILIM determines the LX current-limit trip point. See the Current Limit section for more details. Oscillator Frequency Selection. Connect a resistor from FREQ to GND to set the internal oscillator frequency. See the Frequency Select (FREQ) section for more details. Analog Circuit Ground External Reference Input. Connect to an external reference. FB regulates to the voltage applied to REFIN. Connect REFIN to SS to use the internal 0.6V reference. REFIN is internally pulled to GND when the IC is in shutdown mode. Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. See the Soft-Start and REFIN section for details. Regulator Compensation. Connect the necessary compensation network from COMP to FB. COMP is internally pulled to GND when the IC is in shutdown mode. Feedback Input. Connect to the center tap of an external resistor-divider from the output to GND to set the output voltage. See the Compensation Design section for more details. Power-Good Output. Open-drain output that is high impedance when VFB 90% of VREFIN and VREFIN > 540mV. PWRGD is internally pulled low when the IC is in shutdown mode, or when VVDL, VIN, or VVL is below the UVLO threshold, or the IC is in thermal shutdown. Oscillator Output. The SYNCOUT output is 180 out-of-phase from the internal oscillator to facilitate running a second regulator out-of-phase to reduce input ripple. Synchronization Input. Synchronize to an external clock with a frequency of 250kHz to 1.2MHz. Connect SYNC to GND to disable the synchronization function. High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.22F ceramic capacitor. Inductor Connection. All LX pins are internally connected together. Connect all LX pins to the switched side of the inductor. LX is high impedance when the IC is in shutdown mode. Not Internally Connected Enable Input. Logic input to enable/disable the MAX8654. Drive EN high to enable the IC. Drive EN low to place the IC in a low-power shutdown mode. Exposed Pad. Connect to a large PGND ground plane to optimize thermal performance. EP is internally connected to GND and PGND.
15 16 17
SS COMP FB
18
PWRGD
19 20 21 22-29 30, 33 31 --
SYNCOUT SYNC BST LX N.C. EN EP
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12V, 8A 1.2MHz Step-Down Regulator MAX8654
Block Diagram
VL
EN
SHUTDOWN CONTROL
UVLO CIRCUITRY CURRENT-LIMIT COMPARATOR
VL REG
VDL REG
MAX8654
VP
ILIM ILIM THRESHOLD LX BST
BIAS GENERATOR
VOLTAGE REFERENCE
BST CAPACITOR CHARGING SWITCH
IN
SS
SOFT-START CONTROL LOGIC LX LX
THERMAL SHUTDOWN
REFIN FB COMP
ERROR AMPLIFIER
PWM COMPARATOR
PGND VDL
1VP-P COMP LOW DETECTOR FREQ SYNC SYNCOUT SHDN 90% REFIN REFIN 0.54V GND PWRGD
OSCILLATOR FB
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9
12V, 8A 1.2MHz Step-Down Regulator MAX8654
INPUT 4.5V TO 14V 10F 10F 0.1F IN VP BST 0.22F 1.0H
OUTPUT 3.3V, 8A 1nF
MAX8654
VL VL 1F 2.2F VDL
LX 2 x 22F PGND 4.99k 100
FB FREQ ILIM 100k 75k 0.022F IN REFIN SS SYNC VL SYNCOUT 20k EN GND PWRGD 10nF COMP 22pF 3.57k 1.1k
Figure 1. Typical Application Circuit, 3.3V, 8A, 500kHz
Detailed Description
The MAX8654 high-efficiency, voltage-mode switching regulator is capable of delivering up to 8A of output current. The MAX8654 provides output voltages from 0.6V to 0.85 x VIN from 4.5V to 14V input supplies, making them ideal for on-board point-of-load applications. The output voltage accuracy is better than 1% over temperature. The MAX8654 allows for all ceramic-capacitor designs and faster transient responses. The device is available in a 6mm x 6mm 36-pin thin QFN-EP package. The SYNCOUT function allows end users to operate two MAX8654s at the same switching frequency with 180 out-of-phase operation to minimize the input ripple current, consequently reducing the input capacitance requirements. The REFIN function makes the MAX8654
an ideal candidate for DDR and tracking power supplies. Using internal low RDS(ON) n-channel MOSFETs for both high- and low-side switches maintains high efficiency at both heavy load and high switching frequencies. The MAX8654 uses voltage-mode control architecture with a high-bandwidth (20MHz) error amplifier. The voltage-mode control architecture allows up to 1.2MHz switching, reducing board area. The op-amp voltage error amplifier works with type 3 compensation to fully utilize the bandwidth of the high-frequency switching to obtain fast transient response. Adjustable soft-start time provides flexibility to minimize input startup inrush current. The open-drain power-good (PWRGD) output goes high impedance when the output reaches 90% of its regulation point.
10
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12V, 8A 1.2MHz Step-Down Regulator
Controller Function
The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the PWM comparator and generates the driver signals for both high-side and low-side MOSFETs. The break-before-make logic and the timing for charging the bootstrap capacitors are calculated by the controller logic block. The error signal from the voltage-error amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator, and thus the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the VCOMP signal or when the currentlimit threshold is exceeded. The low-side switch is then turned on for the remainder of the oscillator cycle.
Soft-Start and REFIN
The MAX8654 utilizes an adjustable soft-start function to limit inrush current during startup. An 8A (typ) current source charges an external capacitor connected to SS to increase the capacitor voltage in a controlled manner. The soft-start time is adjusted by the value of the external capacitor from SS to GND. The required capacitance value is determined as: C= 8A x t SS 0.6V
MAX8654
Current Limit
The MAX8654 adjustable current limit is set by a resistor, RILIM, connected from ILIM to GND. The current through RILIM determines the LX current-limit trip point: RILIM (k) = 800 / ILXLIM (A) where ILXLIM is the LX current-limit threshold. The valid RILIM range is 40k to 200k. RILIM of 100k sets a typical peak current limit of 8A, sourcing or sinking at LX. When current flowing out of LX exceeds this limit, the high-side MOSFET turns off and the synchronous rectifier turns on. The synchronous rectifier remains on until the inductor current falls below the low-side current limit. This lowers the duty cycle and causes the output voltage to droop until the current limit is no longer exceeded. When the negative current limit is exceeded, the device turns off the synchronous rectifier, forcing the inductor current to flow through the high-side MOSFET body diode, back to the input, until the beginning of the next cycle, or until the inductor current drops to zero. The MAX8654 uses a hiccup mode to prevent overheating during short-circuit output conditions. The device enters hiccup mode when VFB drops below 420mV for more than 12s, pulling COMP and REFIN low. The IC turns off for 900 clock cycles and then enters soft-start for 110 clock cycles. If the short-circuit condition remains, the IC shuts down for another 512 clock cycles. The IC repeats this behavior until the short-circuit condition is removed.
where tSS is the required soft-start time in seconds. The MAX8654 also features an external reference input (REFIN). The IC regulates FB to the voltage applied to REFIN. The internal soft-start is not available when using an external reference. A method of soft-start when using an external reference is shown in Figure 2. When using an external reference, in order to avoid current limit during soft-start, care should be taken to ensure the following condition: COUT x dVREFIN I + IOUT < ILXLIM - P-P 2 dt
where IOUT is the maximum output current, COUT is the output capacitance, and IP-P is the peak-to-peak inductor ripple current. Connect REFIN to SS to use the internal 0.6V reference.
R1 REFIN
R2
C
MAX8654
Figure 2. Typical Soft-Start Implementation with External Reference
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11
12V, 8A 1.2MHz Step-Down Regulator MAX8654
Undervoltage Lockout (UVLO)
The UVLO circuitry inhibits switching when VIN or VVDL is below 4.20V (typ) or VVL is below 3V. Once these voltages are above the thresholds, UVLO clears and the soft-start function activates; 100mV of hysteresis is built in for glitch immunity.
Shutdown Mode
Drive EN to GND to shut down the IC and reduce quiescent current to 10A (typ). During shutdown, the outputs of the MAX8654 are high impedance. Drive EN high to enable the MAX8654.
Thermal Protection
Thermal-overload protection limits total power dissipation in the device. When the junction temperature exceeds T J = +165C, a thermal sensor forces the device into shutdown, allowing the die to cool. The thermal sensor turns the device on again after the junction temperature cools by 20C, causing a pulsed output during continuous overload conditions. The soft-start sequence begins after a thermal-shutdown condition.
High-Side MOSFET Driver Supply (BST)
The gate-drive voltage for the high-side, n-channel switch is generated by a flying capacitor boost circuit. The capacitor between BST and LX is charged from the VDL supply while the low-side MOSFET is on. When the low-side MOSFET is switched off, the stored voltage of the capacitor is stacked above LX to provide the necessary turn-on voltage for the high-side internal MOSFET.
Frequency Select (FREQ)
The switching frequency in fixed-frequency PWM operation is resistor programmable from 250kHz to 1.2MHz. Set the switching frequency of the IC with a resistor (RFREQ) from FREQ to GND. RFREQ is calculated as: 1 RFREQ = 52.63 x - 0.05 k fS where fS is the desired switching frequency in MHz.
Applications Information
VL and VDL Decoupling
To decrease the noise effects due to the high switching frequency and maximize the output accuracy of the MAX8654, decouple VDL with a minimum of 2.2F ceramic capacitor from VDL to PGND. Also, decouple VL with a 1F ceramic capacitor from VL to GND. Place these capacitors as close to the respective pins as possible.
Inductor Selection
Choose an inductor with the following equation: L= VOUT x (VIN - VOUT ) fS x VIN x LIR x IOUT(MAX)
SYNC Function (SYNC, SYNCOUT)
The MAX8654 features a SYNC function that allows the switching frequency to be synchronized to any external clock frequency that is higher than the internal clock frequency. Drive SYNC with a square wave at the desired synchronization frequency. A rising edge on SYNC triggers the internal SYNC circuitry. Connect SYNC to GND to disable the function and operate with the internal oscillator. The SYNCOUT output generates a clock signal that is 180 out-of-phase with its internal oscillator, or the signal applied to SYNC. This allows for another MAX8654 to be synchronized 180 out-of-phase to reduce the input ripple current.
Power-Good Output (PWRGD)
PWRGD is an open-drain output that goes high impedance once the soft-start ramp has concluded, provided VREFIN is above 0.54V and VFB is greater than 90% of VREFIN. PWRGD pulls low when VFB is less than 90% of V REFIN and V REFIN is less than 0.54V for 48 clock cycles. PWRGD is low during shutdown, when pulled up to VVL.
where LIR is the ratio of the inductor ripple current to average continuous current at the minimum duty cycle. Choose LIR between 20% to 40% for best performance and stability. Use a low-loss inductor with the lowest possible DC resistance that fits in the allotted dimensions. Powered iron-ferrite core types are often the best choice for performance. With any core material, the core must be large enough not to saturate at the peak inductor current (IPEAK). Calculate IPEAK as follows: IPEAK = (1 + LIR 2 ) x IOUT(MAX)
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12V, 8A 1.2MHz Step-Down Regulator
Output Capacitor Selection
The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor's ESR, and the voltage drop due to the capacitor's ESL. Calculate the output voltage ripple due to the output capacitance, ESR, and ESL as: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: VRIPPLE(C) = IP-P 8 x COUT x fS
Input Capacitor Selection
The input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the IC. The total input capacitance must be equal to or greater than the value given by the following equation to keep the input ripple voltage within specifications and minimize the high-frequency ripple current being fed back to the input source: CIN _ MIN = D x TS x IOUT VIN _ RIPPLE
MAX8654
VRIPPLE(ESR) = IP-P x ESR I VRIPPLE(ESL) = P-P x ESL t ON The peak-to-peak inductor ripple current (IP-P) is: V - VOUT VOUT IP-P = IN x fS x L VIN Use these equations for initial capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output voltage ripple. Since the inductor ripple current is a factor of the inductor value, the output voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The low ESL and ESR of ceramic capacitors make ripple voltages negligible. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short time, the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for more details.
where VIN_RIPPLE is the maximum allowed input ripple voltage across the input capacitors and is recommended to be less than 2% of the minimum input voltage. D is the duty cycle (VOUT / VIN) and TS is 1 / fS (switching frequency). The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source but are instead shunted through the input capacitor. High source impedance requires high input capacitance. The input capacitor must meet the ripple-current requirement imposed by the switching currents. The RMS input ripple current is given by: IRIPPLE = ILOAD x VOUT x (VIN - VOUT ) VIN
where IRIPPLE is the input RMS ripple current.
Compensation Design
The power-transfer function consists of one double pole and one zero. The double pole is introduced by the output filtering inductor L and the output filtering capacitor CO. The ESR of the output filtering capacitor determines the zero. The double pole and zero frequencies are given as follows: 1 fP1_ LC = fP2 _ LC = R + ESR ) 2 x L x C O x ( O RO + RL fZ _ ESR = 1 2 x ESR x CO
where RL is equal to the sum of the output inductor's DCR and the internal switch resistance, RDS(ON). RO is the output load resistance, which is equal to the rated
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13
12V, 8A 1.2MHz Step-Down Regulator MAX8654
output voltage divided by the rated output current. ESR is the total equivalent series resistance (ESR) of the output filtering capacitor. If there is more than one output capacitor of the same type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single output capacitor divided by the total number of output capacitors. The high-switching frequency range of the MAX8654 allows the use of ceramic-output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher than the unity-gain crossover frequency, fC, and the zero cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40dB and a phase shift of 180 per decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth, closed-loop system. Therefore, use type 3 compensation as shown in Figure 3. Type 3 compensation possesses three poles and two zeros with the first pole, fP1_EA, located at zero frequency (DC). Locations of other poles and zeros of the type 3 compensation are given by: 1 2 x R1 x C1 1 fZ2 _ EA = 2 x R3 x C3 1 fP3 _ EA = 2 x R1 x C2 fZ1_ EA = fP2 _ EA = 1 2 x R2 x C3
L LX VOUT COUT R3 R2 C3 FB R1 COMP R4 C2 C1
MAX8654
Figure 3. Type 3 Compensation Network
The zero-cross frequency of the closed loop, fC, should be less than 20% of the switching frequency, fS. Higher zero-cross frequency results in faster transient response. It is recommended that the zero-cross frequency of the closed loop should be chosen between 10% and 20% of the switching frequency. Once fC is chosen, C1 is calculated from the following equation: 1.5625 x VIN C1 = R 2 x x R3 x (1 + L ) x fC RO Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type 3 compensation less than the LC double-pole frequency in order to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency. Hence: R1 = 1 x 0.8 x C1 1 x 0.8 x R 3 L x CO x (RO + ESR) RL + RO L x CO x (RO + ESR) RL + RO
The above equations are based on the assumptions that C1>>C2, and R3>>R2, which are true in most applications. Placements of these poles and zeros are determined by the frequencies of the double pole and ESR zero of the power-transfer function. It is also a function of the desired closed-loop bandwidth. The following section outlines the step-by-step design procedure to calculate the required compensation components for the MAX8654. Begin by setting the desired output voltage. The output voltage is set using a resistor-divider from the output to GND with FB at the center tap (R3 and R4 in Figure 3). Calculate R4 as: 0.6 x R3 R4 = VOUT - 0.6
C3 =
Set the second compensation pole, fP2_EA, at fZ_ESR yields: R2 = CO x ESR C3
Set the third compensation pole at the switching frequency. Calculate C2 as follows: 1 C2 = x R1 x fS x 2
14
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12V, 8A 1.2MHz Step-Down Regulator
The above equations provide accurate compensation when the zero-cross frequency is significantly higher than the double-pole frequency. When the zero-cross frequency is near the double-pole frequency, the actual zero-cross frequency is higher than the calculated frequency. In this case, lowering the value of R1 reduces the zero-cross frequency. Also, set the third pole of the type 3 compensation close to the switching frequency if the zero-cross frequency is above 200kHz to boost the phase margin. Note that the value of R4 can be altered to make the values of the compensation components practical. The recommended range for R3 is 2k to 10k. 1) Connect input and output capacitors, VVP and VVDL capacitors to the power ground plane; connect all other capacitors to the signal ground plane. 2) Place capacitors on VVP, VIN, VVL, VVDL, and SS as close as possible to the IC and its corresponding pin using direct traces. Keep power ground plane (connected to PGND) and signal ground plane (connected to GND) separate. 3) Keep the high-current paths as short and wide as possible. Keep the path of switching current short and minimize the loop area formed by LX, the output capacitors, and the input capacitors. 4) Connect IN, LX, and PGND separately to a large copper area to help cool the IC to further improve efficiency and long-term reliability. 5) Ensure all feedback connections are short and direct. Place the feedback resistors and compensation components as close to the IC as possible. 6) Route high-speed switching nodes, such as LX, away from sensitive analog areas (FB, COMP).
MAX8654
PCB Layout Considerations and Thermal Performance
Careful PCB layout is critical to achieve clean and stable operation. It is highly recommended to duplicate the MAX8654 EV kit layout for optimum performance. If deviation is necessary, follow these guidelines for good PCB layout:
OPEN-LOOP GAIN COMPENSATION TRANSFER FUNCTION
THIRD POLE DOUBLE POLE
GAIN (dB)
POWER-STAGE TRANSFER FUNCTION
SECOND POLE
ESR ZERO
FIRST AND SECOND ZEROS
f
Figure 4. Transfer Function for Type 3 Compensation
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15
12V, 8A 1.2MHz Step-Down Regulator MAX8654
Pin Configuration
PROCESS: BiCMOS
TOP VIEW LX LX LX LX LX LX BST SYNC SYNCOUT
Chip Information
20
27
26
25
24
23
22
21
19
Package Information
LX LX N.C. EN GND N.C. PGND PGND PGND
28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10
PWRGD FB COMP SS REFIN GND FREQ ILIM VL
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 36 TQFN PACKAGE CODE T3666-3 DOCUMENT NO. 21-0141
MAX8654
PGND PGND
PGND VDL IN IN
THIN QFN
16
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IN IN VP
12V, 8A 1.2MHz Step-Down Regulator
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 8/06 4/08 7/09 Initial release Updated Ordering Information, Pin Description, and Package Information. Updated Current Limit and Input Capacitor Selection sections. DESCRIPTION PAGES CHANGED -- 1, 8, 14, 16 11, 13
MAX8654
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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