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Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
Recommended Application:
ATI RS/RD690 systems using AMD K8 processors & SB600 Southbridge
ICS951464
Key Specifications:
* * * * CPU outputs cycle-to-cycle jitter < 85ps SRC outputs cycle-to-cycle jitter < 125ps ATIG outputs cycle-to-cycle jitter < 125ps +/- 300ppm frequency accuracy on CPU, SRC & ATIG clocks
Output Features:
* * * * * * 2 6 2 1 2 3 - 0.7V current-mode differential CPU pairs - 0.7V current-mode differential SRC pairs - 0.7V current-mode differential ATIG pairs - HyperTransport clock seed - 48MHz USB clock - 14.318MHz Reference clock
Features/Benefits:
* * * * * 3 - Programmable Clock Request pins for SRC and ATIG clocks ATIGCLKs are programmable for frequency Spread Spectrum for EMI reduction Outputs may be disabled via SMBus External crystal load capacitors for maximum frequency accuracy
Pin Configuration
GNDREF VDDREF X1 X2 VDD48 48MHz_0 48MHz_1 GND48 SMBCLK SMBDAT RESET_IN# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 SRCCLKT4 SRCCLKC4 GNDSRC VDDSRC SRCCLKT2 SRCCLKC2 VDDSRC GNDSRC *CLKREQB# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 FS0/REF0 FS1/REF1 FS2/REF2 **PD VDDHTT HTTCLK0 GNDHTT *CLKREQA# CPUCLK8T0 CPUCLK8C0 VDDCPU GNDCPU CPUCLK8T1 CPUCLK8C1 VDDA GNDA IREF SRCCLKT0 SRCCLKC0 GNDSRC VDDSRC ATIGCLKT0 ATIGCLKC0 VDDATIG GNDATIG ATIGCLKT1 ATIGCLKC1 *CLKREQC#
56-Pin SSOP/TSSOP
Note: Pins preceeded by * have a 120 Kohm Internal Pull Up resistor Pins preceeded by ** have a 120 Kohm Internal Pull Down resistor
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
951464AGLF
1211B--09/17/09
1
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Pin Description
PIN #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PIN NAME
GNDREF VDDREF X1 X2 VDD48 48MHz_0 48MHz_1 GND48 SMBCLK SMBDAT RESET_IN# SRCCLKT7 SRCCLKC7 VDDSRC GNDSRC SRCCLKT6 SRCCLKC6 SRCCLKT5 SRCCLKC5 SRCCLKT4 SRCCLKC4 GNDSRC VDDSRC SRCCLKT2 SRCCLKC2 VDDSRC GNDSRC *CLKREQB#
TYPE
PWR PWR IN OUT PWR OUT OUT PWR IN I/O IN OUT OUT PWR PWR OUT OUT OUT OUT OUT OUT PWR PWR OUT OUT PWR PWR IN
DESCRIPTION
Ground pin for the REF outputs. Ref, XTAL power supply, nominal 3.3V Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Power pin for the 48MHz output.3.3V 48MHz clock output. 48MHz clock output. Ground pin for the 48MHz outputs Clock pin of SMBUS circuitry, 5V tolerant Data pin of SMBUS circuitry, 5V tolerant Real time active low input. When active, SMBus is reset to power up default. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Ground pin for the SRC outputs Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
2
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Pin Description (Continued)
PIN #
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
PIN NAME
*CLKREQC# ATIGCLKC1 ATIGCLKT1 GNDATIG VDDATIG ATIGCLKC0 ATIGCLKT0 VDDSRC GNDSRC SRCCLKC0 SRCCLKT0 IREF GNDA VDDA CPUCLK8C1 CPUCLK8T1 GNDCPU VDDCPU CPUCLK8C0 CPUCLK8T0 *CLKREQA# GNDHTT HTTCLK0 VDDHTT **PD FS2/REF2 FS1/REF1 FS0/REF0
TYPE
IN OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT IN PWR OUT PWR IN I/O I/O I/O
DESCRIPTION
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Complementary clock of differential ATIGCLK clock pair. True clock of differential ATIGCLK clock pair. Ground for ATIG clocks Power supply ATIG clocks, nominal 3.3V Complementary clock of differential ATIGCLK clock pair. True clock of differential ATIGCLK clock pair. Supply for SRC clocks, 3.3V nominal Ground pin for the SRC outputs Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin for the PLL core. 3.3V power for the PLL core. Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal Complementary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Ground pin for the HTT outputs 3.3V Hyper Transport output Supply for HTT clocks, nominal 3.3V. Asynchronous active high input pin used to power down the device. The internal clocks are disabled and the VCO is stopped. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock.
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
3
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
General Description The ICS951464 is a main clock synthesizer chip that provides all clocks required for ATI RS/RD690-based systems. An SMBus interface allows full control of the device. Block Diagram
REF(2:0)
X1 X2
Xtal Osc.
Fixed PLL
48MHz(1:0)
HTTCLK0
SRCCLK(7:0) FS(2:0) CLKREQA# CLKREQB# CLKREQC# RESET_IN# SMBDAT SMBCLK Programmable Spread PLLs
Control Logic
Programmable Dividers CPUCLK(2:0)
ATIGCLK(2:0)
IREF
951464 Power Group Table VDD Pin# GND Pin# 2 1 5 8 14,26 15,27 23 22 36 37 33 32 42 41 46 45 52 50 Description Crsytal, REF VDD & VSS I/O & Core 48M Core and Output; FIX PLL Analog/Digital SRC I/O & Core SRC I/O & Core; SRC PLL Digital SRC I/O & Core; SRC PLL Analog ATIG I/O & Core; ATIG PLL Analog/Digital CPU PLL Analog CPU I/O & Core; CPU PLL Digital HTT I/O & Core
1211B--09/17/09
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
4
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Table1: CPU and HTT Frequency Selection Table Byte 0 Bit4 Bit3 Bit2 Bit1 Bit0 CPUCLK HTT Spread Overclock (2:0) CPU CPU CPU CPU CPU (MHz) % % (MHz) SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Hi-Z X/2 230.00 240.00 100.00 133.33 166.67 200.00 250.00 260.00 270.00 280.00 102.00 136.00 170.00 204.00 210.00 220.00 230.00 240.00 100.00 133.33 166.67 200.00 250.00 260.00 270.00 280.00 102.00 136.00 170.00 204.00 Hi-Z X/3 76.67 80.00 66.67 66.67 66.67 66.67 83.33 86.67 90.00 93.33 68.00 68.00 68.00 68.00 70.00 73.33 76.67 80.00 66.67 66.67 66.67 66.67 83.33 86.67 90.00 93.33 68.00 68.00 68.00 68.00 None None None None None None None None None None None None None None None None -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5%
15% 20% 0% 25% 30% 35% 40% 2% 5% 10% 15% 20% 0% 25% 30% 35% 40% 2%
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
5
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Table2: SRC Frequency Selection Table Byte 5 Byte 0 SRC Bit 5 Bit3 Bit2 Bit1 Bit0 SRC SRC SRC SRC SRC (MHz) SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 100.00 0 0 0 0 1 101.00 0 0 0 1 0 102.00 0 0 0 1 1 103.00 0 0 1 0 0 104.00 0 0 1 0 1 105.00 0 0 1 1 0 106.00 0 0 1 1 1 107.00 0 1 0 0 0 100.00 0 1 0 0 1 101.00 0 1 0 1 0 102.00 0 1 0 1 1 103.00 0 1 1 0 0 104.00 0 1 1 0 1 105.00 0 1 1 1 0 106.00 0 1 1 1 1 107.00 1 0 0 0 0 100.00 1 0 0 0 1 101.00 1 0 0 1 0 102.00 1 0 0 1 1 103.00 1 0 1 0 0 104.00 1 0 1 0 1 105.00 1 0 1 1 0 106.00 1 0 1 1 1 107.00 1 1 0 0 0 100.00 1 1 0 0 1 101.00 1 1 0 1 0 102.00 1 1 0 1 1 103.00 1 1 1 0 0 104.00 1 1 1 0 1 105.00 1 1 1 1 0 106.00 1 1 1 1 1 107.00
SRC Spread OverClock % % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7% 0% 1% 2% 3% 4% 5% 6% 7%
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
6
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Table3: ATIG Frequency Selection Table Byte 9 Byte 0 Bit 6 Bit4 Bit3 Bit1 Bit0 ATIG (MHz) ATIG ATIG ATIG ATIG ATIG SS_EN FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00 100.00 105.00 110.00 115.00 120.00 125.00 130.00 135.00
ATIG Spread OverClock % % 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.25% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% -0.5% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35% 0% 5% 10% 15% 20% 25% 30% 35%
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
7
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Table 4: CPU Divider Ratios B19b(7:4) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0) Table 5: HTT Divider Ratios B20b(3:0) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0) Table 6: ATIG Divider Ratios B19b(3:0) 00 Bit 00 0000 01 0001 10 0010 11 0011 Address LSB Divider (1:0)
2 3 5 15 Div
Divider (3:2) 01 10 0100 4 1000 0101 6 1001 0110 10 1010 0111 30 1011 Address Address
8 12 20 60 Div
11 1100 1101 1110 1111 Address
MSB 16 24 40 120 Div
Divider (3:2) 4 3 5 15 Div 01 0100 0101 0110 0111 Address 8 6 10 30 10 1000 1001 1010 1011 Address 16 12 20 60 Div 11 1100 1101 1110 1111 Address MSB 32 24 40 120 Div
Divider (3:2) 2 3 5 7 Div 01 0100 0101 0110 0111 Address 4 6 10 14 10 1000 1001 1010 1011 Address 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 16 24 40 56 Div
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
8
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
General SMBus serial interface information for the ICS951464
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK
Byte N + X - 1 N P Not acknowledge stoP bit
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
9
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register Byte 0 Pin # Name Control Function Type Latched Input or SMBus RW FS Source Bit 7 Frequency Select ATIG SS_EN ATIG Spread Spectrum Enable RW Bit 6 SRC SS_EN SRC Spread Spectrum Enable RW Bit 5 CPU SS_EN CPU Spread Spectrum Enable RW Bit 4 CPU FS3 CPU Freq Select Bit 3 RW Bit 3 CPU FS2 CPU Freq Select Bit 2 RW Bit 2 CPU FS1 CPU Freq Select Bit 1 RW Bit 1 CPU FS0 CPU Freq Select Bit 0 RW Bit 0 Note: Each Spread Spectrum Enable bit is independent from the other. Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks. SMBus Table: Output Control Register Byte 1 Pin # Name 7 48MHz_1 Bit 7 6 48MHz_0 Bit 6 54 REF2 Bit 5 55 REF1 Bit 4 56 REF0 Bit 3 51 HTTCLK0 Bit 2 44,43 CPUCLK1 Bit 1 48,47 CPUCLK0 Bit 0
0 Latched Inputs Disable Disable Disable
1 SMBus Enable Enable Enable
PWD 0 0 0 0 0 Latch Latch Latch
See Table 1: CPU Frequency Selection Table
Control Function 48MHz_1 Output Enable 48MHz_0 Output Enable REF2 Output Enable REF1 Output Enable REF0 Output Enable HTTCLK0 Output Enable CPUCLK1 Output Enable CPUCLK0 Output Enable
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
SMBus Table: ATIGCLK and CLKREQB# Output Control Register Byte 2 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 31,30 ATIGCLK1 ATIGCLK1 Output Enable Bit 5 35,34 ATIGCLK0 ATIGCLK0 Output Enable Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 24,25 REQBSRC2 20,21 REQBSRC4 CLKREQB# Controls SRC4 Reserved CLKREQB# Controls SRC2 Reserved
Type
0
1
RW RW RW
Disable Disable Does not control Does not control
Enable Enable Controls
PWD 1 1 1 1 0 0
RW
Controls
0 0
SMBus Table: SRCCLK Output Control Register Byte 3 Pin # Name Control Function 12,13 SRCCLK7 Bit 7 16,17 SRCCLK6 Bit 6 18,19 SRCCLK5 Bit 5 Master Output control. Enables 20,21 SRCCLK4 Bit 4 or disables output, regardless of Reserved Bit 3 CLKREQ# inputs. 24,25 SRCCLK2 Bit 2 Reserved Bit 1 39,38 SRCCLK0 Bit 0
Type RW RW RW RW RW RW
0 Disable Disable Disable Disable Reserved Disable Reserved Disable
1 Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
10
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
SMBus Table: CLKREQA# and CLKREQC# Output Control Register Byte 4 Pin # Name Control Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 31,30 35,34 39,38 REQCATIG1 REQCATIG0 REQCSRC0 12,13 16,17 18,19 REQASRC7 REQASRC6 REQASRC5 CLKREQA# Controls SRC7 CLKREQA# Controls SRC6 CLKREQA# Controls SRC5 Reserved Reserved CLKREQC# Controls ATIG1 CLKREQC# Controls ATIG0 CLKREQC# Controls SRC0
Type RW RW RW
0 Does not control Does not control Does not control
1 Controls Controls Controls
PWD 0 0 0 0 0
RW RW RW
Does not control Does not control Does not control
Controls Controls Controls
0 0 0
SMBus Table: CPU Stop Control and SRC Frequency Select Register Byte 5 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 SRC, Differential Output Disable Hi-Z or Driven when disable Bit 4 ATIG Mode SRC FS3 SRC Freq Select Bit 3 Bit 3 Bit 2 Bit 1 Bit 0 SRC FS2 SRC FS1 SRC FS0 SRC Freq Select Bit 2 SRC Freq Select Bit 1 SRC Freq Select Bit 0
Type
0
1
PWD 0 0 0 0 0 0 0 0
RW RW RW RW RW
Driven
Hi-Z
See Table 2: SRC Frequency Selection Table
SMBus Table: Device ID Register Byte 6 Pin # Name Device ID7 (MSB) Bit 7 Device ID6 Bit 6 Device ID5 Bit 5 Device ID4 Bit 4 Device ID3 Bit 3 Device ID2 Bit 2 Device ID1 Bit 1 Device ID0 (LSB) Bit 0 SMBus Table: Revision and Vendor ID Register Byte 7 Pin # Name RID3 Bit 7 RID2 Bit 6 RID1 Bit 5 RID0 Bit 4 VID3 Bit 3 VID2 Bit 2 VID1 Bit 1 VID0 Bit 0
Control Function
DEVICE ID
Type R R R R R R R R
0 -
1 -
PWD 0 1 1 0 0 0 1 0
Control Function REVISION ID
VENDOR ID
Type R R R R R R R R
0 -
1 -
PWD x x x x 0 0 0 1
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
11
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
SMBus Table: Byte Count Register Byte 8 Pin # Name BC7 Bit 7 BC6 Bit 6 BC5 Bit 5 BC4 Bit 4 BC3 Bit 3 BC2 Bit 2 BC1 Bit 1 BC0 Bit 0
Control Function
Byte Count Programming b(7:0)
Type RW RW RW RW RW RW RW RW
PWD 0 0 0 Writing to this register will 0 congiure how many bytes will be read back, default is 9 1 bytes. 0 0 1
0
1
SMBus Table: REF2, 48MHz Output Strength Control and ATIG Frequency Select Register Byte 9 Pin # Name Control Function Type 0 1 54 REF2Str REF2 Strength Control RW 1X 2X Bit 7 7 48MHz_1Str 48MHz_1 Strength Control RW 1X 2X Bit 6 6 48MHz_0Str 48MHz_0 Strength Control RW 1X 2X Bit 5 Reserved Bit 4 ATIG FS3 ATIG Freq Select Bit 3 RW Bit 3 ATIG FS2 ATIG Freq Select Bit 2 RW See Table 3: ATIG Bit 2 Frequency Selection Table ATIG FS1 ATIG Freq Select Bit 1 RW Bit 1 ATIG FS0 ATIG Freq Select Bit 0 RW Bit 0 SMBus Table: PLLs M/N Programming Enable and REF1, REF0 Output Strength Control Register Byte 10 Pin # Name Control Function Type 0 M/N_EN PLLs M/N Programming Enable RW Disable Bit 7 55 REF1Str REF1 Strength Control RW 1X Bit 6 56 REF0Str REF0 Strength Control RW 1X Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit 1 Reserved Bit 0 SMBus Table: CPU PLL VCO Frequency Control Register Byte 11 Pin # Name Control Function N Div8 N Divider Prog bit 8 Bit 7 N Div 9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 SMBus Table: CPU PLL VCO Frequency Control Register Byte 12 Pin # Name Control Function N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
PWD 1 1 1 0 0 0 0 0
1 Enable 2X 2X
PWD 0 1 1 0 0 0 0 0
Type RW RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD X X X X X X X X
Type RW RW RW RW RW RW RW RW
0
1
The decimal representation of M and N Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
PWD X X X X X X X X
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ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
SMBus Table: CPU PLL Spread Spectrum Control Register Byte 13 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 SSP4 Spread Spectrum Programming Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0 SMBus Table: CPU PLL Spread Spectrum Control Register Byte 14 Pin # Name Control Function Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 SMBus Table: ATIG PLL VCO Frequency Control Register Byte 15 Pin # Name Control Function N Div8 N Divider Prog bit 8 Bit 7 N Div9 N Divider Prog bit 9 Bit 6 M Div5 Bit 5 M Div4 Bit 4 M Div3 Bit 3 M Divider Programming bits M Div2 Bit 2 M Div1 Bit 1 M Div0 Bit 0 SMBus Table: ATIG PLL VCO Frequency Control Register Byte 16 Pin # Name Control Function N Div7 Bit 7 N Div6 Bit 6 N Div5 Bit 5 N Div4 Bit 4 N Divider Programming b(7:0) N Div3 Bit 3 N Div2 Bit 2 N Div1 Bit 1 N Div0 Bit 0 SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 17 Pin # Name Control Function SSP7 Bit 7 SSP6 Bit 6 SSP5 Bit 5 SSP4 Spread Spectrum Programming Bit 4 b(7:0) SSP3 Bit 3 SSP2 Bit 2 SSP1 Bit 1 SSP0 Bit 0
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
Type RW RW RW RW RW RW RW RW
PWD X X These Spread Spectrum bits in Byte 13 and 14 will program X X the spread pecentage. It is recommended to use ICS X Spread % table for spread X programming. X X
0
1
Type RW RW RW RW RW RW RW
PWD 0 X These Spread Spectrum bits X in Byte 13 and 14 will program X the spread pecentage. It is X recommended to use ICS X Spread % table for spread X programming. X
0
1
Type RW RW RW RW RW RW RW RW
PWD X The decimal representation of X M and N Divier in Byte 17 and X 18 will configure the VCO X frequency. Default at power X up = Byte 0 Rom table. VCO X Frequency = 14.318 x X [NDiv(9:0)+8] / [MDiv(5:0)+2] X
0
1
Type RW RW RW RW RW RW RW RW
PWD X The decimal representation of X M and N Divier in Byte 17 and X 18 will configure the VCO X frequency. Default at power X up = Byte 0 Rom table. VCO X Frequency = 14.318 x X [NDiv(9:0)+8] / [MDiv(5:0)+2] X
0
1
Type RW RW RW RW RW RW RW RW
PWD X X These Spread Spectrum bits in Byte 19 and 20 will program X X the spread pecentage. It is recommended to use ICS X Spread % table for spread X programming. X X
1211B--09/17/09
0
1
13
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
SMBus Table: ATIG PLL Spread Spectrum Control Register Byte 18 Pin # Name Control Function Reserved Bit 7 SSP14 Bit 6 SSP13 Bit 5 SSP12 Bit 4 Spread Spectrum Programming SSP11 Bit 3 b(14:8) SSP10 Bit 2 SSP9 Bit 1 SSP8 Bit 0 SMBus Table: CPU and ATIG Divider Ratio Programming Bits Select Register Byte 19 Pin # Name Control Function CPU_Div3 Bit 7 CPU_Div2 CPU_Divider Ratio Bit 6 Programming Bits CPU_Div1 Bit 5 CPU_Div0 Bit 4 ATIG_Div3 Bit 3 ATIG_Div2 ATIG_Divider Ratio Bit 2 Programming Bits ATIG_Div1 Bit 1 Bit 0 ATIG_Div0
Type RW RW RW RW RW RW RW
PWD 0 X These Spread Spectrum bits X in Byte 19 and 20 will program X the spread pecentage. It is X recommended to use ICS X Spread % table for spread X programming. X
0
1
Type RW RW RW RW RW RW RW RW
0
1
See Table 4: CPU Divider Ratios
See Table 5: ATIG Divider Ratios
PWD X X X X X X X X
SMBus Table: HTT Divider Ratio Programming Bits Select Register Byte 20 Pin # Name Control Function Reserved Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 HTT_Div3 Bit 3 HTT_Div2 HTT_Divider Ratio Bit 2 Programming Bits HTT_Div1 Bit 1 HTT_Div0 Bit 0
Type
0
1
RW RW RW RW
See Table 6: HTT Divider Ratios
PWD 0 0 0 0 X X X X
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
14
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Absolute Max
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection HBM
1
SYMBOL VDD_A VDD_In Ts Tambient Tcase ESD prot
CONDITIONS -
MIN
TYP
MAX VDD + 0.5V
UNITS V V
Notes 1 1 1 1 1 1
GND 0.5 -65 0 2000
VDD + 0.5V 150 70 115
C
C C V
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance VIH_FS VIL_FS IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Clk Stabilization Modulation Frequency Tdrive_PD Tfall_PD Trise_PD SMBus Voltage VDD TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD to 1st clock Triangular Modulation CPU output enable after PD de-assertion PD fall time of PD rise time of 2.7 CONDITIONS* 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V 14.31818 7 5 6 5 1.8 30 33 300 5 5 5.5 0.4 4 1000 300 MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 VDD + 0.3 0.35 400 70 12 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA V V mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns Notes 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Low-level Output Voltage VOL @ IPULLUP Current sinking at IPULLUP VOL = 0.4 V (Max VIL - 0.15) to SMBCLK/SMBDAT TRI2C (Min VIH + 0.15) Clock/Data Rise Time SMBCLK/SMBDAT (Min VIH + 0.15) to TFI2C Clock/Data Fall Time (Max VIL - 0.15) *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
1 2
Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems 1211B--09/17/09
15
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Electrical Characteristics - K8 Push Pull Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load PARAMETER Rising Edge Rate Falling Edge Rate Differential Voltage Change in VDIFF_DC Magnitude Common Mode Voltage Change in Common Mode Voltage Jitter, Cycle to cycle SYMBOL V/t V/t VDIFF VDIFF VCM VCM Measured at the AMD64 processor's test load. (singleended measurement) Measurement from differential wavefrom. Maximum difference of cycle time between 2 adjacent cycles. Measured using the JIT2 software package with a Tek 7404 scope. TIE (Time Interval Error) measurement technique: Sample resolution = 50 ps, Sample Duration = 10 s Measurement from differential wavefrom Average value during switching transition. Used for determining series termination value. Measurement from differential wavefrom CONDITIONS Measured at the AMD64 processor's test load. 0 V +/- 400 mV (differential measurement) MIN 2 2 0.4 -150 1.05 -200 1.25 1.25 TYP MAX 10 10 2.3 150 1.45 200 UNITS V/ns V/ns V mV V mV NOTES 1 1 1 1 1 1
tjcyc-cyc
0
50
85
ps
1
Jitter, Accumulated
tja
-1000
1000
1,2,3
Duty Cycle
dt3
45
53
%
1
Output Impedance
RON
15
35
55
1
Group Skew
1 2 3
tsrc-skew
50
ps
1
Guaranteed by design and characterization, not 100% tested in production. All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz Spread Spectrum is off
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
16
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Electrical Characteristics - HTTCLK Clock
PARAMETER Long Accuracy PCI33 Clock period HTT66 Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle
1 2
SYMBOL ppm Tperiod Tperiod VOH VOL IOH IOL V/t V/t tr1 tf1 dt1 tjcyc-cyc V
CONDITIONS see Tperiod min-max values 33.33MHz output nominal 33.33MHz output spread 66.67MHz output nominal 66.67MHz output spread IOH = -1 mA IOL = 1 mA
OH @MIN
MIN -300 29.9910 29.9910 14.9955 14.9955 2.4
TYP
MAX 300 30.0090 30.1598 15.0045 15.0799 0.55
UNITS ppm ns ns ns ns V V mA mA mA mA V/ns V/ns ns ns % ps
Notes 1,2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
= 1.0 V
-33 -33 30 38 1 1 0.5 0.5 45 4 4 2 2 55 180
VOH@ MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising edge rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
*TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that REF is at 14.31818MHz
Electrical Characteristics - SRC/ATIG 0.7V Current Mode Differential Pair
PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vx ppm Tperiod Tabsmin tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V 45 CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 550 140 -300 9.9970 9.9970 9.8720 175 175 700 700 125 125 55 100 85 300 10.0030 10.0533 850 150 1150 TYP MAX UNITS mV mV mV mV mV mV ppm ns ns ns ps ps ps ps % ps ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1 1 1 1 1 1 1
VOH = 0.525V VOL = 0.175V Measurement from differential dt3 Duty Cycle wavefrom VT = 50% tsk3 Skew Measurement from differential tjcyc-cyc Jitter, Cycle to cycle wavefrom *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475
1 2 3
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
1211B--09/17/09
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
17
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Electrical Characteristics - USB - 48MHz
PARAMETER Long Accuracy Clock period Clock Low Time Clock High Time Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle to cycle
1 2
SYMBOL ppm Tperiod Tlow Thigh VOH VOL IOH IOL tr_USB tf_USB dt1 tskew tjcyc-cyc
CONDITIONS* see Tperiod min-max values 48.00MHz output nominal Measure from < 0.6V Measure from > 2.0V IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN -100 20.8229 9.3750 9.3750 2.4
TYP
MAX 100 20.8344 11.4580 11.4580 0.55
UNITS NOTES ppm ns ns ns V V mA mA mA mA ns ns % ps ps 1,2 2 2 2 1 1 1 1 1 1 1 1 1 1 1,2
-33 -33 30 38 0.5 0.5 45 1.5 1.5 55 100 130
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22 (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification
Electrical Characteristics - REF-14.318MHz
PARAMETER Long Accuracy Clock period Clock Low Time Clock High Time Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Skew Duty Cycle Jitter
1 2
SYMBOL ppm Tperiod Tlow Thigh VOH VOL IOH IOL tr1 tf1 tsk1 dt1 tjcyc-cyc
CONDITIONS see Tperiod min-max values 14.318MHz output nominal Measure from < 0.6V Measure from > 2.0V IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN -100 69.8270 30.9290 30.9290 2.4
TYP
MAX 100 69.8550 37.9130 37.9130 0.4
UNITS ppm ns ns ns V V mA mA ns ns ps % ps
Notes 1,2 2 2 2 1 1 1 1 1 1 1 1 1
-29 29
-23 27 1.5 1.5 100
44
53 200
56 300
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22 (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
18
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
RESET_IN# - Assertion (transition from '1' to '0')
Asserting RESET_IN pin stops all the outputs including CPU, SRC, ATIG, PCI and USB with the REF[2:0] running. The pin is a Schmitt trigger input with debouncing. After it is triggered, REF clocks will wait for two clock cycle to ensure the RESET_IN is asserted. Then, it will take 3uS for the clocks to stop without glitches. The clock chip will be power down and re-power up, and SMBus will be reloaded. It will take no more than 2.5mS for the clocks to come out with correct frequencies and no glitches.
** Deassertion of RESET_IN# (transition from '0' to '1') has NO effect on the clocks.
2 clock cycles RESET_IN#
3 uS max
2.5mS max
REF [2:0] *CLKS
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
19
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
SRC Routing Information
SRC Reference Clock Common Recommendations for Differential Routing Dimension or Value L1 length, Route as non-coupled 50 ohm trace. 0.5 max L2 length, Route as non-coupled 50 ohm trace. 0.2 max L3 length, Route as non-coupled 50 ohm trace. 0.2 max Rs 33 Rt 49.9 Down Device Differential Routing L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Differential Routing to PCI Express Connector L4 length, Route as coupled microstrip 100 ohm differential trace. L4 length, Route as coupled stripline 100 ohm differential trace. Dimension or Value 2 min to 16 max 1.8 min to 14.4 max Unit inch inch inch ohm ohm Unit inch inch Figure 2, 3 2, 3 2, 3 2, 3 2, 3 Figure 2 2
Dimension or Value 0.25 to 14 max 0.225 min to 12.6 max
Unit inch inch
Figure 3 3
L1 Rs L1'
L2 L4 L2' Rs Rt Rt PCI Ex REF_CLK Test Load L4'
Fig.1
HSCL Output Buffer
L3'
L3
L1 Rs L1'
L2 L4 L2' Rs Rt Rt PCI Ex Board Down Device REF_CLK Input L4'
Fig.2
HSCL Output Buffer
L3'
L3
L1 Rs L1'
L2 L4 L4' L2' Rs Rt Rt PCI Ex Add In Board REF_CLK Input
Fig.3
HSCL Output Buffer
L3'
L3
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
20
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS951464 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad
Via to VDD 2K W
8.2K W Clock trace to load Series Term. Res.
Fig. 1
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
21
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL A A1 b c D E E1 e h L N a VARIATIONS N 56 D mm. MIN 18.31 MAX 18.55 MIN .720 D (inch) MAX .730 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
951464yFLFT
Example:
XXXX y F LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
22
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS a 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
aaa C
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Reference Doc.: JEDEC Publication 95, M O-153
Ordering Information
951464yGLFT
Example:
XXXX y G LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers)
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8TM - based Systems
1211B--09/17/09
23
ICS951464
IDTTM/ICSTM Programmable System Clock Chip for ATI RS/RD690 K8 TM - based Systems
Revision History
Rev. A B Issue Date Description 4/9/2008 Going to Release. 9/17/2009 Updated Power Group table. Page # 4
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TM
(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA
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