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To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
Mitsubishi 32-Bit RISC Single-Chip Microcomputers
M32R Family M32R/ECU Series
32180
G r o u p
User's Manual
http://www.infomicom.maec.co.jp/
The latest version of this manual is published at the Mitsubishi microcomputer home page shown above. Please make sure you are using the latest version of the manual.
Rev. 1.0
Jan. 24, 2003
Keep safety first in your circuit designs!
*
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
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*
*
*
*
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*
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Revision History
Rev. Date of Issue
Page
32180 Group User's Manual
Contents of Revision Changes Made
1.0 Jan. 24, 2003
-
First edition issued
(1/1)
Before Use
* Guide to Understanding the Register Table
(1) Bit number: Indicates a register's bit number. (2) Register border: The registers enclosed with thick border lines must be accessed in halfwords or words. (3) Status after reset: The initial state of each register after reset is indicated in hexadecimal or binary. (4) Status after reset: The initial state of each register after reset is indicated bitwise. 0: This bit is "0" after reset. 1: This bit is "1" after reset. ?: This bit is undefined after reset. (5) The shaded bits mean that they have no functions assigned. (6) Read conditions: R: This bit can be accessed for read. ?: The value read from this bit is undefined. (Reading this bit has no effect.) 0: The value read from this bit is always "0". 1: The value read from this bit is always "1". (7) Write conditions: W: This bit can be accessed for write. N: This bit is write protected. 0: To write to this bit, always write "0". 1: To write to this bit, always write "1". -: Writing to this bit has no effect. (It does not matter whether this bit is set to "0" or "1" by writing in software.) Note: Care must be taken when writing to this bit. See Note in each register table. (1)
XXXRegister(XXX)
(5)
b0
AAA 0
1
BBB 0
2
CCC 0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
(2) (4)
(3)
b 0 1 2 3-15 Bit name AAA
*** *** ***
R W W W
Function bit bit bit 0: 1: 0: 1: 0: 1:
*** *** *** *** *** ***
bit bit bit bit bit bit
R R
BBB
*** *** ***
*** ***
*** ***
*** ***
CCC
*** *** ***
*** ***
*** ***
*** ***
R (Note 1) 0 0
No function assigned. Fix to "0".
Note 1: Only writing "0" is effective. Writing "1" has no effect, in which case the bit retains the value it had before the write.
(6) (7)
* Notation of active-low pins (signals)
The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.
Table of contents
CHAPTER 1 OVERVIEW 1.1 Outline of the 32180 Group --------------------------------------------------------------------------------------------- 1-2 1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU) --------------------------------------------- 1-2 1.1.2 1.1.2 Built-in Multiplier/Accumulator ---------------------------------------------------------------------- 1-3 1.1.3 Built-in Single-precision FPU -------------------------------------------------------------------------------- 1-3 1.1.4 Built-in Flash Memory and RAM ---------------------------------------------------------------------------- 1-3 1.1.5 Built-in Clock Frequency Multiplier ------------------------------------------------------------------------- 1-4 1.1.6 Powerful Peripheral Functions Built-in -------------------------------------------------------------------- 1-4 1.2 Block Diagram -------------------------------------------------------------------------------------------------------------- 1-5 1.3 Pin Functions --------------------------------------------------------------------------------------------------------------- 1-8 1.4 Pin Assignments ----------------------------------------------------------------------------------------------------------- 1-14 CHAPTER 2 CPU 2.1 CPU Registers ------------------------------------------------------------------------------------------------------------- 2-2 2.2 General-purpose Registers --------------------------------------------------------------------------------------------- 2-2 2.3 Control Registers ---------------------------------------------------------------------------------------------------------- 2-2 2.3.1 Processor Status Word Register: PSW (CR0) ---------------------------------------------------------- 2-3 2.3.2 Condition Bit Register: CBR (CR1) ------------------------------------------------------------------------ 2-4 2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3) ------------------------- 2-4 2.3.4 Backup PC: BPC (CR6) -------------------------------------------------------------------------------------- 2-4 2.3.5 Floating-point Status Register: FPSR (CR7) ------------------------------------------------------------ 2-5 2.4 Accumulator ----------------------------------------------------------------------------------------------------------------- 2-7 2.5 Program Counter ---------------------------------------------------------------------------------------------------------- 2-7 2.6 Data Formats --------------------------------------------------------------------------------------------------------------- 2-8 2.6.1 Data Types ------------------------------------------------------------------------------------------------------- 2-8 2.6.2 Data Formats ---------------------------------------------------------------------------------------------------- 2-9 2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution ----------------- 2-14 2.8 Precautions on CPU ----------------------------------------------------------------------------------------------------- 2-14 CHAPTER 3 ADDRESS SPACE 3.1 Outline of the Address Space ------------------------------------------------------------------------------------------ 3-2 3.2 Operation Modes ---------------------------------------------------------------------------------------------------------- 3-4 3.3 Internal ROM and Extended External Areas ------------------------------------------------------------------------ 3-5 3.3.1 Internal ROM Area --------------------------------------------------------------------------------------------- 3-5 3.3.2 Extended External Area -------------------------------------------------------------------------------------- 3-5 3.4 Internal RAM and SFR Areas ------------------------------------------------------------------------------------------ 3-6 3.4.1 Internal RAM Area --------------------------------------------------------------------------------------------- 3-6 3.4.2 SFR (Special Function Register) Area -------------------------------------------------------------------- 3-6 3.5 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 3-35 3.6 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 3-36 3.7 Notes on Address Space ------------------------------------------------------------------------------------------------ 3-38
(1)
CHAPTER 4 EIT 4.1 Outline of EIT --------------------------------------------------------------------------------------------------------------- 4-2 4.2 EIT Events ------------------------------------------------------------------------------------------------------------------ 4-3 4.2.1 Exception --------------------------------------------------------------------------------------------------------- 4-3 4.2.2 Interrupt ----------------------------------------------------------------------------------------------------------- 4-5 4.2.3 Trap ---------------------------------------------------------------------------------------------------------------- 4-6 4.3 EIT Processing Procedure ---------------------------------------------------------------------------------------------- 4-6 4.4 EIT Processing Mechanism --------------------------------------------------------------------------------------------- 4-7 4.5 Acceptance of EIT Events ----------------------------------------------------------------------------------------------- 4-8 4.6 Saving and Restoring the PC and PSW ----------------------------------------------------------------------------- 4-8 4.7 EIT Vector Entry ----------------------------------------------------------------------------------------------------------- 4-10 4.8 Exception Processing ---------------------------------------------------------------------------------------------------- 4-11 4.8.1 Reserved Instruction Exception (RIE) --------------------------------------------------------------------- 4-11 4.8.2 Address Exception (AE) -------------------------------------------------------------------------------------- 4-12 4.8.3 Floating-Point Exception (FPE) ----------------------------------------------------------------------------- 4-13 4.9 Interrupt Processing ------------------------------------------------------------------------------------------------------ 4-15 4.9.1 Reset Interrupt (RI) -------------------------------------------------------------------------------------------- 4-15 4.9.2 System Break Interrupt (SBI) -------------------------------------------------------------------------------- 4-15 4.9.3 External Interrupt (EI) ----------------------------------------------------------------------------------------- 4-17 4.10 Trap Processing ---------------------------------------------------------------------------------------------------------- 4-18 4.10.1 Trap ---------------------------------------------------------------------------------------------------------------- 4-18 4.11 EIT Priority Levels ------------------------------------------------------------------------------------------------------- 4-19 4.12 Example of EIT Processing ------------------------------------------------------------------------------------------- 4-20 4.13 Precautions on EIT ------------------------------------------------------------------------------------------------------ 4-22 CHAPTER 5 INTERRUPT CONTROLLER (ICU) 5.1 Outline of the Interrupt Controller -------------------------------------------------------------------------------------- 5-2 5.2 ICU Related Registers --------------------------------------------------------------------------------------------------- 5-4 5.2.1 Interrupt Vector Register ------------------------------------------------------------------------------------- 5-5 5.2.2 Interrupt Request Mask Register --------------------------------------------------------------------------- 5-6 5.2.3 SBI (System Break Interrupt) Control Register --------------------------------------------------------- 5-7 5.2.4 Interrupt Control Registers ----------------------------------------------------------------------------------- 5-8 5.3 Interrupt Request Sources in Internal Peripheral I/O ------------------------------------------------------------- 5-11 5.4 ICU Vector Table ---------------------------------------------------------------------------------------------------------- 5-12 5.5 Description of Interrupt Operation ------------------------------------------------------------------------------------- 5-13 5.5.1 Acceptance of Internal Peripheral I/O Interrupts ------------------------------------------------------- 5-13 5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers -------------------------------------------- 5-15 5.6 Description of System Break Interrupt (SBI) Operation ---------------------------------------------------------- 5-18 5.6.1 Acceptance of SBI --------------------------------------------------------------------------------------------- 5-18 5.6.2 SBI Processing by Handler ---------------------------------------------------------------------------------- 5-18 CHAPTER 6 INTERNAL MEMORY 6.1 6.2 6.3 6.4 Outline of the Internal Memory ----------------------------------------------------------------------------------------- 6-2 Internal RAM ---------------------------------------------------------------------------------------------------------------- 6-2 Internal Flash Memory --------------------------------------------------------------------------------------------------- 6-2 Registers Associated with the Internal Flash Memory ----------------------------------------------------------- 6-4 6.4.1 Flash Mode Register ------------------------------------------------------------------------------------------ 6-4
(2)
6.4.2 Flash Status Registers ---------------------------------------------------------------------------------------- 6-5 6.4.3 Flash Status Register 2 (FSTAT2) ------------------------------------------------------------------------- 6-5 6.4.4 Flash Control Registers --------------------------------------------------------------------------------------- 6-7 6.4.5 Virtual Flash S Bank Registers ----------------------------------------------------------------------------- 6-11 6.5 Programming the Internal Flash Memory ---------------------------------------------------------------------------- 6-12 6.5.1 Outline of Internal Flash Memory Programming -------------------------------------------------------- 6-12 6.5.2 Controlling Operation Modes during Flash Programming -------------------------------------------- 6-17 6.5.3 P8 Data Register ----------------------------------------------------------------------------------------------- 6-18 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory ----------------------------------- 6-20 6.5.5 Flash Programming Time (Reference) -------------------------------------------------------------------- 6-29 6.6 Virtual Flash Emulation Function -------------------------------------------------------------------------------------- 6-30 6.6.1 Virtual Flash Emulation Area -------------------------------------------------------------------------------- 6-31 6.6.2 Entering Virtual Flash Emulation Mode ------------------------------------------------------------------- 6-33 6.6.3 Application Example of Virtual Flash Emulation Mode ------------------------------------------------ 6-34 6.7 Connecting to A Serial Programmer ---------------------------------------------------------------------------------- 6-36 6.8 Internal Flash Memory Protect Function ----------------------------------------------------------------------------- 6-38 6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory -------------------------------------- 6-39 CHAPTER 7 RESET 7.1 Outline of Reset ------------------------------------------------------------------------------------------------------------ 7-2 7.2 Reset Operation ----------------------------------------------------------------------------------------------------------- 7-2 7.2.1 Reset at Power-on --------------------------------------------------------------------------------------------- 7-3 7.2.2 Reset during Operation --------------------------------------------------------------------------------------- 7-3 7.2.3 Reset at Entering RAM Backup Mode -------------------------------------------------------------------- 7-3 7.2.4 Reset Vector Relocation during Flash Programming -------------------------------------------------- 7-3 7.3 Internal State Immediately after Reset ------------------------------------------------------------------------------- 7-4 7.4 Things to Be Considered after Reset --------------------------------------------------------------------------------- 7-4 CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS 8.1 Outline of Input/Output Ports ------------------------------------------------------------------------------------------- 8-2 8.2 Selecting Pin Functions -------------------------------------------------------------------------------------------------- 8-3 8.3 Input/Output Port Related Registers ---------------------------------------------------------------------------------- 8-5 8.3.1 Port Data Registers -------------------------------------------------------------------------------------------- 8-7 8.3.2 Port Direction Registers -------------------------------------------------------------------------------------- 8-8 8.3.3 Port Operation Mode Registers ----------------------------------------------------------------------------- 8-9 8.3.4 Port Peripheral Output Select Registers ------------------------------------------------------------------ 8-20 8.3.5 Port Input Special Function Control Register ------------------------------------------------------------ 8-21 8.4 Port Input Level Switching Function ---------------------------------------------------------------------------------- 8-24 8.5 Port Peripheral Circuits -------------------------------------------------------------------------------------------------- 8-27 8.6 Precautions on Input/Output Ports ------------------------------------------------------------------------------------ 8-31 CHAPTER 9 DMAC 9.1 Outline of the DMAC ------------------------------------------------------------------------------------------------------ 9-2 9.2 DMAC Related Registers ------------------------------------------------------------------------------------------------ 9-4 9.2.1 DMA Channel Control Registers --------------------------------------------------------------------------- 9-6 9.2.2 DMA Software Request Generation Registers ---------------------------------------------------------- 9-18 9.2.3 DMA Source Address Registers ---------------------------------------------------------------------------- 9-19
(3)
9.2.4 DMA Destination Address Registers ---------------------------------------------------------------------- 9-20 9.2.5 DMA Transfer Count Registers ----------------------------------------------------------------------------- 9-21 9.2.6 DMA Interrupt Related Registers --------------------------------------------------------------------------- 9-22 9.3 Functional Description of the DMAC ---------------------------------------------------------------------------------- 9-27 9.3.1 DMA Transfer Request Sources ---------------------------------------------------------------------------- 9-27 9.3.2 DMA Transfer Processing Procedure --------------------------------------------------------------------- 9-33 9.3.3 Starting DMA ---------------------------------------------------------------------------------------------------- 9-34 9.3.4 DMA Channel Priority ----------------------------------------------------------------------------------------- 9-34 9.3.5 Gaining and Releasing Control of the Internal Bus ---------------------------------------------------- 9-34 9.3.6 Transfer Units --------------------------------------------------------------------------------------------------- 9-35 9.3.7 Transfer Counts ------------------------------------------------------------------------------------------------- 9-35 9.3.8 Address Space -------------------------------------------------------------------------------------------------- 9-35 9.3.9 Transfer Operation --------------------------------------------------------------------------------------------- 9-35 9.3.10 End of DMA and Interrupt ------------------------------------------------------------------------------------ 9-37 9.3.11 Each Register Status after Completion of DMA Transfer -------------------------------------------- 9-37 9.4 Precautions about the DMAC ------------------------------------------------------------------------------------------ 9-38 CHAPTER 10 MULTIJUNCTION TIMERS 10.1 Outline of Multijunction Timers --------------------------------------------------------------------------------------- 10-2 10.2 Common Units of Multijunction Timers ----------------------------------------------------------------------------- 10-9 10.2.1 MJT Common Unit Register Map -------------------------------------------------------------------------- 10-10 10.2.2 Prescaler Unit -------------------------------------------------------------------------------------------------- 10-12 10.2.3 Clock Bus and Input/Output Event Bus Control Unit ------------------------------------------------- 10-13 10.2.4 Input Processing Control Unit ------------------------------------------------------------------------------ 10-17 10.2.5 Output Flip-flop Control Unit -------------------------------------------------------------------------------- 10-26 10.2.6 Interrupt Control Unit ----------------------------------------------------------------------------------------- 10-35 10.3 TOP (Output-Related 16-Bit Timer) --------------------------------------------------------------------------------- 10-64 10.3.1 Outline of TOP -------------------------------------------------------------------------------------------------- 10-64 10.3.2 Outline of Each Mode of TOP ------------------------------------------------------------------------------- 10-66 10.3.3 TOP Related Register Map ---------------------------------------------------------------------------------- 10-68 10.3.4 TOP Control Registers ---------------------------------------------------------------------------------------- 10-70 10.3.5 TOP Counters (TOP0CT-TOP10CT) --------------------------------------------------------------------- 10-75 10.3.6 TOP Reload Registers (TOP0RL-TOP10RL) ----------------------------------------------------------- 10-76 10.3.7 TOP Correction Registers (TOP0CC-TOP10CC) ----------------------------------------------------- 10-77 10.3.8 TOP Enable Control Registers ------------------------------------------------------------------------------ 10-78 10.3.9 Operation in TOP Single-shot Output Mode (with Correction Function) -------------------------- 10-80 10.3.10 Operation in TOP Delayed Single-shot Output Mode (with Correction Function) -------------- 10-86 10.3.11 Operation in TOP Continuous Output Mode (without Correction Function) --------------------- 10-91 10.4 TIO (Input/Output-Related 16-Bit Timer) --------------------------------------------------------------------------- 10-94 10.4.1 Outline of TIO --------------------------------------------------------------------------------------------------- 10-94 10.4.2 Outline of Each Mode of TIO -------------------------------------------------------------------------------- 10-96 10.4.3 TIO Related Register Map ----------------------------------------------------------------------------------- 10-99 10.4.4 TIO Control Registers ----------------------------------------------------------------------------------------- 10-101 10.4.5 TIO Counters (TIO0CT-TIO9CT) -------------------------------------------------------------------------- 10-109 10.4.6 TIO Reload 0/ Measure Registers (TIO0RL0-TIO9RL0) --------------------------------------------- 10-110 10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1) ---------------------------------------------------------- 10-111 10.4.8 TIO Enable Control Registers ------------------------------------------------------------------------------- 10-112 10.4.9 Operation in TIO Measure Free-Run/ Clear Input Modes -------------------------------------------- 10-114
(4)
10.4.10 Operation in TIO Noise Processing Input Mode -------------------------------------------------------- 10-116 10.4.11 Operation in TIO PWM Output Mode ---------------------------------------------------------------------- 10-117 10.4.12 Operation in TIO Single-shot Output Mode (without Correction Function) ----------------------- 10-120 10.4.13 Operation in TIO Delayed Single-shot Output Mode (without Correction Function) ----------- 10-122 10.4.14 Operation in TIO Continuous Output Mode (without Correction Function) ----------------------- 10-124 10.5 TMS (Input-Related 16-Bit Timer) ----------------------------------------------------------------------------------- 10-126 10.5.1 Outline of TMS -------------------------------------------------------------------------------------------------- 10-126 10.5.2 Outline of TMS Operation ------------------------------------------------------------------------------------ 10-126 10.5.3 TMS Related Register Map ---------------------------------------------------------------------------------- 10-128 10.5.4 TMS Control Registers ---------------------------------------------------------------------------------------- 10-129 10.5.5 TMS Counters (TMS0CT, TMS1CT) ---------------------------------------------------------------------- 10-130 10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0) ---------------------------------------------- 10-130 10.5.7 Operation of TMS Measure Input -------------------------------------------------------------------------- 10-131 10.6 TML (Input-Related 32-Bit Timer) ------------------------------------------------------------------------------------ 10-132 10.6.1 Outline of TML -------------------------------------------------------------------------------------------------- 10-132 10.6.2 Outline of TML Operation ------------------------------------------------------------------------------------ 10-133 10.6.3 TML Related Register Map ---------------------------------------------------------------------------------- 10-133 10.6.4 TML Control Registers ---------------------------------------------------------------------------------------- 10-134 10.6.5 TML Counters --------------------------------------------------------------------------------------------------- 10-135 10.6.6 TML Measure Registers -------------------------------------------------------------------------------------- 10-135 10.6.7 Operation of TML Measure Input --------------------------------------------------------------------------- 10-136 10.7 TID (Input-Related 16-Bit Timer) ------------------------------------------------------------------------------------- 10-138 10.7.1 Outline of TID ---------------------------------------------------------------------------------------------------- 10-138 10.7.2 TID Related Register Map ----------------------------------------------------------------------------------- 10-140 10.7.3 TID Control & Prescaler Enable Registers --------------------------------------------------------------- 10-141 10.7.4 TID Counters (TID0CT, TID1CT and TID2CT) ---------------------------------------------------------- 10-144 10.7.5 TID Reload Registers (TID0RL, TID0RL and TID2RL) ----------------------------------------------- 10-144 10.7.6 Outline of Each Mode of TID -------------------------------------------------------------------------------- 10-145 10.8 TOU (Output-Related 24-Bit Timer) --------------------------------------------------------------------------------- 10-150 10.8.1 Outline of TOU -------------------------------------------------------------------------------------------------- 10-150 10.8.2 Outline of Each Mode of TOU ------------------------------------------------------------------------------- 10-152 10.8.3 TOU Related Register Map ---------------------------------------------------------------------------------- 10-154 10.8.4 TOU Control Registers ---------------------------------------------------------------------------------------- 10-158 10.8.5 TOU Counters --------------------------------------------------------------------------------------------------- 10-161 10.8.6 TOU Reload Registers ---------------------------------------------------------------------------------------- 10-164 10.8.7 TOU Enable Protect Registers ------------------------------------------------------------------------------ 10-168 10.8.8 TOU Count Enable Registers ------------------------------------------------------------------------------- 10-169 10.8.9 PWMOFF Input Processing Control Registers ---------------------------------------------------------- 10-171 10.8.10 PWM Output Control Registers ----------------------------------------------------------------------------- 10-174 10.8.11 PWM Output Disable Level Control Registers ---------------------------------------------------------- 10-177 10.8.12 Operation in TOU PWM Output Mode -------------------------------------------------------------------- 10-179 10.8.13 Operation in TOU Single-shot PWM Output Mode (without Correction Function) ------------- 10-184 10.8.14 Operation in TOU Delayed Single-shot Output Mode (without Correction Function) -------------- 10-186 10.8.15 Operation in TOU Single-shot Output Mode (without Correction Function) --------------------- 10-188 10.8.16 Operation in TOU Continuous Output Mode (without Correction Function) --------------------- 10-190 10.8.17 0% or 100% Duty-Cycle Wave Output during PWM Output and Single-shot PWM Output Modes - 10-192 10.8.18 PWM Output Disable Function ------------------------------------------------------------------------------ 10-197 10.8.19 Example Application for Using the 32180 in Motor Control ------------------------------------------ 10-201
(5)
CHAPTER 11 A-D CONVERTERS 11.1 Outline of A-D Converters --------------------------------------------------------------------------------------------- 11-2 11.1.1 Conversion Modes --------------------------------------------------------------------------------------------- 11-6 11.1.2 Operation Modes ----------------------------------------------------------------------------------------------- 11-6 11.1.3 Special Operation Modes ------------------------------------------------------------------------------------ 11-9 11.1.4 A-D Converter Interrupt and DMA Transfer Requests ------------------------------------------------ 11-12 11.1.5 Sample-and-Hold Function ----------------------------------------------------------------------------------- 11-12 11.2 A-D Converter Related Registers ------------------------------------------------------------------------------------ 11-13 11.2.1 A-D Single Mode Registers 0 ------------------------------------------------------------------------------- 11-16 11.2.2 A-D Single Mode Registers 1 ------------------------------------------------------------------------------- 11-18 11.2.3 A-D Scan Mode Registers 0 --------------------------------------------------------------------------------- 11-20 11.2.4 A-D Scan Mode Registers 1 --------------------------------------------------------------------------------- 11-22 11.2.5 A-D Conversion Speed Control Registers --------------------------------------------------------------- 11-24 11.2.6 A-D Disconnection Detection Assist Function Control Registers ----------------------------------- 11-25 11.2.7 A-D Disconnection Detection Assist Method Select Registers ------------------------------------- 11-26 11.2.8 A-D Successive Approximation Registers --------------------------------------------------------------- 11-29 11.2.9 A-D Comparate Data Registers ----------------------------------------------------------------------------- 11-30 11.2.10 10-bit A-D Data Registers ------------------------------------------------------------------------------------ 11-31 11.2.11 8-bit A-D Data Registers -------------------------------------------------------------------------------------- 11-32 11.3 Functional Description of A-D Converters ------------------------------------------------------------------------- 11-33 11.3.1 How to Find Analog Input Voltages ------------------------------------------------------------------------ 11-33 11.3.2 A-D Conversion by Successive Approximation Method ---------------------------------------------- 11-34 11.3.3 Comparator Operation ---------------------------------------------------------------------------------------- 11-35 11.3.4 Calculating the A-D Conversion Time --------------------------------------------------------------------- 11-36 11.3.5 Accuracy of A-D Conversion -------------------------------------------------------------------------------- 11-39 11.4 Inflow Current Bypass Circuit ----------------------------------------------------------------------------------------- 11-41 11.5 Precautions on Using A-D Converters------------------------------------------------------------------------------ 11-43 CHAPTER 12 SERIAL I/O 12.1 Outline of Serial I/O ----------------------------------------------------------------------------------------------------- 12-2 12.2 Serial I/O Related Registers ------------------------------------------------------------------------------------------ 12-5 12.2.1 SIO Interrupt Related Registers ---------------------------------------------------------------------------- 12-6 12.2.2 SIO Transmit Control Registers ---------------------------------------------------------------------------- 12-14 12.2.3 SIO Transmit/Receive Mode Registers ------------------------------------------------------------------- 12-15 12.2.4 SIO Transmit Buffer Registers ------------------------------------------------------------------------------ 12-18 12.2.5 SIO Receive Buffer Registers ------------------------------------------------------------------------------- 12-19 12.2.6 SIO Receive Control Registers ----------------------------------------------------------------------------- 12-20 12.2.7 SIO Baud Rate Registers ------------------------------------------------------------------------------------ 12-23 12.3 Transmit Operation in CSIO Mode ---------------------------------------------------------------------------------- 12-24 12.3.1 Setting the CSIO Baud Rate --------------------------------------------------------------------------------- 12-24 12.3.2 Initializing CSIO Transmission ------------------------------------------------------------------------------ 12-25 12.3.3 Starting CSIO Transmission --------------------------------------------------------------------------------- 12-27 12.3.4 Successive CSIO Transmission ---------------------------------------------------------------------------- 12-27 12.3.5 Processing at End of CSIO Transmission ---------------------------------------------------------------- 12-28 12.3.6 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-28 12.3.7 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-28 12.3.8 Example of CSIO Transmit Operation -------------------------------------------------------------------- 12-30
(6)
12.4 Receive Operation in CSIO Mode ----------------------------------------------------------------------------------- 12-32 12.4.1 Initialization for CSIO Reception ---------------------------------------------------------------------------- 12-32 12.4.2 Starting CSIO Reception ------------------------------------------------------------------------------------- 12-34 12.4.3 Processing at End of CSIO Reception -------------------------------------------------------------------- 12-34 12.4.4 About Successive Reception -------------------------------------------------------------------------------- 12-35 12.4.5 Flags Showing the Status of CSIO Receive Operation ----------------------------------------------- 12-36 12.4.6 Example of CSIO Receive Operation --------------------------------------------------------------------- 12-37 12.5 Precautions on Using CSIO Mode ----------------------------------------------------------------------------------- 12-39 12.6 Transmit Operation in UART Mode --------------------------------------------------------------------------------- 12-40 12.6.1 Setting the UART Baud Rate -------------------------------------------------------------------------------- 12-40 12.6.2 UART Transmit/Receive Data Formats ------------------------------------------------------------------- 12-40 12.6.3 Initializing UART Transmission ----------------------------------------------------------------------------- 12-42 12.6.4 Starting UART Transmission -------------------------------------------------------------------------------- 12-44 12.6.5 Successive UART Transmission --------------------------------------------------------------------------- 12-44 12.6.6 Processing at End of UART Transmission --------------------------------------------------------------- 12-44 12.6.7 Transmit Interrupts --------------------------------------------------------------------------------------------- 12-44 12.6.8 Transmit DMA Transfer Request --------------------------------------------------------------------------- 12-45 12.6.9 Example of UART Transmit Operation -------------------------------------------------------------------- 12-46 12.7 Receive Operation in UART Mode ---------------------------------------------------------------------------------- 12-48 12.7.1 Initialization for UART Reception --------------------------------------------------------------------------- 12-48 12.7.2 Starting UART Reception ------------------------------------------------------------------------------------ 12-50 12.7.3 Processing at End of UART Reception ------------------------------------------------------------------- 12-50 12.7.4 Example of UART Receive Operation -------------------------------------------------------------------- 12-52 12.7.5 Start Bit Detection during UART Reception -------------------------------------------------------------- 12-54 12.8 Fixed Period Clock Output Function -------------------------------------------------------------------------------- 12-55 12.9 Precautions on Using UART Mode ---------------------------------------------------------------------------------- 12-56 CHAPTER 13 CAN MODULE 13.1 Outline of the CAN Module -------------------------------------------------------------------------------------------- 13-2 13.2 CAN Module Related Registers -------------------------------------------------------------------------------------- 13-4 13.2.1 CAN Control Registers ---------------------------------------------------------------------------------------- 13-15 13.2.2 CAN Status Registers ----------------------------------------------------------------------------------------- 13-18 13.2.3 CAN Frame Format Select Registers --------------------------------------------------------------------- 13-21 13.2.4 CAN Configuration Registers -------------------------------------------------------------------------------- 13-22 13.2.5 CAN Timestamp Count Registers -------------------------------------------------------------------------- 13-24 13.2.6 CAN Error Count Registers ---------------------------------------------------------------------------------- 13-25 13.2.7 CAN Baud Rate Prescalers ---------------------------------------------------------------------------------- 13-26 13.2.8 CAN Interrupt Related Registers --------------------------------------------------------------------------- 13-27 13.2.9 CAN Cause of Error Registers ------------------------------------------------------------------------------ 13-45 13.2.10 CAN Mode Registers ------------------------------------------------------------------------------------------ 13-46 13.2.11 CAN DMA Transfer Request Select Registers ---------------------------------------------------------- 13-47 13.2.12 CAN Mask Registers ------------------------------------------------------------------------------------------ 13-48 13.2.13 CAN Single-Shot Mode Control Registers --------------------------------------------------------------- 13-52 13.2.14 CAN Message Slot Control Registers --------------------------------------------------------------------- 13-53 13.2.15 CAN Message Slots ------------------------------------------------------------------------------------------- 13-57 13.3 CAN Protocol ------------------------------------------------------------------------------------------------------------- 13-72 13.3.1 CAN Protocol Frames ----------------------------------------------------------------------------------------- 13-72 13.3.2 Data Formats during CAN Transmission/Reception --------------------------------------------------- 13-73
(7)
13.3.3 CAN Controller Error States --------------------------------------------------------------------------------- 13-74 13.4 Initializing the CAN Module -------------------------------------------------------------------------------------------- 13-75 13.4.1 Initializing the CAN Module ---------------------------------------------------------------------------------- 13-75 13.5 Transmitting Data Frames --------------------------------------------------------------------------------------------- 13-78 13.5.1 Data Frame Transmit Procedure --------------------------------------------------------------------------- 13-78 13.5.2 Data Frame Transmit Operation ---------------------------------------------------------------------------- 13-79 13.5.3 Transmit Abort Function -------------------------------------------------------------------------------------- 13-80 13.6 Receiving Data Frames ------------------------------------------------------------------------------------------------ 13-81 13.6.1 Data Frame Receive Procedure ---------------------------------------------------------------------------- 13-81 13.6.2 Data Frame Receive Operation ----------------------------------------------------------------------------- 13-82 13.6.3 Reading Out Received Data Frames ---------------------------------------------------------------------- 13-84 13.7 Transmitting Remote Frames ----------------------------------------------------------------------------------------- 13-86 13.7.1 Remote Frame Transmit Procedure ----------------------------------------------------------------------- 13-86 13.7.2 Remote Frame Transmit Operation ------------------------------------------------------------------------ 13-87 13.7.3 Reading Out Received Data Frames when Set for Remote Frame Transmission ------------- 13-89 13.8 Receiving Remote Frames -------------------------------------------------------------------------------------------- 13-91 13.8.1 Remote Frame Receive Procedure ------------------------------------------------------------------------ 13-91 13.8.2 Remote Frame Receive Operation ------------------------------------------------------------------------ 13-92 13.9 Precautions about CAN Module -------------------------------------------------------------------------------------- 13-94 CHAPTER 14 REAL TIME DEBUGGER (RTD) 14.1 Outline of the Real-Time Debugger (RTD) ------------------------------------------------------------------------ 14-2 14.2 Pin Functions of the RTD ---------------------------------------------------------------------------------------------- 14-3 14.3 Functional Description of the RTD ----------------------------------------------------------------------------------- 14-4 14.3.1 Outline of the RTD Operation ------------------------------------------------------------------------------ 14-4 14.3.2 Operation of RDR (Real-time RAM Content Output) ------------------------------------------------- 14-4 14.3.3 Operation of the WRR (RAM Content Forcible Rewrite) --------------------------------------------- 14-6 14.3.4 Operation of VER (Continuous Monitor) ----------------------------------------------------------------- 14-7 14.3.5 Operation of VEI (Interrupt Request) --------------------------------------------------------------------- 14-7 14.3.6 Operation of RCV (Recover from Runaway) ----------------------------------------------------------- 14-8 14.3.7 Method for Setting a Specified Address when Using the RTD ------------------------------------- 14-9 14.3.8 Resetting the RTD --------------------------------------------------------------------------------------------- 14-10 14.4 Typical Connection with the Host ------------------------------------------------------------------------------------ 14-11 CHAPTER 15 EXTERNAL BUS INTERFACE 15.1 Outline of the External Bus Interface ------------------------------------------------------------------------------- 15-2 15.1.1 External Bus Interface Related Signals ------------------------------------------------------------------ 15-2 15.2 External Bus Interface Related Registers ------------------------------------------------------------------------- 15-4 15.2.1 Port Operation Mode Registers ---------------------------------------------------------------------------- 15-4 15.2.2 Port Peripheral Output Select Register ------------------------------------------------------------------ 15-8 15.2.3 Bus Mode Control Register --------------------------------------------------------------------------------- 15-9 15.3 Read/Write Operations ------------------------------------------------------------------------------------------------- 15-10 15.4 Bus Arbitration ------------------------------------------------------------------------------------------------------------ 15-16 15.5 Typical Connection of External Extension Memory ------------------------------------------------------------- 15-18 15.6 Example of Bus Voltage Settings Using VCC-BUS ------------------------------------------------------------- 15-21 CHAPTER 16 WAIT CONTROLLER
(8)
16.1 Outline of the Wait Controller ----------------------------------------------------------------------------------------- 16-2 16.2 Wait Controller Related Registers ----------------------------------------------------------------------------------- 16-4 16.2.1 CS Area Wait Control Registers ---------------------------------------------------------------------------- 16-4 16.3 Typical Operation of the Wait Controller --------------------------------------------------------------------------- 16-6 CHAPTER 17 RAM BACKUP MODE 17.1 Outline of RAM Backup Mode ---------------------------------------------------------------------------------------- 17-2 17.2 Example of RAM Backup when Power is Down ----------------------------------------------------------------------- 17-3 17.2.1 Normal Operating State --------------------------------------------------------------------------------------- 17-3 17.2.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-4 17.3 Example of RAM Backup for Saving Power Consumption ---------------------------------------------------- 17-5 17.3.1 Normal Operating State --------------------------------------------------------------------------------------- 17-5 17.3.2 RAM Backup State --------------------------------------------------------------------------------------------- 17-6 17.3.3 Precautions to Be Observed at Power-On --------------------------------------------------------------- 17-7 17.4 Exiting RAM Backup Mode (Wakeup) ------------------------------------------------------------------------------ 17-8 CHAPTER 18 OSCILLATOR CIRCUIT 18.1 Oscillator Circuit ---------------------------------------------------------------------------------------------------------- 18-2 18.1.1 Example of an Oscillator Circuit ---------------------------------------------------------------------------- 18-2 18.1.2 XIN Oscillation Stoppage Detection Circuit -------------------------------------------------------------- 18-3 18.1.3 Oscillation Drive Capability Select Function ------------------------------------------------------------- 18-5 18.1.4 System Clock Output Function ------------------------------------------------------------------------------ 18-7 18.1.5 Oscillation Stabilization Time at Power-On -------------------------------------------------------------- 18-7 18.2 Clock Generator Circuit ------------------------------------------------------------------------------------------------ 18-8 CHAPTER 19 JTAG 19.1 Outline of JTAG ---------------------------------------------------------------------------------------------------------- 19-2 19.2 Configuration of the JTAG Circuit ------------------------------------------------------------------------------------ 19-3 19.3 JTAG Registers ---------------------------------------------------------------------------------------------------------- 19-4 19.3.1 Instruction Register (JTAGIR) ------------------------------------------------------------------------------- 19-4 19.3.2 Data Register ---------------------------------------------------------------------------------------------------- 19-5 19.4 Basic Operation of JTAG ---------------------------------------------------------------------------------------------- 19-6 19.4.1 Outline of JTAG Operation ----------------------------------------------------------------------------------- 19-6 19.4.2 IR Path Sequence ---------------------------------------------------------------------------------------------- 19-8 19.4.3 DR Path Sequence -------------------------------------------------------------------------------------------- 19-9 19.4.4 Inspecting and Setting Data Registers -------------------------------------------------------------------- 19-10 19.5 Boundary Scan Description Language ----------------------------------------------------------------------------- 19-11 19.6 Notes on Board Design when Connecting JTAG ---------------------------------------------------------------------- 19-12 19.7 Processing Pins when Not Using JTAG ---------------------------------------------------------------------------- 19-14 CHAPTER 20 POWER SUPPLY CIRCUIT 20.1 Configuration of the Power Supply Circuit ------------------------------------------------------------------------- 20-2 20.2 Power-On Sequence ---------------------------------------------------------------------------------------------------- 20-3 20.2.1 Power-On Sequence when Not Using RAM Backup -------------------------------------------------- 20-3 20.2.2 Power-On Sequence when Using RAM Backup -------------------------------------------------------- 20-4 20.3 Power-Off Sequence ---------------------------------------------------------------------------------------------------- 20-5 20.3.1 Power-Off Sequence when Not Using RAM Backup -------------------------------------------------- 20-5 20.3.2 Power-Off Sequence when Using RAM Backup ------------------------------------------------------- 20-6
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CHAPTER 21 ELECTRICAL CHARACTERISTICS 21.1 Absolute Maximum Ratings ------------------------------------------------------------------------------------------- 21-2 21.2 Electrical Characteristics when VCCE = 5 V, f(XIN) = 10 MHz ---------------------------------------------- 21-3 21.2.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 10 MHz) ------------------- 21-3 21.2.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) ----------------------------------------- 21-5 21.2.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 10 MHz) -------------------------- 21-6 21.3 Electrical Characteristics when VCCE = 5 V, f(XIN) = 8 MHz ------------------------------------------------ 21-7 21.3.1 Recommended Operating Conditions (when VCCE = 5 V, f(XIN) = 8 MHz) -------------------- 21-7 21.3.2 D.C. Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ------------------------------------------- 21-9 21.3.3 A-D Conversion Characteristics (when VCCE = 5 V, f(XIN) = 8 MHz) ---------------------------- 21-10 21.4 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 10 MHz -------------------------------------------- 21-11 21.4.1 Recommended Operating Conditions (when VCCE = 3.3 V 0.3 V, f(XIN) = 10 MHz) ------ 21-11 21.4.2 D.C. Characteristics (when VCCE = 3.3 V 0.3 V, f(XIN) = 10 MHz) ---------------------------- 21-13 21.4.3 A-D Conversion Characteristics (when VCCE = 3.3 V 0.3 V, f(XIN) = 10 MHz) ------------- 21-14 21.5 Electrical Characteristics when VCCE = 3.3 V, f(XIN) = 8 MHz ---------------------------------------------- 21-15 21.5.1 Recommended Operating Conditions (when VCCE = 3.3 V 0.3 V f(XIN) = 8 MHz) -------- 21-15 21.5.2 D.C. Characteristics (when VCCE = 3.3 V 0.3 V, f(XIN) = 8 MHz) ------------------------------ 21-17 21.5.3 A-D Conversion Characteristics (when VCCE = 3.3 V 0.3 V, f(XIN) = 8 MHz) --------------- 21-18 21.6 Flash Memory Related Characteristics ----------------------------------------------------------------------------- 21-19 21.7 A.C. Characteristics (when VCCE = 5 V) -------------------------------------------------------------------------- 21-20 21.7.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-20 21.7.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-24 21.7.3 A.C. Characteristics-------------------------------------------------------------------------------------------- 21-27 21.8 A.C. Characteristics (when VCCE = 3.3 V) ----------------------------------------------------------------------- 21-36 21.8.1 Timing Requirements ------------------------------------------------------------------------------------------ 21-36 21.8.2 Switching Characteristics ------------------------------------------------------------------------------------- 21-40 21.8.3 A.C. Characteristics-------------------------------------------------------------------------------------------- 21-43 CHAPTER 22 TYPICAL CHARACTERISTICS To be written at a later time --------------------------------------------------------------------------------------------------- 22-2
APPENDIX 1 MECHANICAL SPECIFICAITONS Appendix 1.1 Dimensional Outline Drawing ------------------------------------------------------------------- Appendix 1-2
APPENDIX 2 INSTRUCTION PROCESSING TIME Appendix 2.1 32180 Instruction Processing Time ------------------------------------------------------------ Appendix 2-2
APPENDIX 3 PROCESSING OF UNUSED PINS Appendix 3.1 Example Processing of Unused Pins ---------------------------------------------------------- Appendix 3-2
APPENDIX 4 SUMMARY OF PRECAUTIONS
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Appendix 4.1 Precautions about the CPU -------------------------------------------------------------------------Appendix 4.1.1 Precautions Regarding Data Transfer -----------------------------------------------Appendix 4.2 Precautions about the Address Space -----------------------------------------------------------------Appendix 4.2.1 Virtual Flash Emulation Function ------------------------------------------------------Appendix 4.3 Precautions about EIT -----------------------------------------------------------------------------------Appendix 4.4 Precautions To Be Observed when Programming Internal Flash Memory -------------------------Appendix 4.5 Precautions to Be Observed after Reset ---------------------------------------------------------------Appendix 4.5.1 Input/output Ports -------------------------------------------------------------------------Appendix 4.6 Precautions about Input/Output Ports ------------------------------------------------------------------Appendix 4.6.1 When Using Input/Output Ports in Output Mode ----------------------------------Appendix 4.6.2 About the Port Input Disable Function -----------------------------------------------Appendix 4.7 Precautions about the DMAC -------------------------------------------------------------------------Appendix 4.7.1 About Writing to the DMAC Related Registers ------------------------------------Appendix 4.7.2 Manipulating the DMAC Related Registers by DMA Transfer -----------------Appendix 4.7.3 About the DMA Interrupt Request Status Register -------------------------------Appendix 4.7.4 About the Stable Operation of DMA Transfer --------------------------------------Appendix 4.8 Precautions about the Multijunction Timers -----------------------------------------------------------Appendix 4.8.1 Precautions on Using TOP Single-Shot Output Mode ---------------------------Appendix 4.8.2 Precautions on Using TOP Delayed Single-Shot Output Mode ---------------Appendix 4.8.3 Precautions on Using TOP Continuous Output Mode ---------------------------Appendix 4.8.4 Precautions on Using TIO Measure Free-Run/Clear Input Modes -----------Appendix 4.8.5 Precautions on Using TIO PWM Output Mode ------------------------------------Appendix 4.8.6 Precautions on Using TIO Single-Shot Output Mode ----------------------------Appendix 4.8.7 Precautions on Using TIO Delayed Single-Shot Output Mode ----------------Appendix 4.8.8 Precautions on Using TIO Continuous Output Mode -----------------------------Appendix 4.8.9 Precautions on Using TMS Measure Input -----------------------------------------Appendix 4.8.10 Precautions on Using TML Measure Input -------------------------------------------
Appendix 4-2 Appendix 4-2 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-3 Appendix 4-4 Appendix 4-4 Appendix 4-4 Appendix 4-4 Appendix 4-4 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-5 Appendix 4-6 Appendix 4-6 Appendix 4-8 Appendix 4-9 Appendix 4-9 Appendix 4-9 Appendix 4-9 Appendix 4-10 Appendix 4-10 Appendix 4-10 Appendix 4-11
Appendix 4.8.11 Precautions on Using TOU PWM Output Mode ------------------------------------ Appendix 4-12 Appendix 4.8.12 Precautions on Using TOU Single-Shot PWM Output Mode -------------------- Appendix 4-12 Appendix 4.8.13 Precautions on Using TOU Delayed Single-Shot Output Mode ---------------Appendix 4.8.14 Precautions on Using TOU Single-Shot Output Mode ---------------------------Appendix 4.8.15 Precautions on Using TOU Continuous Output Mode ---------------------------Appendix 4.9 Precautions about the A-D Converters ---------------------------------------------------------------Appendix 4.10 Precautions about Serial I/O ---------------------------------------------------------------------------Appendix 4.10.1 Precautions on Using CSIO Mode ---------------------------------------------------Appendix 4.10.2 Precautions on Using UART Mode --------------------------------------------------Appendix 4.11 Precautions about RAM Backup Mode --------------------------------------------------------------Appendix 4.11.1 Precautions to Be Observed at Power-On -----------------------------------------Appendix 4.12 Precautions about JTAG ------------------------------------------------------------------------------Appendix 4.12.1 Notes on Board Design when Connecting JTAG ---------------------------------Appendix 4.12.2 Processing Pins when Not Using JTAG --------------------------------------------Appendix 4.13 Precautions about Noise -------------------------------------------------------------------------------Appendix 4.13.1 Reduction of Wiring Length ------------------------------------------------------------Appendix 4.13.2 Inserting a Bypass Capacitor between VSS and VCC Lines ------------------Appendix 4.13.3 Processing Analog Input Pin Wiring -------------------------------------------------Appendix 4.13.4 Consideration about the Oscillator and VCNT Pin -------------------------------Appendix 4.13.5 Processing Input/Output Ports --------------------------------------------------------Appendix 4-12 Appendix 4-13 Appendix 4-13 Appendix 4-14 Appendix 4-17 Appendix 4-17 Appendix 4-18 Appendix 4-19 Appendix 4-19 Appendix 4-20 Appendix 4-20 Appendix 4-22 Appendix 4-23 Appendix 4-23 Appendix 4-26 Appendix 4-26 Appendix 4-27 Appendix 4-31
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CHAPTER 1 OVERVIEW
1.1 1.2 1.3 1.4 Outline of the 32180 Group Block Diagram Pin Functions Pin Assignments
1
1.1 Outline of the 32180 Group
OVERVIEW
1.1 Outline of the 32180 Group
The 32180 group (hereafter simply the 32180) belongs to the M32R/ECU series in the M32R family of Mitsubishi microcomputers. For details about the current development status of the 32180, please contact your nearest office of Mitsubishi or its distributor. Table 1.1.1 Product List
Type Name M32180F8VFP M32180F8TFP ROM Size 1 Mbyte 1 Mbyte RAM Size 48 Kbytes 48 Kbytes Package Type 240-pin QFP: 240P6Y-A (0.5 mm pitch) 240-pin QFP: 240P6Y-A (0.5 mm pitch) Operating Ambient Temperature -40C to 125C (@64 MHz) -40C to 85C (@80 MHz)
1.1.1 M32R Family CPU Core with Built-in FPU (M32R-FPU)
(1) Based on a RISC architecture * The 32180 is a group of 32-bit RISC single-chip microcomputers. The M32R-FPU in this group of microcomputers incorporates a fully IEEE 754-compliant, single-precision FPU in order to materialize the common instruction set and the high-precision arithmetic operation of the M32R CPU. The 32180 products listed in the above table are built around the M32R-FPU and incorporates flash memory, RAM and various peripheral functions, all integrated into a single chip. * The M32R-FPU is constructed based on a RISC architecture. Memory is accessed using load/store instructions, and various arithmetic/logic operations are executed using register-to-register operation instructions. * The internally has sixteen 32-bit general-purpose registers. The instruction set consists of 100 discrete instructions in total (83 instructions common to the M32R family plus 17 FPU and extended instructions). These instructions are either 16 bits or 32 bits long. * In addition to the ordinary load/store instructions, the M32R-FPU supports compound instructions such as Load & Address Update and Store & Address Update. These instructions help to speed up data transfers. (2) Five-stage pipelined processing * The M32R-FPU supports five-stage pipelined instruction processing consisting of Instruction Fetch, Decode, Execute, Memory Access and Write Back (processed in six stages when performing floating-point arithmetic). Not just load/store instructions and register-to-register operation instructions, but also floating-point arithmetic instructions and compound instructions such as Load & Address Update and Store & Address Update are executed in one CPUCLK period (which is equivalent to 12.5 ns when f(CPUCLK) = 80 MHz). * Although instructions are supplied to the execution stage in the order in which they were fetched, it is possible that if the load/store instruction supplied first is extended by wait cycles inserted in memory access, the subsequent register-to-register operation instruction will be executed before that instruction. Using such a facility, which is known as the "out-of-order-completion" mechanism, the M32RFPU is able to control instruction execution without wasting clock cycles. (3) Compact instruction code * The M32R-FPU supports two instruction formats: one 16 bits long, and one 32 bits long. Use of the 16-bit instruction format especially helps to suppress the code size of a program. * Moreover, the availability of 32-bit instructions makes programming easier and provides higher performance at the same clock speed than in architectures where the address space is segmented. For example, some 32-bit instructions allow control to jump to an address 32 Mbytes forward or backward from the currently executed address in one instruction, making programming easy.
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1.1.2 Built-in Multiplier/Accumulator
(1) Built-in high-speed multiplier
OVERVIEW
1.1 Outline of the 32180 Group
* The M32R-FPU contains a 32 bits x 16 bits high-speed multiplier which enables the M32R-FPU to execute a 32 bits x 32 bits integral multiplication instruction in three CPUCLK periods. (2) DSP-comparable sum-of-products instructions * The M32R-FPU supports the following four types of sum-of-products calculation instructions (or multiplication instructions) which each can be executed in one CPUCLK period using a 56-bit accumulator. (1) (2) (3) (4) 16 high-order bits of register x 16 high-order bits of register 16 low-order bits of register x 16 low-order bits of register All 32 bits of register x 16 high-order bits of register All 32 bits of register x 16 low-order bits of register
* The M32R-FPU has some special instructions to round the value stored in the accumulator to 16 or 32 bits or shift the accumulator value before storing in a register to have its digits adjusted. Because these instructions too are executed in one CPUCLK period, when used in combination with highspeed data transfer instructions such as Load & Address Update or Store & Address Update, they enable the M32R-FPU to exhibit superior data processing capability comparable to that of a DSP.
1.1.3 Built-in Single-precision FPU
* The M32R-FPU supports single-precision floating-point arithmetic fully compliant with IEEE 754 standards. Specifically, five exceptions specified in IEEE 754 standards (Inexact, Underflow, Division by Zero, Overflow and Invalid Operation) and four rounding modes (round to nearest, round toward 0, round toward + Infinity and round toward - Infinity) are supported. What's more, because generalpurpose registers are used to perform floating-point arithmetic, the overhead associated with transferring the operand data can be reduced.
1.1.4 Built-in Flash Memory and RAM
* The 32180 contains a RAM that can be accessed with zero wait state, allowing to design a high-speed embedded system. * The internal flash memory can be written to while mounted on a printed circuit board (on-board writing). Use of flash memory facilitates development work, because the chip used at the development stage can be used directly in mass-production, allowing for a smooth transition from prototype to mass-production without the need to change the printed circuit board. * The internal flash memory can be rewritten as many as 100 times. * The internal flash memory has a virtual flash emulation function, allowing the internal RAM to be superficially mapped into part of the internal flash memory. When combined with the internal RealTime Debugger (RTD) and the M32R family's common debug interface (Scalable Debug Interface or SDI), this function makes the ROM table data tuning easy. * The internal RAM can be accessed for reading or rewriting data from an external device independently of the M32R-FPU by using the Real-Time Debugger. The external device is communicated using the Real-Time Debugger's exclusive clock-synchronized serial I/O.
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1.1.5 Built-in Clock Frequency Multiplier
OVERVIEW
1.1 Outline of the 32180 Group
* The 32180 contains a clock frequency multiplier, which is schematically shown in Figure 1.1.1 below.
XIN pin (8MHz-10MHz)
X8 PLL 1/4
CPUCLK (CPU clock) (64MHz-80MHz) BCLK (peripheral clock) (16MHz-20MHz)
Figure 1.1.1 Conceptual Diagram of the Clock Frequency Multiplier Table 1.1.2 Clock
Functional Block CPUCLK BCLK Clock output (BCLK pin output) Features * CPU clock: Defined as f(CPUCLK) when it indicates the operating clock frequency for the M32R-FPU core, internal flash memory and internal RAM. * Peripheral clock: Defined as f(BCLK) when it indicates the operating clock frequency for the internal peripheral I/O and external data bus. * A clock with the same frequency as f(BCLK) is output from this pin.
1.1.6 Powerful Peripheral Functions Built-in
(1) Multijunction timer (MJT) (2) 10-channel DMAC (3) Two 16-channel A-D converters (ADC) (4) 6-channel high-speed serial I/O (SIO) (5) Real-time debugger (RTD) (6) 8-level interrupt controller (ICU) (7) Three operation modes (8) Wait controller (9) 2-channel Full-CAN (10) M32R family's common debug function (Scalable Debug Interface or SDI)
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1.2 Block Diagram
OVERVIEW
1.2 Block Diagram
Figure 1.2.1 shows a block diagram of the 32180. The features of each block are described in Table 1.2.1.
M32R-FPU Core (80 MHz)
Multiplier/Accumulator (32 bits x 16 bits + 56 bits)
Internal Bus Interface DMAC (10 channels)
Internal 32-bit bus
Single-precision FPU (fully IEEE 754 compliant)
Multijunction Timer (64 channels)
Internal 32-bit bus
A-D Converter x 2
(A-D0 : 10-bit converter, 16 channels) (A-D1 : 10-bit converter, 16 channels)
Internal Flash Memory
(1 Mbytes = 1,024 Kbytes)
Internal 16-bit bus
Serial I/O (6 channels)
Internal RAM (48 Kbytes)
Interrupt Controller (32 sources, 8 levels)
Real-Time Debugger (RTD)
Wait Controller
PLL Clock Generator External Bus Interface Data
Full CAN (2 channels)
Internal Power Supply Generator (VDC)
Address
Input/output ports, 158 lines
Figure 1.2.1 Block Diagram of the 32180
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Table 1.2.1 Features of the 32180 (1/2)
Functional Block M32R-FPU CPU core Features performing floating-point arithmetic) * Internal 32-bit structure of the core * Register configuration General-purpose registers: 32 bits x 16 registers Control registers: 32 bits x 6 registers * Instruction set 16 and 32-bit instruction formats 100 discrete instructions and six addressing modes * Internal multiplier/accumulator (32 bits x 16 bits + 56 bits) * Internal single-precision floating-point arithmetic unit (FPU) RAM * Capacity: 48 Kbytes, accessible with zero wait state
OVERVIEW
1.2 Block Diagram
* Implementation: Five-stage pipelined instruction processing (processed in six stages when
* The internal RAM can be accessed for reading or rewriting data from the outside independently of the M32R-FPU by using the Real-Time Debugger, without ever causing the CPU performance to decrease. Flash memory Bus specification * Capacity: 1 Mbytes (1,024 Kbytes), accessible with one wait state * Durability: Rewritable 100 times * Fundamental bus cycle: 12.5 ns (when f(CPUCLK = 80 MHz) * Logical address space : 4 Gbytes linear * Internal bus specification : Internal 32-bit data bus (for CPU <-> internal flash memory and RAM access) (or accessed in 64 bits when accessing the internal flash memory for instructions) : Internal 16-bit data bus (for internal peripheral I/O access) * External area: Maximum 8 Mbytes (during processor mode) * Extended external area: Maximum 8 Mbytes (1 Mbytes + 2 Mbytes x 3 blocks during external extension mode) * External data address: 20-bit address * External data bus: 16-bit data bus * Shortest external bus access: 1 BCLK period during read, 1 BCLK period during write Multijunction timer (MJT) * 64-channel multi-functional timer 16-bit output related timer x 11 channels, 16-bit input/output related timer x 10 channels, 16-bit input related timer x 8 channels, 32-bit input related timer x 8 channels, 16-bit input related up/down timer x 3 channels, and 24-bit output related timer x 24 channels * Flexible timer configuration is possible by interconnecting these timer channels. * Interrupt request: Counter underflow or overflow and rising or falling or both edges or high or low level from the TIN pin (These can be used as external interrupt inputs irrespective of timer operation.) * DMA transfer request: Counter underflow or overflow and rising or falling or both edges or high or low level from the TIN pin (These can be used as external DMA transfer request inputs irrespective of timer DMAC operation.) * Number of channels: 10 * Transfers between internal peripheral I/O's or internal RAM's or between internal peripheral I/O and internal RAM are supported. * Capable of advanced DMA transfers when used in combination with internal peripheral I/O * Transfer request: Software or internal peripheral I/O (A-D converter, MJT, serial I/O or CAN) * DMA channels can be cascaded. (DMA transfer on a channel can be started by completion of a transfer on another channel.) * Interrupt request: DMA transfer counter register underflow
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Table 1.2.1 Features of the 32180 (2/2)
Functional Block A-D converter (ADC) Features * 16 channels: 10-bit resolution A-D converter x 2 blocks
OVERVIEW
1.2 Block Diagram
* Conversion modes: Ordinary conversion modes plus comparator mode * Operation modes: Single conversion mode and n-channel scan mode (n = 1-16) * Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary. * A-D disconnection detection assist function: Influences of the analog input voltage wrapping around from any preceding channel during scan mode operation are suppressed. * An inflow current bypass circuit is built-in. * Can generate an interrupt or start DMA transfer upon completion of A-D conversion. * Either 8 or 10-bit conversion results can be read out. * Interrupt request: Completion of A-D conversion * DMA transfer request: Completion of A-D conversion Serial I/O (SIO) * 6-channel serial I/O * Can be chosen to be clock-synchronized serial I/O or UART. * Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or 156 Kbits per second during UART mode when f(BCLK) = 20 MHz). * Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed * DMA transfer request: Reception completed or transmit buffer empty CAN * 16 message slots x 2 blocks * Compliant with CAN specification 2.0B active. * Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off or single shot * DMA transfer request: Failed to send, transmission completed or reception completed Real-Time Debugger (RTD) * Internal RAM can be rewritten or monitored independently of the CPU by entering a command from the outside. * Comes with exclusive clock-synchronized serial ports. * Interrupt request: RTD interrupt command input Interrupt Controller (ICU) * Controls interrupt requests from the internal peripheral I/O. * Supports 8-level interrupt priority including an interrupt disabled state. * External interrupt: 35 sources (SBI# and TIN0-TIN33) * TIN pin input sensing: Rising, falling or both edges or high or low level Wait Controller PLL Clock * Controls wait states for access to the extended external area. * Insertion of 0-7 wait states by setting up in software + wait state extension by entering WAIT# signal * A multiply-by-8 clock generating circuit * Maximum external input clock frequency (XIN) is 10.0 MHz. (Note 1) * CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM The maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz). * BCLK: Operating clock for the internal peripheral I/O and external data bus The maximum peripheral clock is 20 MHz (peripheral module access when f(XIN) = 10 MHz). * Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin. JTAG VDC Ports * Boundary scan function * Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an external single power supply (5 or 3.3 V). * Input/output pins: 158 pins * The port input threshold can be set in a program to one of three levels individually for each port group (with or without Schmitt circuit, selectable). Note 1: The maximum external input clock frequency (XIN) for the M32180F8VFP is 8.0 MHz.
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1.3 Pin Functions
OVERVIEW
1.3 Pin Functions
Figure 1.3.1 shows the 32180's pin function diagram. Pin functions are described in Table 1.3.1.
OSC-VCC
XIN XOUT Clock VCNT OSC-VCC OSC-VSS Reset Mode Port 0 Port 1 Port 2 Port 3 Address bus RESET# MOD0 MOD1 FP P00/DB0-P07/DB7 P10/DB8-P17/DB15 P20/A23-P27/A30 P30/A15-P37/A22 P41/BLW#/BLE# P42/BHW#/BHE# Port 4 P43/RD# P44/CS0# P45/CS1# P46/A13, P47/A14 P61-P63 Serial I/O Port 6 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 2 3 8 8 8 2
5
P93/TO16-P97/TO20 P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1
Port 9 Serial I/O Port 10 CAN Port 11 Port 12 Multijunction timer
5
VCCE
P103/TO11-P107/TO15 P110/TO0-P117/TO7 P124/TCLK0-P127/TCLK3 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 Port 13
8 4
Data bus
6 8
VCC-BUS
P132/TIN18-P137/TIN23 P140/TIN8-P147/TIN15 P150/TIN0-P157/TIN7 P160/TO21-P167/TO28 P172/TIN24, P173/TIN25 P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 Port 17 Serial I/O Port 14 Port 15 Port 16
8
8 8 2
VCCE
Bus control
M32180F8VFP, M32180F8TFP
8 7
P180/TO29-P187/TO36 P190/TIN26-P196/TIN32 P197/TIN33/PWMOFF2 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5
Port 18 Port 19 Multijunction timer
VCC-BUS
P70/BCLK/WR# Bus control Port 7 RTD P71/WAIT# P72/HREQ# P73/HACK# P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK
VCCE
Port 20
Serial I/O
8
P210/TO37-P217/TO44 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1
Port 21
Multijunction timer
CAN Port 22 Address bus Bus control
VCCE
P82/TXD0 P83/RXD0 Serial I/O Port 8 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 Interrupt controller SBI# AD0IN0-AD0IN15 AD1IN0-AD1IN15 A-D converter AVCC0, AVCC1 AVSS0, AVSS1 VREF0, VREF1 VDDE EXCVDD VCC-BUS 4 16 16 2 2 2
VCC-BUS
P224/A11/CS2# P225/A12/CS3# P226/CS2# P227/CS3# JTMS
VCCE
JTCK JTRST JTDO JTDI 13 7 2 VSS VCCE EXCVCC JTAG
Notes: * The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low. * VCCE : Operates with the VCCE power supply. VCC-BUS : Operates with the VCC-BUS power supply. OSC-VCC : Operates with the OSC-VCC power supply.
Figure 1.3.1 Pin Function Diagram
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Table 1.3.1 Description of Pin Functions (1/5)
Type Power supply Pin Name VCCE EXCVCC VCC-BUS VDDE EXCVDD VSS Clock XIN, XOUT Signal Name Main power supply Bus power supply RAM power supply Internal power supply of RAM Ground Clock input Clock output - Input Output Input/Output Description - - - - Internal power supply -
OVERVIEW
1.3 Pin Functions
Power supply for the device (5.0 V 0.5 V or 3.3 V 0.3 V). This pin connects an external capacitor. Power supply for the bus control pins (5.0 V 0.5 V or 3.3 V 0.3 V). Backup power supply for the internal RAM (5.0 V 0.5 V or 3.3 V 0.3 V). This pin connects an external capacitor for the internal power supply of the internal RAM. Connect all VSS pins to ground (GND). These are clock input/output pins. A PLL-based x8 frequency multiplier is included, which accepts as input a clock whose frequency is 1/8 of the internal CPU clock frequency. (XIN input is 10 MHz when f(CPUCLK) = 80 MHz.)
BCLK
System clock
Output
This pin outputs a clock whose frequency is twice that of the external input clock (XIN). (BCLK output is 20 MHz when f(CPUCLK) = 80 MHz.) Use this clock to synchronize the operation of external devices.
OSC-VCC OSC-VSS VCNT Reset Mode RESET# MOD0, MOD1
Clock power supply - Clock ground PLL control Reset Mode - - Input Input
Power supply for the oscillator circuit. Connect OSC-VCC to the main power supply. Connect OSC-VSS to ground. Connect a resistor and capacitor for control of the PLL circuit. Reset input pin for the internal circuit. Set the microcomputer's operation mode. MOD0 0 0 1 1 MOD1 0 1 0 1 Mode Single-chip mode External extension mode Processor mode (Boot mode) (Note 1) (Settings inhibited)
Flash protect Address bus
FP A11-A30
Flash protect Address bus
Input Output
This special pin protects the flash memory against rewrites in hardware. Twenty address lines (A11-A30) are included, allowing four blocks each up to 2 MB memory space to be connected external to the chip. A31 is not output.
Note 1: Boot mode requires that the FP pin should be at the high level. For details about boot mode, see Chapter 6, "Internal Memory."
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Table 1.3.1 Description of Pin Functions (2/5)
Type Data bus Pin Name DB0-DB15 Signal Name Data bus Input/Output Description
OVERVIEW
1.3 Pin Functions
Input/output This 16-bit data bus is used to connect external devices. When writing in byte units during a write cycle, the output data at the invalid byte position is undefined. During a read cycle, data on the entire 16-bit bus is always read in. However, only the data at the valid byte position is transferred into the internal circuit.
Bus control
CS0#-CS3# Chip select RD# WR# Read Write
Output Output Output Output
These are chip select signals for external devices. This signal is output when reading an external device. This signal is output when writing to an external device. When writing to an external device, this signal indicates the valid byte position to which data is transferred. BHW# and BLW# correspond to the upper address side (bits 0-7 are valid) and the lower address side (bits 8-15 are valid), respectively.
BHW#/BLW# Byte high/low write
BHE# BLE# WAIT# HREQ#
Byte high enable Byte low enable Wait Hold request
Output Output Input Input
During an external device access, this signal indicates that the high-order data (bits 0-7) is valid. During an external device access, this signal indicates that the low-order data (bits 8-15) is valid. When accessing an external device, a low-level input on WAIT# pin extends the wait cycle. This input is used by an external device to request control of the external bus. A low-level input on HREQ# pin places the CPU in a hold state.
HACK# Multijunction timer
Hold acknowledge
Output Input Output Input
This signal notifies that the CPU has entered a hold state and relinquished control of the external bus. Input pins for the multijunction timer. Output pins for the multijunction timer. Clock input pins for the multijunction timer.
TIN0-TIN33 Timer input TO0-TO44 TCLK0 -TCLK3 Timer output Timer clock
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Table 1.3.1 Description of Pin Functions (3/5)
Type A-D converter Pin Name AVCC0, AVCC1 AVSS0, AVSS1 AD0IN0 -AD0IN15 AD1IN0 -AD1IN15 VREF0, VREF1 Interrupt controller Serial I/O SCLKI0/ SCLKO0 SBI# Reference voltage input System break interrupt clock output or CSIO transmit/receive clock input/output Input Input Analog input Input Analog input Input Analog ground - Signal Name Input/Output Description Analog power supply -
OVERVIEW
1.3 Pin Functions
AVCC0 and AVCC1 are the power supply for the A-D0 and the A-D1 converter, respectively. Connect AVCC0 and AVCC1 to the power supply rail. AVSS0 and AVSS1 are the analog ground for the A-D0 and the A-D1 converter, respectively. Connect AVSS0 and AVSS1 to ground. 16-channel analog input pins for the A-D0 converter, i.e., the first block A-D converter. 16-channel analog input pins for the A-D1 converter, i.e., the second block A-D converter. VREF0 and VREF1 are the reference voltage input pin for the A-D0 and the A-D1 converter, respectively. This is the system break interrupt (SBI) input pin for the interrupt controller. This pin outputs a clock derived from BRG output by dividing it by 2. When channel 0 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected.
UART transmit/receive Input/output When channel 0 is in UART mode:
SCLKI1/ SCLKO1
UART transmit/receive Input/output When channel 1 is in UART mode: clock output or CSIO transmit/receive clock input/output This pin outputs a clock derived from BRG output by dividing it by 2. When channel 1 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected.
SCLKI4/ SCLKO4
UART transmit/receive Input/output When channel 4 is in UART mode: clock output or CSIO transmit/receive clock input/output This pin outputs a clock derived from BRG output by dividing it by 2. When channel 4 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected.
SCLKI5/ SCLKO5
UART transmit/receive Input/output When channel 5 is in UART mode: clock output or CSIO transmit/receive clock input/output This pin outputs a clock derived from BRG output by dividing it by 2. When channel 5 is in CSIO mode: This pin accepts as input a transmit/receive clock when external clock is selected or outputs a transmit/receive clock when internal clock is selected.
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Table 1.3.1 Description of Pin Functions (4/5)
Type Serial I/O Pin Name TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TXD4 RXD4 TXD5 RXD5 Real-time debugger (RTD) RTDTXD RTDRXD RTDCLK RTDACK Signal Name Transmit data Received data Transmit data Received data Transmit data Received data Transmit data Received data Transmit data Received data Transmit data Received data RTD transmit data RTD received data RTD clock input RTD acknowledge Input/Output Description Output Input Output Input Output Input Output Input Output Input Output Input Output Input Input Output
OVERVIEW
1.3 Pin Functions
Transmit data output pin for serial I/O channel 0. Received data input pin for serial I/O channel 0. Transmit data output pin for serial I/O channel 1. Received data input pin for serial I/O channel 1. Transmit data output pin for serial I/O channel 2. Received data input pin for serial I/O channel 2. Transmit data output pin for serial I/O channel 3. Received data input pin for serial I/O channel 3. Transmit data output pin for serial I/O channel 4. Received data input pin for serial I/O channel 4. Transmit data output pin for serial I/O channel 5. Received data input pin for serial I/O channel 5. Serial data output pin for the real-time debugger. Serial data input pin for the real-time debugger. Serial data transmit/receive clock input pin for the real-time debugger. A low-level pulse is output from this pin synchronously with the start clock for the real-time debugger's serial data output word. The low-level pulse width indicates the type of command/ data received by the real-time debugger.
CAN JTAG
CTX0, CTX1 Transmit data CRX0, CRX1 Received data JTMS JTCK JTRST JTDI JTDO Test mode select Test clock Test reset Test data input Test data output
Output Input Input Input Input Input Output
This pin outputs data from the CAN module. This pin accepts as input the data for the CAN module. Test mode select input to control the state transition of the test circuit. Clock input for the debug module and test circuit. Test reset input to initialize the test circuit asynchronously with device operation. This pin accepts as input the test instruction code or test data that is serially received. This pin outputs the test instruction code or test data serially.
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Table 1.3.1 Description of Pin Functions (5/5)
Type Input/output ports (Note 1) Pin Name P00-P07 P10-P17 P20-P27 P30-P37 P41-P47 P61-P63 P65-P67 P70-P77 P82-P87 P93-P97 P100-P107 P110-P117 P124-P127 P130-P137 P140-P147 P150-P157 P160-P167 P172-P177 P180-P187 P190-P197 P200-P203 P210-P217 P220-P227 Input/output port 7 Input/output port 8 Input/output port 9 Input/output port 10 Input/output port 11 Input/output port 12 Input/output port 13 Input/output port 14 Input/output port 15 Input/output port 16 Input/output port 17 Input/output port 18 Input/output port 19 Input/output port 20 Input/output port 21 Input/output port 22 Signal Name Input/output port 0 Input/output port 1 Input/output port 2 Input/output port 3 Input/output port 4 Input/output port 6 Input/Output Description Input/output Programmable input/output port.
OVERVIEW
1.3 Pin Functions
Note 1: Input/output port 5 is reserved for future use. P221 and P223 are input-only ports.
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1.4 Pin Assignments
OVERVIEW
1.4 Pin Assignments
Figure 1.4.1 shows the 32180's pin assignment diagram. A pin assignment table is shown in Table 1.4.1.
P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P173/TIN25 P172/TIN24 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 VSS P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 P210/TO37 P211/TO38 P212/TO39 P213/TO40 P214/TO41 P215/TO42 P216/TO43 P217/TO44 P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 VSS VCCE VCC-BUS P226/CS2# P227/CS3# P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 VSS P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS VCCE P93/TO16 P94/TO17 P95/TO18 P96/TO19
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
M32180F8VFP M32180F8TFP
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P147/TIN15 P146/TIN14 P145/TIN13 P144/TIN12 P143/TIN11 P142/TIN10 P141/TIN9 P140/TIN8 P197/TIN33/PWMOFF2 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VSS VCCE VSS VSS VSS SBI# P63 P62 P61 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 VSS VCCE
Note: * The symbol "#" suffixed to the pin (or signal) names means that the pins (or signals) are active-low.
Figure 1.4.1 Pin Assignment Diagram of the 240QFP (Top View)
AVCC1 VSS VCCE P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Package: 240P6Y-A (0.5-mm pitch)
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OVERVIEW
1.4 Pin Assignments
The pins directed for input go to a high-impedance state (Hi-z) when reset. The term "when reset" means that input on RESET# pin is held low (the device remains reset), and that the RESET# pin is released back high (the device comes out of reset). Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (1/6)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVCC1 VSS VCCE P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI (Note 1) JTDO (Note 1) JTRST (Note 1) Function Symbol Port P150 P151 P152 P153 P154 P155 P156 P157 P200 P201 P202 P203 P130 P131 P132 P133 P134 P135 P136 P137 P220 P221 P222 P223 P180 P181 P182 P183 P184 P185 P186 P187 P74 P75 P76 P77 Other than port AVCC1 VSS VCCE TIN0 TIN1 TIN2 TIN3 TIN4 TIN5 TIN6 TIN7 TXD4 RXD4 TXD5 RXD5 TIN16/ PWMOFF0 TIN17/ PWMOFF1 TIN18 TIN19 TIN20 TIN21 TIN22 TIN23 CTX0 CRX0 CTX1 CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# TO29 TO30 TO31 TO32 TO33 TO34 TO35 TO36 RTDTXD RTDRXD RTDACK RTDCLK JTDI JTDO JTRST Other than port Type Condition Function Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input/output Input Input Output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Output Input AVCC1 VSS VCCE P150 P151 P152 P153 P154 P155 P156 P157 P200 P201 P202 P203 P130 P131 P132 P133 P134 P135 P136 P137 P220 P221 P222 P223 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180 P181 P182 P183 P184 P185 P186 P187 P74 P75 P76 P77 JTDI JTDO JTRST Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Pin State When Reset State during reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z XOUT Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State at reset release Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z XOUT Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z
Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.
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Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (2/6)
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Function Symbol Port JTCK (Note 1) JTMS (Note 1) P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15 VCCE VSS AVCC0 VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AVSS0 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 P61 P62 P63 SBI# VSS VSS VSS VCCE VSS EXCVCC P124/TCLK0 P125/TCLK1 P126/TCLK2 P127/TCLK3 P190/TIN26 P191/TIN27 P192/TIN28 P193/TIN29 P100 P101 P102 P103 P104 P105 P106 P107 P61 P62 P63 P124 P125 P126 P127 P190 P191 P192 P193 P194 Other than port JTCK JTMS TO8 TO9 TO10 TO11 TO12 TO13 TO14 TO15 VCCE VSS AVCC0 VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AVSS0 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 SBI# VSS VSS VSS VCCE VSS EXCVCC TCLK0 TCLK1 TCLK2 TCLK3 TIN26 TIN27 TIN28 TIN29 TIN30 Other than port TXD3 CTX1 Type Condition Function Input Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input/output Input/output Input/output Input Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output JTCK JTMS P100 P101 P102 P103 P104 P105 P106 P107 VCCE VSS AVCC0 VREF0 AD0IN0 AD0IN1 AD0IN2 AD0IN3 AD0IN4 AD0IN5 AD0IN6 AD0IN7 AVSS0 AD0IN8 AD0IN9 AD0IN10 AD0IN11 AD0IN12 AD0IN13 AD0IN14 AD0IN15 P61 P62 P63 SBI# VSS VSS VSS VCCE VSS EXCVCC P124 P125 P126 P127 P190 P191 P192 P193 P194
OVERVIEW
1.4 Pin Assignments
Pin State When Reset Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input State during reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State at reset release Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z
100 P194/TIN30
Note 1: The JTCK, JTDI, JTDO and JTMS pins are reset by input from the JTRST pin, and not reset from the RESET# pin.
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Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (3/6)
Pin No. Function Symbol Port P195 P196 P197 P140 P141 P142 P143 P144 P145 P146 P147 P110 P111 P112 P113 P114 P115 P116 P117 P97 P96 P95 P94 P93 P27 Other than port TIN31 TIN32 TIN33/ PWMOFF2 TIN8 TIN9 TIN10 TIN11 TIN12 TIN13 TIN14 TIN15 TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TO20 TO19 TO18 TO17 TO16 VCCE VSS VCC-BUS A30 Other than port Type Condition Function Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 130 P25/A28 P25 A28 Input/output During single-chip and external extension modes During processor mode 131 P24/A27 P24 A27 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 134 P21/A24 P21 A24 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 136 VSS 137 P37/A22 P37 VSS A22 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode P195 P196 P197 P140 P141 P142 P143 P144 P145 P146 P147 P110 P111 P112 P113 P114 P115 P116 P117 P97 P96 P95 P94 P93 VCCE VSS VCC-BUS P27 A30 P26 A29 P25 A28 P24 A27 P23 A26 P22 A25 P21 A24 P20 A23 VSS P37 A22 P36 A21 P35 A20 101 P195/TIN31 102 P196/TIN32 103 P197/TIN33/PWMOFF2 104 P140/TIN8 105 P141/TIN9 106 P142/TIN10 107 P143/TIN11 108 P144/TIN12 109 P145/TIN13 110 P146/TIN14 111 P147/TIN15 112 P110/TO0 113 P111/TO1 114 P112/TO2 115 P113/TO3 116 P114/TO4 117 P115/TO5 118 P116/TO6 119 P117/TO7 120 P97/TO20 121 P96/TO19 122 P95/TO18 123 P94/TO17 124 P93/TO16 125 VCCE 126 VSS 127 VCC-BUS 128 P27/A30
OVERVIEW
1.4 Pin Assignments
Pin State When Reset Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output State during reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State at reset release Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined
129 P26/A29
P26
A29
-
Input/output
132 P23/A26
P23
A26
-
Input/output
133 P22/A25
P22
A25
-
Input/output
135 P20/A23
P20
A23
-
Input/output
138 P36/A21
P36
A21
-
Input/output
139 P35/A20
P35
A20
-
Input/output
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Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (4/6)
Pin No. Function Symbol Port Other than port A19 Other than port Type Condition Function During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 145 P47/A14 P47 A14 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 149 P45/CS1# P45 CS1# Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 153 VCC-BUS 154 VCCE 155 VSS 156 P167/TO28 157 P166/TO27 158 P165/TO26 159 P164/TO25 160 P163/TO24 161 P162/TO23 162 P161/TO22 163 P160/TO21 164 P217/TO44 165 P216/TO43 166 P215/TO42 167 P214/TO41 168 P213/TO40 169 P212/TO39 170 P211/TO38 171 P210/TO37 172 P67 173 P66/SCLKI5/SCLKO5 174 P65/SCLKI4/SCLKO4 175 P87/SCLKI1/SCLKO1 P167 P166 P165 P164 P163 P162 P161 P160 P217 P216 P215 P214 P213 P212 P211 P210 P67 P66 P65 P87 VCC-BUS VCCE VSS TO28 TO27 TO26 TO25 TO24 TO23 TO22 TO21 TO44 TO43 TO42 TO41 TO40 TO39 TO38 TO37 SCLKI5 SCLKI4 SCLKI1 SCLKO5 SCLKO4 SCLKO1 Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output P34 A19 P33 A18 P32 A17 P31 A16 P30 A15 P47 A14 P46 A13 P225 A12 P224 A11 P45 CS1# P44 CS0# P227 CS3# P226 CS2# VCC-BUS VCCE VSS P167 P166 P165 P164 P163 P162 P161 P160 P217 P216 P215 P214 P213 P212 P211 P210 P67 P66 P65 P87
OVERVIEW
1.4 Pin Assignments
Pin State When Reset Type Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input State during reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State at reset release Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z Undefined Hi-z High level Hi-z High level Hi-z High level Hi-z High level Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z
140 P34/A19
P34
Input/output
141 P33/A18
P33
A18
-
Input/output
142 P32/A17
P32
A17
-
Input/output
143 P31/A16
P31
A16
-
Input/output
144 P30/A15
P30
A15
-
Input/output
146 P46/A13
P46
A13
-
Input/output
147 P225/A12/CS3#
P225
A12
CS3#
Input/output
148 P224/A11/CS2#
P224
A11
CS2#
Input/output
150 P44/CS0#
P44
CS0#
-
Input/output
151 P227/CS3#
P227
CS3#
-
Input/output
152 P226/CS2#
P226
CS2#
-
Input/output
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1
Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (5/6)
Pin No. 176 P86/RXD1 Function Symbol Port P86 P85 P84 P83 P82 P174 P175 P176 P177 P173 P172 P17 Other than port RXD1 TXD1 SCLKI0 RXD0 TXD0 TXD2 RXD2 TXD3 RXD3 TIN25 TIN24 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS DB15 Other than port SCLKO0 Type Condition Function Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input/output Input Input Input Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 202 P12/DB10 P12 DB10 Input/output During single-chip and external extension modes During processor mode 203 P11/DB9 P11 DB9 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 205 P07/DB7 P07 DB7 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 207 P05/DB5 P05 DB5 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 209 P03/DB3 P03 DB3 Input/output During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode P86 P85 P84 P83 P82 P174 P175 P176 P177 P173 P172 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS P17 DB15 P16 DB14 P15 DB13 P14 DB12 P13 DB11 P12 DB10 P11 DB9 P10 DB8 P07 DB7 P06 DB6 P05 DB5 P04 DB4 P03 DB3 P02 DB2
OVERVIEW
1.4 Pin Assignments
Pin State When Reset Type Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output Input Input/output State during reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State at reset release Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z
177 P85/TXD1 178 P84/SCLKI0/SCLKO0 179 P83/RXD0 180 P82/TXD0 181 P174/TXD2 182 P175/RXD2 183 P176/TXD3 184 P177/RXD3 185 P173/TIN25 186 P172/TIN24 187 FP 188 MOD0 189 MOD1 190 EXCVDD 191 VSS 192 EXCVCC 193 VDDE 194 VSS 195 VCCE 196 VCC-BUS 197 P17/DB15
198 P16/DB14
P16
DB14
-
Input/output
199 P15/DB13
P15
DB13
-
Input/output
200 P14/DB12
P14
DB12
-
Input/output
201 P13/DB11
P13
DB11
-
Input/output
204 P10/DB8
P10
DB8
-
Input/output
206 P06/DB6
P06
DB6
-
Input/output
208 P04/DB4
P04
DB4
-
Input/output
210 P02/DB2
P02
DB2
-
Input/output
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Table 1.4.1 Pin Assignments of the M32180F8VFP/TFP (6/6)
Pin No. Function Symbol Port Other than port DB1 Other than port Type Condition Function During single-chip and external extension modes During processor mode During single-chip and external extension modes During processor mode 213 VSS 214 P73/HACK# 215 P72/HREQ# 216 P71/WAIT# 217 P70/BCLK/WR# 218 P43/RD# P73 P72 P71 P70 P43 VSS HACK# HREQ# WAIT# BCLK RD# WR# Input/output Input/output Input/output Input/output Input/output During single-chip mode During external extension and processor modes P01 DB1 P00 DB0 VSS P73 P72 P71 P70 P43 RD#
OVERVIEW
1.4 Pin Assignments
Pin State When Reset Type Input Input/output Input Input/output Input Input Input Input Input Output Input Output Input Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input State during reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z State after reset Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z High level Hi-z High level Hi-z High level Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z Hi-z -
211 P01/DB1
P01
Input/output
212 P00/DB0
P00
DB0
-
Input/output
219 P42/BHW#/BHE#
P42
BHW#
BHE#
Input/output
During single-chip mode P42 During external extension and BHW#/BHE# processor modes During single-chip mode P41 BLW#/BLE# VCC-BUS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1 During external extension and processor modes
220 P41/BLW#/BLE# 221 VCC-BUS 222 VSS 223 AD1IN15 224 AD1IN14 225 AD1IN13 226 AD1IN12 227 AD1IN11 228 AD1IN10 229 AD1IN9 230 AD1IN8 231 AVSS1 232 AD1IN7 233 AD1IN6 234 AD1IN5 235 AD1IN4 236 AD1IN3 237 AD1IN2 238 AD1IN1 239 AD1IN0 240 VREF1
P41 -
BLW# VCC-BUS VSS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1
BLE# -
Input/output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input -
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CHAPTER 2 CPU
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 CPU Registers General-purpose Registers Control Registers Accumulator Program Counter Data Formats Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution Precautions on CPU
2
2.1 CPU Registers
CPU
2.1 CPU Registers
The M32R-FPU has 16 general-purpose registers, 6 control registers, an accumulator and a program counter. The accumulator is of 56-bit configuration, and all other registers are of 32-bit configuration.
2.2 General-purpose Registers
The 16 general-purpose registers (R0-R15) are of 32-bit width and are used to retain data and base address, as well as for integer calculations, floating-point operations, etc. R14 is used as the link register and R15 as the stack pointer. The link register is used to store the return address when executing a subroutine call instruction. The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) are alternately represented by R15 depending on the value of the Stack Mode (SM) bit in the Processor Status Word Register (PSW). After reset, the value of the general-purpose registers is undefined.
b0
b31
b0
b31
R0 R1 R2 R3 R4 R5 R6 R7
R8 R9 R10 R11 R12 R13 R14 (Link register) R15 (Stack pointer) (Note 1)
Note 1: The stack pointer functions as either the SPI or the SPU depending on the value of the SM bit in the PSW.
Figure 2.2.1 General-purpose Registers
2.3 Control Registers
There are 6 control registers which are the Processor Status Word Register (PSW), the Condition Bit Register (CBR), the Interrupt Stack Pointer (SPI), the User Stack Pointer (SPU), the Backup PC (BPC) and the Floatingpoint Status Register (FPSR). The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. In addition, the SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instruction.
CRn b0 CR0 CR1 CR2 CR3 CR6 CR7
b31
PSW CBR SPI SPU BPC FPSR
Processor Status Word Register Condition Bit Register Interrupt Stack Pointer User Stack Pointer Backup PC Floating-point Status Register
Notes: * CRn (n = 0-3, 6 and 7) denotes the control register number. * The dedicated MVTC and MVFC instructions are used for writing and reading these control registers. * The SM bit, IE bit and C bit of the PSW can also be set by the SETPSW or CLRPSW instructions.
Figure 2.3.1 Control Registers
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2.3.1 Processor Status Word Register: PSW (CR0)
b0
0
CPU
2.3 Control Registers
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
b16 BSM
?
17 BIE
?
18
0
19
0
20
0
21
0
22
0
23 BC
?
24 SM
0
25 IE
0
26
0
27
0
28
0
29
0
30
0
b31 C
0
BPSW field
PSW field
b 0-15 16 17 18-22 23 24 25 26-30 31 Bit Name No function assigned. Fix to "0". BSM Backup SM Bit BIE Backup IE Bit No function assigned. Fix to "0". BC Backup C Bit SM Stack Mode Bit IE Interrupt Enable Bit No function assigned. Fix to "0". C Condition Bit Indicates carry, borrow or overflow resulting from operations (instruction dependent) 0: Uses R15 as the interrupt stack pointer 1: Uses R15 as the user stack pointer 0: Does not accept interrupt 1: Accepts interrupt 0 R 0 W R R W W Saves value of C bit when EIT occurs Saves value of IE bit when EIT occurs R 0 R W 0 W Saves value of SM bit when EIT occurs Function R 0 R W 0 W
The Processor Status Word Register (PSW) indicates the M32R-FPU status. It consists of the current PSW field which is regularly used, and the BPSW field where a copy of the PSW field is saved when EIT occurs. The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and the Condition (C) bit. The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt Enable (BIE) bit and the Backup Condition (BC) bit. After reset, BSM, BIE and BC are undefined. All other bits are "0".
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2.3.2 Condition Bit Register: CBR (CR1)
CPU
2.3 Control Registers
The Condition Bit Register (CBR) is derived from the PSW register by extracting its Condition (C) bit. The value written to the PSW register's C bit is reflected in this register. The register can only be read. (Writing to the register with the MVTC instruction is ignored.) After reset, the value of CBR is H'0000 0000.
b0
b31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C
CBR
0
2.3.3 Interrupt Stack Pointer: SPI (CR2) and User Stack Pointer: SPU (CR3)
The Interrupt Stack Pointer (SPI) and the User Stack Pointer (SPU) retain the address of the current stack pointer. These registers can be accessed as the general-purpose register R15. R15 switches between representing the SPI and SPU depending on the value of the Stack Mode (SM) bit in the PSW. After reset, the values of the SPI and SPU are undefined.
b0
b31
SPI
SPI
b0
b31
SPU
SPU
2.3.4 Backup PC: BPC (CR6)
The Backup PC (BPC) is used to save the value of the Program Counter (PC) when an EIT occurs. Bit 31 is fixed to "0". When an EIT occurs, the register sets either the PC value when the EIT occurred or the PC value for the next instruction depending on the type of EIT. The BPC value is loaded to the PC when the RTE instruction is executed. However, the values of the lower 2 bits of the PC are always "00" when returned. (PC always returns to the word-aligned address.) After reset, the value of the BPC is undefined.
b0
b31
BPC
BPC
0
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2.3.5 Floating-point Status Register: FPSR (CR7)
b0 FS
0
CPU
2.3 Control Registers
1 FX
0
2 FU
0
3 FZ
0
4 FO
0
5 FV
0
6
0
7
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
b16
0
17 EX
0
18 EU
0
19 EZ
0
20 EO
0
21 EV
0
22
0
23 DN
1
24 CE
0
25 CX
0
26 CU
0
27 CZ
0
28 CO
0
29 CV
0
30
0
b31 RM
0
b 0 1 Bit Name Function R R R W - W
FS Reflects the logical sum of FU, FZ, FO and FV. Floating-point Exception Summary Bit FX Inexact Exception Flag Set to "1" when an inexact exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an underflow exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when a zero divide exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an overflow exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software. Set to "1" when an invalid operation exception occurs (if EIT processing is unexecuted (Note 1)). Once set, the flag retains the value "1" until it is cleared to "0" in software.
2
FU Underflow Exception Flag
R
W
3
FZ Zero Divide Exception Flag FO Overflow Exception Flag FV Invalid Operation Exception Flag No function assigned. Fix to "0". EX Inexact Exception Enable Bit EU Underflow Exception Enable Bit
R
W
4
R
W
5
R
W
6-16 17 18
0 0: Mask EIT processing to be executed when an inexact exception occurs. 1: Execute EIT processing when an inexact exception occurs. 0: Mask EIT processing to be executed when an underflow exception occurs. 1: Execute EIT processing when an underflow exception occurs. 0: Mask EIT processing to be executed when a zero divide exception occurs. 1: Execute EIT processing when a zero divide exception occurs. 0: Mask EIT processing to be executed when an overflow exception occurs. 1: Execute EIT processing when an overflow exception occurs. 0: Mask EIT processing to be executed when an invalid operation exception occurs. 1: Execute EIT processing when an invalid operation exception occurs. 0 0: Handle the denormalized number as a denormalized number. 1: Handle the denormalized number as zero. 0: No unimplemented operation exception occurred. 1: An unimplemented operation exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No inexact exception occurred. 1: An inexact exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". R R R R R R
0 W W
19
EZ Zero Divide Exception Enable Bit
W
20
EO Overflow Exception Enable Bit
W
21
EV Invalid Operation Exception Enable Bit
W
22 23
No function assigned. Fix to "0". DN Denormalized Number Zero Flush Bit (Note 2)
0 W
24
CE Unimplemented Operation Exception Cause Bit
R (Note 3)
25
CX Inexact Exception Cause Bit
R (Note 3)
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26 CU Underflow Exception Cause Bit 27 CZ Zero Divide Exception Cause Bit 28 CO Overflow Exception Cause Bit 29 CV 0: No underflow exception occurred 0: No zero divide exception occurred.
CPU
2.3 Control Registers
R (Note 3)
1: An underflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". R (Note 3) 1: A zero divide exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No overflow exception occurred. 1: An overflow exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 0: No invalid operation exception occurred. R (Note 3) R (Note 3)
Invalid Operation Exception Cause Bit 1: An invalid operation exception occurred. When the bit is set to "1", the execution of an FPU operation instruction will clear it to "0". 30, 31 RM Rounding Mode Selection Bit 00: Round to nearest 01: Round toward Zero 10: Round toward + Infinity 11: Round toward - Infinity Note 1: The phrase "If EIT processing unexecuted" means whenever one of the exceptions occurs, enable bits 17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two exceptions occur at the same time and their corresponding exception enable bits are set differently (one enabled, and the other masked), EIT processing is executed. In this case, these two flags do not change state regardless of the enable bits settings. Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented exception occurs. Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had before the write). R W
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2.4 Accumulator
CPU
2.4 Accumulator
The Accumulator (ACC) is a 56-bit register used for DSP function instructions. The accumulator is handled as a 64-bit register when accessed for read or write. When reading data from the accumulator, the value of bit 8 is sign-extended. When writing data to the accumulator, bits 0 to 7 are ignored. The accumulator is also used for the multiply instruction "MUL," in which case the accumulator value is destroyed by instruction execution. Use the MVTACHI and MVTACLO instructions for writing to the accumulator. The MVTACHI and MVTACLO instructions write data to the high-order 32 bits (bits 0-31) and the low-order 32 bits (bits 32-63), respectively. Use the MVFACHI, MVFACLO and MVFACMI instructions for reading data from the accumulator. The MVFACHI, MVFACLO and MVFACMI instructions read data from the high-order 32 bits (bits 0-31), the low-order 32 bits (bits 32-63) and the middle 32 bits (bits 16-47), respectively. After reset, the value of accumulator is undefined.
(Note 1)
b0 78 15 16
Read range of MVFACMI instruction
31 32 47 48 b63
ACC
Write and read ranges of MVTACHI and MVFACHI instructions
Write and read ranges of MVTACLO and MVFACLO instructions
Note 1: When read, bits 0 to 7 always show the sign-extended value of the value of bit 8. Writing to this bit field is ignored.
2.5 Program Counter
The Program Counter (PC) is a 32-bit counter that retains the address of the instruction being executed. Since the M32R FPU instruction starts with even-numbered addresses, the LSB (bit 31) is always "0". After reset, the value of PC is H'0000 0000.
b0
b31
PC
PC
0
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2.6 Data Formats
2.6.1 Data Types
CPU
2.6 Data Formats
The data types that can be handled by the M32R-FPU instruction set are signed or unsigned 8, 16 and 32-bit integers and single-precision floating-point numbers. The signed integers are represented by 2's complements.
b0
b7
Signed byte (8-bit) integer
S
b0 b7
Unsigned byte (8-bit) integer
b0 b15
Signed halfword (16-bit) integer Unsigned halfword (16-bit) integer
S
b0 b15
b0
b31
Signed word (32-bit) integer
S
b0 b31
Unsigned word (32-bit) integer
b0 b1 b8 b9 b31
Single-precision floating-point number
S
E
F
S: Sign bit; E: Exponent field; F: Fraction field
Figure 2.6.1 Data Types
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2.6.2 Data Formats
(1) Data formats in registers
CPU
2.6 Data Formats
The data sizes in the M32R-FPU registers are always words (32 bits). When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is sign-extended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) to a word (32-bit) quantity before being loaded in the register. When storing data from a register into a memory, the 32-bit data, the 16-bit data on the LSB side and the 8bit data on the LSB side of the register are stored into memory by the ST, STH and STB instructions, respectively.

b0
Sign-extended (LDB instruction) or zero-extended (LDUB instruction)
From memory (LDB, LDUB instructions)
24 b31
Rn
Sign-extended (LDH instruction) or
Byte
From memory (LDH, LDUH instructions)
b31
b0 zero-extended (LDUH instruction) 16
Rn
Halfword
From memory (LD instruction)
b0 b31
Rn
Word

b0 24 b31
Rn
Byte
To memory (STB instruction)
b0 16 b31
Rn
Halfword
To memory (STH instruction)
b0 b31
Rn
Word
To memory (ST instruction)
Figure 2.6.2 Data Formats in Registers
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(2) Data formats in memory
CPU
2.6 Data Formats
The data sizes in memory can be byte (8 bits), halfword (16 bits) or word (32 bits). Although byte data can be located at any address, halfword and word data must be located at the addresses aligned with a halfword boundary (least significant address bit = "0") or a word boundary (two low-order address bits = "00"), respectively. If an attempt is made to access memory data that overlaps the halfword or word boundary, an address exception occurs.
Address +0 address
b0
+1 address
78
+2 address
+3 address
b31
15 16
23 24
Byte Byte Byte Byte Byte
b0 15 b31
Halfword Halfword Halfword
b0 b31
Word
Word
Figure 2.6.3 Data Formats in Memory (3) Endian The diagrams below show a general endian system and the endian adopted for the M32R family of Mitsubishi microcomputers.
Bit endian (H'01)
Byte endian (H'01234567)
Big endian
B'0000001
b0 b7
H'01
HH
H'23
HL
H'45
LH
H'67
LL
Little endian
B'0000001
b7 b0
H'67
LL
H'45
LH
H'23
HL
H'01
HH
Note: * Even when bits are arranged in big endian, H'01 is not B'10000000.
Figure 2.6.4 General Endian System
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Mitsubishi microcomputer family name Endian (bit/byte) Address Data arrangement Bit number Example: 0x01234567
+0
CPU
2.6 Data Formats
7700 and M16C families
M32R family
Little/little
+1 +2 +3 +0
Little/big
+1 +2 +3 +0
Big/big
+1 +2 +3
LL
LH
HL
HH
HH
HL
LH
LL
HH
HL
LH
LL
7-0
15-8
23-16
31-24
31-24
23-16
15-8
7-0
0-7
8-15
16-23
24-31
.byte 67,45,23,01
.byte 01,23,45,67
.byte 01,23,45,67
Note: * The M32R family uses the big endian for both bits and bytes.
Figure 2.6.5 Endian Adopted for the M32R Family (4) Transfer instructions
* Constant transfer
LD24 LDI LDI Rdest, #imm24 Rdest, #imm16 Rdest, #imm8
LD24
Rdest, #imm24
imm24
b0 b23
Rdest
00
b0 8 b31
SETH Rdest, #imm16
SETH Rdest, #imm16
imm16
b0 b15
Rdest
b0 15
00
00
b31
* Register to register transfer
MV MV Rdest, Rsrc
Rsrc
b0 b31
Rdest, Rsrc
Rdest
b0 b31
* Control register transfer
MVTC Rsrc, CRdest MVFC Rdest, CRsrc MVTC Rsrc, CRdest
Rsrc
b0 b31
CRdest
b0 b31
Note: * The condition bit C changes state when data is written to CR0 (PSW) using the MVTC instruction.
Figure 2.6.6 Transfer Instructions
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(5) Transfer from memory (signed) to registers
CPU
2.6 Data Formats
* Signed 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc
label
Memory
Rdest +0 +1 +2 +3
Register
b0
b31
* Signed 16 bits
label
LD24 Rsrc, #label LDH Rdest, @Rsrc
Rdest +0 +1 +2 +3 Determined by MSB 0: Positive number 1: Negative number
00 FF
b0
00 FF
b31
* Signed 8 bits LD24 Rsrc, #label LDB Rdest, @Rsrc
label
Rdest +3 +0 +1 +2 Determined by MSB 0: Positive number 1: Negative number
00 FF
b0
00 FF
00 FF
b31
Figure 2.6.7 Transfer from Memory (Signed) to Registers (6) Transfer from memory (unsigned) to registers
Memory * Unsigned 32 bits LD24 Rsrc, #label LD Rdest, @Rsrc
label Rdest
Register
+0
+1
+2
+3
b0
b31
* Unsigned 16 bits LD24 Rsrc, #label LDUH Rdest, @Rsrc
label Rdest
00
+0 +1 +2 +3 b0
00
b31
* Unsigned 8 bits LD24 Rsrc, #label LDUB Rdest, @Rsrc
label
Rdest
00
+0 +1 +2 +3 b0
00
00
b31
Figure 2.6.8 Transfer from Memory (Unsigned) to Registers
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(7) Notes on data transfer
CPU
2.6 Data Formats
When transferring data, be aware that data arrangements in registers and memory are different.
Data in registers
Data in memory
* Word data (32 bits)
(R0-R15)
HH HL LH LL
+0
HH
+1
HL
+2
LH
+3
LL
b0
b31
b0
b31
* Halfword data (16 bits)
(R0-R15)
H L
+0
H
+1
L
+2
+3
b0
b31
b0
b15
(R0-R15)
H L
+0 b31
+1
+2
H
+3
L
b0
b16
b31
* Byte data (8 bits)
(R0-R15)
b0 b31 b0 +0 b7 +1 +2 +3
(R0-R15)
b0 b31
+0 b8
+1 b15
+2
+3
(R0-R15)
b0 b31
+0
+1
+2 b16 b23
+3
(R0-R15)
b0 b31
+0
+1
+2
+3 b24 b31
Figure 2.6.9 Difference in Data Arrangements
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CPU
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution
The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR instruction finishes. The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction is used to clear the LOCK bit. The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit controls granting of bus control requested by devices other than the CPU. * When LOCK bit = "0" Control of the bus requested by devices other than the CPU is granted * When LOCK bit = "1" Control of the bus requested by devices other than the CPU is denied In the 32180 group, control of the bus may be requested by devices other than the CPU in the following two cases: * When DMA transfer is requested by the internal DMAC * When HREQ# input is pulled low to request that the CPU be placed in a hold state
2.8 Precautions on CPU
* Usage Notes for 0 Division Instruction
Problem and Conditions Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction under the conditions described in (1). (1) If 0 division calculation is executed when the divisor = 0 for instructions DIV, DIVU, REM and REMU, (2) the result will be inaccurate calculations for any of the following instructions that are executed immediately after 0 division: ADDV, ADDX, ADD, ADDI, ADDV3, ADD3, CMP, CMPU, CMPI, CMPUI, SUBV, SUBX, SUB, DIV, DIVU, REM, REMU. Countermeasure Assuming that the 0 division occurrence itself is not expected by the system and therefore is the cause of miscalculations, before executing division or remainder instructions, do a 0 check on the divisor to make sure 0 division does not occur.
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CHAPTER 3 ADDRESS SPACE
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Outline of the Address Space Operation Modes Internal ROM and Extended External Areas Internal RAM and SFR Areas EIT Vector Entry ICU Vector Table Notes on Address Space
3
3.1 Outline of the Address Space
ADDRESS SPACE
3.1 Outline of the Address Space
The logical addresses of the M32R are always handled in 32 bits, providing a linear address space of up to 4 Gbytes. The address space of the M32R/ECU consists of the following: (1) User space * Internal ROM area * Extended external area * Internal RAM area * SFR (Special Function Register) area (2) System space (not open to the user) (1) User space The 2 Gbytes from the address H'0000 0000 to the address H'7FFF FFFF comprise the user space. Located in this space are the internal ROM area, an extended external area, the internal RAM area and the SFR (Special Function Register) area (in which a set of internal peripheral I/O registers exist). Of these, the internal ROM and extended external areas are located differently depending on mode settings as will be described later. (2) System space The 2 Gbytes from the address H'8000 0000 to the address H'FFFF FFFF comprise the system space. This space is reserved for use by development tools such as an in-circuit emulator and debug monitor, and cannot be used by the user.
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Logical address H'0000 0000 16 Mbytes
ADDRESS SPACE
3.1 Outline of the Address Space
EIT vector entry
Internal ROM area 1 Mbytes (Note 1) H'000F FFFF
H'0000 0000
H'0010 0000
CS0 area
H'001F FFFF H'0020 0000
CS1 area User space 2 Gbytes Ghost area in 16-Mbyte units CS2 area
H'005F FFFF H'0060 0000 H'003F FFFF H'0040 0000
CS3 area H'7FFF FFFF H'8000 0000
H'007F FFFF H'0080 0000 H'0080 3FFF H'0080 4000
SFR area 16 Kbytes RAM area 48 Kbytes
H'0080 FFFF H'0081 0000
2 Gbytes
System space
Reserved area 64 Kbytes
H'0081 FFFF H'0082 0000
Ghost area in 128-Kbyte units
H'FFFF FFFF
H'00FF FFFF
Note 1: This area is located differently depending on how chip mode is set.
Figure 3.1.1 Address Space
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3.2 Operation Modes
ADDRESS SPACE
3.2 Operation Modes
The microcomputer is placed in one of the following modes depending on how CPU operation mode is set by MOD0 and MOD1 pins. The operation mode used for rewriting the internal flash memory is described separately in Section 6.5, "Programming the Internal Flash Memory." Table 3.2.1 Operation Mode Settings
MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCCE Operation mode (Note 2) Single-chip mode External extension mode Processor mode (FP = VSS) Reserved (use inhibited)
Note 1: Connect VCCE and VSS to the VCCE input power supply and ground, respectively. Note 2: For the operation mode used to rewrite the internal flash memory (FP = VCCE) which is not shown in the above table, see Section 6.5, "Programming the Internal Flash Memory."
The internal ROM and extended external areas are located differently depending on how operation mode is set. (All other areas in the address space are located the same way.) The diagram below shows how the internal ROM and extended external areas are mapped into the address space in each operation mode. (For flash rewrite mode, see Section 6.5, "Programming the Internal Flash Memory.")
Non-CS0 area H'0000 0000 H'000F FFFF H'0010 0000 H'001F FFFF H'0020 0000 CS1 area H'003F FFFF H'0040 0000
Extended external area Extended external area
Internal ROM area (1 Mbytes)
Internal ROM area (1 Mbytes) CS0 area
CS0 area
CS1 area
CS2 area
CS2 area
H'005F FFFF H'0060 0000
CS3 area
CS3 area
H'007F FFFF
Figure 3.2.1 Internal ROM and Extended External Area Address Mapping of the M32180F8 in Each Operation Mode
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ADDRESS SPACE
3.3 Internal ROM and Extended External Areas
3.3 Internal ROM and Extended External Areas
The 8-Mbyte area in the user space from the address H'0000 0000 to the address H'007F FFFF comprise the internal ROM and extended external areas. For the address mapping of these areas that differs with each operation mode, see Section 3.2, "Operation Modes."
3.3.1 Internal ROM Area
The internal ROM is allocated to the addresses shown below. Located at the beginning of this area is the EIT vector entry (and the ICU vector table). Table 3.3.1 Internal ROM Allocation Address
Type Name M32180F8 Size 1 Mbytes Allocation Address H'0000 0000 to H'000F FFFF
3.3.2 Extended External Area
The extended external area is only available when external extension or processor mode is selected by operation mode settings. When accessing the extended external area, the control signals necessary to access external devices are output. The CS0# through CS3# signals are output corresponding to the address mapping of the extended external area. The CS0#, CS1#, CS2# and CS3# signals are output for the CS0, CS1, CS2 and CS3 areas, respectively. Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode
Operation Mode Single-chip mode External extension mode Address Mapping of Extended External Area None Addresses H'0010 0000 to H'001F FFFF (CS0 area: 1 Mbytes) Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes) Addresses H'0040 0000 to H'005F FFFF (CS2 area: 2 Mbytes) Addresses H'0060 0000 to H'007F FFFF (CS3 area: 2 Mbytes) Processor mode Addresses H'0000 0000 to H'001F FFFF (CS0 area: 2 Mbytes) Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes) Addresses H'0040 0000 to H'005F FFFF (CS2 area: 2 Mbytes) Addresses H'0060 0000 to H'007F FFFF (CS3 area: 2 Mbytes)
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3.4 Internal RAM and SFR Areas
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
The 8-Mbyte area from the address H'0080 0000 to the address H'00FF FFFF comprise the internal RAM and SFR (Special Function Register) areas. Of these, the space that the user can actually use is a 128-Kbyte area from the address H'0080 0000 to the address H'0081 FFFF. The other areas here are ghosts in 128-Kbyte units. (Do not use the ghost area intentionally during programming.)
3.4.1 Internal RAM Area
The internal RAM area is allocated to the addresses shown below. Table 3.4.1 Internal RAM Allocation Address
Type Name M32180F8 Size 48 Kbytes Allocation Address H'0080 4000 to H'0080 FFFF
3.4.2 SFR (Special Function Register) Area
The addresses H'0080 0000 to H'0080 3FFFF comprise the SFR (Special Function Register) area. Located in this area are the internal peripheral I/O registers.
H'0080 0000
SFR area (16 Kbytes)
H'0080 3FFF H'0080 4000
H'0080 7FFF H'0080 8000
Internal RAM (48 Kbytes)
Virtual flash emulation areas separated in 4-Kbyte units can be allocated here. For details, see Section 6.6.
H'0080 FFFF
Figure 3.4.1 Internal RAM and SFR (Special Function Register) Areas of the M32180F8
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0 H'0080 0000 Interrupt Controller (ICU) H'0080 007E H'0080 0080 H'0080 00EE H'0080 0100 Serial I/O 0-3 H'0080 0146 H'0080 0180 Wait Controller H'0080 0186 H'0080 01E0 Flash control H'0080 01F8 H'0080 0200 MJT (common part) H'0080 023E H'0080 0240 MJT(TOP) H'0080 02FE H'0080 0300 MJT(TIO) H'0080 03BE H'0080 03C0 MJT(TMS) H'0080 03D8 H'0080 03E0 MJT(TML0) H'0080 03FE H'0080 0400 DMAC H'0080 0478 H'0080 11FE Multijunction timer (MJT) H'0080 0C8C H'0080 0C8E H'0080 0C90 H'0080 0CE2 H'0080 0A00 78 15 +0 address +1 address H'0080 078C H'0080 078E H'0080 0790
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
0
78 15 +0 address +1 address MJT(TID0) MJT(TOU0) Multijunction timer (MJT)
H'0080 07E2 A-D0 Converter
Serial I/O 4-5 H'0080 0A26
H'0080 0A80 H'0080 0AEE H'0080 0B8C H'0080 0B8E H'0080 0B90 H'0080 0BE2 A-D1 Converter
MJT(TID1) MJT(TOU1)
MJT(TID2) MJT(TOU2)
Multijunction timer (MJT)
H'0080 0FE0 MJT(TML1) H'0080 0FFE H'0080 1000 CAN0
H'0080 0700 Input/output port H'0080 077F
H'0080 1400 CAN1 H'0080 15FE
Note: * The Real-time Debugger (RTD) is an independent module that is operated from the outside, and is transparent to the CPU.
Figure 3.4.2 Outline Mapping of the SFR Area
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SFR Area Register Map (1/27)
Address b0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 +0 address b7 b8 Interrupt Vector Register (IVECT) (Use inhibited area) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) (SBICR) (Use inhibited area)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 5-5
(Use inhibited area) (Use inhibited area)
5-6 5-7
|
H'0080 0060 H'0080 0062 H'0080 0064 H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E H'0080 0080 H'0080 0082 H'0080 0084
CAN0 Transmit/Receive & Error Interrupt Control Register TIN30-33 Input Interrupt Control Register (ICAN0CR) (ITIN3033CR) TID2 Output Interrupt Control Register A-D1 Conversion Interrupt Control Register (ITID2CR) (IAD1CCR) SIO4, 5 Transmit/Receive Interrupt Control Register TOU1, 2 Output Interrupt Control Register (ISIO45CR) (ITOU12CR) TID1 Output Interrupt Control Register RTD Interrupt Control Register (ITID1CR) (IRTDCR) SIO2, 3 Transmit/Receive Interrupt Control Register DMA5-9 Interrupt Control Register (ISIO23CR) (IDMA59CR) TOU0 Output Interrupt Control Register TID0 Output Interrupt Control Register (ITOU0CR) (ITID0CR) A-D0 Conversion Interrupt Control Register SIO0 Transmit Interrupt Control Register (IAD0CCR) (ISIO0TXCR) SIO0 Receive Interrupt Control Register SIO1 Transmit Interrupt Control Register (ISIO0RXCR) (ISIO1TXCR) SIO1 Receive Interrupt Control Register DMA0-4 Interrupt Control Register (ISIO1RXCR) (IDMA04CR) TIO0-3 Output Interrupt Control Register TOP6, 7 Output Interrupt Control Register (ITIO03CR) (ITOP67CR) TOP0-5 Output Interrupt Control Register TIO8, 9 Output Interrupt Control Register (ITOP05CR) (ITIO89CR) TIO4-7 Output Interrupt Control Register TOP10 Output Interrupt Control Register (ITIO47CR) (ITOP10CR) TOP8, 9 Output Interrupt Control Register TMS0, 1 Output Interrupt Control Register (ITOP89CR) (ITMS01CR) TIN7-11 Input Interrupt Control Register TIN0-2 Input Interrupt Control Register (ITIN711CR) (ITIN02CR) TIN12-19 Input Interrupt Control Register TIN20-29 Input Interrupt Control Register (ITIN1219CR) (ITIN2029CR) TIN3-6 Input Interrupt Control Register CAN1 Transmit/Receive & Error Interrupt Control Register (ITIN36CR) (ICAN1CR) A-D0 Single Mode Register 0 A-D0 Single Mode Register 1 (AD0SIM0) (AD0SIM1) (Use inhibited area)
5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 11-16 11-18
A-D0 Scan Mode Register 0 A-D0 Scan Mode Register 1 (AD0SCM0) (AD0SCM1) H'0080 0086 A-D0 Disconnection Detection Assist Function Control Register A-D0 Conversion Speed Control Register (AD0DDACR) (AD0CVSCR) H'0080 0088 A-D0 Successive Approximation Register (AD0SAR) H'0080 008A A-D0 Disconnection Detection Assist Method Select Register (AD0DDASEL) H'0080 008C A-D0 Comparate Data Register (AD0CMP) H'0080 008E (Use inhibited area) H'0080 0090 H'0080 0092 H'0080 0094 H'0080 0096 H'0080 0098 H'0080 009A 10-bit A-D0 Data Register (AD0DT0) 10-bit A-D0 Data Register (AD0DT1) 10-bit A-D0 Data Register (AD0DT2) 10-bit A-D0 Data Register (AD0DT3) 10-bit A-D0 Data Register (AD0DT4) 10-bit A-D0 Data Register (AD0DT5) 0 1 2 3 4 5
11-20 11-22 11-25 11-24 11-29 11-26 11-30
11-31 11-31 11-31 11-31 11-31 11-31
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SFR Area Register Map (2/27)
Address b0 H'0080 009C H'0080 009E H'0080 00A0 H'0080 00A2 H'0080 00A4 H'0080 00A6 H'0080 00A8 H'0080 00AA H'0080 00AC H'0080 00AE +0 address b7 b8 10-bit A-D0 Data Register 6 (AD0DT6) 10-bit A-D0 Data Register 7 (AD0DT7) 10-bit A-D0 Data Register 8 (AD0DT8) 10-bit A-D0 Data Register 9 (AD0DT9) 10-bit A-D0 Data Register 10 (AD0DT10) 10-bit A-D0 Data Register 11 (AD0DT11) 10-bit A-D0 Data Register 12 (AD0DT12) 10-bit A-D0 Data Register 13 (AD0DT13) 10-bit A-D0 Data Register 14 (AD0DT14) 10-bit A-D0 Data Register 15 (AD0DT15) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31
|
H'0080 00D0 H'0080 00D2 H'0080 00D4 H'0080 00D6 H'0080 00D8 H'0080 00DA H'0080 00DC H'0080 00DE H'0080 00E0 H'0080 00E2 H'0080 00E4 H'0080 00E6 H'0080 00E8 H'0080 00EA H'0080 00EC H'0080 00EE
8-bit A-D0 Data Register 0 (AD08DT0) 8-bit A-D0 Data Register 1 (AD08DT1) 8-bit A-D0 Data Register 2 (AD08DT2) 8-bit A-D0 Data Register 3 (AD08DT3) 8-bit A-D0 Data Register 4 (AD08DT4) 8-bit A-D0 Data Register 5 (AD08DT5) 8-bit A-D0 Data Register 6 (AD08DT6) 8-bit A-D0 Data Register 7 (AD08DT7) 8-bit A-D0 Data Register 8 (AD08DT8) 8-bit A-D0 Data Register 9 (AD08DT9) 8-bit A-D0 Data Register 10 (AD08DT10) 8-bit A-D0 Data Register 11 (AD08DT11) 8-bit A-D0 Data Register 12 (AD08DT12) 8-bit A-D0 Data Register 13 (AD08DT13) 8-bit A-D0 Data Register 14 (AD08DT14) 8-bit A-D0 Data Register 15 (AD08DT15)
11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32
|
H'0080 0100 H'0080 0102
|
H'0080 0110 H'0080 0112 H'0080 0114
SIO23 Interrupt Request Status Register SIO03 Interrupt Request Enable Register (SI23STAT) (SI03EN) SIO03 Interrupt Request Source Select Register (Use inhibited area) (SI03SEL) (Use inhibited area) SIO0 Transmit Control Register SIO0 Transmit/Receive Mode Register (S0TCNT) (S0MOD) SIO0 Transmit Buffer Register (S0TXB) SIO0 Receive Buffer Register (S0RXB)
12-9 12-10 12-11
12-14 12-15 12-18 12-19
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SFR Area Register Map (3/27)
Address b0 H'0080 0116 SIO0 Receive Control Register (S0RCNT) (Use inhibited area) +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 SIO0 Baud Rate Register (S0BAUR)
See pages 12-20 12-23
|
H'0080 0120 H'0080 0122 H'0080 0124 H'0080 0126
|
H'0080 0130 H'0080 0132 H'0080 0134 H'0080 0136
SIO1 Transmit Control Register SIO1 Transmit/Receive Mode Register (S1TCNT) (S1MOD) SIO1 Transmit Buffer Register (S1TXB) SIO1 Receive Buffer Register (S1RXB) SIO1 Receive Control Register SIO1 Baud Rate Register (S1RCNT) (S1BAUR) (Use inhibited area) SIO2 Transmit Control Register SIO2 Transmit/Receive Mode Register (S2TCNT) (S2MOD) SIO2 Transmit Buffer Register (S2TXB) SIO2 Receive Buffer Register (S2RXB) SIO2 Receive Control Register SIO2 Baud Rate Register (S2RCNT) (S2BAUR) (Use inhibited area) SIO3 Transmit Control Register SIO3 Transmit/Receive Mode Register (S3TCNT) (S3MOD) SIO3 Transmit Buffer Register (S3TXB) SSIO3 Receive Buffer Register (S3RXB) SIO3 Receive Control Register SIO3 Baud Rate Register (S3RCNT) (S3BAUR) (Use inhibited area) CS0 Area Wait Control Register (CS0WTCR) CS2 Area Wait Control Register (CS2WTCR) (Use inhibited area) Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) (Use inhibited area) Virtual Flash S Bank Register (FESBANK0) Virtual Flash S Bank Register (FESBANK1) Virtual Flash S Bank Register (FESBANK2) Virtual Flash S Bank Register (FESBANK3) Virtual Flash S Bank Register (FESBANK4) Virtual Flash S Bank Register (FESBANK5) Virtual Flash S Bank Register (FESBANK6) Virtual Flash S Bank Register (FESBANK7) (Use inhibited area) (Use inhibited area) Prescaler Register 0 (PRS0) 0 1 2 3 4 5 6 7 Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) CS1 Area Wait Control Register (CS1WTCR) CS3 Area Wait Control Register (CS3WTCR)
12-14 12-15 12-18 12-19 12-20 12-23
12-14 12-15 12-18 12-19 12-20 12-23
|
H'0080 0140 H'0080 0142 H'0080 0144 H'0080 0146
12-14 12-15 12-18 12-19 12-20 12-23
|
H'0080 0180 H'0080 0182
16-4 16-4
|
H'0080 01E0 H'0080 01E2 H'0080 01E4 H'0080 01E6 H'0080 01E8 H'0080 01EA H'0080 01EC H'0080 01EE H'0080 01F0 H'0080 01F2 H'0080 01F4 H'0080 01F6
6-4 6-5 6-7 6-8 6-9
6-11 6-11 6-11 6-11 6-11 6-11 6-11 6-11
|
H'0080 0200 H'0080 0202
Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 1 (PRS1)
10-16 10-12
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SFR Area Register Map (4/27)
Address b0 H'0080 0204 Prescaler Register 2 (PRS2) (Use inhibited area) +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 Output Event Bus Control Register (OEBCR)
See pages 10-12 10-17
|
H'0080 0210 H'0080 0212 H'0080 0214 H'0080 0216 H'0080 0218 H'0080 021A
|
H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A
TCLK Input Processing Control Register (TCLKCR) TIN0-4 Input Processing Control Register (TIN04CR) TIN5-8 Input Processing Control Register (TIN58CR) TIN9-11 Input Processing Control Register (TIN911CR) TIN12-19 Input Processing Control Register (TIN1219CR) TIN20-23, TIN30-33 Input Processing Control Register (TIN2023_3033CR) (Use inhibited area) F/F6-15 Source Select Register (FF615S) (Use inhibited area) F/F16-19 Source Select Register (FF1619S) F/F0-15 Protect Register (FF015P) F/F0-15 Data Register (FF015D) (Use inhibited area) F/F16-20 Protect Register (FF1620P) (Use inhibited area) F/F16-20 Data Register (FF1620D) (Use inhibited area) TOP0-5 Interrupt Request Status Register TOP0-5 Interrupt Request Mask Register (TOP05IST) (TOP05IMA) TOP6, 7 Interrupt Request Mask & Status Register TOP8, 9 Interrupt Request Mask & Status Register (TOP67IMS) (TOP89IMS) TIO0-3 Interrupt Request Mask & Status Register TIO4-7 Interrupt Request Mask & Status Register (TIO03IMS) (TIO47IMS) TIO8, 9 Interrupt Request Mask & Status Register TMS0, 1 Interrupt Request Mask & Status Register (TIO89IMS) (TMS01IMS) TIN0-2 Interrupt Request Mask & Status Register TIN3-6 Interrupt Request Mask & Status Register (TIN02IMS) (TIN36IMS) TIN7-11 Interrupt Request Status Register TIN7-11 Interrupt Request Mask Register (TIN711IST) (TIN711IMA) TIN12-19 Interrupt Request Status Register TIN12-19 Interrupt Request Mask Register (TIN1219IST) (TIN1219IMA) TIN20-23 Interrupt Request Mask & Status Register TIN30-33 Interrupt Request Mask & Status Register (TIN2023IMS) (TIN3033IMS) TOP0 Counter (TOP0CT) TOP0 Reload Register (TOP0RL) (Use inhibited area) TOP0 Correction Register (TOP0CC) (Use inhibited area) TOP1 Counter (TOP1CT) TOP1 Reload Register (TOP1RL) (Use inhibited area) TOP1 Correction Register (TOP1CC) (Use inhibited area)
10-20 10-21 10-22 10-23 10-24 10-24
10-28 10-29 10-30 10-32 10-30 10-32
|
H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E H'0080 0240 H'0080 0242 H'0080 0244 H'0080 0246
10-39 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-51 10-53 10-57 10-75 10-76
10-77
|
H'0080 0250 H'0080 0252 H'0080 0254 H'0080 0256
10-75 10-76
10-77
|
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SFR Area Register Map (5/27)
Address b0 H'0080 0260 H'0080 0262 H'0080 0264 H'0080 0266 +0 address b7 b8 TOP2 Counter (TOP2CT) TOP2 Reload Register (TOP2RL) (Use inhibited area) TOP2 Correction Register (TOP2CC) (Use inhibited area) TOP3 Counter (TOP3CT) TOP3 Reload Register (TOP3RL) (Use inhibited area) TOP3 Correction Register (TOP3CC) (Use inhibited area) TOP4 Counter (TOP4CT) TOP4 Reload Register (TOP4RL) (Use inhibited area) TOP4 Correction Register (TOP4CC) (Use inhibited area) TOP5 Counter (TOP5CT) TOP5 Reload Register (TOP5RL) (Use inhibited area) TOP5 Correction Register (TOP5CC) (Use inhibited area) TOP0-5 Control Register 0 (TOP05CR0) (Use inhibited area) (Use inhibited area) TOP6 Counter (TOP6CT) TOP6 Reload Register (TOP6RL) (Use inhibited area) TOP6 Correction Register (TOP6CC) (Use inhibited area) TOP6, 7 Control Register (TOP67CR) (Use inhibited area) TOP7 Counter (TOP7CT) TOP7 Reload Register (TOP7RL) (Use inhibited area) TOP7 Correction Register (TOP7CC) (Use inhibited area)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 10-75 10-76
10-77
|
H'0080 0270 H'0080 0272 H'0080 0274 H'0080 0276
10-75 10-76
10-77
|
H'0080 0280 H'0080 0282 H'0080 0284 H'0080 0286
10-75 10-76
10-77
|
H'0080 0290 H'0080 0292 H'0080 0294 H'0080 0296 H'0080 0298 H'0080 029A H'0080 029C
10-75 10-76
10-77
10-71 TOP0-5 Control Register 1 (TOP05CR1) 10-71
|
H'0080 02A0 H'0080 02A2 H'0080 02A4 H'0080 02A6 H'0080 02A8 H'0080 02AA
10-75 10-76
10-77
10-73
|
H'0080 02B0 H'0080 02B2 H'0080 02B4 H'0080 02B6
10-75 10-76
10-77
|
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SFR Area Register Map (6/27)
Address b0 H'0080 02C0 H'0080 02C2 H'0080 02C4 H'0080 02C6 +0 address b7 b8 TOP8 Counter (TOP8CT) TOP8 Reload Register (TOP8RL) (Use inhibited area) TOP8 Correction Register (TOP8CC) (Use inhibited area) TOP9 Counter (TOP9CT) TOP9 Reload Register (TOP9RL) (Use inhibited area) TOP9 Correction Register (TOP9CC) (Use inhibited area) TOP10 Counter (TOP10CT) TOP10 Reload Register (TOP10RL) (Use inhibited area) TOP10 Correction Register (TOP10CC) (Use inhibited area) TOP8-10 Control Register (TOP810CR) (Use inhibited area)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 10-75 10-76
10-77
|
H'0080 02D0 H'0080 02D2 H'0080 02D4 H'0080 02D6
10-75 10-76
10-77
|
H'0080 02E0 H'0080 02E2 H'0080 02E4 H'0080 02E6 H'0080 02E8 H'0080 02EA
10-75 10-76
10-77
10-74
|
H'0080 02FA H'0080 02FC H'0080 02FE H'0080 0300 H'0080 0302 H'0080 0304 H'0080 0306
TOP External Enable Permit Register (TOPEEN) TOP Enable Protect Register (TOPPRO) TOP Count Enable Register (TOPCEN) TIO0 Counter (TIO0CT) (Use inhibited area) TIO0 Reload 1 Register (TIO0RL1) TIO0 Reload 0/ Measure Register (TIO0RL0) (Use inhibited area) TIO1 Counter (TIO1CT) (Use inhibited area) TIO1 Reload 1 Register (TIO1RL1) TIO1 Reload 0/ Measure Register (TIO1RL0) (Use inhibited area) TIO0-3 Control Register 0 (TIO03CR0) (Use inhibited area) (Use inhibited area) TIO2 Counter (TIO2CT) (Use inhibited area) TIO0-3 Control Register 1 (TIO03CR1)
10-78 10-78 10-79 10-109
10-111 10-110
|
H'0080 0310 H'0080 0312 H'0080 0314 H'0080 0316 H'0080 0318 H'0080 031A H'0080 031C
10-109
10-111 10-110
10-102 10-103
|
H'0080 0320 H'0080 0322
10-109
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3
SFR Area Register Map (7/27)
Address b0 H'0080 0324 H'0080 0326 +0 address
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b7 b8 TIO2 Reload 1 Register (TIO2RL1) TIO2 Reload 0/ Measure Register (TIO2RL0) (Use inhibited area) TIO3 Counter (TIO3CT) (Use inhibited area) TIO3 Reload 1 Register (TIO3RL1) TIO3 Reload 0/ Measure Register (TIO3RL0) (Use inhibited area) TIO4 Counter (TIO4CT) (Use inhibited area) TIO4 Reload 1 Register (TIO4RL1) TIO4 Reload 0/ Measure Register (TIO4RL0) (Use inhibited area) b15
See pages 10-111 10-110
|
H'0080 0330 H'0080 0332 H'0080 0334 H'0080 0336
10-109
10-111 10-110
|
H'0080 0340 H'0080 0343 H'0080 0344 H'0080 0346 H'0080 0348 H'0080 034A TIO4 Control Register (TIO4CR)
10-109
10-111 10-110
TIO5 Control Register (TIO5CR) (Use inhibited area) TIO5 Counter (TIO5CT) (Use inhibited area) TIO5 Reload 1 Register (TIO5RL1) TIO5 Reload 0/ Measure Register (TIO5RL0) (Use inhibited area) TIO6 Counter (TIO6CT) (Use inhibited area) TIO6 Reload 1 Register (TIO6RL1) TIO6 Reload 0/ Measure Register (TIO6RL0) (Use inhibited area)
10-104 10-106
|
H'0080 0350 H'0080 0352 H'0080 0354 H'0080 0356
10-109
10-111 10-110
|
H'0080 0360 H'0080 0362 H'0080 0364 H'0080 0366 H'0080 0368 H'0080 036A TIO6 Control Register (TIO6CR)
10-109
10-111 10-110
TIO7 Control Register (TIO7CR) (Use inhibited area) TIO7 Counter (TIO7CT) (Use inhibited area) TIO7 Reload 1 Register (TIO7RL1) TIO7 Reload 0/ Measure Register (TIO7RL0) (Use inhibited area) TIO8 Counter (TIO8CT) (Use inhibited area) TIO8 Reload 1 Register (TIO8RL1)
10-107 10-108
|
H'0080 0370 H'0080 0372 H'0080 0374 H'0080 0376
10-109
10-111 10-110
|
H'0080 0380 H'0080 0382 H'0080 0384
10-109
10-111
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SFR Area Register Map (8/27)
Address b0 H'0080 0386 H'0080 0388 H'0080 038A TIO8 Control Register (TIO8CR) (Use inhibited area) TIO9 Counter (TIO9CT) (Use inhibited area) +0 address
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b7 b8 TIO8 Reload 0/ Measure Register (TIO8RL0) (Use inhibited area) TIO9 Control Register (TIO9CR) b15
See pages 10-110
10-108 10-109
|
H'0080 0390 H'0080 0392 H'0080 0394 H'0080 0396
10-109
|
H'0080 03BC H'0080 03BE H'0080 03C0 H'0080 03C2 H'0080 03C4 H'0080 03C6 H'0080 03C8 H'0080 03CA
TIO9 Reload 1 Register (TIO9RL1) TIO9 Reload 0/ Measure Register (TIO9RL0) (Use inhibited area) TIO Enable Protect Register (TIOPRO) TIO Count Enable Register (TIOCEN) TMS0 Counter (TMS0CT) TMS0 Measure 3 Register (TMS0MR3) TMS0 Measure 2 Register (TMS0MR2) TMS0 Measure 1 Register (TMS0MR1) TMS0 Measure 0 Register (TMS0MR0) TMS0 Control Register (TMS0CR) (Use inhibited area) TMS1 Counter (TMS1CT) TMS1 Measure 3 Register (TMS1MR3) TMS1 Measure 2 Register (TMS1MR2) TMS1 Measure 1 Register (TMS1MR1) TMS1 Measure 0 Register (TMS1MR0) (Use inhibited area) TML0 Counter (TML0CT) (Upper) (Lower) (Use inhibited area) (Use inhibited area) (Use inhibited area) TML0 Measure 3 Register (TML0MR3) (Upper) (Lower) TML0 Measure 2 Register (TML0MR2) (Upper) (Lower) TML0 Measure 1 Register (TML0MR1) (Upper) (Lower) TML0 Control Register (TML0CR) TMS1 Control Register (TMS1CR)
10-111 10-110
10-112 10-113 10-130 10-130 10-130 10-130 10-130 10-129
|
H'0080 03D0 H'0080 03D2 H'0080 03D4 H'0080 03D6 H'0080 03D8
10-130 10-130 10-130 10-130 10-130
|
H'0080 03E0 H'0080 03E2
10-135
|
H'0080 03EA
10-134
|
H'0080 03F0 H'0080 03F2 H'0080 03F4 H'0080 03F6 H'0080 03F8 H'0080 03FA
10-135
10-135
10-135
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32180 Group User's Manual (Rev.1.0)
3
SFR Area Register Map (9/27)
Address b0 H'0080 03FC H'0080 03FE H'0080 0400 +0 address b7 b8 TML0 Measure 0 Register (TML0MR0)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 (Upper) (Lower)
See pages 10-135
|
H'0080 0408
DMA0-4 Interrupt Request Status Register DMA0-4 Interrupt Request Mask Register (DM04ITST) (DM04ITMK) (Use inhibited area) DMA5-9 Interrupt Request Status Register DMA5-9 Interrupt Request Mask Register (DM59ITST) (DM59ITMK) (Use inhibited area) DMA0 Channel Control Register 0 DMA0 Channel Control Register 1 (DM0CNT0) (DM0CNT1) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0 Transfer Count Register (DM0TCT) DMA5 Channel Control Register 0 DMA5 Channel Control Register 1 (DM5CNT0) (DM5CNT1) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA5 Transfer Count Register (DM5TCT) DMA1 Channel Control Register 0 DMA1 Channel Control Register 1 (DM1CNT0) (DM1CNT1) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Transfer Count Register (DM1TCT) DMA6 Channel Control Register 0 DMA6 Channel Control Register 1 (DM6CNT0) (DM6CNT1) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Transfer Count Register (DM6TCT) DMA2 Channel Control Register 0 DMA2 Channel Control Register 1 (DM2CNT0) (DM2CNT1) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA2 Transfer Count Register (DM2TCT) DMA7 Channel Control Register 0 DMA7 Channel Control Register 1 (DM7CNT0) (DM7CNT1) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Transfer Count Register (DM7TCT) DMA3 Channel Control Register 0 DMA3 Channel Control Register 1 (DM3CNT0) (DM3CNT1) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Transfer Count Register (DM3TCT) DMA8 Channel Control Register 0 DMA8 Channel Control Register 1 (DM8CNT0) (DM8CNT1)
9-24 9-25
9-24 9-25
|
H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448
9-6 9-19 9-20 9-21 9-11 9-19 9-20 9-21 9-7 9-19 9-20 9-21 9-12 9-19 9-20 9-21 9-8 9-19 9-20 9-21 9-13 9-19 9-20 9-21 9-9 9-19 9-20 9-21 9-14
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SFR Area Register Map (10/27)
Address b0 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 +0 address
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
|
H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478
+1 address b7 b8 DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Transfer Count Register (DM8TCT) DMA4 Channel Control Register 0 DMA4 Channel Control Register 1 (DM4CNT0) (DM4CNT1) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Transfer Count Register (DM4TCT) DMA9 Channel Control Register 0 DMA9 Channel Control Register 1 (DM9CNT0) (DM9CNT1) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) (Use inhibited area) DMA5 Software Request Generation (DM5SRI) DMA6 Software Request Generation (DM6SRI) DMA7 Software Request Generation (DM7SRI) DMA8 Software Request Generation (DM8SRI) DMA9 Software Request Generation (DM9SRI) (Use inhibited area) P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P14 Data Register (P14DATA) P16 Data Register (P16DATA) P18 Data Register (P18DATA) P20 Data Register (P20DATA) P22 Data Register (P22DATA) Register Register Register Register Register
See pages b15 9-19 9-20 9-21 9-10 9-19 9-20 9-21 9-15 9-19 9-20 9-21 9-18 9-18 9-18 9-18 9-18
9-18 9-18 9-18 9-18 9-18
|
H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716
P1 Data Register (P1DATA) P3 Data Register (P3DATA) (Use inhibited area) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) (Use inhibited area)
8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7
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SFR Area Register Map (11/27)
Address b0 H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736 P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P14 Direction Register (P14DIR) P16 Direction Register (P16DIR) P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) P22 Direction Register (P22DIR) (Use inhibited area) P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) P6 Operation Mode Register (P6MOD) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) P14 Operation Mode Register (P14MOD) P16 Operation Mode Register (P16MOD) P18 Operation Mode Register (P18MOD) P20 Operation Mode Register (P20MOD) P22 Operation Mode Register (P22MOD) +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) (Use inhibited area) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) (Use inhibited area)
See pages 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8
|
H'0080 0740 H'0080 0742 H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756
P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) Port Input Special Function Control Register (PICNT) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) P19 Operation Mode Register (P19MOD) P21 Operation Mode Register (P21MOD) (Use inhibited area) (Use inhibited area)
8-9 8-10 8-11 8-21 8-11 8-12 8-12 8-13 8-13 8-14 8-14 8-15 8-15 8-16 8-16 8-17 8-17 8-18 8-18 8-19 8-19
|
H'0080 0760 H'0080 0762 H'0080 0764
|
H'0080 076A
Port Group 0, 1 Input Level Setting Register Port Group 2, 3 Input Level Setting Register (PG01LEV) (PG23LEV) Port Group 4, 5 Input Level Setting Register Port Group 6, 7 Input Level Setting Register (PG45LEV) (PG67LEV) Port Group 8 Input Level Setting Register (Use inhibited area) (PG8LEV) (Use inhibited area) P10 Peripheral Output Select Register (P10SMOD) (Use inhibited area) P22 Peripheral Output Select Register (P22SMOD) (Use inhibited area) (Use inhibited area) (Use inhibited area)
8-25 8-25 8-25
8-20
|
H'0080 0776
(Use inhibited area)
8-20
|
H'0080 077E
Bus Mode Control Register (BUSMODC)
15-9
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SFR Area Register Map (12/27)
Address b0 H'0080 0780 H'0080 0782 H'0080 0784 H'0080 0786 +0 address b7 b8 PWM Output 0 Disable Control Register (PO0DISCR) PWM Output 1 Disable Control Register (PO1DISCR) PWM Output 2 Disable Control Register (PO2DISCR) Clock Control Register (CLKCR) (Use inhibited
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 PWM Output 0 Disable Level Control Register (PO0LVCR) PWM Output 1 Disable Level Control Register (PO1LVCR) PWM Output 2 Disable Level Control Register (PO2LVCR) (Use inhibited area) area)
See pages 10-174 10-177 10-174 10-177 10-175 10-177 18-5
|
H'0080 078C H'0080 078E H'0080 0790 H'0080 0792 H'0080 0794 H'0080 0796 H'0080 0798 H'0080 079A H'0080 079C H'0080 079E H'0080 07A0 H'0080 07A2 H'0080 07A4 H'0080 07A6 H'0080 07A8 H'0080 07AA H'0080 07AC H'0080 07AE H'0080 07B0 H'0080 07B2 H'0080 07B4 H'0080 07B6 H'0080 07B8 H'0080 07BA H'0080 07BC H'0080 07BE H'0080 07C0 H'0080 07C2
TID0 Counter (TID0CT) TID0 Reload Register (TID0RL) TOU0_0 Counter (TOU00CTW)
10-144 10-144 (Upper) (TOU00CTH) (Lower) (TOU00CT) TOU0_0 Reload 1 Register (TOU00RL1) TOU0_0 Reload 0 Register (TOU00RL0) (Upper) (TOU01CTH) (Lower) (TOU01CT) TOU0_1 Reload 1 Register (TOU01RL1) TOU0_1 Reload 0 Register (TOU01RL0) (Upper) (TOU02CTH) (Lower) (TOU02CT) TOU0_2 Reload 1 Register (TOU02RL1) TOU0_2 Reload 0 Register (TOU02RL0) (Upper) (TOU03CTH) (Lower) (TOU03CT) TOU0_3 Reload 1 Register (TOU03RL1) TOU0_3 Reload 0 Register (TOU03RL0) (Upper) (TOU04CTH) (Lower) (TOU04CT) TOU0_4 Reload 1 Register (TOU04RL1) TOU0_4 Reload 0 Register (TOU04RL0) (Upper) (TOU05CTH) (Lower) (TOU05CT) TOU0_5 Reload 1 Register (TOU05RL1) TOU0_5 Reload 0 Register (TOU05RL0) (Upper) (TOU06CTH) (Lower) (TOU06CT) 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163
TOU0_0 Reload Register (TOU00RLW)
TOU0_1 Counter (TOU01CTW)
TOU0_1 Reload Register (TOU01RLW)
TOU0_2 Counter (TOU02CTW)
TOU0_2 Reload Register (TOU02RLW)
TOU0_3 Counter (TOU03CTW)
TOU0_3 Reload Register (TOU03RLW)
TOU0_4 Counter (TOU04CTW)
TOU0_4 Reload Register (TOU04RLW)
TOU0_5 Counter (TOU05CTW)
TOU0_5 Reload Register (TOU05RLW)
TOU0_6 Counter (TOU06CTW)
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SFR Area Register Map (13/27)
Address b0 H'0080 07C4 H'0080 07C6 H'0080 07C8 H'0080 07CA H'0080 07CC H'0080 07CE H'0080 07D0 H'0080 07D2 H'0080 07D4 H'0080 07D6 H'0080 07D8 H'0080 07DA H'0080 07DC H'0080 07DE H'0080 07E0 H'0080 07E2 +0 address b7 b8 TOU0_6 Reload Register (TOU06RLW)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-12 10-141 10-58 10-31 10-33 10-158 10-158 10-168 10-169 10-171 10-25 10-53
|
H'0080 0A00 H'0080 0A02
TOU0_6 Reload 1 Register (TOU06RL1) TOU0_6 Reload 0 Register (TOU06RL0) TOU0_7 Counter (Upper) (TOU07CTW) (TOU07CTH) (Lower) (TOU07CT) TOU0_7 Reload Register TOU0_7 Reload 1 Register (TOU07RLW) (TOU07RL1) TOU0_7 Reload 0 Register (TOU07RL0) Prescaler Register 3 TID0 Control & Prescaler 3 Enable Register (PRS3) (TID0PRS3EN) TOU0 Interrupt Request Mask Register TOU0 Interrupt Request Status Register (TOU0IMA) (TOU0IST) (Use inhibited area) F/F21-28 Protect Register (FF2128P) (Use inhibited area) F/F21-28 Data Register (FF2128D) TOU0 Control Register 1 (TOU0CR1) TOU0 Control Register 0 (TOU0CR0) (Use inhibited area) TOU0 Enable Protect Register (TOU0PRO) (Use inhibited area) TOU0 Count Enable Register (TOU0CEN) PWMOFF0 Input Processing Control Register TIN24, 25 Input Processing Control Register (PWMOFF0CR) (TIN2425CR) TIN24, 25 Interrupt Request Mask Register TIN24, 25 Interrupt Request Status Register (TIN2425IMA) (TIN2425IST) (Use inhibited area) SIO45 Interrupt Request Status Register SIO45 Interrupt Request Enable Register (SI45STAT) (SI45EN) SIO45 Interrupt Source Select Register (Use inhibited area) (SI45SEL) (Use inhibited area) SIO4 Transmit Control Register SIO4 Transmit/Receive Mode Register (S4TCNT) (S4MOD) SIO4 Transmit Buffer Register (S4TXB) SIO4 Receive Buffer Register (S4RXB) SIO4 Receive Control Register SIO4 Baud Rate Register (S4RCNT) (S4BAUR) (Use inhibited area) SIO5 Transmit Control Register SIO5 Transmit/Receive Mode Register (S5TCNT) (S5MOD) SIO5 Transmit Buffer Register (S5TXB) SIO5 Receive Buffer Register (S5RXB) SIO5 Receive Control Register SIO5 Baud Rate Register (S5RCNT) (S5BAUR) (Use inhibited area) A-D1 Single Mode Register 0 (AD1SIM0) (Use inhibited area) A-D1 Scan Mode Register 0 A-D1 Scan Mode Register 1 (AD1SCM0) (AD1SCM1) A-D1 Disconnection Detection Assist Function Control Register A-D1 Conversion Speed Control Register (AD1DDACR) (AD1CVSCR) A-D1 Successive Approximation Register (AD1SAR) A-D1 Single Mode Register 1 (AD1SIM1)
12-9 12-10 12-11
|
H'0080 0A10 H'0080 0A12 H'0080 0A14 H'0080 0A16
12-14 12-15 12-18 12-19 12-20 12-23
|
H'0080 0A20 H'0080 0A22 H'0080 0A24 H'0080 0A26
12-14 12-15 12-18 12-19 12-20 12-23
|
H'0080 0A80 H'0080 0A82 H'0080 0A84 H'0080 0A86 H'0080 0A88
11-16 11-18
11-20 11-22 11-25 11-24 11-29
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32180 Group User's Manual (Rev.1.0)
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SFR Area Register Map (14/27)
Address b0 H'0080 0A8A H'0080 0A8C H'0080 0A8E H'0080 0A90 H'0080 0A92 H'0080 0A94 H'0080 0A96 H'0080 0A98 H'0080 0A9A H'0080 0A9C H'0080 0A9E H'0080 0AA0 H'0080 0AA2 H'0080 0AA4 H'0080 0AA6 H'0080 0AA8 H'0080 0AAA H'0080 0AAC H'0080 0AAE +0 address
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b7 b8 A-D1 Disconnection Detection Assist Method Select Register (AD1DDASEL) A-D1 Comparate Data Register (AD1CMP) (Use inhibited area) 10-bit A-D1 Data Register 0 (AD1DT0) 10-bit A-D1 Data Register 1 (AD1DT1) 10-bit A-D1 Data Register 2 (AD1DT2) 10-bit A-D1 Data Register 3 (AD1DT3) 10-bit A-D1 Data Register 4 (AD1DT4) 10-bit A-D1 Data Register 5 (AD1DT5) 10-bit A-D1 Data Register 6 (AD1DT6) 10-bit A-D1 Data Register 7 (AD1DT7) 10-bit A-D1 Data Register 8 (AD1DT8) 10-bit A-D1 Data Register 9 (AD1DT9) 10-bit A-D1 Data Register 10 (AD1DT10) 10-bit A-D1 Data Register 11 (AD1DT11) 10-bit A-D1 Data Register 12 (AD1DT12) 10-bit A-D1 Data Register 13 (AD1DT13) 10-bit A-D1 Data Register 14 (AD1DT14) 10-bit A-D1 Data Register 15 (AD1DT15) (Use inhibited area)
See pages b15 11-26 11-30
11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31 11-31
|
H'0080 0AD0 H'0080 0AD2 H'0080 0AD4 H'0080 0AD6 H'0080 0AD8 H'0080 0ADA H'0080 0ADC H'0080 0ADE H'0080 0AE0 H'0080 0AE2 H'0080 0AE4 H'0080 0AE6 H'0080 0AE8 H'0080 0AEA H'0080 0AEC (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area) (Use inhibited area)
8-bit A-D1 Data Register 0 (AD18DT0) 8-bit A-D1 Data Register 1 (AD18DT1) 8-bit A-D1 Data Register 2 (AD18DT2) 8-bit A-D1 Data Register 3 (AD18DT3) 8-bit A-D1 Data Register 4 (AD18DT4) 8-bit A-D1 Data Register 5 (AD18DT5) 8-bit A-D1 Data Register 6 (AD18DT6) 8-bit A-D1 Data Register 7 (AD18DT7) 8-bit A-D1 Data Register 8 (AD18DT8) 8-bit A-D1 Data Register 9 (AD18DT9) 8-bit A-D1 Data Register 10 (AD18DT10) 8-bit A-D1 Data Register 11 (AD18DT11) 8-bit A-D1 Data Register 12 (AD18DT12) 8-bit A-D1 Data Register 13 (AD18DT13) 8-bit A-D1 Data Register 14 (AD18DT14)
11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32 11-32
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SFR Area Register Map (15/27)
Address b0 H'0080 0AEE (Use inhibited area) (Use inhibited area) TID1 Counter (TID1CT) TID1 Reload Register (TID1RL) TOU1_0 Counter (TOU10CTW) +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 8-bit A-D1 Data Register 15 (AD18DT15)
See pages 11-32
|
H'0080 0B8C H'0080 0B8E H'0080 0B90 H'0080 0B92 H'0080 0B94 H'0080 0B96 H'0080 0B98 H'0080 0B9A H'0080 0B9C H'0080 0B9E H'0080 0BA0 H'0080 0BA2 H'0080 0BA4 H'0080 0BA6 H'0080 0BA8 H'0080 0BAA H'0080 0BAC H'0080 0BAE H'0080 0BB0 H'0080 0BB2 H'0080 0BB4 H'0080 0BB6 H'0080 0BB8 H'0080 0BBA H'0080 0BBC H'0080 0BBE H'0080 0BC0 H'0080 0BC2 H'0080 0BC4 H'0080 0BC6 H'0080 0BC8 H'0080 0BCA
10-144 10-144 (Upper) (TOU10CTH) (Lower) (TOU10CT) TOU1_0 Reload 1 Register (TOU10RL1) TOU1_0 Reload 0 Register (TOU10RL0) (Upper) (TOU11CTH) (Lower) (TOU11CT) TOU1_1 Reload 1 Register (TOU11RL1) TOU1_1 Reload 0 Register (TOU11RL0) (Upper) (TOU12CTH) (Lower) (TOU12CT) TOU1_2 Reload 1 Register (TOU12RL1) TOU1_2 Reload 0 Register (TOU12RL0) (Upper) (TOU13CTH) (Lower) (TOU13CT) TOU1_3 Reload 1 Register (TOU13RL1) TOU1_3 Reload 0 Register (TOU13RL0) (Upper) (TOU14CTH) (Lower) (TOU14CT) TOU1_4 Reload 1 Register (TOU14RL1) TOU1_4 Reload 0 Register (TOU14RL0) (Upper) (TOU15CTH) (Lower) (TOU15CT) TOU1_5 Reload 1 Register (TOU15RL1) TOU1_5 Reload 0 Register (TOU15RL0) (Upper) (TOU16CTH) (Lower) (TOU16CT) TOU1_6 Reload 1 Register (TOU16RL1) TOU1_6 Reload 0 Register (TOU16RL0) (Upper) (TOU17CTH) (Lower) (TOU17CT) 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163
TOU1_0 Reload Register (TOU10RLW)
TOU1_1 Counter (TOU11CTW)
TOU1_1 Reload Register (TOU11RLW)
TOU1_2 Counter (TOU12CTW)
TOU1_2 Reload Register (TOU12RLW)
TOU1_3 Counter (TOU13CTW)
TOU1_3 Reload Register (TOU13RLW)
TOU1_4 Counter (TOU14CTW)
TOU1_4 Reload Register (TOU14RLW)
TOU1_5 Counter (TOU15CTW)
TOU1_5 Reload Register (TOU15RLW)
TOU1_6 Counter (TOU16CTW)
TOU1_6 Reload Register (TOU16RLW)
TOU1_7 Counter (TOU17CTW)
3-22
32180 Group User's Manual (Rev.1.0)
3
SFR Area Register Map (16/27)
Address b0 H'0080 0BCC H'0080 0BCE H'0080 0BD0 H'0080 0BD2 H'0080 0BD4 H'0080 0BD6 H'0080 0BD8 H'0080 0BDA H'0080 0BDC H'0080 0BDE H'0080 0BE0 H'0080 0BE2 +0 address b7 b8 TOU1_7 Reload Register (TOU17RLW)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 10-164 10-167 10-166 10-12 10-142 10-60 10-31 10-33 10-159 10-159 10-168 10-169 10-171 10-25 10-54
|
H'0080 0C8C H'0080 0C8E H'0080 0C90 H'0080 0C92 H'0080 0C94 H'0080 0C96 H'0080 0C98 H'0080 0C9A H'0080 0C9C H'0080 0C9E H'0080 0CA0 H'0080 0CA2 H'0080 0CA4 H'0080 0CA6 H'0080 0CA8 H'0080 0CAA H'0080 0CAC H'0080 0CAE H'0080 0CB0 H'0080 0CB2 H'0080 0CB4 H'0080 0CB6
TOU1_7 Reload 1 Register (TOU17RL1) TOU1_7 Reload 0 Register (TOU17RL0) Prescaler Register 4 TID1 Control & Prescaler 4 Enable Register (PRS4) (TID1PRS4EN) TOU1 Interrupt Request Mask Register TOU1 Interrupt Request Status Register (TOU1IMA) (TOU1IST) (Use inhibited area) F/F29-36 Protect Register (FF2936P) (Use inhibited area) F/F29-36 Data Register (FF2936D) TOU1 Control Register 1 (TOU1CR1) TOU1 Control Register 0 (TOU1CR0) (Use inhibited area) TOU1 Enable Protect Register (TOU1PRO) (Use inhibited area) TOU1 Count Enable Register (TOU1CEN) PWMOFF1 Input Processing Control Register TIN26, 27 Input Processing Control Register (PWMOFF1CR) (TIN2627CR) TIN26, 27 Interrupt Request Mask Register TIN26, 27 Interrupt Request Status Register (TIN2627IMA) (TIN2627IST) (Use inhibited area) TID2 Counter (TID2CT) TID2 Reload Register (TID2RL) TOU2_0 Counter (TOU20CTW)
10-144 10-144 (Upper) (TOU20CTH) (Lower) (TOU20CT) TOU2_0 Reload 1 Register (TOU20RL1) TOU2_0 Reload 0 Register (TOU20RL0) (Upper) (TOU21CTH) (Lower) (TOU21CT) TOU2_1 Reload 1 Register (TOU21RL1) TOU2_1 Reload 0 Register (TOU21RL0) (Upper) (TOU22CTH) (Lower) (TOU22CT) TOU2_2 Reload 1 Register (TOU22RL1) TOU2_2 Reload 0 Register (TOU22RL0) (Upper) (TOU23CTH) (Lower) (TOU23CT) TOU2_3 Reload 1 Register (TOU23RL1) TOU2_3 Reload 0 Register (TOU23RL0) (Upper) (TOU24CTH) (Lower) (TOU24CT) TOU2_4 Reload 1 Register (TOU24RL1) TOU2_4 Reload 0 Register (TOU24RL0) 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166
TOU2_0 Reload Register (TOU20RLW)
TOU2_1 Counter (TOU21CTW)
TOU2_1 Reload Register (TOU21RLW)
TOU2_2 Counter (TOU22CTW)
TOU2_2 Reload Register (TOU22RLW)
TOU2_3 Counter (TOU23CTW)
TOU2_3 Reload Register (TOU23RLW)
TOU2_4 Counter (TOU24CTW)
TOU2_4 Reload Register (TOU24RLW)
3-23
32180 Group User's Manual (Rev.1.0)
3
SFR Area Register Map (17/27)
Address b0 H'0080 0CB8 H'0080 0CBA H'0080 0CBC H'0080 0CBE H'0080 0CC0 H'0080 0CC2 H'0080 0CC4 H'0080 0CC6 H'0080 0CC8 H'0080 0CCA H'0080 0CCC H'0080 0CCE H'0080 0CD0 H'0080 0CD2 H'0080 0CD4 H'0080 0CD6 H'0080 0CD8 H'0080 0CDA H'0080 0CDC H'0080 0CDE H'0080 0CE0 H'0080 0CE2 +0 address b7 b8 TOU2_5 Counter (TOU25CTW)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-161 10-163 10-164 10-167 10-166 10-12 10-143 10-61 10-31 10-34 10-160 10-160 10-168 10-169 10-172 10-25 10-54
|
H'0080 0FE0 H'0080 0FE2
(Upper) (TOU25CTH) (Lower) (TOU25CT) TOU2_5 Reload Register TOU2_5 Reload 1 Register (TOU25RLW) (TOU25RL1) TOU2_5 Reload 0 Register (TOU25RL0) TOU2_6 Counter (Upper) (TOU26CTW) (TOU26CTH) (Lower) (TOU26CT) TOU2_6 Reload Register TOU2_6 Reload 1 Register (TOU26RLW) (TOU26RL1) TOU2_6 Reload 0 Register (TOU26RL0) TOU2_7 Counter (Upper) (TOU27CTW) (TOU27CTH) (Lower) (TOU27CT) TOU2_7 Reload Register TOU2_7 Reload 1 Register (TOU27RLW) (TOU27RL1) TOU2_7 Reload 0 Register (TOU27RL0) Prescaler Register 5 TID2 Control & Prescaler 5 Enable Register (PRS5) (TID2PRS5EN) TOU2 Interrupt Request Mask Register TOU2 Interrupt Request Status Register (TOU2IMA) (TOU2IST) (Use inhibited area) F/F37-44 Protect Register (FF3744P) (Use inhibited area) F/F37-44 Data Register (FF3744D) TOU2 Control Register 1 (TOU2CR1) TOU2 Control Register 0 (TOU2CR0) (Use inhibited area) TOU2 Enable Protect Register (TOU2PRO) (Use inhibited area) TOU2 Count Enable Register (TOU2CEN) PWMOFF2 Input Processing Control Register TIN28, 29 Input Processing Control Register (PWMOFF2CR) (TIN2829CR) TIN28, 29 Interrupt Request Mask Register TIN28, 29 Interrupt Request Status Register (TIN2829IMA) (TIN2829IST) (Use inhibited area) TML1 Counter (TML1CT) (Upper) (Lower) (Use inhibited area) (Use inhibited area) (Use inhibited area) TML1 Measure 3 Register (TML1MR3) (Upper) (Lower) TML1 Measure 2 Register (TML1MR2) (Upper) (Lower) TML1 Measure 1 Register (TML1MR1) (Upper) (Lower) TML1 Control Register (TML1CR)
10-135
|
H'0080 0FEA
10-134
|
H'0080 0FF0 H'0080 0FF2 H'0080 0FF4 H'0080 0FF6 H'0080 0FF8 H'0080 0FFA
10-135
10-135
10-135
3-24
32180 Group User's Manual (Rev.1.0)
3
SFR Area Register Map (18/27)
Address b0 H'0080 0FFC H'0080 0FFE +0 address b7 b8 TML1 Measure 0 Register (TML1MR0)
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15 (Upper) (Lower) (Use inhibited area)
See pages 10-135
|
H'0080 1000 H'0080 1002 H'0080 1004 H'0080 1006 H'0080 1008 H'0080 100A H'0080 100C H'0080 100E H'0080 1010 H'0080 1012 H'0080 1014 H'0080 1016 H'0080 1018
CAN0 Control Register (CAN0CNT) CAN0 Status Register (CAN0STAT) CAN0 Frame Format Select Register (CAN0FFS) CAN0 Configuration Register (CAN0CONF) CAN0 Timestamp Count Register (CAN0TSTMP) CAN0 Receive Error Count Register CAN0 Transmit Error Count Register (CAN0REC) (CAN0TEC) CAN0 Slot Interrupt Request Status Register (CAN0SLIST) (Use inhibited area) CAN0 Slot Interrupt Request Enable Register (CAN0SLIEN) (Use inhibited area) CAN0 Error Interrupt Request Status Register CAN0 Error Interrupt Request Enable Register (CAN0ERIST) (CAN0ERIEN) CAN0 Baud Rate Prescaler CAN0 Cause of Error Register (CAN0BRP) (CAN0EF) CAN0 Mode Register CAN0 DMA Transfer Request Select Register (CAN0MOD) (CAN0DMARQ) (Use inhibited area) CAN0 Global Mask Register Standard ID 0 CAN0 Global Mask Register Standard ID 1 (C0GMSKS0) (C0GMSKS1) CAN0 Global Mask Register Extended ID 0 CAN0 Global Mask Register Extended ID 1 (C0GMSKE0) (C0GMSKE1) CAN0 Global Mask Register Extended ID 2 (Use inhibited area) (C0GMSKE2) (Use inhibited area) CAN0 Local Mask Register A Standard ID 0 CAN0 Local Mask Register A Standard ID 1 (C0LMSKAS0) (C0LMSKAS1) CAN0 Local Mask Register A Extended ID 0 CAN0 Local Mask Register A Extended ID 1 (C0LMSKAE0) (C0LMSKAE1) CAN0 Local Mask Register A Extended ID 2 (Use inhibited area) (C0LMSKAE2) (Use inhibited area) CAN0 Local Mask Register B Standard ID 0 CAN0 Local Mask Register B Standard ID 1 (C0LMSKBS0) (C0LMSKBS1) CAN0 Local Mask Register B Extended ID 0 CAN0 Local Mask Register B Extended ID 1 (C0LMSKBE0) (C0LMSKBE1) CAN0 Local Mask Register B Extended ID 2 (Use inhibited area) (C0LMSKBE2) (Use inhibited area) CAN0 Single Shot Mode Control Register (CAN0SSMODE) (Use inhibited area) CAN0 Single-Shot Interrupt Request Status Register (CAN0SSIST) (Use inhibited area) CAN0 Single-Shot Interrupt Request Enable Register (CAN0SSIEN) CAN0 Message Slot 0 Control Register CAN0 Message Slot 1 Control Register (C0MSL0CNT) (C0MSL1CNT)
13-15 13-18 13-21 13-22 13-24 13-25 13-29
13-30
13-31 13-32 13-26 13-45 13-46 13-47
|
H'0080 1028 H'0080 102A H'0080 102C H'0080 102E H'0080 1030 H'0080 1032 H'0080 1034 H'0080 1036 H'0080 1038 H'0080 103A H'0080 103C H'0080 103E H'0080 1040 H'0080 1042 H'0080 1044 H'0080 1046 H'0080 1048 H'0080 1050
13-48 13-49 13-50
13-48 13-49 13-50
13-48 13-49 13-50
13-52
13-33
3-34 13-53
3-25
32180 Group User's Manual (Rev.1.0)
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SFR Area Register Map (19/27)
Address b0 H'0080 1052 H'0080 1054 H'0080 1056 H'0080 1058 H'0080 105A H'0080 105C H'0080 105E +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-53 13-53 13-53 13-53 13-53 13-53 13-53
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H'0080 1100 H'0080 1102 H'0080 1104 H'0080 1106 H'0080 1108 H'0080 110A H'0080 110C H'0080 110E H'0080 1110 H'0080 1112 H'0080 1114 H'0080 1116 H'0080 1118 H'0080 111A H'0080 111C H'0080 111E H'0080 1120 H'0080 1122 H'0080 1124 H'0080 1126 H'0080 1128 H'0080 112A H'0080 112C H'0080 112E H'0080 1130 H'0080 1132 H'0080 1134
CAN0 Message Slot 2 Control Register CAN0 Message Slot 3 Control Register (C0MSL2CNT) (C0MSL3CNT) CAN0 Message Slot 4 Control Register CAN0 Message Slot 5 Control Register (C0MSL4CNT) (C0MSL5CNT) CAN0 Message Slot 6 Control Register CAN0 Message Slot 7 Control Register (C0MSL6CNT) (C0MSL7CNT) CAN0 Message Slot 8 Control Register CAN0 Message Slot 9 Control Register (C0MSL8CNT) (C0MSL9CNT) CAN0 Message Slot 10 Control Register CAN0 Message Slot 11 Control Register (C0MSL10CNT) (C0MSL11CNT) CAN0 Message Slot 12 Control Register CAN0 Message Slot 13 Control Register (C0MSL12CNT) (C0MSL13CNT) CAN0 Message Slot 14 Control Register CAN0 Message Slot 15 Control Register (C0MSL14CNT) (C0MSL15CNT) (Use inhibited area) CAN0 Message Slot 0 Standard ID 0 CAN0 Message Slot 0 Standard ID 1 (C0MSL0SID0) (C0MSL0SID1) CAN0 Message Slot 0 Extended ID 0 CAN0 Message Slot 0 Extended ID 1 (C0MSL0EID0) (C0MSL0EID1) CAN0 Message Slot 0 Extended ID 2 CAN0 Message Slot 0 Data Length Register (C0MSL0EID2) (C0MSL0DLC) CAN0 Message Slot 0 Data 0 CAN0 Message Slot 0 Data 1 (C0MSL0DT0) (C0MSL0DT1) CAN0 Message Slot 0 Data 2 CAN0 Message Slot 0 Data 3 (C0MSL0DT2) (C0MSL0DT3) CAN0 Message Slot 0 Data 4 CAN0 Message Slot 0 Data 5 (C0MSL0DT4) (C0MSL0DT5) CAN0 Message Slot 0 Data 6 CAN0 Message Slot 0 Data 7 (C0MSL0DT6) (C0MSL0DT7) CAN0 Message Slot 0 Timestamp (C0MSL0TSP) CAN0 Message Slot 1 Standard ID 0 CAN0 Message Slot 1 Standard ID 1 (C0MSL1SID0) (C0MSL1SID1) CAN0 Message Slot 1 Extended ID 0 CAN0 Message Slot 1 Extended ID 1 (C0MSL1EID0) (C0MSL1EID1) CAN0 Message Slot 1 Extended ID 2 CAN0 Message Slot 1 Data Length Register (C0MSL1EID2) (C0MSL1DLC) CAN0 Message Slot 1 Data 0 CAN0 Message Slot 1 Data 1 (C0MSL1DT0) (C0MSL1DT1) CAN0 Message Slot 1 Data 2 CAN0 Message Slot 1 Data 3 (C0MSL1DT2) (C0MSL1DT3) CAN0 Message Slot 1 Data 4 CAN0 Message Slot 1 Data 5 (C0MSL1DT4) (C0MSL1DT5) CAN0 Message Slot 1 Data 6 CAN0 Message Slot 1 Data 7 (C0MSL1DT6) (C0MSL1DT7) CAN0 Message Slot 1 Timestamp (C0MSL1TSP) CAN0 Message Slot 2 Standard ID 0 CAN0 Message Slot 2 Standard ID 1 (C0MSL2SID0) (C0MSL2SID1) CAN0 Message Slot 2 Extended ID 0 CAN0 Message Slot 2 Extended ID 1 (C0MSL2EID0) (C0MSL2EID1) CAN0 Message Slot 2 Extended ID 2 CAN0 Message Slot 2 Data Length Register (C0MSL2EID2) (C0MSL2DLC) CAN0 Message Slot 2 Data 0 CAN0 Message Slot 2 Data 1 (C0MSL2DT0) (C0MSL2DT1) CAN0 Message Slot 2 Data 2 CAN0 Message Slot 2 Data 3 (C0MSL2DT2) (C0MSL2DT3) CAN0 Message Slot 2 Data 4 CAN0 Message Slot 2 Data 5 (C0MSL2DT4) (C0MSL2DT5) CAN0 Message Slot 2 Data 6 CAN0 Message Slot 2 Data 7 (C0MSL2DT6) (C0MSL2DT7) CAN0 Message Slot 2 Timestamp (C0MSL2TSP) CAN0 Message Slot 3 Standard ID 0 CAN0 Message Slot 3 Standard ID 1 (C0MSL3SID0) (C0MSL3SID1) CAN0 Message Slot 3 Extended ID 0 CAN0 Message Slot 3 Extended ID 1 (C0MSL3EID0) (C0MSL3EID1) CAN0 Message Slot 3 Extended ID 2 CAN0 Message Slot 3 Data Length Register (C0MSL3EID2) (C0MSL3DLC)
13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62
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32180 Group User's Manual (Rev.1.0)
3
SFR Area Register Map (20/27)
Address b0 H'0080 1136 H'0080 1138 H'0080 113A H'0080 113C H'0080 113E H'0080 1140 H'0080 1142 H'0080 1144 H'0080 1146 H'0080 1148 H'0080 114A H'0080 114C H'0080 114E H'0080 1150 H'0080 1152 H'0080 1154 H'0080 1156 H'0080 1158 H'0080 115A H'0080 115C H'0080 115E H'0080 1160 H'0080 1162 H'0080 1164 H'0080 1166 H'0080 1168 H'0080 116A H'0080 116C H'0080 116E H'0080 1170 H'0080 1172 H'0080 1174 H'0080 1176 H'0080 1178 H'0080 117A CAN0 Message Slot 3 (C0MSL3DT0) CAN0 Message Slot 3 (C0MSL3DT2) CAN0 Message Slot 3 (C0MSL3DT4) CAN0 Message Slot 3 (C0MSL3DT6) Data 0 +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68
CAN0 Message Slot 3 Data 1 (C0MSL3DT1) Data 2 CAN0 Message Slot 3 Data 3 (C0MSL3DT3) Data 4 CAN0 Message Slot 3 Data 5 (C0MSL3DT5) Data 6 CAN0 Message Slot 3 Data 7 (C0MSL3DT7) CAN0 Message Slot 3 Timestamp (C0MSL3TSP) CAN0 Message Slot 4 Standard ID 0 CAN0 Message Slot 4 Standard ID 1 (C0MSL4SID0) (C0MSL4SID1) CAN0 Message Slot 4 Extended ID 0 CAN0 Message Slot 4 Extended ID 1 (C0MSL4EID0) (C0MSL4EID1) CAN0 Message Slot 4 Extended ID 2 CAN0 Message Slot 4 Data Length Register (C0MSL4EID2) (C0MSL4DLC) CAN0 Message Slot 4 Data 0 CAN0 Message Slot 4 Data 1 (C0MSL4DT0) (C0MSL4DT1) CAN0 Message Slot 4 Data 2 CAN0 Message Slot 4 Data 3 (C0MSL4DT2) (C0MSL4DT3) CAN0 Message Slot 4 Data 4 CAN0 Message Slot 4 Data 5 (C0MSL4DT4) (C0MSL4DT5) CAN0 Message Slot 4 Data 6 CAN0 Message Slot 4 Data 7 (C0MSL4DT6) (C0MSL4DT7) CAN0 Message Slot 4 Timestamp (C0MSL4TSP) CAN0 Message Slot 5 Standard ID 0 CAN0 Message Slot 5 Standard ID 1 (C0MSL5SID0) (C0MSL5SID1) CAN0 Message Slot 5 Extended ID 0 CAN0 Message Slot 5 Extended ID 1 (C0MSL5EID0) (C0MSL5EID1) CAN0 Message Slot 5 Extended ID 2 CAN0 Message Slot 5 Data Length Register (C0MSL5EID2) (C0MSL5DLC) CAN0 Message Slot 5 Data 0 CAN0 Message Slot 5 Data 1 (C0MSL5DT0) (C0MSL5DT1) CAN0 Message Slot 5 Data 2 CAN0 Message Slot 5 Data 3 (C0MSL5DT2) (C0MSL5DT3) CAN0 Message Slot 5 Data 4 CAN0 Message Slot 5 Data 5 (C0MSL5DT4) (C0MSL5DT5) CAN0 Message Slot 5 Data 6 CAN0 Message Slot 5 Data 7 (C0MSL5DT6) (C0MSL5DT7) CAN0 Message Slot 5 Timestamp (C0MSL5TSP) CAN0 Message Slot 6 Standard ID 0 CAN0 Message Slot 6 Standard ID 1 (C0MSL6SID0) (C0MSL6SID1) CAN0 Message Slot 6 Extended ID 0 CAN0 Message Slot 6 Extended ID 1 (C0MSL6EID0) (C0MSL6EID1) CAN0 Message Slot 6 Extended ID 2 CAN0 Message Slot 6 Data Length Register (C0MSL6EID2) (C0MSL6DLC) CAN0 Message Slot 6 Data 0 CAN0 Message Slot 6 Data 1 (C0MSL6DT0) (C0MSL6DT1) CAN0 Message Slot 6 Data 2 CAN0 Message Slot 6 Data 3 (C0MSL6DT2) (C0MSL6DT3) CAN0 Message Slot 6 Data 4 CAN0 Message Slot 6 Data 5 (C0MSL6DT4) (C0MSL6DT5) CAN0 Message Slot 6 Data 6 CAN0 Message Slot 6 Data 7 (C0MSL6DT6) (C0MSL6DT7) CAN0 Message Slot 6 Timestamp (C0MSL6TSP) CAN0 Message Slot 7 Standard ID 0 CAN0 Message Slot 7 Standard ID 1 (C0MSL7SID0) (C0MSL7SID1) CAN0 Message Slot 7 Extended ID 0 CAN0 Message Slot 7 Extended ID 1 (C0MSL7EID0) (C0MSL7EID1) CAN0 Message Slot 7 Extended ID 2 CAN0 Message Slot 7 Data Length Register (C0MSL7EID2) (C0MSL7DLC) CAN0 Message Slot 7 Data 0 CAN0 Message Slot 7 Data 1 (C0MSL7DT0) (C0MSL7DT1) CAN0 Message Slot 7 Data 2 CAN0 Message Slot 7 Data 3 (C0MSL7DT2) (C0MSL7DT3) CAN0 Message Slot 7 Data 4 CAN0 Message Slot 7 Data 5 (C0MSL7DT4) (C0MSL7DT5)
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32180 Group User's Manual (Rev.1.0)
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SFR Area Register Map (21/27)
Address b0 H'0080 117C H'0080 117E H'0080 1180 H'0080 1182 H'0080 1184 H'0080 1186 H'0080 1188 H'0080 118A H'0080 118C H'0080 118E H'0080 1190 H'0080 1192 H'0080 1194 H'0080 1196 H'0080 1198 H'0080 119A H'0080 119C H'0080 119E H'0080 11A0 H'0080 11A2 H'0080 11A4 H'0080 11A6 H'0080 11A8 H'0080 11AA H'0080 11AC H'0080 11AE H'0080 11B0 H'0080 11B2 H'0080 11B4 H'0080 11B6 H'0080 11B8 H'0080 11BA H'0080 11BC H'0080 11BE H'0080 11C0 +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58
CAN0 Message Slot 7 Data 6 CAN0 Message Slot 7 Data 7 (C0MSL7DT6) (C0MSL7DT7) CAN0 Message Slot 7 Timestamp (C0MSL7TSP) CAN0 Message Slot 8 Standard ID 0 CAN0 Message Slot 8 Standard ID 1 (C0MSL8SID0) (C0MSL8SID1) CAN0 Message Slot 8 Extended ID 0 CAN0 Message Slot 8 Extended ID 1 (C0MSL8EID0) (C0MSL8EID1) CAN0 Message Slot 8 Extended ID 2 CAN0 Message Slot 8 Data Length Register (C0MSL8EID2) (C0MSL8DLC) CAN0 Message Slot 8 Data 0 CAN0 Message Slot 8 Data 1 (C0MSL8DT0) (C0MSL8DT1) CAN0 Message Slot 8 Data 2 CAN0 Message Slot 8 Data 3 (C0MSL8DT2) (C0MSL8DT3) CAN0 Message Slot 8 Data 4 CAN0 Message Slot 8 Data 5 (C0MSL8DT4) (C0MSL8DT5) CAN0 Message Slot 8 Data 6 CAN0 Message Slot 8 Data 7 (C0MSL8DT6) (C0MSL8DT7) CAN0 Message Slot 8 Timestamp (C0MSL8TSP) CAN0 Message Slot 9 Standard ID 0 CAN0 Message Slot 9 Standard ID 1 (C0MSL9SID0) (C0MSL9SID1) CAN0 Message Slot 9 Extended ID 0 CAN0 Message Slot 9 Extended ID 1 (C0MSL9EID0) (C0MSL9EID1) CAN0 Message Slot 9 Extended ID 2 CAN0 Message Slot 9 Data Length Register (C0MSL9EID2) (C0MSL9DLC) CAN0 Message Slot 9 Data 0 CAN0 Message Slot 9 Data 1 (C0MSL9DT0) (C0MSL9DT1) CAN0 Message Slot 9 Data 2 CAN0 Message Slot 9 Data 3 (C0MSL9DT2) (C0MSL9DT3) CAN0 Message Slot 9 Data 4 CAN0 Message Slot 9 Data 5 (C0MSL9DT4) (C0MSL9DT5) CAN0 Message Slot 9 Data 6 CAN0 Message Slot 9 Data 7 (C0MSL9DT6) (C0MSL9DT7) CAN0 Message Slot 9 Timestamp (C0MSL9TSP) CAN0 Message Slot 10 Standard ID 0 CAN0 Message Slot 10 Standard ID 1 (C0MSL10SID0) (C0MSL10SID1) CAN0 Message Slot 10 Extended ID 0 CAN0 Message Slot 10 Extended ID 1 (C0MSL10EID0) (C0MSL10EID1) CAN0 Message Slot 10 Extended ID 2 CAN0 Message Slot 10 Data Length Register (C0MSL10EID2) (C0MSL10DLC) CAN0 Message Slot 10 Data 0 CAN0 Message Slot 10 Data 1 (C0MSL10DT0) (C0MSL10DT1) CAN0 Message Slot 10 Data 2 CAN0 Message Slot 10 Data 3 (C0MSL10DT2) (C0MSL10DT3) CAN0 Message Slot 10 Data 4 CAN0 Message Slot 10 Data 5 (C0MSL10DT4) (C0MSL10DT5) CAN0 Message Slot 10 Data 6 CAN0 Message Slot 10 Data 7 (C0MSL10DT6) (C0MSL10DT7) CAN0 Message Slot 10 Timestamp (C0MSL10TSP) CAN0 Message Slot 11 Standard ID 0 CAN0 Message Slot 11 Standard ID 1 (C0MSL11SID0) (C0MSL11SID1) CAN0 Message Slot 11 Extended ID 0 CAN0 Message Slot 11 Extended ID 1 (C0MSL11EID0) (C0MSL11EID1) CAN0 Message Slot 11 Extended ID 2 CAN0 Message Slot 11 Data Length Register (C0MSL11EID2) (C0MSL11DLC) CAN0 Message Slot 11 Data 0 CAN0 Message Slot 11 Data 1 (C0MSL11DT0) (C0MSL11DT1) CAN0 Message Slot 11 Data 2 CAN0 Message Slot 11 Data 3 (C0MSL11DT2) (C0MSL11DT3) CAN0 Message Slot 11 Data 4 CAN0 Message Slot 11 Data 5 (C0MSL11DT4) (C0MSL11DT5) CAN0 Message Slot 11 Data 6 CAN0 Message Slot 11 Data 7 (C0MSL11DT6) (C0MSL11DT7) CAN0 Message Slot 11 Timestamp (C0MSL11TSP) CAN0 Message Slot 12 Standard ID 0 CAN0 Message Slot 12 Standard ID 1 (C0MSL12SID0) (C0MSL12SID1)
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32180 Group User's Manual (Rev.1.0)
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SFR Area Register Map (22/27)
Address b0 H'0080 11C2 H'0080 11C4 H'0080 11C6 H'0080 11C8 H'0080 11CA H'0080 11CC H'0080 11CE H'0080 11D0 H'0080 11D2 H'0080 11D4 H'0080 11D6 H'0080 11D8 H'0080 11DA H'0080 11DC H'0080 11DE H'0080 11E0 H'0080 11E2 H'0080 11E4 H'0080 11E6 H'0080 11E8 H'0080 11EA H'0080 11EC H'0080 11EE H'0080 11F0 H'0080 11F2 H'0080 11F4 H'0080 11F6 H'0080 11F8 H'0080 11FA H'0080 11FC H'0080 11FE +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71
|
H'0080 1400 H'0080 1402 H'0080 1404
CAN0 Message Slot 12 Extended ID 0 CAN0 Message Slot 12 Extended ID 1 (C0MSL12EID0) (C0MSL12EID1) CAN0 Message Slot 12 Extended ID 2 CAN0 Message Slot 12 Data Length Register (C0MSL12EID2) (C0MSL12DLC) CAN0 Message Slot 12 Data 0 CAN0 Message Slot 12 Data 1 (C0MSL12DT0) (C0MSL12DT1) CAN0 Message Slot 12 Data 2 CAN0 Message Slot 12 Data 3 (C0MSL12DT2) (C0MSL12DT3) CAN0 Message Slot 12 Data 4 CAN0 Message Slot 12 Data 5 (C0MSL12DT4) (C0MSL12DT5) CAN0 Message Slot 12 Data 6 CAN0 Message Slot 12 Data 7 (C0MSL12DT6) (C0MSL12DT7) CAN0 Message Slot 12 Timestamp (C0MSL12TSP) CAN0 Message Slot 13 Standard ID 0 CAN0 Message Slot 13 Standard ID 1 (C0MSL13SID0) (C0MSL13SID1) CAN0 Message Slot 13 Extended ID 0 CAN0 Message Slot 13 Extended ID 1 (C0MSL13EID0) (C0MSL13EID1) CAN0 Message Slot 13 Extended ID 2 CAN0 Message Slot 13 Data Length Register (C0MSL13EID2) (C0MSL13DLC) CAN0 Message Slot 13 Data 0 CAN0 Message Slot 13 Data 1 (C0MSL13DT0) (C0MSL13DT1) CAN0 Message Slot 13 Data 2 CAN0 Message Slot 13 Data 3 (C0MSL13DT2) (C0MSL13DT3) CAN0 Message Slot 13 Data 4 CAN0 Message Slot 13 Data 5 (C0MSL13DT4) (C0MSL13DT5) CAN0 Message Slot 13 Data 6 CAN0 Message Slot 13 Data 7 (C0MSL13DT6) (C0MSL13DT7) CAN0 Message Slot 13 Timestamp (C0MSL13TSP) CAN0 Message Slot 14 Standard ID 0 CAN0 Message Slot 14 Standard ID 1 (C0MSL14SID0) (C0MSL14SID1) CAN0 Message Slot 14 Extended ID 0 CAN0 Message Slot 14 Extended ID 1 (C0MSL14EID0) (C0MSL14EID1) CAN0 Message Slot 14 Extended ID 2 CAN0 Message Slot 14 Data Length Register (C0MSL14EID2) (C0MSL14DLC) CAN0 Message Slot 14 Data 0 CAN0 Message Slot 14 Data 1 (C0MSL14DT0) (C0MSL14DT1) CAN0 Message Slot 14 Data 2 CAN0 Message Slot 14 Data 3 (C0MSL14DT2) (C0MSL14DT3) CAN0 Message Slot 14 Data 4 CAN0 Message Slot 14 Data 5 (C0MSL14DT4) (C0MSL14DT5) CAN0 Message Slot 14 Data 6 CAN0 Message Slot 14 Data 7 (C0MSL14DT6) (C0MSL14DT7) CAN0 Message Slot 14 Timestamp (C0MSL14TSP) CAN0 Message Slot 15 Standard ID 0 CAN0 Message Slot 15 Standard ID 1 (C0MSL15SID0) (C0MSL15SID1) CAN0 Message Slot 15 Extended ID 0 CAN0 Message Slot 15 Extended ID 1 (C0MSL15EID0) (C0MSL15EID1) CAN0 Message Slot 15 Extended ID 2 CAN0 Message Slot 15 Data Length Register (C0MSL15EID2) (C0MSL15DLC) CAN0 Message Slot 15 Data 0 CAN0 Message Slot 15 Data 1 (C0MSL15DT0) (C0MSL15DT1) CAN0 Message Slot 15 Data 2 CAN0 Message Slot 15 Data 3 (C0MSL15DT2) (C0MSL15DT3) CAN0 Message Slot 15 Data 4 CAN0 Message Slot 15 Data 5 (C0MSL15DT4) (C0MSL15DT5) CAN0 Message Slot 15 Data 6 CAN0 Message Slot 15 Data 7 (C0MSL15DT6) (C0MSL15DT7) CAN0 Message Slot 15 Timestamp (C0MSL15TSP) (Use inhibited area) CAN1 Control Register (CAN1CNT) CAN1 Status Register (CAN1STAT) CAN1 Frame Format Select Register (CAN1FFS)
13-15 13-18 13-21
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32180 Group User's Manual (Rev.1.0)
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SFR Area Register Map (23/27)
Address b0 H'0080 1406 H'0080 1408 H'0080 140A H'0080 140C H'0080 140E H'0080 1410 H'0080 1412 H'0080 1414 H'0080 1416 H'0080 1418 +0 address
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b7 b8 CAN1 Configuration Register (CAN1CONF) CAN1 Timestamp Count Register (CAN1TSTMP) CAN1 Receive Error Count Register CAN1 Transmit Error Count Register (CAN1REC) (CAN1TEC) CAN1 Slot Interrupt Request Status Register (CAN1SLIST) (Use inhibited area) CAN1 Slot Interrupt Request Enable Register (CAN1SLIEN) (Use inhibited area) CAN1 Error Interrupt Request Status Register CAN1 Error Interrupt Request Enable Register (CAN1ERIST) (CAN1ERIEN) CAN1 Baud Rate Prescaler CAN1 Cause of Error Register (CAN1BRP) (CAN1EF) CAN1 Mode Register (Use inhibited area) (CAN1MOD) (Use inhibited area) CAN1 Global Mask Register Standard ID 0 CAN1 Global Mask Register Standard ID 1 (C1GMSKS0) (C1GMSKS1) CAN1 Global Mask Register Extended ID 0 CAN1 Global Mask Register Extended ID 1 (C1GMSKE0) (C1GMSKE1) CAN1 Global Mask Register Extended ID 2 (Use inhibited area) (C1GMSKE2) (Use inhibited area) CAN1 Local Mask Register A Standard ID 0 CAN1 Local Mask Register A Standard ID 1 (C1LMSKAS0) (C1LMSKAS1) CAN1 Local Mask Register A Extended ID 0 CAN1 Local Mask Register A Extended ID 1 (C1LMSKAE0) (C1LMSKAE1) CAN1 Local Mask Register A Extended ID 2 (Use inhibited area) (C1LMSKAE2) (Use inhibited area) CAN1 Local Mask Register B Standard ID 0 CAN1 Local Mask Register B Standard ID 1 (C1LMSKBS0) (C1LMSKBS1) CAN1 Local Mask Register B Extended ID 0 CAN1 Local Mask Register B Extended ID 1 (C1LMSKBE0) (C1LMSKBE1) CAN1 Local Mask Register B Extended ID 2 (Use inhibited area) (C1LMSKBE2) (Use inhibited area) CAN1 Single-Shot Mode Control Register (CAN1SSMODE) (Use inhibited area) CAN1 Single-Shot Interrupt Request Status Register (CAN1SSIST) (Use inhibited area) CAN1 Single-Shot Interrupt Request Enable Register (CAN1SSIEN) (Use inhibited area) CAN1 Message Slot 0 Control Register (C1MSL0CNT) CAN1 Message Slot 2 Control Register (C1MSL2CNT) CAN1 Message Slot 4 Control Register (C1MSL4CNT) CAN1 Message Slot 6 Control Register (C1MSL6CNT) CAN1 Message Slot 8 Control Register (C1MSL8CNT) CAN1 Message Slot 10 Control Register (C1MSL10CNT) CAN1 Message Slot 1 Control Register (C1MSL1CNT) CAN1 Message Slot 3 Control Register (C1MSL3CNT) CAN1 Message Slot 5 Control Register (C1MSL5CNT) CAN1 Message Slot 7 Control Register (C1MSL7CNT) CAN1 Message Slot 9 Control Register (C1MSL9CNT) CAN1 Message Slot 11 Control Register (C1MSL11CNT)
See pages b15 13-22 13-24 13-25 13-29
13-30
13-31 13-32 13-26 13-45 13-46
|
H'0080 1428 H'0080 142A H'0080 142C H'0080 142E H'0080 1430 H'0080 1432 H'0080 1434 H'0080 1436 H'0080 1438 H'0080 143A H'0080 143C H'0080 143E H'0080 1440 H'0080 1442 H'0080 1444 H'0080 1446 H'0080 1448
13-48 13-49 13-50
13-48 13-49 13-50
13-48 13-49 13-50
13-52
13-33
13-34
|
H'0080 1450 H'0080 1452 H'0080 1454 H'0080 1456 H'0080 1458 H'0080 145A
13-53 13-53 13-53 13-53 13-53 13-53
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SFR Area Register Map (24/27)
Address b0 H'0080 145C H'0080 145E +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-53 13-53
|
H'0080 1500 H'0080 1502 H'0080 1504 H'0080 1506 H'0080 1508 H'0080 150A H'0080 150C H'0080 150E H'0080 1510 H'0080 1512 H'0080 1514 H'0080 1516 H'0080 1518 H'0080 151A H'0080 151C H'0080 151E H'0080 1520 H'0080 1522 H'0080 1524 H'0080 1526 H'0080 1528 H'0080 152A H'0080 152C H'0080 152E H'0080 1530 H'0080 1532 H'0080 1534 H'0080 1536 H'0080 1538 H'0080 153A H'0080 153C H'0080 153E
CAN1 Message Slot 12 Control Register CAN1 Message Slot 13 Control Register (C1MSL12CNT) (C1MSL13CNT) CAN1 Message Slot 14 Control Register CAN1 Message Slot 15 Control Register (C1MSL14CNT) (C1MSL15CNT) (Use inhibited area) CAN1 Message Slot 0 Standard ID 0 CAN1 Message Slot 0 Standard ID 1 (C1MSL0SID0) (C1MSL0SID1) CAN1 Message Slot 0 Extended ID 0 CAN1 Message Slot 0 Extended ID 1 (C1MSL0EID0) (C1MSL0EID1) CAN1 Message Slot 0 Extended ID 2 CAN1 Message Slot 0 Data Length Register (C1MSL0EID2) (C1MSL0DLC) CAN1 Message Slot 0 Data 0 CAN1 Message Slot 0 Data 1 (C1MSL0DT0) (C1MSL0DT1) CAN1 Message Slot 0 Data 2 CAN1 Message Slot 0 Data 3 (C1MSL0DT2) (C1MSL0DT3) CAN1 Message Slot 0 Data 4 CAN1 Message Slot 0 Data 5 (C1MSL0DT4) (C1MSL0DT5) CAN1 Message Slot 0 Data 6 CAN1 Message Slot 0 Data 7 (C1MSL0DT6) (C1MSL0DT7) CAN1 Message Slot 0 Timestamp (C1MSL0TSP) CAN1 Message Slot 1 Standard ID 0 CAN1 Message Slot 1 Standard ID 1 (C1MSL1SID0) (C1MSL1SID1) CAN1 Message Slot 1 Extended ID 0 CAN1 Message Slot 1 Extended ID 1 (C1MSL1EID0) (C1MSL1EID1) CAN1 Message Slot 1 Extended ID 2 CAN1 Message Slot 1 Data Length Register (C1MSL1EID2) (C1MSL1DLC) CAN1 Message Slot 1 Data 0 CAN1 Message Slot 1 Data 1 (C1MSL1DT0) (C1MSL1DT1) CAN1 Message Slot 1 Data 2 CAN1 Message Slot 1 Data 3 (C1MSL1DT2) (C1MSL1DT3) CAN1 Message Slot 1 Data 4 CAN1 Message Slot 1 Data 5 (C1MSL1DT4) (C1MSL1DT5) CAN1 Message Slot 1 Data 6 CAN1 Message Slot 1 Data 7 (C1MSL1DT6) (C1MSL1DT7) CAN1 Message Slot 1 Timestamp (C1MSL1TSP) CAN1 Message Slot 2 Standard ID 0 CAN1 Message Slot 2 Standard ID 1 (C1MSL2SID0) (C1MSL2SID1) CAN1 Message Slot 2 Extended ID 0 CAN1 Message Slot 2 Extended ID 1 (C1MSL2EID0) (C1MSL2EID1) CAN1 Message Slot 2 Extended ID 2 CAN1 Message Slot 2 Data Length Register (C1MSL2EID2) (C1MSL2DLC) CAN1 Message Slot 2 Data 0 CAN1 Message Slot 2 Data 1 (C1MSL2DT0) (C1MSL2DT1) CAN1 Message Slot 2 Data 2 CAN1 Message Slot 2 Data 3 (C1MSL2DT2) (C1MSL2DT3) CAN1 Message Slot 2 Data 4 CAN1 Message Slot 2 Data 5 (C1MSL2DT4) (C1MSL2DT5) CAN1 Message Slot 2 Data 6 CAN1 Message Slot 2 Data 7 (C1MSL2DT6) (C1MSL2DT7) CAN1 Message Slot 2 Timestamp (C1MSL2TSP) CAN1 Message Slot 3 Standard ID 0 CAN1 Message Slot 3 Standard ID 1 (C1MSL3SID0) (C1MSL3SID1) CAN1 Message Slot 3 Extended ID 0 CAN1 Message Slot 3 Extended ID 1 (C1MSL3EID0) (C1MSL3EID1) CAN1 Message Slot 3 Extended ID 2 CAN1 Message Slot 3 Data Length Register (C1MSL3EID2) (C1MSL3DLC) CAN1 Message Slot 3 Data 0 CAN1 Message Slot 3 Data 1 (C1MSL3DT0) (C1MSL3DT1) CAN1 Message Slot 3 Data 2 CAN1 Message Slot 3 Data 3 (C1MSL3DT2) (C1MSL3DT3) CAN1 Message Slot 3 Data 4 CAN1 Message Slot 3 Data 5 (C1MSL3DT4) (C1MSL3DT5) CAN1 Message Slot 3 Data 6 CAN1 Message Slot 3 Data 7 (C1MSL3DT6) (C1MSL3DT7) CAN1 Message Slot 3 Timestamp (C1MSL3TSP)
13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71
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SFR Area Register Map (25/27)
Address b0 H'0080 1540 H'0080 1542 H'0080 1544 H'0080 1546 H'0080 1548 H'0080 154A H'0080 154C H'0080 154E H'0080 1550 H'0080 1552 H'0080 1554 H'0080 1556 H'0080 1558 H'0080 155A H'0080 155C H'0080 155E H'0080 1560 H'0080 1562 H'0080 1564 H'0080 1566 H'0080 1568 H'0080 156A H'0080 156C H'0080 156E H'0080 1570 H'0080 1572 H'0080 1574 H'0080 1576 H'0080 1578 H'0080 157A H'0080 157C H'0080 157E H'0080 1580 H'0080 1582 H'0080 1584 +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62
CAN1 Message Slot 4 Standard ID 0 CAN1 Message Slot 4 Standard ID 1 (C1MSL4SID0) (C1MSL4SID1) CAN1 Message Slot 4 Extended ID 0 CAN1 Message Slot 4 Extended ID 1 (C1MSL4EID0) (C1MSL4EID1) CAN1 Message Slot 4 Extended ID 2 CAN1 Message Slot 4 Data Length Register (C1MSL4EID2) (C1MSL4DLC) CAN1 Message Slot 4 Data 0 CAN1 Message Slot 4 Data 1 (C1MSL4DT0) (C1MSL4DT1) CAN1 Message Slot 4 Data 2 CAN1 Message Slot 4 Data 3 (C1MSL4DT2) (C1MSL4DT3) CAN1 Message Slot 4 Data 4 CAN1 Message Slot 4 Data 5 (C1MSL4DT4) (C1MSL4DT5) CAN1 Message Slot 4 Data 6 CAN1 Message Slot 4 Data 7 (C1MSL4DT6) (C1MSL4DT7) CAN1 Message Slot 4 Timestamp (C1MSL4TSP) CAN1 Message Slot 5 Standard ID 0 CAN1 Message Slot 5 Standard ID 1 (C1MSL5SID0) (C1MSL5SID1) CAN1 Message Slot 5 Extended ID 0 CAN1 Message Slot 5 Extended ID 1 (C1MSL5EID0) (C1MSL5EID1) CAN1 Message Slot 5 Extended ID 2 CAN1 Message Slot 5 Data Length Register (C1MSL5EID2) (C1MSL5DLC) CAN1 Message Slot 5 Data 0 CAN1 Message Slot 5 Data 1 (C1MSL5DT0) (C1MSL5DT1) CAN1 Message Slot 5 Data 2 CAN1 Message Slot 5 Data 3 (C1MSL5DT2) (C1MSL5DT3) CAN1 Message Slot 5 Data 4 CAN1 Message Slot 5 Data 5 (C1MSL5DT4) (C1MSL5DT5) CAN1 Message Slot 5 Data 6 CAN1 Message Slot 5 Data 7 (C1MSL5DT6) (C1MSL5DT7) CAN1 Message Slot 5 Timestamp (C1MSL5TSP) CAN1 Message Slot 6 Standard ID 0 CAN1 Message Slot 6 Standard ID 1 (C1MSL6SID0) (C1MSL6SID1) CAN1 Message Slot 6 Extended ID 0 CAN1 Message Slot 6 Extended ID 1 (C1MSL6EID0) (C1MSL6EID1) CAN1 Message Slot 6 Extended ID 2 CAN1 Message Slot 6 Data Length Register (C1MSL6EID2) (C1MSL6DLC) CAN1 Message Slot 6 Data 0 CAN1 Message Slot 6 Data 1 (C1MSL6DT0) (C1MSL6DT1) CAN1 Message Slot 6 Data 2 CAN1 Message Slot 6 Data 3 (C1MSL6DT2) (C1MSL6DT3) CAN1 Message Slot 6 Data 4 CAN1 Message Slot 6 Data 5 (C1MSL6DT4) (C1MSL6DT5) CAN1 Message Slot 6 Data 6 CAN1 Message Slot 6 Data 7 (C1MSL6DT6) (C1MSL6DT7) CAN1 Message Slot 6 Timestamp (C1MSL6TSP) CAN1 Message Slot 7 Standard ID 0 CAN1 Message Slot 7 Standard ID 1 (C1MSL7SID0) (C1MSL7SID1) CAN1 Message Slot 7 Extended ID 0 CAN1 Message Slot 7 Extended ID 1 (C1MSL7EID0) (C1MSL7EID1) CAN1 Message Slot 7 Extended ID 2 CAN1 Message Slot 7 Data Length Register (C1MSL7EID2) (C1MSL7DLC) CAN1 Message Slot 7 Data 0 CAN1 Message Slot 7 Data 1 (C1MSL7DT0) (C1MSL7DT1) CAN1 Message Slot 7 Data 2 CAN1 Message Slot 7 Data 3 (C1MSL7DT2) (C1MSL7DT3) CAN1 Message Slot 7 Data 4 CAN1 Message Slot 7 Data 5 (C1MSL7DT4) (C1MSL7DT5) CAN1 Message Slot 7 Data 6 CAN1 Message Slot 7 Data 7 (C1MSL7DT6) (C1MSL7DT7) CAN1 Message Slot 7 Timestamp (C1MSL7TSP) CAN1 Message Slot 8 Standard ID 0 CAN1 Message Slot 8 Standard ID 1 (C1MSL8SID0) (C1MSL8SID1) CAN1 Message Slot 8 Extended ID 0 CAN1 Message Slot 8 Extended ID 1 (C1MSL8EID0) (C1MSL8EID1) CAN1 Message Slot 8 Extended ID 2 CAN1 Message Slot 8 Data Length Register (C1MSL8EID2) (C1MSL8DLC)
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SFR Area Register Map (26/27)
Address b0 H'0080 1586 H'0080 1588 H'0080 158A H'0080 158C H'0080 158E H'0080 1590 H'0080 1592 H'0080 1594 H'0080 1596 H'0080 1598 H'0080 159A H'0080 159C H'0080 159E H'0080 15A0 H'0080 15A2 H'0080 15A4 H'0080 15A6 H'0080 15A8 H'0080 15AA H'0080 15AC H'0080 15AE H'0080 15B0 H'0080 15B2 H'0080 15B4 H'0080 15B6 H'0080 15B8 H'0080 15BA H'0080 15BC H'0080 15BE H'0080 15C0 H'0080 15C2 H'0080 15C4 H'0080 15C6 H'0080 15C8 H'0080 15CA CAN1 Message Slot 8 (C1MSL8DT0) CAN1 Message Slot 8 (C1MSL8DT2) CAN1 Message Slot 8 (C1MSL8DT4) CAN1 Message Slot 8 (C1MSL8DT6) Data 0 +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68
CAN1 Message Slot 8 Data 1 (C1MSL8DT1) Data 2 CAN1 Message Slot 8 Data 3 (C1MSL8DT3) Data 4 CAN1 Message Slot 8 Data 5 (C1MSL8DT5) Data 6 CAN1 Message Slot 8 Data 7 (C1MSL8DT7) CAN1 Message Slot 8 Timestamp (C1MSL8TSP) CAN1 Message Slot 9 Standard ID 0 CAN1 Message Slot 9 Standard ID 1 (C1MSL9SID0) (C1MSL9SID1) CAN1 Message Slot 9 Extended ID 0 CAN1 Message Slot 9 Extended ID 1 (C1MSL9EID0) (C1MSL9EID1) CAN1 Message Slot 9 Extended ID 2 CAN1 Message Slot 9 Data Length Register (C1MSL9EID2) (C1MSL9DLC) CAN1 Message Slot 9 Data 0 CAN1 Message Slot 9 Data 1 (C1MSL9DT0) (C1MSL9DT1) CAN1 Message Slot 9 Data 2 CAN1 Message Slot 9 Data 3 (C1MSL9DT2) (C1MSL9DT3) CAN1 Message Slot 9 Data 4 CAN1 Message Slot 9 Data 5 (C1MSL9DT4) (C1MSL9DT5) CAN1 Message Slot 9 Data 6 CAN1 Message Slot 9 Data 7 (C1MSL9DT6) (C1MSL9DT7) CAN1 Message Slot 9 Timestamp (C1MSL9TSP) CAN1 Message Slot 10 Standard ID 0 CAN1 Message Slot 10 Standard ID 1 (C1MSL10SID0) (C1MSL10SID1) CAN1 Message Slot 10 Extended ID 0 CAN1 Message Slot 10 Extended ID 1 (C1MSL10EID0) (C1MSL10EID1) CAN1 Message Slot 10 Extended ID 2 CAN1 Message Slot 10 Data Length Register (C1MSL10EID2) (C1MSL10DLC) CAN1 Message Slot 10 Data 0 CAN1 Message Slot 10 Data 1 (C1MSL10DT0) (C1MSL10DT1) CAN1 Message Slot 10 Data 2 CAN1 Message Slot 10 Data 3 (C1MSL10DT2) (C1MSL10DT3) CAN1 Message Slot 10 Data 4 CAN1 Message Slot 10 Data 5 (C1MSL10DT4) (C1MSL10DT5) CAN1 Message Slot 10 Data 6 CAN1 Message Slot 10 Data 7 (C1MSL10DT6) (C1MSL10DT7) CAN1 Message Slot 10 Timestamp (C1MSL10TSP) CAN1 Message Slot 11 Standard ID 0 CAN1 Message Slot 11 Standard ID 1 (C1MSL11SID0) (C1MSL11SID1) CAN1 Message Slot 11 Extended ID 0 CAN1 Message Slot 11 Extended ID 1 (C1MSL11EID0) (C1MSL11EID1) CAN1 Message Slot 11 Extended ID 2 CAN1 Message Slot 11 Data Length Register (C1MSL11EID2) (C1MSL11DLC) CAN1 Message Slot 11 Data 0 CAN1 Message Slot 11 Data 1 (C1MSL11DT0) (C1MSL11DT1) CAN1 Message Slot 11 Data 2 CAN1 Message Slot 11 Data 3 (C1MSL11DT2) (C1MSL11DT3) CAN1 Message Slot 11 Data 4 CAN1 Message Slot 11 Data 5 (C1MSL11DT4) (C1MSL11DT5) CAN1 Message Slot 11 Data 6 CAN1 Message Slot 11 Data 7 (C1MSL11DT6) (C1MSL11DT7) CAN1 Message Slot 11 Timestamp (C1MSL11TSP) CAN1 Message Slot 12 Standard ID 0 CAN1 Message Slot 12 Standard ID 1 (C1MSL12SID0) (C1MSL12SID1) CAN1 Message Slot 12 Extended ID 0 CAN1 Message Slot 12 Extended ID 1 (C1MSL12EID0) (C1MSL12EID1) CAN1 Message Slot 12 Extended ID 2 CAN1 Message Slot 12 Data Length Register (C1MSL12EID2) (C1MSL12DLC) CAN1 Message Slot 12 Data 0 CAN1 Message Slot 12 Data 1 (C1MSL12DT0) (C1MSL12DT1) CAN1 Message Slot 12 Data 2 CAN1 Message Slot 12 Data 3 (C1MSL12DT2) (C1MSL12DT3) CAN1 Message Slot 12 Data 4 CAN1 Message Slot 12 Data 5 (C1MSL12DT4) (C1MSL12DT5)
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SFR Area Register Map (27/27)
Address b0 H'0080 15CC H'0080 15CE H'0080 15D0 H'0080 15D2 H'0080 15D4 H'0080 15D6 H'0080 15D8 H'0080 15DA H'0080 15DC H'0080 15DE H'0080 15E0 H'0080 15E2 H'0080 15E4 H'0080 15E6 H'0080 15E8 H'0080 15EA H'0080 15EC H'0080 15EE H'0080 15F0 H'0080 15F2 H'0080 15F4 H'0080 15F6 H'0080 15F8 H'0080 15FA H'0080 15FC H'0080 15FE +0 address b7 b8
ADDRESS SPACE
3.4 Internal RAM and SFR Areas
+1 address b15
See pages 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71 13-57 13-58 13-59 13-60 13-61 13-62 13-63 13-64 13-65 13-66 13-67 13-68 13-69 13-70 13-71
CAN1 Message Slot 12 Data 6 CAN1 Message Slot 12 Data 7 (C1MSL12DT6) (C1MSL12DT7) CAN1 Message Slot 12 Timestamp (C1MSL12TSP) CAN1 Message Slot 13 Standard ID 0 CAN1 Message Slot 13 Standard ID 1 (C1MSL13SID0) (C1MSL13SID1) CAN1 Message Slot 13 Extended ID 0 CAN1 Message Slot 13 Extended ID 1 (C1MSL13EID0) (C1MSL13EID1) CAN1 Message Slot 13 Extended ID 2 CAN1 Message Slot 13 Data Length Register (C1MSL13EID2) (C1MSL13DLC) CAN1 Message Slot 13 Data 0 CAN1 Message Slot 13 Data 1 (C1MSL13DT0) (C1MSL13DT1) CAN1 Message Slot 13 Data 2 CAN1 Message Slot 13 Data 3 (C1MSL13DT2) (C1MSL13DT3) CAN1 Message Slot 13 Data 4 CAN1 Message Slot 13 Data 5 (C1MSL13DT4) (C1MSL13DT5) CAN1 Message Slot 13 Data 6 CAN1 Message Slot 13 Data 7 (C1MSL13DT6) (C1MSL13DT7) CAN1 Message Slot 13 Timestamp (C1MSL13TSP) CAN1 Message Slot 14 Standard ID 0 CAN1 Message Slot 14 Standard ID 1 (C1MSL14SID0) (C1MSL14SID1) CAN1 Message Slot 14 Extended ID 0 CAN1 Message Slot 14 Extended ID 1 (C1MSL14EID0) (C1MSL14EID1) CAN1 Message Slot 14 Extended ID 2 CAN1 Message Slot 14 Data Length Register (C1MSL14EID2) (C1MSL14DLC) CAN1 Message Slot 14 Data 0 CAN1 Message Slot 14 Data 1 (C1MSL14DT0) (C1MSL14DT1) CAN1 Message Slot 14 Data 2 CAN1 Message Slot 14 Data 3 (C1MSL14DT2) (C1MSL14DT3) CAN1 Message Slot 14 Data 4 CAN1 Message Slot 14 Data 5 (C1MSL14DT4) (C1MSL14DT5) CAN1 Message Slot 14 Data 6 CAN1 Message Slot 14 Data 7 (C1MSL14DT6) (C1MSL14DT7) CAN1 Message Slot 14 Timestamp (C1MSL14TSP) CAN1 Message Slot 15 Standard ID 0 CAN1 Message Slot 15 Standard ID 1 (C1MSL15SID0) (C1MSL15SID1) CAN1 Message Slot 15 Extended ID 0 CAN1 Message Slot 15 Extended ID 1 (C1MSL15EID0) (C1MSL15EID1) CAN1 Message Slot 15 Extended ID 2 CAN1 Message Slot 15 Data Length Register (C1MSL15EID2) (C1MSL15DLC) CAN1 Message Slot 15 Data 0 CAN1 Message Slot 15 Data 1 (C1MSL15DT0) (C1MSL15DT1) CAN1 Message Slot 15 Data 2 CAN1 Message Slot 15 Data 3 (C1MSL15DT2) (C1MSL15DT3) CAN1 Message Slot 15 Data 4 CAN1 Message Slot 15 Data 5 (C1MSL15DT4) (C1MSL15DT5) CAN1 Message Slot 15 Data 6 CAN1 Message Slot 15 Data 7 (C1MSL15DT6) (C1MSL15DT7) CAN1 Message Slot 15 Timestamp (C1MSL15TSP)
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3.5 EIT Vector Entry
ADDRESS SPACE
3.5 EIT Vector Entry
The EIT vector entry is located at the beginning of the internal ROM/extended external areas. The branch instruction for jumping to the start address of each EIT event processing handler is written here. Note that it is the branch instruction and not the jump address itself that is written here. For details, see Chapter 4, "EIT."
0
31
H'0000 0000 H'0000 0004 RI (Reset Interrupt) H'0000 0008 H'0000 000C H'0000 0010 H'0000 0014 SBI (System Break Interrupt) H'0000 0018 H'0000 001C H'0000 0020 H'0000 0024 RIE (Reserved Instruction Exception) H'0000 0028 H'0000 002C H'0000 0030 H'0000 0034 AE (Address Exception) H'0000 0038 H'0000 003C H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0080 H'0000 0090 TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 EI (External Interrupt) (Note 1) FPE (Floating-Point Exception)
Note 1: When flash entry bit = 1 (flash E/W enable mode), the EI vector entry is located at H'0080 4000.
Figure 3.5.1 EIT Vector Entry
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3.6 ICU Vector Table
ADDRESS SPACE
3.6 ICU Vector Table
The ICU vector table is used by the internal interrupt controller of the microcomputer. This table has the addresses shown below, at which the start addresses of interrupt handlers for the interrupt requests from respective internal peripheral I/Os are set. For details, see Chapter 5, "Interrupt Controller." ICU Vector Table Memory Map (1/2)
Address b0 H'0000 0094 H'0000 0096 H'0000 0098 H'0000 009A H'0000 009C H'0000 009E H'0000 00A0 H'0000 00A2 H'0000 00A4 H'0000 00A6 H'0000 00A8 H'0000 00AA H'0000 00AC H'0000 00AE H'0000 00B0 H'0000 00B2 H'0000 00B4 H'0000 00B6 H'0000 00B8 H'0000 00BA H'0000 00BC H'0000 00BE H'0000 00C0 H'0000 00C2 H'0000 00C4 H'0000 00C6 H'0000 00C8 H'0000 00CA H'0000 00CC H'0000 00CE H'0000 00D0 H'0000 00D2 H'0000 00D4 H'0000 00D6 +0 address b7 b8 TIN3-6 Input Interrupt Handler Start Address (A0-A15) TIN3-6 Input Interrupt Handler Start Address (A16-A31) TIN20-29 Input Interrupt Handler Start Address (A0-A15) TIN20-29 Input Interrupt Handler Start Address (A16-A31) TIN12-19 Input Interrupt Handler Start Address (A0-A15) TIN12-19 Input Interrupt Handler Start Address (A16-A31) TIN0-2 Input Interrupt Handler Start Address (A0-A15) TIN0-2 Input Interrupt Handler Start Address (A16-A31) TIN7-11 Input Interrupt Handler Start Address (A0-A15) TIN7-11 Input Interrupt Handler Start Address (A16-A31) TMS0, 1 Output Interrupt Handler Start Address (A0-A15) TMS0, 1 Output Interrupt Handler Start Address (A16-A31) TOP8, 9 Output Interrupt Handler Start Address (A0-A15) TOP8, 9 Output Interrupt Handler Start Address (A16-A31) TOP10 Output Interrupt Handler Start Address (A0-A15) TOP10 Output Interrupt Handler Start Address (A16-A31) TIO4-7 Output Interrupt Handler Start Address (A0-A15) TIO4-7 Output Interrupt Handler Start Address (A16-A31) TIO8, 9 Output Interrupt Handler Start Address (A0-A15) TIO8, 9 Output Interrupt Handler Start Address (A16-A31) TOP0-5 Output Interrupt Handler Start Address (A0-A15) TOP0-5 Output Interrupt Handler Start Address (A16-A31) TOP6, 7 Output Interrupt Handler Start Address (A0-A15) TOP6, 7 Output Interrupt Handler Start Address (A16-A31) TIO0-3 Output Interrupt Handler Start Address (A0-A15) TIO0-3 Output Interrupt Handler Start Address (A16-A31) DMA0-4 Interrupt Handler Start Address (A0-A15) DMA0-4 Interrupt Handler Start Address (A16-A31) SIO1 Receive Interrupt Handler Start Address (A0-A15) SIO1 Receive Interrupt Handler Start Address (A16-A31) SIO1 Transmit Interrupt Handler Start Address (A0-A15) SIO1 Transmit Interrupt Handler Start Address (A16-A31) SIO0 Receive Interrupt Handler Start Address (A0-A15) SIO0 Receive Interrupt Handler Start Address (A16-A31) +1 address b15
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ICU Vector Table Memory Map (2/2)
Address b0 H'0000 00D8 H'0000 00DA H'0000 00DC H'0000 00DE H'0000 00E0 H'0000 00E2 H'0000 00E4 H'0000 00E6 H'0000 00E8 H'0000 00EA H'0000 00EC H'0000 00EE H'0000 00F0 H'0000 00F2 H'0000 00F4 H'0000 00F6 H'0000 00F8 H'0000 00FA H'0000 00FC H'0000 00FE H'0000 0100 H'0000 0102 H'0000 0104 H'0000 0106 H'0000 0108 H'0000 010A H'0000 010C H'0000 010E H'0000 0110 H'0000 0112 +0 address b7 b8 SIO0 Transmit Interrupt Handler Start Address (A0-A15) SIO0 Transmit Interrupt Handler Start Address (A16-A31)
ADDRESS SPACE
3.6 ICU Vector Table
+1 address b15
A-D0 Conversion Interrupt Handler Start Address (A0-A15) A-D0 Conversion Interrupt Handler Start Address (A16-A31) TID0 Input Interrupt Handler Start Address (A0-A15) TID0 Input Interrupt Handler Start Address (A16-A31) TOU0 Output Interrupt Handler Start Address (A0-A15) TOU0 Output Interrupt Handler Start Address (A16-A31) DMA5-9 Interrupt Handler Start Address (A0-A15) DMA5-9 Interrupt Handler Start Address (A16-A31) SIO2, 3 Transmit/receive Interrupt Handler Start Address (A0-A15) SIO2, 3 Transmit/receive Interrupt Handler Start Address (A16-A31) RTD Interrupt Handler Start Address (A0-A15) RTD Interrupt Handler Start Address (A16-A31) TID1 Input Interrupt Handler Start Address (A0-A15) TID1 Input Interrupt Handler Start Address (A16-A31) TOU1 + TOU2 Output Interrupt Handler Start Address (A0-A15) TOU1 + TOU2 Output Interrupt Handler Start Address (A16-A31) SIO4, 5 Transmit/receive Interrupt Handler Start Address (A0-A15) SIO4, 5 Transmit/receive Interrupt Handler Start Address (A16-A31) A-D1 Conversion Interrupt Handler Start Address (A0-A15) A-D1 Conversion Interrupt Handler Start Address (A16-A31) TID2 Input Interrupt Handler Start Address (A0-A15) TID2 Input Interrupt Handler Start Address (A16-A31) TIN30-33 Input Interrupt Handler Start Address (A0-A15) TIN30-33 Input Interrupt Handler Start Address (A16-A31) CAN0 Transmit/receive & Error Interrupt Handler Start Address (A0-A15) CAN0 Transmit/receive & Error Interrupt Handler Start Address (A16-A31) CAN1 Transmit/receive & Error Interrupt Handler Start Address (A0-A15) CAN1 Transmit/receive & Error Interrupt Handler Start Address (A16-A31)
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3.7 Notes about Address Space
* Virtual flash emulation function
ADDRESS SPACE 3.7 Notes about Address Space
The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H'0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the virtual flash emulation function. This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the flash memory contents at the addresses specified by the Virtual Flash Bank Register. For details about this function, see Section 6.6, "Virtual Flash Emulation Function."
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CHAPTER 4 EIT
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 Outline of EIT EIT Events EIT Processing Procedure EIT Processing Mechanism Acceptance of EIT Events Saving and Restoring the PC and PSW EIT Vector Entry Exception Processing Interrupt Processing Trap Processing EIT Priority Levels Example of EIT Processing Precautions on EIT
4
4.1 Outline of EIT
EIT
4.1 Outline of EIT
If some event occurs when the CPU is executing an ordinary program, it may become necessary to suspend the program being executed and execute another program. Events like this one are referred to by a generic name as EIT (Exception, Interrupt and Trap). (1) Exception This is an event related to the context being executed. It is generated by an error or violation during instruction execution. This type of event includes Address Exception (AE), Reserved Instruction Exception (RIE) and FloatingPoint Exception (FPE). (2) Interrupt This is an event generated irrespective of the context being executed. It is generated by a hardware-derived signal from an external source, as well as by the internal peripheral I/O. This type of event includes Reset Interrupt (RI), System Break Interrupt (SBI) and External Interrupt (EI). (3) Trap This refers to a software interrupt generated by executing a TRAP instruction. This type of event is intentionally generated in a program as in the OS's system call by the programmer.
EIT
Exception (Exception)
Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE)
Interrupt (Interrupt)
Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI)
Trap (Trap)
Trap (TRAP)
Figure 4.1.1 Classification of EITs
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4.2 EIT Events
4.2.1 Exception
(1) Reserved Instruction Exception (RIE)
EIT
4.2 EIT Events
Reserved Instruction Exception (RIE) occurs when execution of a reserved instruction (unimplemented instruction) is detected. (2) Address Exception (AE) Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. (3) Floating-point Exception (FPE) Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in the IEEE 754 standard (OVF/UDF/IXCT/DIV0/IVLD) is detected. Each exception processing is outlined below. 1) Overflow Exception (OVF) The exception occurs when the absolute value of the operation result exceeds the largest describable precision in the floating-point format. The following table shows the operation results when an OVF occurs. Table 4.2.1 Operation Results When an OVF Occurred
Operation Result (Content of the Destination Register) Rounding Mode Sign of the Result When the OVF EIT processing is masked (Note 1) +MAX -Infinity +Infinity -MAX +MAX -MAX +Infinity -Infinity No change When the OVF EIT processing is executed (Note 2)
-Infinity +Infinity 0 Nearest
+ + + + -
Note 1: When the overflow exception enable (EO) bit (FPSR register bit 20) = "0" Note 2: When the overflow exception enable (EO) bit (FPSR register bit 20) = "1" Note: * If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time. * +MAX = H'7F7F FFFF, -MAX = H'FF7F FFFF
2) Underflow Exception (UDF) The exception occurs when the absolute value of the operation result is less than the largest describable precision in the floating-point format. The following table shows the operation results when a UDF occurs. Table 4.2.2 Operation Results when a UDF Occurred
Operation Result (Content of the Destination Register) When UDF EIT processing is masked (Note 1) DN = 0: An unimplemented exception occurs DN = 1: 0 is returned When UDF EIT processing is executed (Note 2) No change
Note 1: When the underflow exception enable (EU) bit (FPSR register bit 18) = "0" Note 2: When the underflow exception enable (EU) bit (FPSR register bit 18) = "1"
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EIT
4.2 EIT Events
3) Inexact Exception (IXCT) The exception occurs when the operation result differs from a result led out with an infinite range of precision. The following table shows the operation results and the respective conditions in which each IXCT occurs. Table 4.2.3 Operation Results when an IXCT Occurred
Operation Result (Content of the Destination Register) Occurrence Condition When the IXCT EIT processing for is masked (Note 1) Reference OVF operation results Rounded value When the IXCT EIT processing is executed (Note 2) No change No change
Overflow occurs in OVF masked condition Rounding occurs
Note 1: When the inexact exception enable (EX) bit (FPSR register bit 17) = "0" Note 2: When the inexact exception enable (EX) bit (FPSR register bit 17) = "1"
4) Zero Division Exception (DIV0) The exception occurs when a finite nonzero value is divided by zero. The following table shows the operation results when a DIV0 is occurs. Table 4.2.4 Operation Results When a DIV0 Occurred
Operation Result (Content of the Destination Register) Dividend When the DIV0 EIT processing is masked (Note 1) +-Infinity (Sign is derived by exclusive ORing the signs of the divisor and dividend.) When the DIV0 EIT processing is executed (Note 2) No change
Nonzero finite value
Note 1: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "0" Note 2: When the zero division exception enable (EZ) bit (FPSR register bit 19) = "1"
Please note that the DIV0 EIT processing does not occur in the following conditions. Table 4.2.5 Cases in Which No DIV0 Occur
Dividend 0 Infinity Behavior An invalid operation exception occurs No exceptions occur (with the result = "Infinity")
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Table 4.2.6 Operation Results When an IVLD Occurred
EIT
4.2 EIT Events
5) Invalid Operation Exception (IVLD) The exception occurs when an invalid operation is executed. The following table shows the operation results and the respective conditions in which each IVLD occurs.
Operation Result (Content of the Destination Register) Occurrence Condition When the IVLD EIT When the IVLD EIT processing is masked (Note 1) processing is executed (Note 2)
Operation for SNaN operand +Infinity-(+Infinity), -Infinity-(-Infinity) 0 x Infinity 0 / 0, Infinity / Infinity When FTOI Return value when pre-conversion signed bit is: instruction was "0": H 7FFF FFFF When an integer conversion executed "1": H 8000 0000 overflowed When NaN or Infinity was converted When FTOS Return value when pre-conversion signed bit is: into an integer instruction was "0": H 0000 7FFF executed "1": H FFFF 8000 When < or > comparison was performed on NaN Comparison results (comparison invalid) No change QNaN
Note 1: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "0" Note 2: When the invalid operation exception enable (EV) bit (FPSR register bit 21) = "1" Note: * NaN (Not a Number) SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction is "0". When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs are useful in identifying program bugs when used as the initial value in a variable. However, SNaNs cannot be generated by hardware. QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction is "1". Even when QNaN is used as the source operand in an operation, an IVLD will not occur (excluding comparison and format conversion). Because a result can be checked by the arithmetic operations, QNaN allows the user to debug without executing an EIT processing. QNaNs are created by hardware.
6) Unimplemented Exception (UIPL) The exception occurs when the denormalized number zero flush (DN) bit (FPSR register bit 23) = "0" and a denormalized number is given as an operation operand. (Note 1) Because the UIPL has no enable bits available, it cannot be masked when they occur. The destination register remains unchanged. Note 1: A UDF occurs when the intermediate result of an operation is a denormalized number, in which case if the DN bit (FPSR register bit 23) = "0", an UIPL occurs.
4.2.2 Interrupt
(1) Reset Interrupt (RI) Reset Interrupt (RI) is always accepted by entering the RESET# signal. The reset interrupt is assigned the highest priority. For details about the reset interrupt, see Chapter 7, "Reset." (2) System Break Interrupt (SBI) System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. This interrupt can only be used in cases when after interrupt processing, control will not return to the program that was being executed when the interrupt occurred. (3) External Interrupt (EI) External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt controller. The interrupt controller manages these interrupts by assigning each one of eight priority levels including an interrupt-disabled state.
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4.2.3 Trap
EIT
4.2 EIT Events
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen distinct vector addresses are provided corresponding to TRAP instruction operands 0-15.
4.3 EIT Processing Procedure
EIT processing consists of two parts, one in which they are handled automatically by hardware, and one in which they are handled by user-created programs (EIT handlers). The procedure for processing EITs when accepted, except for a rest interrupt, is shown below.
EIT request generated Program execution restarted
Instruction Instruction Instruction A B C
Program suspended and EIT request accepted
Instruction Instruction C D
Instruction processing-canceled type (RIE, AE)
Instruction processing-completed type (FPE, EI, TRAP)
PCBPC PSWBPSW Hardware preprocessing (Note 1)
Hardware postprocessing
(Note 1) BPSWPSW BPCPC
User-created EIT handler EIT vector entry
Branch instruction BPC, PSW, FPSR and general-purpose registers are saved to the stack
EIT handler except for SBI
Processing by handler General-purpose registers, PSW, FPSR and BPC are restored from the stack RTE instruction
(SBI)
SBI (System Break Interrupt processing)
Program terminated or system is reset
Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.
Figure 4.3.1 Outline of the EIT Processing Procedure When an EIT is accepted, the CPU branches to the EIT vector after hardware preprocessing (as will be described later). The EIT vector has an entry address assigned for each EIT. This is where the BRA (branch) instruction for the EIT handler (not the jump address itself) is written. In the hardware preprocessing, the PC is transferred to the BPC (backup PC), and the content of the PSW register's PSW field is transferred to the BPSW field in that register. Other necessary operations must be performed in the user-created EIT handler. These include saving the BPC and PSW registers (including the BPSW field) and the general-purpose registers to be used in the EIT handler to the stack. In addition, the accumulator and the FPSR register must be saved to the stack as necessary. Remember that all these registers must be saved to the stack in a program by the user. When processing by the EIT handler is completed, restore the saved registers from the stack and finally execute the RTE instruction. Control is thereby returned from the EIT processing to the program that was being executed when the EIT occurred. (This does not apply to the System Break Interrupt, however.) In the hardware postprocessing, the BPC is returned to the PC, and the content of the PSW register's BPSW field is returned to the PSW field in that register. Note that the values stored in the BPC and the PSW register's BPSW field after executing the RTE instruction are undefined.
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4.4 EIT Processing Mechanism
EIT
4.4 EIT Processing Mechanism
The EIT processing mechanism consists of the M32R CPU core and the interrupt controller for internal peripheral I/ Os. It also has the backup registers for the PC and PSW (the BPC register and the BPSW field of the PSW register). The EIT processing mechanism is shown below.
M32R/ECU
M32R CPU core
RESET#
RI
RI AE, RIE, FPE, TRAP
High
Priority SBI# Interrupt controller (ICU) SBI SBI
Internal peripheral I/Os
EI
EI Low IE flag (PSW)
BPC register
BPSW PSW
PC register
PSW register
Figure 4.4.1 EIT Processing Mechanism
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4.5 Acceptance of EIT Events
EIT
4.5 Acceptance of EIT Events
When an EIT event occurs, the CPU suspends the program it has hitherto been executing and branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs and the timing at which they are accepted are shown below. Table 4.5.1 Acceptance of EIT Events
EIT Event Reserved Instruction Exception (RIE) Address Exception (AE) Floating-Point Exception (FPE) Reset Interrupt (RI) System Break Interrupt (SBI) External Interrupt (EI) Trap (TRAP) Type of Processing Instruction processingcanceled type Instruction processingcanceled type Instruction processingcompleted type Instruction processingaborted type Instruction processingcompleted type Instruction processingcompleted type Instruction processingcompleted type Acceptance Timing During instruction execution During instruction execution Break in instructions Each machine cycle Break in instructions (word boundary only) Break in instructions (word boundary only) Break in instructions Values Set in BPC Register PC value of the instruction that generated RIE PC value of the instruction that generated AE PC value of the instruction that generated FPE + 4 Undefined value PC value of the next instruction PC value of the next instruction PC value of TRAP instruction + 4
4.6 Saving and Restoring the PC and PSW
The following describes operation of the microcomputer at the time when it accepts an EIT and when it executes the RTE instruction.
(1) Hardware preprocessing when an EIT is accepted
[1] Save the PSW register's SM, IE and C bits in its backup field. BSM SM BIE IE BC C [2] Update the PSW register's SM, IE and C bits SM Remains unchanged (RIE, AE, FPE, TRAP) or cleared to "0" (SBI, EI, RI) IE Cleared to "0" C Cleared to "0" [3] Save the PC register BPC PC [4] Set the vector address in the PC register Branches to the EIT vector and executes the branch (BRA) instruction written in it, thereby transferring control to the user-created EIT handler.
(2) Hardware postprocessing when the RTE instruction is executed
[A] Restore the PSW register's SM, IE and C bits from its backup field. SM BSM IE BIE C BC [B] Restore the PC register from the BPC register. PC BPC Note: * The values stored in the BPC and the PSW register's BSM, BIE and BC bits after executing the RTE instruction are undefined.
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[1] Saving the SM, IE and C bits BSM BIE BC SM IE C
EIT
4.6 Saving and Restoring the PC and PSW
[3] Saving the PC BPC PC
[4] Setting the vector address in the PC PC Vector address
[2] Updating the SM, IE and C bits SM IE C Unchanged or 0 0 0
[A] Restoring the SM, IE and C bits from the backup field SM IE C BSM BIE BC
[B] Restoring the PC from the BPC register The value stored in the BPC register after executing the RTE instruction is undefined.
The values stored in the BSM, BIE and BC bits after executing the RTE instruction are undefined.
PSW
BPC
PC
When EIT is accepted
[1] [2]
[3] [4]
When RTE instruction is executed
[A]
[B]
BPSW field
0(MSB) 7 8 15 16 17 23 24 25
PSW field
31(LSB)
PSW
0000000000000000
00000
00000
BSM
BIE
BC
SM
IE
C
Figure 4.6.1 Saving and Restoring the PC and PSW
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4.7 EIT Vector Entry
EIT
4.7 EIT Vector Entry
The EIT vector entry is located in the user space beginning with the address H'0000 0000. The table below lists the EIT vector entry. Table 4.7.1 EIT Vector Entry
Name Reset Interrupt System Break Reserved Instruction Exception Address Exception Trap AE TRAP0 TRAP1 TRAP2 TRAP3 TRAP4 TRAP5 TRAP6 TRAP7 TRAP8 TRAP9 TRAP10 TRAP11 TRAP12 TRAP13 TRAP14 TRAP15 External Interrupt Floating-Point Exception EI FPE H'0000 0030 H'0000 0040 H'0000 0044 H'0000 0048 H'0000 004C H'0000 0050 H'0000 0054 H'0000 0058 H'0000 005C H'0000 0060 H'0000 0064 H'0000 0068 H'0000 006C H'0000 0070 H'0000 0074 H'0000 0078 H'0000 007C H'0000 0090 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 Unchanged 0 0 Unchanged 0 PC of the instruction that generated RIE PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of TRAP instruction + 4 PC of the next instruction PC of the instruction that generated FPE + 4 Abbreviation Vector Address RI SBI RIE H'0000 0010 H'0000 0020 SM 0 IE 0 0 BPC Undefined PC of the next instruction PC of the instruction that generated RIE H'0000 0000 (Note 1) 0
Interrupt
Unchanged 0
H'0000 0080 (Note 2) 0
Note 1: During boot mode, the CPU starts executing the boot program after reset. For details, see Section 6.5, "Programming the Internal Flash Memory." Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM (address H'0080 4000). For details, see Section 6.5, "Programming the Internal Flash Memory."
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4.8 Exception Processing
4.8.1 Reserved Instruction Exception (RIE)
EIT
4.8 Exception Processing
[Occurrence Conditions] Reserved Instruction Exception (RIE) occurs when a reserved instruction (unimplemented instruction) is detected. Instruction check is performed on the op-code part of the instruction. When a reserved instruction exception occurs, the instruction that generated it is not executed. If an external interrupt is requested at the same time a reserved instruction exception is detected, it is the reserved instruction exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM SM BIE IE BC C (2) Updating SM, IE and C bits The PSW register's SM, IE and C bits are updated as shown below. SM Unchanged IE 0 C 0 (3) Saving the PC The PC value of the instruction that generated the reserved instruction exception is set in the BPC register. For example, if the instruction that generated the reserved instruction exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the reserved instruction exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to `00' when returned to the PC.)
+0 Address H'00
Return address
+1
+2
+3 Address H'00
Return address
+0
+1
+2
+3
H'04 H'08 H'0C
RIE occurred
H'04 H'08 H'0C
RIE occurred
BPC
H'04
BPC
H'06
Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE)
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EIT
4.8 Exception Processing
(4) Branching to the EIT vector entry The CPU branches to the address H'0000 0020 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H'0000 0020 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated a RIE (see Figure 4.8.1). Except when using reserved instruction exceptions intentionally, occurrence of a reserved instruction exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the reserved instruction exception handler to the program that was being executed when the exception occurred.
4.8.2 Address Exception (AE)
[Occurrence Conditions] Address Exception (AE) occurs when an attempt is made to access a misaligned address in Load or Store instructions. The following lists the combination of instructions and accessed addresses that may cause address exceptions to occur. * Two low-order address bits accessed in the LDH, LDUH or STH instruction are `01' or `11' * Two low-order address bits accessed in the LD, ST, LOCK or UNLOCK instruction are `01,' `10' or `11' When an address exception occurs, memory access by the instruction that generated the exception is not performed. If an external interrupt is requested at the same time an address exception is detected, it is the address exception that is accepted. [EIT Processing] (1) Saving SM, IE and C bits The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM SM BIE IE BC C (2) Updating SM, IE and C bits The PSW register's SM, IE and C bits are updated as shown below. SM Unchanged IE 0 C 0 (3) Saving the PC The PC value of the instruction that generated the address exception is set in the BPC register. For example, if the instruction that generated the address exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction that generated the address exception is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC register bit 30 indicates whether the instruction that generated the reserved instruction exception resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 4. (This is because the 2 low-order address bits are cleared to `00' when returned to the PC.)
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+0 Address H'00
Return address
EIT
4.8 Exception Processing
+1
+2
+3 Address H'00
Return address
+0
+1
+2
+3
H'04 H'08 H'0C
AE occurred
H'04 H'08 H'0C
AE occurred
BPC
H'04
BPC
H'06
Figure 4.8.2 Example of a Return Address for Address Exception (AE) (4) Branching to the EIT vector entry The CPU branches to the address H'0000 0030 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H'0000 0030 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from a word-boundary instruction including the instruction that generated an AE (see Figure 4.8.2). Except when using address exceptions intentionally, occurrence of an address exception suggests that the system has some fatal fault already existing in it. In such a case, therefore, do not return from the address exception handler to the program that was being executed when the exception occurred.
4.8.3 Floating-Point Exception (FPE)
[Occurrence Conditions] Floating-Point Exception (FPE) occurs when Unimplemented Exception (UIPL) or one of the five exceptions specified in IEEE 754 standards (OVF, UDF, IXCT, DIV0 or IVLD) is detected. Note, however, that the EIT processing described below is executed only when the exception that occurred is one whose exception enable bit in the FPSR register is set to "1" or an unimplemented exception. [EIT Processing] (1) Saving SM, IE and C bits The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM SM BIE IE BC C (2) Updating SM, IE and C bits The PSW register's SM, IE and C bits are updated as shown below. SM Unchanged IE 0 C 0
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EIT
4.8 Exception Processing
(3) Saving the PC The PC value of the instruction that generated the FPE exception + 4 is set in the BPC register. Because all of the instructions that generate an FPE exception are 32 bits long, the address to which the RTE returns is always the instruction next to the one that generated the FPE exception. (4) Branching to the EIT vector entry The CPU branches to the address H'0000 0090 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H'0000 0090 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC, PSW and FPSR registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.
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4.9 Interrupt Processing
4.9.1 Reset Interrupt (RI)
EIT
4.9 Interrupt Processing
[Occurrence Conditions] A reset interrupt is unconditionally accepted in any machine cycle by pulling the RESET# input signal low. The reset interrupt is assigned the highest priority among all EITs. [EIT Processing] (1) Initializing SM, IE and C bits The PSW register's SM, IE and C bits are initialized as shown below. SM 0 IE 0 C 0 For the reset interrupt, the values of SM, IE and C bits are undefined. (2) Branching to the EIT vector entry The CPU branches to the address H'0000 0000 in the user space. However, when operating in boot mode, the CPU jumps to the boot program. For details, see Section 6.5, "Programming the Internal Flash Memory." (3) Jumping from the EIT vector entry to the user program The CPU executes the instruction written by the user at the address H'0000 0000 of the EIT vector entry. In the reset vector entry, be sure to initialize the PSW and SPI registers before jumping to the start address of the user program.
4.9.2 System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt cannot be masked by the PSW register IE bit. Therefore, the system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred. [Occurrence Conditions] A system break interrupt is accepted by a falling edge on SBI# input pin. (The system break interrupt cannot be masked by the PSW register IE bit.) In no case will a system break interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.) Note also that because of the instruction processing-completed type, a system break interrupt is accepted after the instruction is completed.
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Order in which instructions are executed
Address 1000 Address 1002 Address 1004
EIT
4.9 Interrupt Processing
Address 1000
16-bit instruction 16-bit instruction
32-bit instruction
x
Interrupt may be accepted Interrupt cannot Interrupt may be accepted be accepted Interrupt may be accepted
Figure 4.9.1 Timing at Which System Break Interrupt (SBI) is Accepted
[EIT Processing] (1) Saving SM, IE and C bits The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM SM BIE IE BC C (2) Updating SM, IE and C bits The PSW register's SM, IE and C bits are updated as shown below. SM 0 IE 0 C 0 (3) Saving the PC The address of the next instruction (always on word boundary) following one in which the interrupt was detected is stored in the BPC register. If the interrupt was detected in a branch instruction, then the next instruction is one that exists at the jump address. (4) Branching to the EIT vector entry The CPU branches to the address H'0000 0010 in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H'0000 0010 of the EIT vector entry to jump to the start address of the user-created handler. The system break interrupt can only be used when the system has some fatal event already existing in it when the interrupt is detected. Also, this interrupt must be used on condition that after processing by the SBI handler, control will not return to the program that was being executed when the system break interrupt occurred.
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4.9.3 External Interrupt (EI)
EIT
4.9 Interrupt Processing
An external interrupt is generated upon an interrupt request which is output by the microcomputer's internal interrupt controller. The interrupt controller manages interrupt requests by assigning each one of seven priority levels. For details, see Chapter 5, "Interrupt Controller." For details about the interrupt request sources, see each section in which the relevant internal peripheral I/O is described. [Occurrence Conditions] External interrupts are managed based on interrupt requests from each internal peripheral I/O by the microcomputer's internal interrupt controller, and are sent to the CPU via the interrupt controller. The CPU checks these interrupt requests at a break in instructions residing on word boundaries, and when an interrupt request is detected and the PSW register IE flag = "1", accepts it as an external interrupt. In no case will an external interrupt be activated immediately after executing a 16-bit instruction that starts from a word boundary. (For 16-bit branch instructions, however, the interrupt is accepted immediately after branching.)
Order in which instructions are executed
Address 1000 Address 1002 Address 1004 Address 1008
16-bit instruction 16-bit instruction
32-bit instruction
x
Interrupt may be accepted Interrupt cannot be accepted Interrupt may be accepted Interrupt may be accepted
Figure 4.9.2 Timing at Which External Interrupt (EI) is Accepted [EIT Processing] (1) Saving SM, IE and C bits The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM SM BIE IE BC C (2) Updating SM, IE and C bits The PSW register's SM, IE and C bits are updated as shown below. SM 0 IE 0 C 0 (3) Saving the PC The content of the PC register (always on word boundary) is saved to the BPC register. (4) Branching to the EIT vector entry The CPU branches to the address H'0000 0080 in the user space. However, when operating in flash E/W enable mode, the CPU goes to the beginning of the internal RAM (address H'0080 4000). (For details, see Section 6.5, "Programming the Internal Flash Memory.") This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the address H'0000 0080 of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the user-created EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. Also, save the accumulator and FPSR register as necessary.
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EIT
4.9 Interrupt Processing
(6) Returning from the EIT handler At the end of the EIT handler, restore the saved registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed.
4.10 Trap Processing
4.10.1 Trap
[Occurrence Conditions] Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen traps are generated, each corresponding to one of TRAP instruction operands 0-15. Accordingly, sixteen vector entries are provided. [EIT Processing] (1) Saving SM, IE and C bits The PSW register's SM, IE and C bits are saved to the respective backup bits: BSM, BIE and BC. BSM SM BIE IE BC C (2) Updating SM, IE and C bits The PSW register's SM, IE and C bits are updated as shown below. SM Unchanged IE 0 C 0 (3) Saving the PC When the trap instruction is executed, the PC value of TRAP instruction + 4 is set in the BPC register. For example, if the TRAP instruction is located at address 4, the value H'08 is set in the BPC register. Similarly, if the TRAP instruction is located at address 6, the value H'0A is set in the BPC register. The value of the BPC register bit 30 indicates whether the trap instruction resides on a word boundary (BPC register bit 30 = "0") or not on a word boundary (BPC register bit 30 = "1"). However, in either case of the above, the address to which the RTE instruction returns after the EIT handler has terminated is address 8. (This is because the 2 low-order address bits are cleared to `00' when returned to the PC.)
+0 Address
+1
+2
+3 Address H'00
Return address
+0
+1
+2
+3
Return address
H'00 H'04 TRAP instruction H'08 H'0C
H'04 H'08 H'0C
TRAP instruction
BPC
H'08
BPC
H'0A
Figure 4.10.1 Example of a Return Address for Trap (TRAP)
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EIT
4.10 Trap Processing
(4) Branching to the EIT vector entry The CPU branches to the addresses H'0000 0040-H'0000 007C in the user space. This is the last operation performed in hardware preprocessing. (5) Jumping from the EIT vector entry to the user-created handler The CPU executes the BRA instruction written by the user at the addresses H'0000 0040-H'0000 007C of the EIT vector entry to jump to the start address of the user-created handler. At the beginning of the usercreated EIT handler, first save the BPC and PSW registers and the necessary general-purpose registers to the stack. (6) Returning from the EIT handler At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW registers from the stack and execute the RTE instruction. When the RTE instruction is executed, hardware postprocessing is automatically performed. At this time, the CPU restarts from the next word-boundary instruction including the instruction that generates a trap (see Figure 4.10.1).
4.11 EIT Priority Levels
The table below lists the priority levels of EIT events. When two or more EITs occur simultaneously, the event with the highest priority is accepted first. Table 4.11.1 Priority of EIT Events and How Returned from EIT
Priority 2 EIT Event Address Exception (AE) Reserved Instruction Exception (RIE) Floating-Point Exception (FPE) Trap (TRAP) 3 4 System Break Interrupt (SBI) External Interrupt (EI) Instruction processing-completed type PC of the next instruction Instruction processing-completed type Instruction processing-completed type Instruction processing-completed type Type of Processing Instruction processing-aborted type Instruction processing-canceled type Instruction processing-canceled type Values Set in BPC Register Undefined PC of the instruction that generated AE PC of the instruction that generated AE PC of the instruction that generated FPE + 4 TRAP instruction + 4 PC of the next instruction 1 (Highest) Reset Interrupt (RI)
Note that for External Interrupt (EI), the priority levels of interrupt requests from each peripheral I/O are set by the microcomputer's internal interrupt controller. For details, see Chapter 5, "Interrupt Controller."
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4.12 Example of EIT Processing
(1) When RIE, AE, FPE, SBI, EI or TRAP occurs singly
EIT
4.12 Example of EIT Processing
IE = 1 BPC register = Return address A IE = 0 RIE, AE, FPE, SBI, EI or TRAP occurs singly Return address A: IE = 1 RTE instruction If IE = 0, no events but reset and SBI are accepted.
: EIT handler
Figure 4.12.1 Processing of Events When RIE, AE, FPE, SBI, EI or TRAP Occurs Singly
(2) When RIE, AE, FPE or TRAP and EI occur simultaneously
IE = 1 IE = 0 RIE, AE, FPE or TRAP and EI occur simultaneously Return address A:
RIE, AE, FPE or TRAP is accepted first. BPC register = Return address A
RTE instruction IE = 1 IE = 0 IE = 1 EI is accepted next. BPC register = Return address A RTE instruction : EIT handler
Figure 4.12.2 Processing of Events When RIE, AE, FPE or TRAP and EI Occur Simultaneously
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EIT vector entry
BRA instruction
EIT
4.12 Example of EIT Processing
(Other than SBI) EIT handler
(SBI)
PCBPC Hardware preprocessing PSWBPSW (Note 1)
Save BPC to the stack
Save PSW to the stack System Break Interrupt (SBI) processing
Program being executed
Save general-purpose registers to the stack
EIT event occurs
Processing by EIT handler
Program terminated or system reset
Restore general-purpose registers from the stack
(Note 1) Hardware BPSWPSW postprocessing BPCPC
Restore PSW from the stack
Restore BPC from the stack
RTE
Note 1: Indicates saving and restoring the PSW register bits between its PSW and BPSW fields.
Figure 4.12.3 Example of EIT Processing
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4.13 Precautions on EIT
EIT
4.13 Precautions on EIT
The Address Exception (AE) requires caution because if one of the instructions that use "register indirect + register update" addressing mode (following three) generates an address exception when it is executed, the values of the registers to be automatically updated (Rsrc and Rsrc2) become undefined. Except that the values of Rsrc and Rsrc2 become undefined, these instructions behave the same way as when used in other addressing modes. * Applicable instructions LD Rdest, @Rsrc+ ST Rsrc1, @-Rsrc2 ST Rsrc1, @+Rsrc2 If the above case applies, consider the fact that the register values become undefined when you design the processing to be performed after executing said instructions. (If an address exception occurs, it means that the system has some fatal fault already existing in it. Therefore, address exceptions must be used on condition that control will not be returned from the address exception handler to the program that was being executed when the exception occurred.)
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CHAPTER 5 INTERRUPT CONTROLLER (ICU)
5.1 5.2 5.3 5.4 5.5 5.6 Outline of the Interrupt Controller ICU Related Registers Interrupt Request Sources in Internal Peripheral I/O ICU Vector Table Description of Interrupt Operation Description of System Break Interrupt (SBI) Operation
5
5.1 Outline of the Interrupt Controller
INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller
The Interrupt Controller (ICU) manages maskable interrupts from internal peripheral I/Os and a system break interrupt (SBI). The maskable interrupts from internal peripheral I/Os are sent to the M32R CPU as external interrupts (EI). The maskable interrupts from internal peripheral I/Os are managed by assigning them one of eight priority levels including an interrupt-disabled state. If two or more interrupt requests with the same priority level occur at the same time, their priorities are resolved by predetermined hardware priority. The source of an interrupt request generated in internal peripheral I/Os is identified by reading the relevant interrupt status register provided for internal peripheral I/Os. On the other hand, the system break interrupt (SBI) is recognized when a low-going transition occurs on the SBI# signal input pin. This interrupt is used for emergency purposes such as when power outage is detected or a fault condition is notified by an external watchdog timer, so that it is always accepted irrespective of the PSW register IE bit status. When the CPU has finished servicing an SBI, shut down or reset the system without returning to the program that was being executed when the interrupt occurred. Specifications of the Interrupt Controller are outlined below. Table 5.1.1 Outline of the Interrupt Controller (ICU)
Item Interrupt request source Priority management Specification Maskable interrupt requests from internal peripheral I/Os: 32 sources (Note 1) System break interrupt request: 1 source (entered from SBI# pin) 8 priority levels including an interrupt-disabled state (However, interrupts with the same priority level have their priorities resolved by fixed hardware priority.) Note 1: There are actually a total of 179 interrupt request resources when counted individually, which are grouped into 32 interrupt request resources.
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Interrupt Controller
INTERRUPT CONTROLLER (ICU)
5.1 Outline of the Interrupt Controller
System Break Interrupt (SBI) request generated (nonmaskable) SBI Control Register (SBICR) SBI# SBIREQ SBI To the CPU core
Peripheral circuits
Interrupt request Interrupt request Interrupt request
Edge Edge Edge
IREQ
Priority resolved by interrupt priority levels set
ILEVEL
Priority resolved by fixed hardware priority
IREQ IREQ
External Interrupt (EI) request generated (maskable)
Interrupt Vector Register (IVECT)
IMASK comparison
EI To the CPU core NEW_IMASK
IREQ
Interrupt control circuit Interrupt control circuit Interrupt control circuit
Level IREQ Level IREQ Level
Interrupt Request Mask Register (IMASK)
Interrupt Control Register
Figure 5.1.1 Block Diagram of the Interrupt Controller
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5.2 ICU Related Registers
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
The diagram below shows a register map associated with the Interrupt Controller (ICU). ICU Related Register Map
Address b0 H'0080 0000 H'0080 0002 H'0080 0004 H'0080 0006 +0 address b7 b8 Interrupt Vector Register (IVECT) (Use inhibited area) Interrupt Request Mask Register (IMASK) SBI Control Register (SBICR) (Use inhibited area) CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR) TID2 Output Interrupt Control Register (ITID2CR) SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) TID1 Output Interrupt Control Register (ITID1CR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) TOU0 Output Interrupt Control Register (ITOU0CR) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) TIO0-3 Output Interrupt Control Register (ITIO03CR) TOP0-5 Output Interrupt Control Register (ITOP05CR) TIO4-7 Output Interrupt Control Register (ITIO47CR) TOP8,9 Output Interrupt Control Register (ITOP89CR) TIN7-11 Input Interrupt Control Register (ITIN711CR) TIN12-19 Input Interrupt Control Register (ITIN1219CR) TIN3-6 Input Interrupt Control Register (ITIN36CR) TIN30-33 Input Interrupt Control Register (ITIN3033CR) A-D1 Conversion Interrupt Control Register (IAD1CCR) TOU1,2 Output Interrupt Control Register (ITOU12CR) RTD Interrupt Control Register (IRTDCR) DMA5-9 Interrupt Control Register (IDMA59CR) TID0 Output Interrupt Control Register (ITID0CR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) DMA0-4 Interrupt Control Register (IDMA04CR) TOP6,7 Output Interrupt Control Register (ITOP67CR) TOP8,9 Output Interrupt Control Register (ITOP89CR) TOP10 Output Interrupt Control Register (ITOP10CR) TMS0,1 Output Interrupt Control Register (ITMS01CR) TIN0-2 Input Interrupt Control Register (ITIN02CR) TIN20-29 Input Interrupt Control Register (ITIN2029CR) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR) 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 5-8 (Use inhibited area) (Use inhibited area) +1 address b15 5-5 See pages
5-6 5-7
|
H'0080 0060 H'0080 0062 H'0080 0064 H'0080 0066 H'0080 0068 H'0080 006A H'0080 006C H'0080 006E H'0080 0070 H'0080 0072 H'0080 0074 H'0080 0076 H'0080 0078 H'0080 007A H'0080 007C H'0080 007E
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5.2.1 Interrupt Vector Register
Interrupt Vector Register (IVECT)
b0
?
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers

5
?
1
?
2
?
3
?
4
?
6
?
7
IVECT ?
8
?
9
?
10
?
11
?
12
?
13
?
14
?
b15
?
b 8 Bit Name IVECT Function When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in this register. Note: * This register must always be accessed in halfwords (2 bytes). (This is a read-only register.) R R W N
16 low-order bits of ICU vector table address
The Interrupt Vector Register (IVECT) is used when an interrupt request is accepted to store the 16-low-order bits of the ICU vector table address for the accepted interrupt request source. Before this function can work, the ICU vector table (addresses H'0000 0094 through H'0000 0113) must have set in it the start addresses of interrupt handlers for each internal peripheral I/O. When an interrupt request is accepted, the 16-low-order bits of the ICU vector table address for the accepted interrupt request source are stored in the IVECT register. In the EIT handler, read the content of this IVECT register using the LDH instruction to get the ICU vector table address. When the IVECT register is read, operations (1) to (4) below are automatically performed in hardware. (1) The interrupt priority level of the accepted interrupt request source (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) (2) The interrupt request bit for the accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). (3) The interrupt request (EI) to the CPU core is deasserted. (4) The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: * Do not read the Interrupt Vector Register (IVECT) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0"). In the EIT handler, furthermore, read the Interrupt Request Mask Register (IMASK) first before reading the IVECT register. * To reenable interrupts (by setting the IE bit to "1") after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. (The ICU vector table readout in the EI handler processing example in Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O is an access to the internal ROM and, therefore, does not require adding a dummy access.)
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5.2.2 Interrupt Request Mask Register
Interrupt Request Mask Register (IMASK)
b0
0
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers

6 b7
1
1
0
2
0
3
0
4
0
5
1
IMASK 1
b 0-4 5-7 Bit Name No function assigned. Fix to "0" IMASK Interrupt mask bit 000: Disable maskable interrupts 001: Accept interrupts with priority level 0 010: Accept interrupts with priority levels 0-1 011: Accept interrupts with priority levels 0-2 100: Accept interrupts with priority levels 0-3 101: Accept interrupts with priority levels 0-4 110: Accept interrupts with priority levels 0-5 111: Accept interrupts with priority levels 0-6 Function R 0 R W 0 W
The Interrupt Request Mask Register (IMASK) is used to finally determine whether or not to accept an interrupt request after comparing its priority with the priority levels (Interrupt Control Register ILEVEL bits) that have been set for each interrupt request source. When the Interrupt Vector Register (IVECT) described above is read, the interrupt priority level of the accepted interrupt request source is set in this IMASK register as a new mask value. When any value is written to the IMASK register, operations (1) to (2) below are automatically performed in hardware. (1) The interrupt request (EI) to the CPU core is deasserted. (2) The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Notes: * Do not write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = "0"). * To reenable interrupts (by setting the IE bit to "1") after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts.
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SBI (System Break Interrupt) Control Register (SBICR)
b0
0
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
5.2.3 SBI (System Break Interrupt) Control Register

1
0
2
0
3
0
4
0
5
0
6
0
b7
SBIREQ 0
b 0-6 7 Bit Name No function assigned. Fix to "0" SBIREQ SBI request bit Note 1: This bit can only be cleared (see below) Function 0: SBI not requested 1: SBI requested R W
0 0 R(Note 1)
The System Break Interrupt (SBI) is an interrupt request generated by a falling edge on the SBI# signal input pin. When a falling edge on the SBI# signal input pin is detected and this bit is set to "1", a system break interrupt (SBI) request is generated to the CPU. This bit cannot be set to "1" in software, it can only be cleared. To clear this bit to "0", follow the procedure described below. 1. Write "1" to the SBI request bit. 2. Write "0" to the SBI request bit. Note: * Unless this bit is set to "1", do not perform the above clearing operation.
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5.2.4 Interrupt Control Registers
TIN30-33 Input Interrupt Control Register (ITIN3033CR) TID2 Output Interrupt Control Register (ITID2CR) A-D1 Conversion Interrupt Control Register (IAD1CCR) SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR) TOU1,2 Output Interrupt Control Register (ITOU12CR) TID1 Output Interrupt Control Register (ITID1CR) RTD Interrupt Control Register (IRTDCR) SIO2,3 Transmit/Receive Interrupt Control Register (ISIO23CR) DMA5-9 Interrupt Control Register (IDMA59CR) TOU0 Output Interrupt Control Register (ITOU0CR) TID0 Output Interrupt Control Register (ITID0CR) A-D0 Conversion Interrupt Control Register (IAD0CCR) SIO0 Transmit Interrupt Control Register (ISIO0TXCR) SIO0 Receive Interrupt Control Register (ISIO0RXCR) SIO1 Transmit Interrupt Control Register (ISIO1TXCR) SIO1 Receive Interrupt Control Register (ISIO1RXCR) DMA0-4 Interrupt Control Register (IDMA04CR) TIO0-3 Output Interrupt Control Register (ITIO03CR) TOP6,7 Output Interrupt Control Register (ITOP67CR) TOP0-5 Output Interrupt Control Register (ITOP05CR) TIO8,9 Output Interrupt Control Register (ITIO89CR) TIO4-7 Output Interrupt Control Register (ITIO47CR) TOP10 Output Interrupt Control Register (ITOP10CR) TOP8,9 Output Interrupt Control Register (ITOP89CR) TMS0,1 Output Interrupt Control Register (ITMS01CR) TIN7-11 Input Interrupt Control Register (ITIN711CR) TIN0-2 Input Interrupt Control Register (ITIN02CR) TIN12-19 Input Interrupt Control Register (ITIN1219CR) TIN20-29 Input Interrupt Control Register (ITIN2029CR)
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR)
0065> 0066> 0067>
0075> 0076> 0077>

TIN3-6 Input Interrupt Control Register (ITIN36CR) CAN1 Transmit/Receive & Error Interrupt Control Register (ICAN1CR)
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b0 (b8
0
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
1 9
0
2 10
0
3 11
IREQ 0
4 12
0
5 13
1
6 14
ILEVEL 1
b7 b15)
1
b 0-2 (8-10) 3 (11) IREQ Interrupt request bit At read 0: Interrupt not requested 1: Interrupt requested At write 0: Clear interrupt request 1: Generate interrupt request At read 0: Interrupt not requested 1: Interrupt requested 4 (12) 5-7 (13-15) ILEVEL Interrupt priority level bits 000: Interrupt priority level 0 001: Interrupt priority level 1 010: Interrupt priority level 2 011: Interrupt priority level 3 100: Interrupt priority level 4 101: Interrupt priority level 5 110: Interrupt priority level 6 111: Interrupt priority level 7 (interrupt disabled) R W No function assigned. Fix to "0" 0 0 R 0 R W Bit Name No function assigned. Fix to "0" Function R 0 W 0
(1) IREQ (Interrupt Request) bit (Bit 3 or 11) When an interrupt request from some internal peripheral I/O occurs, the corresponding IREQ (Interrupt Request) bit is set to "1". This bit can be set and cleared in software for only edge-recognized interrupt request sources (and not for level-recognized interrupt request sources). Also, when this bit is set by an edge-recognized interrupt request generated, it is automatically cleared to "0" by reading the Interrupt Vector Register (IVECT) (not cleared in the case of level-recognized interrupt request). If the IREQ bit is cleared in software at the same time it is set by an interrupt request generated, clearing in software has priority. Also, if the IREQ bit is cleared by reading the Interrupt Vector Register (IVECT) at the same time it is set by an interrupt request generated, clearing by a read of the IVECT register has priority. Note: * External Interrupt (EI) to the CPU core is not deasserted by clearing the IREQ bit. External Interrupt (EI) to the CPU core can only be deasserted by the following operation: (1) Reset (2) IVECT register read (3) Write to the IMASK register
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Interrupt request from each internal peripheral I/O
Bit 3 or 11
INTERRUPT CONTROLLER (ICU)
5.2 ICU Related Registers
IREQ Set
Set/clear
Data bus
F/F
Interrupt enabled
Reset IVECT read IMASK write
Clear
Bits 5-7 or bits 13-15
3
ILEVEL (levels 0-7)
Interrupt priority resolving circuit
Set
F/F
EI
To the CPU core
Figure 5.2.1 Configuration of the Interrupt Control Register (Edge-recognized Type)
Interrupt request from each group internal peripheral I/O
Group interrupt
Read Data bus
b3, b11
Read-only circuit
IREQ
Reset IVECT read IMASK write
Interrupt enabled
Clear
b5-b7, b13-b15 3
ILEVEL (levels 0-7)
Interrupt priority resolving circuit
Set
F/F
EI
To the CPU core
Figure 5.2.2 Configuration of the Interrupt Control Register (Level-recognized Type) (2) ILEVEL (Interrupt Priority Level) (Bits 5-7 or bits 13-15) These bits set the priority levels of interrupt requests from each internal peripheral I/O. Set these bits to `111' to disable or any value `000' through `110' to enable the interrupt from some internal peripheral I/O. When an interrupt occurs, the Interrupt Controller resolves priority between this interrupt and other interrupt sources based on ILEVEL settings and finally compares priority with the IMASK value to determine whether to forward an EI request to the CPU or keep the interrupt request pending. The table below shows the relationship between ILEVEL settings and the IMASK values at which interrupts are accepted. Table 5.2.1 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set 0 (ILEVEL = "000") 1 (ILEVEL = "001") 2 (ILEVEL = "010") 3 (ILEVEL = "011") 4 (ILEVEL = "100") 5 (ILEVEL = "101") 6 (ILEVEL = "110") 7 (ILEVEL = "111") IMASK values at which interrupts are accepted Accepted when IMASK is 1-7 Accepted when IMASK is 2-7 Accepted when IMASK is 3-7 Accepted when IMASK is 4-7 Accepted when IMASK is 5-7 Accepted when IMASK is 6-7 Accepted when IMASK is 7 Not accepted (interrupts disabled)
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INTERRUPT CONTROLLER (ICU)
5.3 Interrupt Request Sources in Internal Peripheral I/O
5.3 Interrupt Request Sources in Internal Peripheral I/O
The Interrupt Controller receives as inputs the interrupt requests from MJT (multijunction timer), DMAC, serial I/O, A-D converter, RTD and CAN. For details about these interrupts, see each section in which the relevant internal peripheral I/O is described. Table 5.3.1 Interrupt Request Sources in Internal Peripheral I/O
Interrupt Request Sources TIN3-6 input interrupt request TIN20-29 input interrupt request TIN12-19 input interrupt request TIN0-2 input interrupt request TIN7-11 input interrupt request TMS0,1 output interrupt request TOP8,9 output interrupt request TOP10 output interrupt request TIO4-7 output interrupt request TIO8,9 output interrupt request TOP0-5 output interrupt request TOP6,7 output interrupt request TIO0-3 output interrupt request DMA0-4 interrupt request SIO1 receive interrupt request SIO1 transmit interrupt request SIO0 receive interrupt request SIO0 transmit interrupt request A-D0 conversion interrupt request TID0 output interrupt request Contents TIN3-TIN6 inputs TIN20-TIN29 inputs TIN12-TIN19 inputs TIN0-TIN2 inputs TIN7-TIN11 inputs TMS0, TMS1 output TOP8, TOP9 output TOP10 output TIO4-TIO7 outputs TIO8, TIO9 outputs TOP0-TOP5 outputs TOP6-TOP7 outputs TIO0-TIO3 outputs DMA0-4 transfer completed SIO1 reception-completed or receive error interrupt SIO1 transmission-completed or transmit buffer empty interrupt SIO0 reception-completed or receive error interrupt SIO0 transmission-completed or transmit buffer empty interrupt A-D0 converter's scan mode one-shot operation, single mode or comparate mode completed TID0 output Number of Input Sources 4 10 8 3 5 2 2 1 4 2 6 2 4 5 1 1 1 1 1 1 8 5 4 1 1 16 4 1 1 4 35 35 ICU Type of Input Source ( Note 1) Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized
TOU0 output interrupt request TOU0_0-TOU0_7 outputs DMA5-9 interrupt request DMA5-9 transfer completed SIO2,3 transmit/receive interrupt SIO2,3 reception-completed or receive error interrupt, request RTD interrupt request TID1 output interrupt request TOU1,2 output interrupt request SIO4,5 transmit/receive interrupt request A-D1 conversion interrupt request transmission-completed or transmit buffer empty interrupt RTD interrupt generation command TID1 output TOU1_0-TOU1_7 outputs, TOU2_0-TOU2_7 outputs SIO4,5 reception-completed or receive error interrupt, transmission-completed or transmit buffer empty interrupt A-D1 converter's scan mode one-shot operation,
single mode or comparate mode completed TID2 output interrupt request TID2 output TIN30-33 input interrupt request TIN30-TIN33 inputs CAN0 transmit/receive & error interrupt request CAN1 transmit/receive & error interrupt request CAN0 transmission or reception completed, CAN0 error passive, CAN0 error bus-off, CAN0 bus error, single shot CAN1 transmission or reception completed, CAN1 error passive, CAN1 error bus-off, CAN1 bus error, single shot
Note 1: ICU type of input source * Edge-recognized: Interrupt requests are generated on a falling edge of the interrupt signal supplied to the ICU. * Level-recognized: Interrupt requests are generated when the interrupt signal supplied to the ICU is held low. For this type of interrupt, the ICU's Interrupt Control Register IRQ bit cannot be set or cleared in software.
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5.4 ICU Vector Table
INTERRUPT CONTROLLER (ICU)
5.4 ICU Vector Table
The ICU vector table is used to set the start addresses of interrupt handlers for each internal peripheral I/O. The 32-source interrupt requests are assigned the following vector table addresses. Table 5.4.1 ICU Vector Table Addresses
Interrupt Request Source TIN3-6 input interrupt request TIN20-29 input interrupt request TIN12-19 input interrupt request TIN0-2 input interrupt request TIN7-11 input interrupt request TMS0,1 output interrupt request TOP8,9 output interrupt request TOP10 output interrupt request TIO4-7 output interrupt request TIO8,9 output interrupt request TOP0-5 output interrupt request TOP6,7 output interrupt request TIO0-3 output interrupt request DMA0-4 interrupt request SIO1 receive interrupt request SIO1 transmit interrupt request SIO0 receive interrupt request SIO0 transmit interrupt request A-D0 conversion interrupt request TID0 output interrupt request TOU0 output interrupt request DMA5-9 interrupt request SIO2,3 transmit/receive interrupt request RTD interrupt request TID1 output interrupt request TOU1,2 output interrupt request SIO4,5 transmit/receive interrupt request A-D1 conversion interrupt request TID2 output interrupt request TIN30-33 input interrupt request CAN0 transmit/receive & error interrupt request CAN1 transmit/receive & error interrupt request ICU Vector Table Addresses H'0000 0094 H'0000 0098 H'0000 009C H'0000 00A0 H'0000 00A4 H'0000 00A8 H'0000 00AC H'0000 00B0 H'0000 00B4 H'0000 00B8 H'0000 00BC H'0000 00C0 H'0000 00C4 H'0000 00C8 H'0000 00CC H'0000 00D0 H'0000 00D4 H'0000 00D8 H'0000 00DC H'0000 00E0 H'0000 00E4 H'0000 00E8 H'0000 00EC H'0000 00F0 H'0000 00F4 H'0000 00F8 H'0000 00FC H'0000 0100 H'0000 0104 H'0000 0108 H'0000 010C H'0000 0110 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H'0000 0097 H'0000 009B H'0000 009F H'0000 00A3 H'0000 00A7 H'0000 00AB H'0000 00AF H'0000 00B3 H'0000 00B7 H'0000 00BB H'0000 00BF H'0000 00C3 H'0000 00C7 H'0000 00CB H'0000 00CF H'0000 00D3 H'0000 00D7 H'0000 00DB H'0000 00DF H'0000 00E3 H'0000 00E7 H'0000 00EB H'0000 00EF H'0000 00F3 H'0000 00F7 H'0000 00FB H'0000 00FF H'0000 0103 H'0000 0107 H'0000 010B H'0000 010F H'0000 0113
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5.5 Description of Interrupt Operation
INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
5.5.1 Acceptance of Internal Peripheral I/O Interrupts
An interrupt request from any internal peripheral I/O is checked to see whether or not to accept by comparing its ILEVEL value set in the Interrupt Control Register and the IMASK value of the Interrupt Request Mask Register. If its priority is higher than the IMASK value, the interrupt request is accepted. However, if two or more interrupt requests occur simultaneously, the Interrupt Controller resolves priority between these interrupt requests following the procedure described below. 1) The ILEVEL values set in the Interrupt Control Registers for the respective internal peripheral I/Os are compared with each other. 2) If the ILEVEL values are the same, priorities are resolved according to the predetermined hardware priority. 3) The ILEVEL and IMASK values are compared. If two or more interrupt requests occur simultaneously, the Interrupt Controller first compares their priority levels set in each Interrupt Control Register's ILEVEL bit to select an interrupt request that has the highest priority. If the interrupt requests have the same ILEVEL value, their priorities are resolved according to the hardware fixed priority. The interrupt request thus selected has its ILEVEL value compared with the IMASK value and if its priority is higher than the IMASK value, the Interrupt Controller sends an EI request to the CPU. Interrupt requests may be masked by setting the Interrupt Request Mask Register and the Interrupt Control Register's ILEVEL bit (disabled at level 7) provided for each internal peripheral I/O and the PSW register IE bit.
1) Interrupt requested or not Resolve priority according to Interrupt Priority Level (ILEVEL)
2) Resolve priority according to hardware priority
3) Compare with IMASK value Accept interrupt if PSW register IE bit = 1
(ILEVEL settings) TIN3-6 input interrupt request TIO4-7 output interrupt request TOP8,9 output interrupt request SIO0 transmit interrupt request DMA0-4 interrupt request A-D0 conversion interrupt request Level 3 Level 4 Level 5 Level 3 Level 1 Level 3 Requested Requested Requested Requested Not requested Requested Level 3 Level 3 Hardware fixed priority Level 3
Can be accepted when IMASK = 4-7
Figure 5.5.1 Example of Priority Resolution when Accepting Interrupt Requests
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Table 5.5.1 Hardware Fixed Priority Levels
Priority High Interrupt Request Source TIN3-6 input interrupt request TIN20-29 input interrupt request TIN12-19 input interrupt request TIN0-2 input interrupt request TIN7-11 input interrupt request TMS0,1 output interrupt request TOP8,9 output interrupt request TOP10 output interrupt request TIO4-7 output interrupt request TIO8,9 output interrupt request TOP0-5 output interrupt request TOP6,7 output interrupt request TIO0-3 output interrupt request DMA0-4 interrupt request SIO1 receive interrupt request SIO1 transmit interrupt request SIO0 receive interrupt request SIO0 transmit interrupt request A-D0 conversion interrupt request TID0 output interrupt request TOU0 output interrupt request DMA5-9 interrupt request RTD interrupt request TID1 output interrupt request TOU1,2 output interrupt request A-D1 conversion interrupt request TID2 output interrupt request TIN30-33 input interrupt request CAN0 transmit/receive & error interrupt request CAN1 transmit/receive & error interrupt Low request H'0000 0110 H'0000 0094 H'0000 0098 H'0000 009C H'0000 00A0 H'0000 00A4 H'0000 00A8 H'0000 00AC H'0000 00B0 H'0000 00B4 H'0000 00B8 H'0000 00BC H'0000 00C0 H'0000 00C4 H'0000 00C8 H'0000 00CC H'0000 00D0 H'0000 00D4 H'0000 00D8 H'0000 00DC H'0000 00E0 H'0000 00E4 H'0000 00E8 H'0000 00F0 H'0000 00F4 H'0000 00F8 H'0000 0100 H'0000 0104 H'0000 0108 H'0000 010C
INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
ICU Vector Table Address - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H'0000 0097 H'0000 009B H'0000 009F H'0000 00A3 H'0000 00A7 H'0000 00AB H'0000 00AF H'0000 00B3 H'0000 00B7 H'0000 00BB H'0000 00BF H'0000 00C3 H'0000 00C7 H'0000 00CB H'0000 00CF H'0000 00D3 H'0000 00D7 H'0000 00D8 H'0000 00DF H'0000 00E3 H'0000 00E7 H'0000 00EB H'0000 00EF H'0000 00F3 H'0000 00F7 H'0000 00FB H'0000 00FF H'0000 0103 H'0000 0107 H'0000 010B H'0000 010F H'0000 0113
ICU Type of Input Source Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Edge-recognized Edge-recognized Level-recognized Level-recognized Level-recognized
SIO2,3 transmit/receive interrupt request H'0000 00EC
SIO4,5 transmit/receive interrupt request H'0000 00FC
Table 5.5.2 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set 0 (ILEVEL = "000") 1 (ILEVEL = "001") 2 (ILEVEL = "010") 3 (ILEVEL = "011") 4 (ILEVEL = "100") 5 (ILEVEL = "101") 6 (ILEVEL = "110") 7 (ILEVEL = "111") IMASK values at which interrupts are accepted Accepted when IMASK is 1-7 Accepted when IMASK is 2-7 Accepted when IMASK is 3-7 Accepted when IMASK is 4-7 Accepted when IMASK is 5-7 Accepted when IMASK is 6-7 Accepted when IMASK is 7 Not accepted (interrupts disabled)
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(1) Branching to the interrupt handler
INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
5.5.2 Processing by Internal Peripheral I/O Interrupt Handlers
Upon accepting an interrupt request, the CPU branches to the EIT vector entry after performing the hardware preprocessing as described in Section 4.3, "EIT Processing Procedure." The EIT vector entry for External Interrupt (EI) is located at the address H'0000 0080. This address is where the instruction (not the jump address itself) for branching to the beginning of the interrupt handler routine for external interrupt requests is written. (2) Processing in the External Interrupt (EI) handler A typical operation of the External Interrupt (EI) handler (for interrupts from internal peripheral I/O) is shown in Figure 5.5.2. [1] Saving each register to the stack Save the BPC, PSW and general-purpose registers to the stack. Also, save the accumulator and FPSR register to the stack as necessary. [2] Reading the Interrupt Request Mask Register (IMASK) and saving to the stack Read the Interrupt Request Mask Register and save its content to the stack. [3] Reading the Interrupt Vector Register (IVECT) Read the Interrupt Vector Register. This register holds the 16 low-order address bits of the ICU vector table for the accepted interrupt request source that was stored in it when accepting an interrupt request. When the Interrupt Vector Register is read, the following processing is automatically performed in hardware: * The interrupt priority level of the accepted interrupt request (ILEVEL) is set in the IMASK register as a new IMASK value. (Interrupts with lower priority levels than that of the accepted interrupt request source are masked.) * The accepted interrupt request source is cleared (not cleared for level-recognized interrupt request sources). * The interrupt request (EI) to the CPU core is dropped. * The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). [4] Reading and overwriting the Interrupt Request Mask Register (IMASK) Read the Interrupt Request Mask Register and overwrite it with the read value. This write to the IMASK register causes the following processing to be automatically performed in hardware: * The interrupt request (EI) to the CPU core is dropped. * The ICU's internal sequencer is activated to start internal processing (interrupt priority resolution). Note: * Processing in [4] here is unnecessary when multiple interrupts are to be enabled in [6] below. [5] Reading the ICU vector table Read the ICU vector table for the accepted interrupt request source. The relevant ICU vector table address can be obtained by zero-extending the content of the Interrupt Vector Register that was read in [3] (i.e., the 16 low-order address bits of the ICU vector table for the accepted interrupt request source). The ICU vector table must have set in it the start address of the interrupt handler for the interrupt request source concerned.) [6] Enabling multiple interrupts To enable another higher priority interrupt while processing the accepted interrupt (i.e., enabling multiple interrupts), set the PSW register IE bit to "1". [7] Branching to the internal peripheral I/O interrupt handler Branch to the start address of the interrupt handler that was read out in [5]. [8] Processing in the internal peripheral I/O interrupt handler [9] Disabling interrupts Clear the PSW register IE bit to "0" to disable interrupts.
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INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
[10] Restoring the Interrupt Request Mask Register (IMASK) Restore the Interrupt Request Mask Register that was saved to the stack in [2]. [11] Restoring registers from the stack Restore the registers that were saved to the stack in [1]. [12] Completion of external interrupt processing Execute the RTE instruction to complete the external interrupt processing. The program returns to the state in which it was before the currently processed interrupt request was accepted. (3) Identifying the source of the interrupt request generated If any internal peripheral I/O has two or more interrupt request sources, check the Interrupt Request Status Register provided for each internal peripheral I/O to identify the source of the interrupt request generated. (4) Enabling multiple interrupts To enable multiple interrupts in the interrupt handler, set the PSW register IE (Interrupt Enable) bit to enable interrupt requests to be accepted. However, before writing "1" to the IE bit, be sure to save each register (BPC, PSW, general-purpose registers and IMASK) to the stack. Note: * Before enabling multiple interrupts, read the Interrupt Vector Register (IVECT) and then the ICU vector table, as shown in Figure 5.5.2, "Typical Handler Operation for Interrupts from Internal Peripheral I/O."
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EI (External Interrupt) vector entry
INTERRUPT CONTROLLER (ICU)
5.5 Description of Interrupt Operation
H'0000 0080
BRA instruction EI (External Interrupt) handler
Hardware preprocessing when EIT is accepted
(Note 1)
Save BPC to the stack Save PSW to the stack Save general-purpose registers to the stack
[1]
Program being executed
[2]
Interrupt generated
Read and save Interrupt Request Mask Register (IMASK) to the stack Read Interrupt Vector Register (IVECT) Read and overwrite Interrupt Request Mask Register (IMASK)
H'0080 0004
IMASK
[3]
H'0080 0000
(Note 2)
IVECT
[4]
(Note 2) (Note 3)
[5] [6] [7]
Hardware postprocessing when RTE instruction is executed
(Note 1)
ICU vector table Read ICU vector table
H'0000 0094
Set PSW register IE bit to 1 (Note 4)
(Note 5)
Interrupt handler start address
H'0000 0113
Branch to the interrupt handler for each internal peripheral I/O
Interrupt handler
Interrupt handler
[8]
[9]
[10]
Clear PSW register IE bit to 0 Restore Interrupt Request Mask Register (IMASK) from the stack Restore general-purpose registers from the stack
(Note 4)
(Note 2)
[11]
Restore PSW from the stack
[1] to [12]: Processing of EI by interrupt handler
Restore BPC from the stack
[12]
RTE
Note 1: For operations at EIT acceptance and return from EIT, also see Section 4.3, "EIT Processing Procedure." Note 2: Do not read the Interrupt Vector Register (IVECT) or write to the Interrupt Request Mask Register (IMASK) in the EIT handler unless interrupts are disabled (PSW register IE bit = 0). Note 3: When multiple interrupts are disabled, execute processing in [4]. Processing in [4] is unnecessary if multiple interrupts are enabled by executing processing in [6] and [9]. Note 4: To enable multiple interrupts, execute processing in [6] and [9]. Note 5: To reenable interrupts (by setting the IE bit to 1) after reading the Interrupt Vector Register (IVECT), perform a dummy access to the internal memory, etc. before reenabling interrupts. In the example here, there is no need to add a dummy access because the ICU vector table is read after reading the IVECT register. Similarly, to reenable interrupts (by setting the IE bit to 1) after writing to the Interrupt Request Mask Register (IMASK), perform a dummy access to the internal memory, etc. before reenabling interrupts.
Figure 5.5.2 Typical Handler Operation for Interrupts from Internal Peripheral I/O
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5.6.1 Acceptance of SBI
INTERRUPT CONTROLLER (ICU)
5.6 Description of System Break Interrupt (SBI) Operation
5.6 Description of System Break Interrupt (SBI) Operation
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is detected or a fault condition is notified by an external watchdog timer. The system break interrupt is accepted anytime upon detection of a falling edge on the SBI# signal input pin no matter how the PSW register IE bit is set, and cannot be masked.
5.6.2 SBI Processing by Handler
When the system break interrupt generated has been serviced, shut down or reset the system without returning to the program that was being executed when the interrupt occurred.
SBI (System Break Interrupt) vector entry
H'0000 0010
BRA instruction
SBI (System Break Interrupt) handler
Program being executed
Processing to shut down the system (Note 1)
SBI generated
Shut down or reset the system
Note 1: Do not return to the program that was being executed when the interrupt occurred.
Figure 5.6.1 Typical SBI Operation
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CHAPTER 6 INTERNAL MEMORY
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Outline of the Internal Memory Internal RAM Internal Flash Memory Registers Associated with the Internal Flash Memory Programming the Internal Flash Memory Virtual Flash Emulation Function Connecting to A Serial Programmer Internal Flash Memory Protect Function Precautions To Be Taken when Rewriting the Internal Flash Memory
6
6.1 Outline of the Internal Memory
The 32180 internally contains the following types of memory: * 48-Kbyte RAM * 1-Mbyte (1,024-Kbyte) flash memory
INTERNAL MEMORY
6.1 Outline of the Internal Memory
6.2 Internal RAM
Specifications of the internal RAM are shown below. Table 6.2.1 Specifications of the Internal RAM
Item Size Location address Wait insertion Internal bus connection Dual port Specification 48 Kbytes H'0080 4000 to H'0080 FFFF Operates with zero wait states Connected by 32-bit bus By using the Real-Time Debugger (RTD), data can be read (monitored) or written to any area of the internal RAM via serial communication from external devices independently of the CPU. (See Chapter 14, "Real-Time Debugger.") Notes: * Immediately after power-on reset (for the power-on case in which VDDE also goes up from GND), the value of the RAM is undefined. * If the RAM is reset during RAM backup (power for only VDDE is on), the RAM retains the value it had immediately before being reset.
6.3 Internal Flash Memory
Specifications of the internal flash memory are shown below. Table 6.3.1 Specifications of the Internal Flash Memory
Item Size Location address Wait insertion Durability Internal bus connection Specification 1 Mbytes (1,024 Kbytes) H'0000 0000 to H'000F FFFF Operates with one wait state Can be rewritten 100 times Instruction access: Connected by 64-bit bus (Transfer rates equivalent to zero wait states on 32-bit bus are possible.) Data access: Connected by 32-bit bus Other Virtual flash emulation function is incorporated. (See Section 6.6, "Virtual Flash Emulation Function.")
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H'0000 0000 H'0000 4000 H'0000 6000 H'0000 8000 H'0001 0000
INTERNAL MEMORY
6.3 Internal Flash Memory
Internal flash memory area of the M32180F8 (1,024 Kbytes)
16KB 8KB 8KB 32KB 64KB
Block 0 Block 1 Block 2 Block 3 Unequal blocks
Block 4
H'0002 0000
64KB
H'0003 0000
Block 5
64KB
H'0004 0000
Block 6
64KB
H'0005 0000
Block 7
64KB
H'0006 0000
Block 8
64KB
H'0007 0000
Block 9
64KB
H'0008 0000
Block 10
64KB
H'0009 0000
Block 11 Equal blocks
64KB
H'000A 0000
Block 12
64KB
H'000B 0000
Block 13
64KB
H'000C 0000
Block 14
64KB
H'000D 0000
Block 15
64KB
H'000E 0000
Block 16
64KB
H'000F 0000
Block 17
64KB
H'000F FFFF
Block 18
Figure 6.3.1 Block Configuration of the M32180F8's Internal Flash Memory
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INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory
6.4 Registers Associated with the Internal Flash Memory
A register map associated with the internal flash memory is shown below. Internal Flash Memory Related Register Map
Address b0 H'0080 01E0 H'0080 01E2 H'0080 01E4 H'0080 01E6 H'0080 01E8 H'0080 01EA H'0080 01EC H'0080 01EE H'0080 01F0 H'0080 01F2 H'0080 01F4 H'0080 01F6 Flash Mode Register (FMOD) Flash Control Register 1 (FCNT1) Flash Control Register 3 (FCNT3) (Use inhibited area) Virtual Flash S Bank Register (FESBANK0) Virtual Flash S Bank Register (FESBANK1) Virtual Flash S Bank Register (FESBANK2) Virtual Flash S Bank Register (FESBANK3) Virtual Flash S Bank Register (FESBANK4) Virtual Flash S Bank Register (FESBANK5) Virtual Flash S Bank Register (FESBANK6) Virtual Flash S Bank Register (FESBANK7) 0 1 2 3 4 5 6 7 6-11 6-11 6-11 6-11 6-11 6-11 6-11 6-11 +0 address b7 b8 Flash Status Register 1 (FSTAT1) Flash Control Register 2 (FCNT2) Flash Control Register 4 (FCNT4) +1 address b15 6-4 6-5 6-7 6-8 6-9 See pages
6.4.1 Flash Mode Register
Flash Mode Register (FMOD)
b0
0

4
0
1
0
2
0
3
0
5
0
6
0
b7
FPMOD
?
b 0-6 7 Bit Name No function assigned. Fix to "0" FPMOD External FP pin status bit 0: FP pin = "low" 1: FP pin = "high" Function R 0 R W 0 -
The Flash Mode Register (FMOD) is a read-only status register, with its FPMOD bit indicating the FP (Flash Protect) pin status. The internal flash memory is enabled for programming or erase operation only when FPMOD = "1", and is protected against programming or erase operation when FPMOD = "0".
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6.4.2 Flash Status Registers
INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory
There are two registers to indicate the status of the internal flash memory: Flash Status Register 1 (FSTAT1) located in the SFR area (H'0080 01E1) and Flash Status Register 2 (FSTAT2) included in the internal flash memory. Use these two status registers (FSTAT1 and FSTAT2) to control the programming or erase operation performed on the internal flash memory.
Flash Status Register 1 (FSTAT1)
b8
0

13
0
9
0
10
0
11
0
12
0
14
0
b15
FSTAT
1
b 8-14 15 Bit Name No function assigned. Fix to "0". FSTAT Ready/busy status bit 0: Busy 1: Ready Function R 0 R W 0 -
Flash Status Register 1 (FSTAT1) is a read-only status register used to know the status of the programming or erase operation performed on the internal flash memory. When FSTAT = "0" (busy), the internal flash memory is being programmed or erased, during which time do not start a new programming or erase operation on it. When FSTAT = "1" (ready), a new programming or erase operation can be started on it. Furthermore, while FSTAT = "0" (busy), do not operate on the FCNT4 register FRESET bit described later.
6.4.3 Flash Status Register 2 (FSTAT2)
Flash Status Register 2 (FSTAT2)
b8
FBUSY 1 0
9
10
0
11
0
12
0
13
0
14
0
b15
0
ERASE WRERR1 WRERR2
b 8 9 10 11 12 13-15 Bit Name FBUSY Flash busy bit No function assigned. Fix to "0". ERASE Erase status confirmation bit WRERR1 Write status confirmation bit 1 WRERR2 Write status confirmation bit 2 No function assigned. Fix to "0". 0: Erase normally operating or terminated 1: Erase error occurred 0: Programming normally operating or terminated 1: Programming error occurred 0: Programming normally operating or terminated 1: Over-programming occurred R 0 - 0 Function 0: Being programmed or erased 1: Ready state 0 R R 0 - - R R W -
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INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory
This status register is included in the internal flash memory, and can be enabled for read by writing the Read Status command (H'7070) to any address of the internal flash memory. For details, see Section 6.5, "Programming the Internal Flash Memory." Flash Status Register 2 (FSTAT2) consists of the following four read-only status bits that indicate the operation condition of the internal flash memory. (1) FBUSY (Flash Busy) bit (Bit 8) The FBUSY bit is used to determine whether the operation on the internal flash memory is finished when it is being programmed or erased. When FBUSY = "0", it means that the programming or erase operation is being executed; when FBUSY = "1", the operation is finished. (2) ERASE (Erase status) bit (Bit 10) The ERASE bit is used to determine after execution of processing whether the erase operation performed on the internal flash memory resulted in an error. When ERASE = "0", it means that the erase operation terminated normally; when ERASE = "1", the erase operation terminated in an error. (3) WRERR1 (Write status 1) bit (Bit 11) The WRERR1 bit is used to determine after completion of processing whether the programming operation performed on the internal flash memory resulted in an error. When WRERR1 = "0", it means that the programming operation terminated normally; when WRERR1 = "1", the programming operation terminated in an error. The condition under which WRERR1 is set to "1" is when any bit other than those that must be "0" is found to be "0" by comparison between the write data and the data in the internal flash memory. (4) WRERR2 (Write status 2) bit (Bit 12) The WRERR2 bit is used to determine after execution of processing whether the programming operation performed on the internal flash memory resulted in an error. When WRERR2 = "0", it means that the programming operation terminated normally; when WRERR2 = "1", the programming operation terminated in an error. The condition under which WRERR2 is set to "1" is when the internal flash memory cannot be written to even by repeating the programming operation a specified number of times.
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6.4.4 Flash Control Registers
Flash Control Register 1 (FCNT1)
b0
0
INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory

5
0
1
0
2
0
3
FENTRY 0
4
0
6
0
b7
FEMMOD 0
b 0-2 3 4-6 7 Bit Name No function assigned. Fix to "0". FENTRY Flash E/W enable mode entry bit No function assigned. Fix to "0". FEMMOD Virtual flash emulation mode bit 0: Normal mode 1: Virtual flash emulation mode 0: Normal read 1: Program/erase enable Function R 0 R 0 R W 0 W 0 W
Flash Control Register 1 (FCNT1) consists of the following two bits to control the internal flash memory. (1) FENTRY (Flash Mode Entry) bit (Bit 3) The FENTRY bit controls entry to flash E/W enable mode. Flash E/W enable mode can only be entered when FENTRY = "1". To set the FENTRY bit to "1", write "0" and then "1" to the FENTRY bit in succession while the FP pin = "high". To clear the FENTRY bit, check to see that the FSTAT1 register FSTAT bit = "1" (ready) and then write "0" to the FENTRY bit. Note that the following operations cannot be performed while programming or erasing the internal flash memory (FSTAT1 register FSTAT bit = "0" (busy)). If one of these operations is attempted, the FENTRY bit is cleared to "0" in hardware. 1) Writing "0" to the FENTRY bit 2) Entering a low-level signal to the FP pin 3) Entering a low-level signal to the RESET# pin When running a program resident in the internal flash memory while the FENTRY bit = "0", the EI vector entry is located at the address H'0000 0080 of the internal flash memory. When running the flash write/erase program in the RAM while the FENTRY bit = "1", the EI vector entry is located at the address H'0080 4000 of the RAM, allowing the flash programming/erase operation to be controlled using interrupts. Table 6.4.1 Changes of the EI Vector Entry by FENTRY
FENTRY 0 1 EI Vector Entry Internal flash memory area Internal RAM area Address H'0000 0080 H'0080 4000
(2) FEMMOD (Virtual Flash Emulation Mode) bit (Bit 7) The FEMMOD bit controls entry to virtual flash emulation mode. Virtual flash emulation mode is entered by setting the FEMMOD bit to "1" while the FENTRY bit = "0". (For details, see Section 6.6, "Virtual Flash Emulation Function.")
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Flash Control Register 2 (FCNT2)
b8
0
INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory

13
0
9
0
10
0
11
0
12
0
14
0
b15
FPROT 0
b 8-14 15 Bit Name No function assigned. Fix to "0". FPROT Unlock bit 0: Protection by lock bit effective 1: Protection by lock bit invalidated Function R 0 R W 0 W
Flash Control Register 2 (FCNT2) controls invalidation of the internal flash memory protection by a lock bit (protection against programming/erase operation). Protection of the internal flash memory is invalidated by setting the FPROT bit to "1", so that any blocks protected by a lock bit can now be programmed or erased. To set the FPROT bit to "1", write "0" and then "1" to the FPROT bit in succession while the FENTRY bit = "1". To clear the FPROT bit to "0", write "0" to the FPROT bit. If one of the following operations is attempted, the FPROT bit is cleared to "0". 1) Writing "0" to the FPROT bit 2) Entering a low-level signal to the FP pin 3) Clearing the FENTRY bit to "0" 4) Entering a low-level signal to the RESET# pin
FENTRY = 1 YES
NO
FENTRY = 1
FPROT = 0
FPROT = 0 FPROT is not set to 1 if a write cycle to any other area occurs during this time. FPROT = 1
Figure 6.4.1 Protection Unlocking Flow
FPROT = 1
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Flash Control Register 3 (FCNT3)
b0
0
INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory

5
0
1
0
2
0
3
0
4
0
6
0
b7
FELEVEL 0

b 0-6 7 Bit Name No function assigned. Fix to "0". FELEVEL Erase margin-up bit 0: Normal level 1: Raise erase margin up Function R 0 R W 0 W
Flash Control Register 3 (FCNT3) controls the depth of erase levels when erasing the internal flash memory with one of erase commands. The internal flash memory erase level can be deepened by setting the FELEVEL bit to "1".
Flash Control Register 4 (FCNT4)
b8
0

13
0
9
0
10
0
11
0
12
0
14
0
b15
FRESET 0
b 8-14 15 Bit Name No function assigned. Fix to "0". FRESET Flash reset bit 0: No operation 1: Reset Function R 0 R W 0 W
Flash Control Register 4 (FCNT4) controls initializing each status bit of Flash Status Register 2 (FSTAT2) or canceling a programming/erase operation. Setting the FRESET bit to "1" initializes each status bit of the FSTAT2 register or cancels a programming/erase operation. The FRESET bit is effective only when the FENTRY bit = "1". If the FENTRY bit = "0", the FRESET bit information is ignored. When programming or easing the internal flash memory, make sure the FRESET bit remains "0". An example for clearing each status of FSTAT2 during a programming/erase operation, and an example for forcibly terminating (canceling) a programming/erase operation due to time-out are shown below.
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FENTRY = 0
INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory
FENTRY = 1
Program/erase the flash memory * At this point in time, the FSTAT1 register FSTAT bit = 1 (ready). Error found YES FRESET = 1
Programming/erase operation terminated normally
NO
FRESET = 0
Program/erase the flash memory
Figure 6.4.2 Example of FCNT4 Register Operation 1 (Clearing each status of the FSTAT2 register)
Flash programming/erase operation has timed out Forcibly terminate
FRESET = 1
FRESET = 0
Figure 6.4.3 Example of FCNT4 Register Operation 2 (Forcibly terminating operation when programming/ erasing the internal flash memory)
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INTERNAL MEMORY
6.4 Registers Associated with the Internal Flash Memory
6.4.5 Virtual Flash S Bank Registers
Virtual Flash S Bank Register 0 (FESBANK0) Virtual Flash S Bank Register 1 (FESBANK1) Virtual Flash S Bank Register 2 (FESBANK2) Virtual Flash S Bank Register 3 (FESBANK3) Virtual Flash S Bank Register 4 (FESBANK4) Virtual Flash S Bank Register 5 (FESBANK5) Virtual Flash S Bank Register 6 (FESBANK6) Virtual Flash S Bank Register 7 (FESBANK7)
b0
MODENS

7
0
1
0
2
0
3
0
4
0
5
0
6
0
8
0
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
SBANKAD
0
b 0 1-7 8 Bit Name MODENS Virtual flash emulation enable bit No function assigned. Fix to "0". SBANKAD S bank address Note: * These registers must always be accessed in halfwords. Start address A12-A19 of the relevant S bank Function 0: Disable virtual flash emulation function 1: Enable virtual flash emulation function R R 0 R W W 0 W
(1) MODENS (Virtual Flash Emulation Enable) bit (Bit 0) The MODENS bit can be set to "1" after entering virtual flash emulation mode (by setting the FEMMOD bit to "1" while the FENTRY bit = "0"). This causes the virtual flash emulation function to be enabled for the S bank area selected by the SBANKAD bits. (2) SBANKAD (S Bank Address) bits (Bits 8-15) The SBANKAD bits are provided for selecting one of the S banks that are separated every 4 KB. Use these SBANKAD bits to set the eight bits A12-A19 of the 32-bit start address of the desired S bank. Note: * For details, see Section 6.6, "Virtual Flash Emulation Function."
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
6.5 Programming the Internal Flash Memory
6.5.1 Outline of Internal Flash Memory Programming
To program or erase the internal flash memory, there are following two methods to choose depending on the situation: (1) When the flash write/erase program does not exist in the internal flash memory (2) When the flash write/erase program already exists in the internal flash memory For (1), set the FP pin = "high", MOD0 = "high" and MOD1 = "low" to enter boot mode. In this case, the CPU starts running the boot program immediately after reset. The boot program transfers the flash write/erase program into the internal RAM. After the transfer, jump to a location in the RAM and use the RAM-resident program to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in boot mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. For (2), set the FP pin = "high", MOD0 = "low" and MOD1 = "low" to enter single-chip mode. Transfer the flash write/erase program from the internal flash memory in which it has been prepared into the internal RAM. After the transfer, jump to the RAM and use the program transferred into the RAM to set the Flash Control Register 1 (FCNT1) FENTRY bit to "1" to make the internal flash memory ready for programming/erase operation (i.e., placed in single-chip mode + flash E/W enable mode). When the above is done, use the flash write/erase program that has been transferred into the internal RAM to program or erase the internal flash memory. Or flash E/W enable mode can be entered from external extension mode by setting the FP pin = "high", MOD0 = "low" and MOD1 = "high". During flash E/W enable mode (FP pin = 1, FENTRY = 1), the EIT vector entry for External Interrupt (EI) is relocated to the start address (H'0080 4000) of the internal RAM. During normal mode, it is located in the flash area (H'0000 0080).
Flash E/W enable mode (FENTRY = 1)
Normal mode (FENTRY = 0)
H'0000 0000
Internal ROM area
H'0000 0000
Internal ROM area
EI vector entry
(H'0000 0080)
H'0080 3FFF H'0080 4000
Internal RAM
EI vector entry
(H'0080 4000)
H'0080 3FFF H'0080 4000
Internal RAM
H'00FF FFFF
H'00FF FFFF
Figure 6.5.1 EI Vector Entry during Flash E/W Enable Mode
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
(1) When the flash write/erase program does not exist in the internal flash memory In this case, the boot program is used to program or erase the internal flash memory. To transfer the write data, use serial I/O1 in clock-synchronized serial mode. To program or erase the internal flash memory using a flash programmer, follow the procedure described below.
FP = L or H MOD1 = L
MOD0 = L RESET = L
* Initial state (Flash write/erase program nonexistent in the internal flash memory)
RAM
CPU
Flash memory
Boot program Write data SIO1 External device (e.g., flash programmer) M32R/ECU
FP = H
MOD1 = L
MOD0 = H RESET = H
* Set the FP pin high, MOD0 pin high and MOD1 pin low to place the flash memory in boot mode + flash E/W enable mode. * Dessert reset signal and start up with the boot program. * Transfer the flash write/erase program into the RAM. * Jump to the flash write/erase program in the RAM.
RAM
Flash write/ erase program
CPU
Flash memory
Boot program Write data SIO1 External device (e.g., flash programmer) M32R/ECU
FP = H
MOD1 = L
MOD0 = H RESET = H
RAM
Flash write/ erase program
CPU
* Using the flash write/erase program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. * Program or erase the internal flash memory using the flash write/erase program. * When finished, reset MOD0 low and jump to the internal flash memory or apply a reset to enter normal mode.
Flash memory
Flash write data
Boot program
SIO1 M32R/ECU
Write data External device (e.g., flash programmer)
Figure 6.5.2 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program does not exist in it)
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POWER ON
Mode selected
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
Reset signal deasserted (Boot program starts)
Reset signal deasserted
Mode selected
RESET# pin
MOD0 pin MOD1 pin FP pin Settings by the boot program FENTRY bit
Flash programming/erasing by the boot program
Figure 6.5.3 Internal Flash Memory Write/Erase Timing (when the flash write/erase program does not exist in it)
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
(2) When the flash write/erase program already exists in the internal flash memory In this case, the flash write/erase program prepared in the internal flash memory is used to program or erase the internal flash memory. For programming/erase operation here, use the internal peripheral circuits in the manner suitable for the programming system. (All resources of the internal peripheral circuits such as the data bus, serial I/O and ports can be used.) The following shows an example for programming or erasing the internal flash memory by using serial I/O0 in single-chip mode.
FP = L or H
MOD1 = L
MOD0 = L
* Initial state (Flash write/erase program existing in the internal flash memory) * An ordinary program in the internal flash memory is being executed.
RAM
CPU
Flash write/ erase program
SIO0
Write data External device
M32R/ECU
FP = H
MOD1 = L
MOD0 = L
* Set the FP pin high, MOD1 pin low and MOD0 pin low to place the flash memory in single-chip + flash E/W enable mode. * After determining the FP pin and MOD1 pin levels, transfer the flash write/erase program from the internal flash memory area into the RAM. * Jump to the flash write/erase program in the RAM.
RAM
Flash write/ erase program
CPU
Flash memory
SIO0
Write data External device
M32R/ECU
FP = H
MOD1 = L
MOD0 = L
RAM
Flash write/ erase program
* Using the flash write/erase program in the RAM, set the Flash Control Register 1 (FCNT1) FENTRY bit to 1. * Program or erase the internal flash memory using the flash write/erase program in the RAM. * When finished, jump to the program in the flash memory or apply a reset to enter normal mode.
CPU
Flash memory
Flash write data
SIO0
Write data External device
M32R/ECU
Figure 6.5.4 Procedure for Programming/Erasing the Internal Flash Memory (when the flash write/erase program already exists in it)
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
Flash rewrite Flash mode turned on starts
Flash mode turned off
RESET# pin High or low
MOD0 pin Low MOD1 pin High or low (single-chip or external extension) FP pin High or low FENTRY bit
Flash programming/erasing by the flash write/erase program Flash write/erase program transferred into the RAM
Figure 6 .5.5 Internal Flash Memory Write/Erase Timing (when the flash write/erase program already exists in it)
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
6.5.2 Controlling Operation Modes during Flash Programming
The microcomputer's operation mode is set by MOD0, MOD1 and Flash Control Register 1 (FCNT1) FENTRY bit. The table below lists operation modes that may be used when programming or erasing the internal flash memory. Table 6.5.1 Operation Modes Set during Flash Programming/Erase
FP 0 1 0 MOD0 MOD1 FENTRY (Note 1) Operation Mode 0 0 1 0 0 0 0 0 0 Processor mode Single-chip mode Reset Vector Entry Start address of internal flash memory (H'0000 0000) Start address of external area (H'0000 0000) 0 1 1 0 0 0 1 1 0 0 0 1 External extension mode Single-chip mode + flash E/W enable 1 1 1 1 1 0 0 0 1 0 1 1 Boot mode Boot mode + flash E/W enable External extension mode + flash E/W enable - 1 1 - Use inhibited Start address of internal flash memory (H'0000 0000) Start address of internal flash memory (H'0000 0000) Boot program starts running Boot program starts running Start address of internal flash memory (H'0000 0000) - - Flash area (H'0000 0080) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) Beginning of internal RAM (H'0080 4000) (H'0000 0080) Flash area (H'0000 0080) External area EI Vector Entry Flash area (H'0000 0080)
Note 1: Indicates the Flash Control Register 1 (FCNT1) FENTRY bit status (- denotes "Don't care"). However, if FP = "0", writing "1" to FENTRY only results in it cleared to "0".
(1) Flash E/W enable mode Flash E/W enable mode is a mode in which the internal flash memory can be programmed or erased. In flash E/W enable mode, no programs can be executed in the internal flash memory. Therefore, the necessary program must be transferred into the internal RAM before entering flash E/W enable mode, so that it can be executed in the RAM. (2) Entering flash E/W enable mode Flash E/W enable mode can only be entered when operating in single-chip, external extension or boot mode. Furthermore, it is only when the FP pin = "high" and the Flash Control Register 1 (FCNT1) FENTRY bit = "1" that flash E/W enable mode can be entered. Flash E/W enable mode cannot be entered when operating in processor mode or the FP pin = "low". (3) Detecting the MOD0 and MOD1 pin levels The MOD0 and MOD1 pin levels ("high" or "low") can be known by checking the P8 Data Register (Port Data Register, H'0080 0708) MOD0DT and MOD1DT bits.
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6.5.3 P8 Data Register
P8 Data Register (P8DATA)
b0
?
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory

4
P84DT ?
1
?
2
?
3
P83DT ?
5
P85DT ?
6
P86DT ?
b7
P87DT ?
MOD0DT MOD1DT P82DT
b 0 1 2 3 4 5 6 7 Bit Name MOD0DT MOD0 data bit MOD1DT MOD1 data bit P82DT Port P82 data bit P83DT Port P83 data bit P84DT Port P84 data bit P85DT Port P85 data bit P86DT Port P86 data bit P87DT Port P87 data bit Note 1: To select the port data to read, use the Port Input Special Function Control Register's port input data select bit (PISEL). Function 0: MOD0 pin = "low" 1: MOD0 pin = "high" 0: MOD1 pin = "low" 1: MOD1 pin = "high" At read Depends on how the Port Direction Register is set * If direction bit = "0" (input mode) 0: Port input pin = "low" 1: Port input pin = "high" * If direction bit = "1" (output mode) (Note 1) 0: Port output latch = "0" / Port pin level = "low" 1: Port output latch = "1" / Port pin level = "high" At write Write to the port output latch R W R R R W - -
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START
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
Enter one of the following modes: * Single-chip mode * Boot mode * External extension mode
FMOD(H'0080 01E0) FPMOD P8DATA(H'0080 0708) D0 = MOD0DT D1 = MOD1DT
Check MOD0/1 and FP pin levels OK
NO
END Transfer the flash write/erase program into the internal RAM
Set the Flash Control Register in SFR area (FCNT1, H'0080 01E2) FENTRY bit to 0
Switched to the flash write/erase program
Set the Flash Control Register in SFR area (FCNT1, H'0080 01E2) FENTRY bit to 1
Go to flash E/W enable mode
Wait for 1 s (using a hardware or software timer)
Execute flash write/erase command and various read commands (Note 1)
Jump to the flash memory or apply reset
Switched to normal mode
END
Note 1: For details about each command, see Section 6.5.4, "Procedure for Programming/Erasing the Internal Flash Memory."
Figure 6.5.6 Procedure for Entering Flash E/W Enable Mode
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
6.5.4 Procedure for Programming/Erasing the Internal Flash Memory
To program or erase the internal flash memory, set up chip mode to enter flash E/W enable mode and execute the flash write/erase program in the internal RAM into which it has been transferred from the internal flash memory. In flash E/W enable mode, because the internal flash memory cannot be accessed for read as in normal mode, no programs present in it can be executed. Therefore, the flash write/erase program must be made available in the internal RAM before entering flash E/W enable mode. (Once flash E/W enable mode is entered into, only flash commands and no other commands can be used to access the internal flash memory.) To access the internal flash memory in flash E/W enable mode, issue commands for the internal flash memory address to be operated on. The table below lists the commands that can be issued in flash E/W enable mode. Note: * During flash E/W enable mode, the internal flash memory cannot be accessed for read or write wordwise. Table 6.5.2 Commands in Flash E/W Enable Mode
Command Name
Read Array command Page Program command Lock Bit Program command Block Erase command Erase All Unlocked Blocks command Read Status Register command Clear Status Register command Read Lock Bit Status command Verify command (Note 1)
Issued Command Data
H'FFFF H'4141 H'7777 H'2020 H'A7A7 H'7070 H'5050 H'7171 H'D0D0
Note 1: * This command is used in conjunction with Lock Bit Program, Block Erase and Erase All Unlocked Blocks operations. * This command must be issued immediately after the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command. * If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by the Read Array command (H'FFFF), the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is canceled. * If the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is followed by other than the Verify (H'D0D0) or Read Array (H'FFFF) command, the Lock Bit Program, Block Erase or Erase All Unlocked Blocks command is not executed normally and terminated in error.
(1) Read Array command Writing the command (H'FFFF) to any address of the internal flash memory places it in read mode. Then read the desired flash memory address, and the content of that address will be read out. Before exiting flash E/W enable mode, always be sure to execute the Read Array command.
START
Write the Read Array command (H'FFFF) to any address of the internal flash memory
Read the desired flash memory address
END
Figure 6.5.7 Read Array Command
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(2) Page Program command
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
The internal flash memory is programmed one page at a time, each page consisting of 256 bytes (lower addresses H'00 to H'FF). To program the flash memory, write the Page Program command (H'4141) to any address of the internal flash memory and then the program data to the address to be programmed. The protected flash memory blocks cannot be accessed for write by the Page Program command. Page programming is automatically performed by the internal control circuit, and whether the Page Program command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = "0" (busy), the next programming (by the Page Program command) cannot be performed.
START
Write the Page Program command (H'4141) to any address of the internal flash memory
Write the program data to the internal flash memory address to be programmed (Note 1)
Write the next program data to the previously programmed address + 2
NO
Finished programming one page?
YES Internal flash memory is programmed by Page Program (Note 2)
Wait for 1 s (using a hardware or software timer)
NO FSTAT bit = 1 YES
Read any address of the internal flash memory (Note 3) to check for programming error (see Figure 6.4.2)
TIME OUT? 0.5s YES
NO
To next page
NO
Forcibly terminated (see Figure 6.4.3.) Last address?
YES
END
Note 1: Start programming from the beginning of a 256-byte boundary (lower address H'00). Note 2: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 3: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error.
Figure 6.5.8 Page Program Command
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(3) Lock Bit Program command
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
The internal flash memory can be protected against programming/erase operation one block at a time. The Lock Bit Program command is provided for protecting the flash memory blocks. Write the Lock Bit Program command (H'7777) to any address of the internal flash memory. Next, write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected, and this memory block is thereby protected against programming/erase operation. To remove protection, use the Flash Control Register 2 (FCNT2) FPROT bit to invalidate protection by a block bit (see Section 6.4.3, "Flash Control Registers") and erase the flash memory block whose protection is to be removed. (The content of that memory block is also erased.) Executing a programming/erase operation on flash memory blocks protected by a lock bit results in an error. If erased, the FSTAT2 register ERASE bit is set to "1" (erase error occurred); if programmed, the FSTAT2 register WRERR1 bit is set to "1" (programming error occurred). The table below lists the target flash memory blocks and their addresses to be specified when writing the Verify command. Table 6.5.3 M32180F8 Target Blocks and Specified Addresses
Target Block 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Specified Address H'0000 3FFE H'0000 5FFE H'0000 7FFE H'0000 FFFE H'0001 FFFE H'0002 FFFE H'0003 FFFE H'0004 FFFE H'0005 FFFE H'0006 FFFE H'0007 FFFE H'0008 FFFE H'0009 FFFE H'000A FFFE H'000B FFFE H'000C FFFE H'000D FFFE H'000E FFFE H'000F FFFE
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START
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
Write the Lock Bit Program command (H'7777) to any address of the internal flash memory
Write the Verify command (H'D0D0) to the last even address of the flash memory block to be protected
Lock bit is programmed by Lock Bit Program (Note 1)
Wait for 1 s (using a hardware or software timer)
NO FSTAT bit = 1 YES TIME OUT? 0.5s Read any address of the internal flash memory (Note 2) to check for programming error (see Figure 6.4.2) YES Forcibly terminated (see Figure 6.4.3.) NO
END
Note 1: When a programming operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error.
Figure 6.5.9 Lock Bit Program Command
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(4) Block Erase command
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
The Block Erase command erases the content of the internal flash memory one block at a time. To perform this operation, write the Block Erase command (H'2020) to any address of the internal flash memory. Next, write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased (see Table 6.5.3, "M32180F8 Target Blocks and Specified Addresses"). The protected flash memory blocks cannot be erased by the Block Erase command. Block erase operation is automatically performed by the internal control circuit, and whether the Block Erase command has finished can be known by checking the Flash Status Register 1 (FSTAT1) FSTAT bit. (See Section 6.4.2, "Flash Status Registers.") While the FSTAT bit = "0" (busy), the next block erase operation (by the Block Erase command) cannot be performed.
START
Write the Block Erase command (H'2020) to any address of the internal flash memory
Write the Verify command (H'D0D0) to the last even address of the flash memory block to be erased
Internal flash memory contents are erased by the Block Erase command (Note 1)
Wait for 1 s (using a hardware or software timer)
NO FSTAT bit = 1 YES TIME OUT? 1s Read any address of the internal flash memory (Note 2) to check for programming error (see Figure 6.4.2) YES Forcibly terminated (see Figure 6.4.3.) NO
END
Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error.
Figure 6.5.10 Block Erase Command
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(5) Erase All Unlocked Blocks command
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
The Erase All Unlocked Blocks command erases all flash memory blocks that are not protected. To erase all unlocked blocks, write the command (H'A7A7) to any address of the internal flash memory. Next, write the Verify command (H'D0D0) to any address of the internal flash memory, and all unlocked memory blocks are thereby erased.
START
Write the Erase All Unlocked Blocks command (H'A7A7) to any address of the internal flash memory
Write the Verify command (H'D0D0) to any address of the internal flash memory
Flash memory contents are erased by Erase All Unlocked Blocks (Note 1)
Wait for 1 s (using a hardware or software timer)
NO FSTAT bit = 1 YES TIME OUT? 10s Read any address of the internal flash memory Note 2 to check for erase error (see Figure 6.4.2) YES Forcibly terminated (see Figure 6.4.3.) NO
END
Note 1: When an erase operation started, the internal flash memory is automatically readied to run the Read Status command, so that there is no need to enter the Read Status command until another command is entered. Note 2: Inspect the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to check for programming error.
Figure 6.5.11 Erase All Unlocked Blocks Command
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(6) Read Status command
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
The Read Status command reads the content of Flash Status Register 2 (FSTAT2) that indicates whether flash memory programming or erase operation has terminated normally. To read Flash Status Register 2, write the Read Status command (H'7070) to any address of the internal flash memory. Next, read any address of the internal flash memory, and Flash Status Register 2 (FSTAT2) will be read out.
START
Write the Read Status command (H'7070) to any address of the internal flash memory
Read any address of the internal flash memory
END
Figure 6.5.12 Read Status Command (7) Clear Status Register command The Clear Status Register command clears the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) and WRERR2 (write status 2) bits to "0". Write the Clear Status Register command (H'5050) to any address of the internal flash memory, and Flash Status Register 2 is thereby initialized. If an error occurs when programming or erasing the internal flash memory and the Flash Status Register 2 ERASE (erase status), WRERR1 (write status 1) or WRERR2 (write status 2) bit is set to "1", the next programming or erase operation cannot be executed unless each status bit is cleared to "0".
START
Write the Clear Status Register command (H'5050) to any address of the internal flash memory
END
Figure 6.5.13 Clear Status Register Command
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(8) Read Lock Bit Status command
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
The Read Lock Bit Status command is provided for checking whether a flash memory block is protected against programming/erase operation. Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory. Next, read the last even address of the flash memory block to be checked (see Table 6.5.3, "M32180F8 Target Blocks and Specified Addresses"), and the read data shows whether the target block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) in the read data both are "0", it means that the target memory block is protected. If the FLBST0 (lock bit 0) and FLBST1 (lock bit 1) both are "1", it means that the target memory block is not protected.
START
Write the Read Lock Bit Status command (H'7171) to any address of the internal flash memory
Read the last even address of the flash memory block to be checked
END
Figure 6.5.14 Read Lock Bit Status Command
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Lock Bit Status Register (FLBST)
b0
?
INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
1
FLBST0
2
?
3
?
4
?
5
?
6
?
7
?
8
?
9
FLBST1
10
?
11
?
12
?
13
?
14
?
b15
?
?
?
b 0 1 2-8 9 Bit Name No function assigned. FLBST0 Lock bit 0 No function assigned. FLBST1 Lock bit 1 No function assigned. 0: Protected 1: Not protected (Same content as FLBST0 is output) 10-15 ? - 0: Protected 1: Not protected ? R - - Function R ? R W - -
The Lock Bit Status Register is a read-only register, which is included for each memory block independently of one another. The following shows how the lock bits in this register are set. a) Setting the lock bit to "0" (protected) Issue the Lock Bit Program command (H'7777) to the memory block to be protected. b) Setting the lock bit to "1" (not protected) Set the Flash Control Register 2 FPROT bit to invalidate protection by a block bit, then issue the Block Erase command (H'2020) or Erase All Unlocked Blocks command (H'A7A7) to erase the memory block which is to be unprotected. This is the only way to set the lock bit to "1". In no way can the lock bit alone be set to "1". c) Lock bit status after reset Because the lock bits are nonvolatile, they are unaffected by a reset and power-off.
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INTERNAL MEMORY
6.5 Programming the Internal Flash Memory
6.5.5 Flash Programming Time (Reference)
The following shows the time needed to program internal flash memory for reference. (1) Time required for transfer by SIO (for a transfer data size of 1,024 KB) 1/57,600 bps x 1 (frame) x 11 (number of bits transferred) x 1,024 KB = approx. 200.2 [s] (2) Time required for programming the flash memory 1,024 KB / 256-byte block x 8 ms = approx. 32.8 [s] (3) Time required for erasing the entire area 50 ms x 19 (blocks) = approx. 950 [ms] (4) Total flash programming time (entire 1,024 KB area) When communicating at 57,600 bps via UART, the flash programming time can be ignored because it is very short compared to the serial communication time. Therefore, the total flash programming time can be calculated using the equation below. (1) + (3) = approx. 201 [s] If the transfer time can be ignored by speeding up the serial communication or by other means, the fastest programming time possible can be calculated using the equation below. (2) + (3) = approx. 34 [s]
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6.6 Virtual Flash Emulation Function
INTERNAL MEMORY
6.6 Virtual Flash Emulation Function
The microcomputer has the function to map 4-Kbyte memory blocks beginning with the address H'0080 8000 into areas (S banks) of the internal flash memory that are divided in 4-Kbyte units. This functions is referred to as the Virtual Flash Emulation Function. This function allows the data located in 4-Kbyte blocks of the internal RAM to be changed with the contents of internal flash memory at the addresses specified by the Virtual Flash Bank Register. That way, the relevant RAM data can read out by reading the content of internal flash memory. For applications that require modifying the contents of internal flash memory (e.g., data table) during operation, this function enables dynamic data modification without the need to modify the relevant RAM data. The RAM blocks allocated for virtual flash emulation can be accessed for read and write the same way as in usual RAM. This function, when used in combination with the microcomputer's internal Real-Time Debugger (RTD), allows the data table, etc. created in the internal flash memory to be referenced or rewritten from the outside, thereby facilitating data table tuning from an external device. Note: * Before programming/erasing the internal flash memory, always be sure to exit this virtual flash emulation mode.
H'0080 4000
(Cannot be used for virtual flash emulation)
H'0080 8000 H'0080 9000 H'0080 A000
RAM bank block 0 (FESBANK0) 4 Kbytes RAM bank block 1 (FESBANK1) 4 Kbytes RAM bank block 2 (FESBANK2) 4 Kbytes RAM bank block 3 (FESBANK3) 4 Kbytes RAM bank block 4 (FESBANK4) 4 Kbytes RAM bank block 5 (FESBANK5) 4 Kbytes RAM bank block 6 (FESBANK6) 4 Kbytes RAM bank block 7 (FESBANK7) 4 Kbytes
Internal RAM area
H'0080 B000
H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000
Figure 6.6.1 Internal RAM Bank Configuration of the M32180F8
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6.6.1 Virtual Flash Emulation Area
INTERNAL MEMORY
6.6 Virtual Flash Emulation Function
The following shows the internal flash memory areas in which the Virtual Flash Emulation Function is useful. Using the Virtual Flash S Bank Register (FESBANK0-FESBANK7), select one among all S banks of internal flash memory that are divided in 4-Kbyte units (by setting the eight start address bits A12-A19 of the desired S bank in the Virtual Flash S Bank Register SBANKAD bits). Then set the Virtual Flash S Bank Register's flash emulation enable bit (MODENS) to "1", and the selected S bank area will be replaced with 4-Kbyte blocks of the internal RAM beginning with the address H'0080 8000, up to eight such blocks in all. Notes: * If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0- FESBANK7) and each register's flash emulation enable bit (MODENS) is set to "1" (enabled), the bank is assigned the corresponding internal RAM area (4-Kbyte) according to the priority of Virtual Flash S Bank Registers given below. FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7 * During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory. * Before reading any flash emulation area after setting the Flash Control Register 1 (FCNT1) flash emulation mode bit (FEMMOD) to "1", be sure to check that the flash emulation mode bit (FEMMOD) has been set to "1" by reading it once. * Before reading any flash emulation area after setting the Virtual Flash S Bank Register (FESBANK0-FESBANK7) flash emulation enable bit (MODENS) and bank address bits (SBANKAD), be sure to check that those MODENS and SBANKAD bits have been set to the intended values by reading them once.
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H'0000 0000
INTERNAL MEMORY
6.6 Virtual Flash Emulation Function
S bank 0 (4 Kbytes) S bank 1 (4 Kbytes) S bank 2 (4 Kbytes)

H'0080 4000
H'0000 1000
H'0000 2000
H'000F D000
S bank 253 (4 Kbytes) S bank 254 (4 Kbytes) S bank 255 (4 Kbytes)
H'000F E000
4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes
H'0080 8000 H'0080 9000 H'0080 A000 H'0080 B000 H'0080 C000 H'0080 D000 H'0080 E000 H'0080 F000
H'000F F000
Notes: * If the same bank area is set in two or more Virtual Flash S Bank Registers (FESBANK0-FESBANK7) and each register's flash emulation enable bit (MODENS) is set to 1, the bank is assigned the corresponding internal RAM area in order of priority: FESBANK0 > FESBANK1 > FESBANK2 > FESBANK3 > FESBANK4 > FESBANK5 > FESBANK6 > FESBANK7. * If any 4-Kbyte area (S bank) specified by the Virtual Flash S Bank Register is accessed, its corresponding internal RAM area is accessed. During virtual flash emulation mode, RAM can be accessed for read and write from both the internal RAM area and the flash emulation areas set in the internal flash memory.
Figure 6.6.2 Virtual Flash Emulation Area of the M32180F8
S bank S bank 0 S bank 1 S bank 2
Start address of S bank in flash memory H'0000 0000 (Note 1) H'0000 1000 (Note 1) H'0000 2000 (Note 1)
Values set in S bank address (SBANKAD) bits H'00 H'01 H'02
S bank 254 S bank 255
H'000F E000 (Note 1) H'000F F000 (Note 1)
H'FE H'FF
Note 1: Set the eight start address bits A12-A19 of each S bank of internal flash memory that is divided in 4-Kbyte units in the Virtual Flash S Bank Register's S bank address (SBANKAD) bits.
Figure 6.6.3 Values Set in the M32180F8's Virtual Flash S Bank Register
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6.6.2 Entering Virtual Flash Emulation Mode
INTERNAL MEMORY
6.6 Virtual Flash Emulation Function
To enter virtual flash emulation mode, set the Flash Control Register 1 (FCNT1) FEMMOD bit by writing "1". After entering virtual flash emulation mode, set the Virtual Flash S Bank Register MODENS bit to "1" to enable the Virtual Flash Emulation Function. Even during virtual flash emulation mode, the internal RAM area (H'0080 8000 through H'0080 FFFF) can be accessed the same way as in usual internal RAM.
Settings start
Write flash data to RAM
Enter virtual flash emulation mode FEMMOD 1
Set RAM location address in Virtual Flash S Bank Register SBANKADn Address A12-A19
Enable virtual flash emulation MODENS 1
Settings completed
Figure 6.6.4 Virtual Flash Emulation Mode Sequence
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INTERNAL MEMORY
6.6 Virtual Flash Emulation Function
6.6.3 Application Example of Virtual Flash Emulation Mode
By using two RAM areas that have been set in the same flash area by the Virtual Flash Emulation Function, the data in the flash memory can be replaced successively.
(1) Operation when reset Flash memory
Bank xx
Initial value
Replace area
RAM block 0 RAM block 1
Data write to RAM0
(2) Programming operation using RAM block 0 Flash memory Replaced Bank xx Initial value RAM block 0
Bank xx specified RAM block 0 RAM block 1 Data write to RAM1
(3) Programming operation switched from RAM block 0 to RAM block 1 Flash memory Replaced Bank xx Initial value RAM block 0 RAM block 1
Bank xx specified RAM block 0 RAM block 1
Bank xx specified (settings invalid)
Figure 6.6.5 Application Example of Virtual Flash Emulation Mode (1/2)
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(4) Programming operation using RAM block 1 Flash memory
INTERNAL MEMORY
6.6 Virtual Flash Emulation Function
Replaced Bank xx Initial value RAM block 1
RAM block 0 RAM block 1
(Bank specification cleared) Data write to RAM0
Bank xx specified
(5) Programming operation switched from RAM block 1 to RAM block 0 Flash memory Replaced Bank xx Initial value RAM block 0 RAM block 1
Bank xx specified RAM block 0 RAM block 1
Bank xx specified (settings invalid)
(6) Go to (2) Note: Enclosed in are the valid area.
Figure 6.6.6 Application Example of Virtual Flash Emulation Mode (2/2)
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6.7 Connecting to A Serial Programmer
INTERNAL MEMORY
6.7 Connecting to A Serial Programmer
For the internal flash memory to be rewritten in boot mode + flash E/W enable mode by using a general-purpose serial programmer, several pins on the microcomputer must be processed to make them suitable for the serial programmer, as shown below. Table 6.7.1 Processing Microcomputer Pins before Using a Serial Programmer
Pin Name SCLKI1 RXD1 TXD1 P84 FP MOD0 MOD1 RESET# JTRST XIN XOUT VCNT OSC-VCC OSC-VSS VREF0 VREF1 AVCC0 AVCC1 AVSS0 AVSS1 VDDE VCCE VCC-BUS EXCVCC EXCVDD VSS 175 176 177 178 187 188 189 35 50 32 34 30 31 29, 33 64 240 63 1 73 Analog ground 231 193 RAM backup power supply Connect to the main power supply 5 V +- 10% or 3.3 V +- 10% Depends on the target system Need to be grounded to earth via bypass capacitor 0V Connect to ground Analog power supply Connect to the main power supply Pin No. Function Transfer clock input Serial data input (received data) Serial data output (transmit data) Transmit/receive enable output Flash memory protect Operation mode 0 Operation mode 1 Reset JTAG reset Clock input Clock output Control input for PLL circuit PLL circuit power supply PLL circuit ground Reference voltage input for A-D converter Connect to the main power supply Connect to ground Connect to the main power supply Need to be pulled high Connect to the main power supply Connect to the main power supply Connect to ground After setting MOD0/MOD1, ground and back to main power supply Pull low via resistor Remark Need to be pulled high Need to be pulled high
3, 28, 61, 89, 125, 154, 193 Main power supply 127, 153, 196, 221 91, 192 190 2, 62, 86, 87, 88, 90, 126, 155, 191, 194, 213, 222 Bus power supply Internal power supply Ground
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INTERNAL MEMORY
6.7 Connecting to A Serial Programmer
The diagram below shows an example of a user system configuration which has had a serial programmer connected. After the user system is powered on, the serial programmer writes to the internal flash memory in clocksynchronized serial mode. No communication problems associated with the oscillator frequency may occur. If the system uses any pins that are to be connected to a serial programmer, care must be taken to prevent adverse effects on the system when a serial programmer is connected. Note that the serial programmer uses the addresses H'0000 0084 through H'0000 008F as an area in which to check the ID for flash memory protection. If the internal flash memory needs to be protected, set any ID in this area.
User system board
Connect to the VCCE (5 or 3.3 V) power supply rail
VCCE VDDE OSC-VCC AVCC0, AVCC1 VREF0, VREF1
Connect to Main power supply the user Connect to the system power VCCE (5 or 3.3V) supply rail power supply rail
EXCVCC EXCVDD Flash programmer signals
Main power supply (for reference)
Connector VCC-BUS P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P84/SCLKI0/SCLKO0 MOD0 FP RESET# VSS AVSS0, AVSS1 OSC-VSS
RxD (input) TxD (output) SCLK0 (output) BUSY (input) MOD0 (output) FP (output) RESET (output) GND (common)
To system circuit Set microcomputer operating conditions
2k
MOD1 JTRST
XIN XOUT VCNT
32180
Notes: * Turn on the power for the user system before writing to the internal flash memory. * If P84-P87 are used in the system circuit, connection to a serial programmer must be taken into consideration. * SBI# must be fixed high or low to ensure that no interrupts will be generated. * The pullup resistance values of P84, P86 and P87 must be selected to suit the system design condition. * The typical pullup resistance values of P84, P86 and P87 4.7 to 10 K. * The status of any other ports that are not shown here will not affect flash memory programming. * Make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes while rewriting the internal flash memory.
Figure 6.7.1 Pin Connection Diagram
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INTERNAL MEMORY
6.8 Internal Flash Memory Protect Function
6.8 Internal Flash Memory Protect Function
The internal flash memory has the following four types of protect functions to prevent it from being inadvertently rewritten or illegally copied, programmed or erased. (1) Flash memory protect ID When using a tool to program/erase the internal flash memory such as a general-purpose programmer or emulator, the ID entered by a tool and the ID stored in the internal flash memory are collated. Unless the correct ID is entered, no programming/erase operations can be performed. (For some tools, tool execution is enabled after erasing the entire flash memory area, and the internal flash memory becomes accessible for write.) (2) Protection by FP pin The internal flash memory is protected in hardware against programming/erase operation by pulling the FP (Flash Protect) pin low. Furthermore, because the FP pin level can be known by reading the Flash Mode Register (FMOD)'s FPMOD (external FP pin status) bit in the flash write/erase program, the internal flash memory can also be protected in software. For systems that do not require protection by setting external pins, the FP pin may be fixed high to simplify the operation to program/erase the internal flash memory. (3) Protection by FENTRY bit Flash E/W enable mode cannot be entered into unless the Flash Control Register 1 (FCNT1)'s FENTRY (flash mode entry) bit is set to "1". To set the FENTRY bit to "1", write "0" and then "1" in succession while the FP pin is high. (4) Protection by a lock bit Any block of internal flash memory can be protected by setting the lock bit provided for it to "0". That memory block is disabled against programming/erase operation.
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INTERNAL MEMORY
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory
The following describes precautions to be taken when programming/erasing the internal flash memory. * When the internal flash memory is programmed or erased, a high voltage is generated internally. Because mode transitions during programming/erase operation may cause the chip to break down, make sure the mode setting pin/power supply voltages do not fluctuate to prevent unintended changes of modes. * If the system uses any pins that are to be used by a general-purpose programming/erase tool, care must be taken to prevent adverse effects on the system when the tool is connected. * If the internal flash memory needs to be protected while using a general-purpose programming/erase tool, set any ID in the flash memory protect ID verification area (H'0000 0084 to H'0000 008F). * If the internal flash memory does not need to be protected while using a general-purpose programming/erase tool, fill the entire flash memory protect ID verification area (H'0000 0084 to H'0000 008F) with H'FF. * If the Flash Status Register 2 (FSTAT2)'s each error status is to be cleared (initialized to H'80) by resetting the Flash Control Register 4 (FCNT4) FRESET bit, check to see that the Flash Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) before clearing the error status. * Before resetting the Flash Control Register 1 (FCNT1) FENTRY bit from "1" to "0", check to see that the Flash Status Register 1 (FSTAT1) FSTAT bit = "1" (ready) or the Flash Status Register 2 (FSTAT2) FBUSY bit = "1" (ready). * Do not clear the FENTRY bit if the Flash Status Register 1 (FSTAT1) FSTAT bit = "0" (busy) or the Flash Status Register 2 (FSTAT2) FBUSY bit = "0" (being programmed or erased).
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INTERNAL MEMORY
6.9 Precautions To Be Taken when Rewriting the Internal Flash Memory
This page is blank for reasons of layout.
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CHAPTER 7 RESET
7.1 7.2 7.3 7.4 Outline of Reset Reset Operation Internal State Immediately after Reset Things to Be Considered after Reset
7
7.1 Outline of Reset
RESET
7.1 Outline of Reset
The microcomputer is reset by applying a low-level signal to the RESET# input pin. The microcomputer is gotten out of a reset state by releasing the RESET# input back high, upon which the reset vector entry address is set in the Program Counter (PC) and the CPU starts executing from the reset vector entry.
7.2 Reset Operation
When a low-level signal in width of more than 200 ns (a duration needed for noise cancellation) is applied to the RESET# pin, the microcomputer is reset. At this time, pins on the microcomputer are reset (see the Pin State When Reset in Table 1.4.1, "Pin Assignments"), and an internal bus hold request signal is output internally. Furthermore, the internal circuits (including the CPU) are reset 9-10 BCLK periods later. When the RESET# input is returned high, the microcomputer pins get out of a reset state and the internal bus hold request is deasserted 17-18 BCLK periods later. Then the internal circuits get out of a reset state 15 BCLK periods after that.
Flip-flop RESET# Noise Canceller S R
Counter Pin reset signal OVF Internal circuit reset signal
Figure 7.2.1 Reset Circuit
Duration needed for noise cancellation (Note 1) RESET# pin 200ns Reset signal (internal signal) past the noise canceller Pin reset (Note 2) and internal bus hold request (internal signal) Internal circuit reset (internal signal) 9-10BCLK
Extended for a duration during which the RESET# input is held low
17-18BCLK
15BCLK
Note 1: If the low level duration of the reset signal is less than 200 ns, it is cancelled by the noise canceller. Note 2: The port-related registers also are reset.
Figure 7.2.2 Reset Sequence
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7.2.1 Reset at Power-on
RESET
7.2 Reset Operation
When powering on the microcomputer, hold the RESET# signal input pin low until the rated power supply voltage is reached and the microcomputer's internal x8 clock generator becomes oscillating stably.
7.2.2 Reset during Operation
To reset the microcomputer during operation, hold the RESET# signal input pin low for more than 200 ns.
7.2.3 Reset at Entering RAM Backup Mode
To prevent the RAM access by the CPU or DMA from becoming interrupted by a reset, first an internal bus hold request is output internally after accepting the reset input. Then the internal circuits are reset after the internal bus is placed in a hold state. Note: * Reset input at entering RAM backup mode cannot be used in the following cases (because the internal bus hold request may not be accepted and the RAM contents may be corrupted): * When the lock bit = 1 (see Section 2.7, "Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution") * When executing any instruction present in external memory
7.2.4 Reset Vector Relocation during Flash Programming
When the reset signal is deasserted (released back high) after entering boot mode, the CPU starts executing the boot program. For details, see Section 6.5, "Programming the Internal Flash Memory."
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RESET
7.3 Internal State Immediately after Reset
7.3 Internal State Immediately after Reset
The table below lists the internal state of the microcomputer immediately after it has gotten out of a reset state. For details about the initial register state of each internal peripheral I/O, see each section in this manual in which the relevant internal peripheral I/O is described. Table 7.3.1 Internal State Immediately after Reset
Register PSW CBR SPI SPU BPC FPSR PC R0-R15 ACC (accumulator) RAM (CR0) (CR1) (CR2) (CR3) (CR6) (CR7) State after Reset B'0000 0000 0000 0000 ??00 000? 0000 0000 H'0000 0000 (C bits = 0) Undefined Undefined Undefined H'0000 0100 H'0000 0000 Undefined Undefined Undefined when reset at power-on. (However, if the RAM is gotten out of reset after returning from backup mode, it retains the content it had before being reset.) Note 1: When in boot mode, the CPU executes the boot program. (Only DN bit = 1) (Executed beginning with the address H'0000 0000) (Note 1) (BSM, BIE, BC bits = undefined)
7.4 Things to Be Considered after Reset
* Input/output ports After reset, the microcomputer's input/output ports are disabled against input in order to prevent current from flowing through the port. To use any ports in input mode, set the Port Input Special Function Control Register (PICNT) PIEN0 bit to enable them for input. For details, see Section 8.3, "Input/Output Port Related Registers."
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CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.1 8.2 8.3 8.4 8.5 8.6 Outline of Input/Output Ports Selecting Pin Functions Input/Output Port Related Registers Port Input Level Switching Function Port Peripheral Circuits Precautions on Input/Output Ports
8
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.1 Outline of Input/Output Ports
8.1 Outline of Input/Output Ports
The 32810 has a total of 158 input/output ports from P0 to P22 (except P5, which is reserved for future use). These input/output ports can be used as input or output ports by setting the respective direction registers. Each input/output port is a dual-function or triple-function pin, sharing the pin with other internal peripheral I/O or extended external bus signal line. Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. (If any internal peripheral I/O has still another function, it is also necessary to set the register provided for that peripheral I/O.) The microcomputer also has a port input function enable bit that can be used to prevent current from flowing into the input ports. This helps to simplify the software and hardware processing to be performed immediately after reset or during flash programming. Note that before any ports can be used in input mode, this port input function enable bit must be set accordingly. The input/output ports are outlined below. Table 8.1.1 Outline of Input/Output Ports
Item Number of ports Specification Total 158 ports P0 P1 P2 P3 P4 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 Port function Pin function Pin function selection : : : : : : : : : : : : : : : : : : : : : : P00-P07 P10-P17 P20-P27 P30-P37 P41-P47 P70-P77 P82-P87 P93-P97 P100-P107 P110-P117 P124-P127 P130-P137 P140-P147 P150-P157 P160-P167 P172-P177 P180-P187 P190-P197 P200-P203 P210-P217 P220-P227 (8 ports) (8 ports) (8 ports) (8 ports) (7 ports) (8 ports) (6 ports) (5 ports) (8 ports) (8 ports) (4 ports) (8 ports) (8 ports) (8 ports) (8 ports) (6 ports) (8 ports) (8 ports) (4 ports) (8 ports) (8 ports)
P61-P63, P65-P67 (6 ports)
The input/output ports can individually be set for input or output mode using the direction control register provided for each input/output port. (However, P221 and P223 are input-only ports.) Shared with peripheral I/O or extended external signals to serve dual-functions (or shared with two or more peripheral I/O functions to serve triple-functions) P0-P4, P224-P227: Depends on the CPU operation mode (that is set by MOD0 and MOD1 pins). (Note 1) P6-P22: As set by each input/output port's operation mode register. (However, peripheral I/O pin functions are selected by peripheral I/O registers.)
Note 1: If the CPU operation mode is external extension mode, P0-P3, P44-P47 and P224-P227 initially are input/output port pins, and are switched to extended external signal pin functions by setting the respective port operation mode registers. P41-P43, when in external extension mode, serve as dedicated external bus interface signal pins.
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8.2 Selecting Pin Functions
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.2 Selecting Pin Functions
Each input/output port serves dual functions sharing the pin with other internal peripheral I/O or extended external bus signal line (or triple functions sharing the pin with two or more peripheral I/O functions). Pin functions are selected depending on the current operation mode or by setting the input/output port operation mode registers. P0-P4 and P224-P227, when the CPU is set to operate in processor mode, all are switched to serve as signal pins for external access. The CPU operation mode is determined depending on how the MOD0 and MOD1 pins are set (see the table below). Table 8.2.1 CPU Operation Modes and P0-P4 and P224-P227 Pin Functions
MOD0 VSS VSS VCCE VCCE MOD1 VSS VCCE VSS VCCE Operation Mode Single-chip mode External extension mode Processor mode (FP pin = VSS) Reserved (use inhibited) P0-P4 and P224-P227 Pin Function Input/output port pin Input/output port pin or extended external signal pin (Note 1) Extended external signal pin -
Note 1: P41-P43 serve as dedicated external bus interface signal pins. Note: * VCCE and VSS are connected to 5 or 3.3 V and GND, respectively.
Each input/output port has their functions switched between input/output port pins and internal peripheral I/O pins by setting the respective port operation mode registers. If any internal peripheral I/O has two or more pin functions, use the register provided for that peripheral I/O to select the desired pin function. Note that FP and MOD1 pin settings during internal flash memory programming do not affect the pin functions.
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0 P0 P1 CPU operation mode settings P2 (Note 1) P3 P4 (Reserved) P5 P6 P7 P8 P9 P10 P11 P12 P13 Input/output port operation mode setting registers P14 P15 P16 P17 P18 P19 P20 P21 P22 TO29 TIN26 TXD4 TO37 CTX0 TO30 TIN27 RXD4 TO38 CRX0 TIN16/ TIN17/ PWMOFF0 PWMOFF1 TIN8 TIN0 TO21 TIN9 TIN1 TO22 TO8 TO0 BCLK / WR# MOD0
(Note 3)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.2 Selecting Pin Functions
1 DB1 DB9 A24 A16 BLW# / BLE#
2 DB2 DB10 A25 A17 BHW# / BHE#
3 DB3 DB11 A26 A18 RD#
4 DB4 DB12 A27 A19 CS0#
5 DB5 DB13 A28 A20 CS1#
6 DB6 DB14 A29 A21 A13
7 DB7 DB15 A30 A22 A14
DB0 DB8 A23 A15
(P61) WAIT# MOD1
(Note 3)
(P62) HREQ# TXD0
(P63) HACK# RXD0 TO16
SBI#
(Note 3)
SCLKI4 / SCLKI5 / SCLKO4 SCLKO5
(P67)
RTDTXD RTDRXD RTDACK RTDCLK SCLKI0 / SCLKO0 TO17 TO12 TO4 TCLK0 TXD1 TO18 TO13 TO5 TCLK1 TIN21 TIN13 TIN5 TO26 RXD2 TO34 TIN31 RXD1 TO19 TO14 TO6 TCLK2 TIN22 TIN14 TIN6 TO27 TXD3 TO35 TIN32 SCLKI1 / SCLKO1 TO20 TO15 TO7 TCLK3 TIN23 TIN15 TIN7 TO28 RXD3 TO36 TIN33/ PWMOFF2
TO9 / TO10 / TXD3(Note 2) CTX1(Note 2) TO1 TO2
TO11 TO3
TIN18 TIN10 TIN2 TO23 TIN24 TO31 TIN28 TXD5 TO39 CTX1
TIN19 TIN11 TIN3 TO24 TIN25 TO32 TIN29 RXD5 TO40 CRX1
TIN20 TIN12 TIN4 TO25 TXD2 TO33 TIN30
TO41
TO42
TO43 CS2#
TO44 CS3#
A11 / A12 / CS2#(Note 2) CS3#(Note 2)
(Note 1)
Note 1: During processor mode, these ports are switched to function as extended external signal pins. During external extension mode, only P41-P43 are switched to function as external bus interface pins. Other pins become input/output port pins when reset, so that some of these pins, if needed, must be set to function as external bus interface pins. Note 2: These are triple-function pins. Their desired output function must be selected using the peripheral output select register. Note 3: These ports cannot be used for input/output port function. The SBI#, MOD0 and MOD1 pin input levels can be read from these ports.
Figure 8.2.1 Input/Output Ports and Pin Function Assignments
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
8.3 Input/Output Port Related Registers
The input/output port related registers included in the microcomputer consists of the port data register, port direction register and port operation mode register. Note that P5 is reserved for future use. The tables below show an input/output port related register map. Input/Output Port Related Register Map (1/2)
Address b0 H'0080 0700 H'0080 0702 H'0080 0704 H'0080 0706 H'0080 0708 H'0080 070A H'0080 070C H'0080 070E H'0080 0710 H'0080 0712 H'0080 0714 H'0080 0716 P0 Data Register (P0DATA) P2 Data Register (P2DATA) P4 Data Register (P4DATA) P6 Data Register (P6DATA) P8 Data Register (P8DATA) P10 Data Register (P10DATA) P12 Data Register (P12DATA) P14 Data Register (P14DATA) P16 Data Register (P16DATA) P18 Data Register (P18DATA) P20 Data Register (P20DATA) P22 Data Register (P22DATA) (Use inhibited area) P0 Direction Register (P0DIR) P2 Direction Register (P2DIR) P4 Direction Register (P4DIR) P6 Direction Register (P6DIR) P8 Direction Register (P8DIR) P10 Direction Register (P10DIR) P12 Direction Register (P12DIR) P14 Direction Register (P14DIR) P16 Direction Register (P16DIR) P18 Direction Register (P18DIR) P20 Direction Register (P20DIR) P22 Direction Register (P22DIR) P1 Direction Register (P1DIR) P3 Direction Register (P3DIR) (Use inhibited area) P7 Direction Register (P7DIR) P9 Direction Register (P9DIR) P11 Direction Register (P11DIR) P13 Direction Register (P13DIR) P15 Direction Register (P15DIR) P17 Direction Register (P17DIR) P19 Direction Register (P19DIR) P21 Direction Register (P21DIR) (Use inhibited area) 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 8-8 +0 address b7 b8 P1 Data Register (P1DATA) P3 Data Register (P3DATA) (Use inhibited area) P7 Data Register (P7DATA) P9 Data Register (P9DATA) P11 Data Register (P11DATA) P13 Data Register (P13DATA) P15 Data Register (P15DATA) P17 Data Register (P17DATA) P19 Data Register (P19DATA) P21 Data Register (P21DATA) (Use inhibited area) +1 address b15 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 8-7 See pages
|
H'0080 0720 H'0080 0722 H'0080 0724 H'0080 0726 H'0080 0728 H'0080 072A H'0080 072C H'0080 072E H'0080 0730 H'0080 0732 H'0080 0734 H'0080 0736
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Input/Output Port Related Register Map (2/2)
Address b0 H'0080 0740 H'0080 0742 H'0080 0744 H'0080 0746 H'0080 0748 H'0080 074A H'0080 074C H'0080 074E H'0080 0750 H'0080 0752 H'0080 0754 H'0080 0756 +0 address
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
+1 address b7 b8 b15 P1 Operation Mode Register (P1MOD) P3 Operation Mode Register (P3MOD) Port Input Special Function Control Register (PICNT) P7 Operation Mode Register (P7MOD) P9 Operation Mode Register (P9MOD) P11 Operation Mode Register (P11MOD) P13 Operation Mode Register (P13MOD) P15 Operation Mode Register (P15MOD) P17 Operation Mode Register (P17MOD) P19 Operation Mode Register (P19MOD) P21 Operation Mode Register (P21MOD) (Use inhibited area) (Use inhibited area)
See pages 8-9 8-10 8-11 8-21 8-11 8-12 8-12 8-13 8-13 8-14 8-14 8-15 8-15 8-16 8-16 8-17 8-17 8-18 8-18 8-19 8-19
P0 Operation Mode Register (P0MOD) P2 Operation Mode Register (P2MOD) P4 Operation Mode Register (P4MOD) P6 Operation Mode Register (P6MOD) P8 Operation Mode Register (P8MOD) P10 Operation Mode Register (P10MOD) P12 Operation Mode Register (P12MOD) P14 Operation Mode Register (P14MOD) P16 Operation Mode Register (P16MOD) P18 Operation Mode Register (P18MOD) P20 Operation Mode Register (P20MOD) P22 Operation Mode Register (P22MOD)
|
H'0080 0760 H'0080 0762 H'0080 0764
|
H'0080 076A
Port Group 0,1 Input Level Setting Register Port Group 2,3 Input Level Setting Register (PG01LEV) (PG23LEV) Port Group 4,5 Input Level Setting Register Port Group 6,7 Input Level Setting Register (PG45LEV) (PG67LEV) Port Group 8 Input Level Setting Register (Use inhibited area) (PG8LEV) (Use inhibited area) P10 Peripheral Output Select Register (P10SMOD) (Use inhibited area) P22 Peripheral Output Select Register (P22SMOD) (Use inhibited area)
8-25 8-25 8-25
8-20
|
H'0080 0776
(Use inhibited area)
8-20
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8.3.1 Port Data Registers
P0 Data Register (P0DATA) P1 Data Register (P1DATA) P2 Data Register (P2DATA) P3 Data Register (P3DATA) P4 P6 P7 P8 Data Data Data Data Register Register Register Register (P4DATA) (P6DATA) (P7DATA) (P8DATA)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
0706> 0707> 0708>
P9 Data Register (P9DATA) P10 Data Register (P10DATA) P11 Data Register (P11DATA) P12 Data Register (P12DATA) P13 Data Register (P13DATA) P14 Data Register (P14DATA) P15 Data Register (P15DATA) P16 Data Register (P16DATA) P17 Data Register (P17DATA) P18 Data Register (P18DATA) P19 Data Register (P19DATA) P20 Data Register (P20DATA) P21 Data Register (P21DATA) P22 Data Register (P22DATA)
b0 (b8 ? 1 9 ? 2 10 ? 3 11 ? 4 12 ? 5 13 ? 6 14 ? b7 b15) Pn7DT ?

Pn0DT Pn1DT
Pn2DT Pn3DT
Pn4DT Pn5DT Pn6DT
n = 0-22 (not including P5) b 0(b8) 1(b9) 2(b10) 3(b11) 4(b12) 5(b13) 6(b14) 7(b15) Bit Name Pn0DT Port Pn0 data bit Pn1DT Port Pn1 data bit Pn2DT Port Pn2 data bit Pn3DT Port Pn3 data bit Pn4DT Port Pn4 data bit Pn5DT Port Pn5 data bit Pn6DT Port Pn6 data bit Pn7DT Port Pn7 data bit Function Depends on how the Port Direction Register is set If direction bit = "0" (input mode) 0: Port input pin = "low" 1: Port input pin = "high" If direction bit = "1" (output mode) (Note 1) 0: Port output latch = "0" / Port pin level = "low" 1: Port output latch = "1" / Port pin level = "high" Write to the port output latch R R R R R R R R R W W W W W W W W W
Note 1: To select the port data to read, use the Port Input Special Function Control Register's port input data select bit (PISEL). Notes: * No data bits are provided for the following ports (read as "0", writing has no effect): P40, P60, P90-P92, P120-P123, P170, P171, P204-P207 * The SBI# pin level can be read out by reading the P64DT bit. Writing to the P64DT bit has no effect. * The MOD0 and MOD1 pin levels can be read out by reading the P80DT and P81DT bits, respectively. Writing to the P80DT and P81DT bits has no effect. * P221 and P223 are input-only ports. Writing to the P221DT and P223DT bits has no effect.
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8.3.2 Port Direction Registers
P0 Direction Register (P0DIR) P1 Direction Register (P1DIR) P2 Direction Register (P2DIR) P3 Direction Register (P3DIR) P4 P6 P7 P8 Direction Direction Direction Direction Register Register Register Register (P4DIR) (P6DIR) (P7DIR) (P8DIR)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
0726> 0727> 0728>
P9 Direction Register (P9DIR) P10 Direction Register (P10DIR) P11 Direction Register (P11DIR) P12 Direction Register (P12DIR) P13 Direction Register (P13DIR) P14 Direction Register (P14DIR) P15 Direction Register (P15DIR) P16 Direction Register (P16DIR) P17 Direction Register (P17DIR) P18 Direction Register (P18DIR) P19 Direction Register (P19DIR) P20 Direction Register (P20DIR) P21 Direction Register (P21DIR) P22 Direction Register (P22DIR)
b0 (b8 0 1 9 0 2 10 0 3 11 0 4 12 0 5 13 0 6 14 0 b7 b15) 0

Pn0DR Pn1DR Pn2DR Pn3DR
Pn4DR Pn5DR Pn6DR Pn7DR
n = 0-22 (not including P5) b 0(b8) 1(b9) 2(b10) 3(b11) 4(b12) 5(b13) 6(b14) 7(b15) Bit Name Pn0DR (Port Pn0 direction bit) Pn1DR (Port Pn1 direction bit) Pn2DR (Port Pn2 direction bit) Pn3DR (Port Pn3 direction bit) Pn4DR (Port Pn4 direction bit) Pn5DR (Port Pn5 direction bit) Pn6DR (Port Pn6 direction bit) Pn7DR (Port Pn7 direction bit) P40, P60, P64, P80, P81, P90-P92, P120-P123, P170, P171, P204-P207, P221, P223 * After reset, all ports are set for input mode. Function 0: Input mode 1: Output mode R R R R R R R R R W W W W W W W W W
Notes: * No direction bits are provided for the following ports (read as 0, writing has no effect):
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P0 Operation Mode Register (P0MOD)
b0
P00MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
8.3.3 Port Operation Mode Registers

6
P06MD 0
1
P01MD 0
2
P02MD 0
3
P03MD 0
4
P04MD 0
5
P05MD 0
b7
P07MD 0
b 0 1 2 3 4 5 6 7 Bit Name P00MD Port P00 operation mode bit P01MD Port P01 operation mode bit P02MD Port P02 operation mode bit P03MD Port P03 operation mode bit P04MD Port P04 operation mode bit P05MD Port P05 operation mode bit P06MD Port P06 operation mode bit P07MD Port P07 operation mode bit Function 0: P00 1: DB0 0: P01 1: DB1 0: P02 1: DB2 0: P03 1: DB3 0: P04 1: DB4 0: P05 1: DB5 0: P06 1: DB6 0: P07 1: DB7 R W R R W W R R R W W W R R R W W W
Note: * P0 Operation Mode Register is useful only when the CPU operates in external extension mode.
P1 Operation Mode Register (P1MOD)
b8
P10MD 0

14
P16MD 0
9
P11MD 0
10
P12MD 0
11
P13MD 0
12
P14MD 0
13
P15MD 0
b15
P17MD 0
b 8 9 10 11 12 13 14 15 Bit Name P10MD Port P10 operation mode bit P11MD Port P11 operation mode bit P12MD Port P12 operation mode bit P13MD Port P13 operation mode bit P14MD Port P14 operation mode bit P15MD Port P15 operation mode bit P16MD Port P16 operation mode bit P17MD Port P17 operation mode bit Function 0: P10 1: DB8 0: P11 1: DB9 0: P12 1: DB10 0: P13 1: DB11 0: P14 1: DB12 0: P15 1: DB13 0: P16 1: DB14 0: P17 1: DB15 R R W W R R W W R R R W W W R R W W
Note: * P1 Operation Mode Register is useful only when the CPU operates in external extension mode.
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P2 Operation Mode Register (P2MOD)
b0
P20MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

6
P26MD 0
1
P21MD 0
2
P22MD 0
3
P23MD 0
4
P24MD 0
5
P25MD 0
b7
P27MD 0
b 0 1 2 3 4 5 6 7 Bit Name P20MD Port P20 operation mode bit P21MD Port P21 operation mode bit P22MD Port P22 operation mode bit P23MD Port P23 operation mode bit P24MD Port P24 operation mode bit P25MD Port P25 operation mode bit P26MD Port P26 operation mode bit P27MD Port P27 operation mode bit Function 0: P20 1: A23 0: P21 1: A24 0: P22 1: A25 0: P23 1: A26 0: P24 1: A27 0: P25 1: A28 0: P26 1: A29 0: P27 1: A30 R W R R W W R W R R W W R R R W W W
Note: * P2 Operation Mode Register is useful only when the CPU operates in external extension mode.
P3 Operation Mode Register (P3MOD)
b8
P30MD 0

14
P36MD 0
9
P31MD 0
10
P32MD 0
11
P33MD 0
12
P34MD 0
13
P35MD 0
b15
P37MD 0
b 8 9 10 11 12 13 14 15 Bit Name P30MD Port P30 operation mode bit P31MD Port P31 operation mode bit P32MD Port P32 operation mode bit P33MD Port P33 operation mode bit P34MD Port P34 operation mode bit P35MD Port P35 operation mode bit P36MD Port P36 operation mode bit P37MD Port P37 operation mode bit Function 0: P30 1: A15 0: P31 1: A16 0: P32 1: A17 0: P33 1: A18 0: P34 1: A19 0: P35 1: A20 0: P36 1: A21 0: P37 1: A22 R R W W R R W W R W R R W W R R W W
Note: * P3 Operation Mode Register is useful only when the CPU operates in external extension mode.
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P4 Operation Mode Register (P4MOD)
b0 1 2 3 4
P44MD 0 0 0 0 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

6
P46MD 0
5
P45MD 0
b7
P47MD 0
b 0-3 4 5 6 7 Bit Name No function assigned. Fix to "0". P44MD Port P44 operation mode bit P45MD Port P45 operation mode bit P46MD Port P46 operation mode bit P47MD Port P47 operation mode bit 0: P44 1: CS0# 0: P45 1: CS1# 0: P46 1: A13 0: P47 1: A14 R R W W Function R 0 R R W 0 W W
Note: * P4 Operation Mode Register is useful only when the CPU operates in external extension mode.
P6 Operation Mode Register (P6MOD)
b0 1 2 3 4 5
P65MD 0 0 0 0 0 0

6
P66MD 0 0
b7
b 0-4 5 6 7 Bit Name No function assigned. Fix to "0". P65MD Port P65 operation mode bit P66MD Port P66 operation mode bit No function assigned. Fix to "0". * P61-P63 and P67 are always input/output ports (single-function pins). * Port P64 is the SBI# input-only pin. The pin level can be known by reading the data register for P64. 0: P65 1: SCLKI4/SCLKO4 0: P66 1: SCLKI5/SCLKO5 R 0 W 0 Function R 0 R W 0 W
Notes: * Port P60 is nonexistent.
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P7 Operation Mode Register (P7MOD)
b8
P70MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P76MD 0
9
P71MD 0
10
P72MD 0
11
P73MD 0
12
P74MD 0
13
P75MD 0
b15
P77MD 0
b 8 9 10 11 12 13 14 15 Bit Name P70MD Port P70 operation mode bit P71MD Port P71 operation mode bit P72MD Port P72 operation mode bit P73MD Port P73 operation mode bit P74MD Port P74 operation mode bit P75MD Port P75 operation mode bit P76MD Port P76 operation mode bit P77MD Port P77 operation mode bit Function 0: P70 1: BCLK/WR# 0: P71 1: WAIT# 0: P72 1: HREQ# 0: P73 1: HACK# 0: P74 1: RTDTXD 0: P75 1: RTDRXD 0: P76 1: RTDACK 0: P77 1: RTDCLK R W R R W W R W R R W W R R R W W W
P8 Operation Mode Register (P8MOD)
b0 1 2
P82MD 0 0 0

6
P86MD 0
3
P83MD 0
4
P84MD 0
5
P85MD 0
b7
P87MD 0

b 0,1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". P82MD Port P82 operation mode bit P83MD Port P83 operation mode bit P84MD Port P84 operation mode bit P85MD Port P85 operation mode bit P86MD Port P86 operation mode bit P87MD Port P87 operation mode bit Note: * Ports P80 and P81 are nonexistent. 0: P82 1: TXD0 0: P83 1: RXD0 0: P84 1: SCLKI0/SCLKO0 0: P85 1: TXD1 0: P86 1: RXD1 0: P87 1: SCLKI1/SCLKO1 R R W W R R W W Function R 0 R R W 0 W W
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P9 Operation Mode Register (P9MOD)
b8 9 10 11
P93MD 0 0 0 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P96MD 0
12
P94MD 0
13
P95MD 0
b15
P97MD 0
b 8-10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". P93MD Port P93 operation mode bit P94MD Port P94 operation mode bit P95MD Port P95 operation mode bit P96MD Port P96 operation mode bit P97MD Port P97 operation mode bit Note: * Ports P90-P92 are nonexistent. 0: P93 1: TO16 0: P94 1: TO17 0: P95 1: TO18 0: P96 1: TO19 0: P97 1: TO20 R R R W W W Function R 0 R R W 0 W W
P10 Operation Mode Register (P10MOD)
b0
P100MD 0

6
P106MD 0
1
P101MD 0
2
P102MD 0
3
P103MD 0
4
P104MD 0
5
P105MD 0
b7
P107MD 0
b 0 1 2 3 4 5 6 7 Bit Name P100MD Port P100 operation mode bit P101MD Port P101 operation mode bit P102MD Port P102 operation mode bit P103MD Port P103 operation mode bit P104MD Port P104 operation mode bit P105MD Port P105 operation mode bit P106MD Port P106 operation mode bit P107MD Port P107 operation mode bit Function 0: P100 1: TO8 0: P101 1: TO9/TXD3 (Note 1) 0: P102 1: TO10/CTX1 (Note 1) 0: P103 1: TO11 0: P104 1: TO12 0: P105 1: TO13 0: P106 1: TO14 0: P107 1: TO15 R R W W R R W W R R W W R R R W W W
Note 1: These functions are selected using the P10 Peripheral Output Select Register.
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P11 Operation Mode Register (P11MOD)
b8
P110MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P116MD 0
9
P111MD 0
10
P112MD 0
11
P113MD 0
12
P114MD 0
13
P115MD 0
b15
P117MD 0
b 8 9 10 11 12 13 14 15 Bit Name P110MD Port P110 operation mode bit P111MD Port P111 operation mode bit P112MD Port P112 operation mode bit P113MD Port P113 operation mode bit P114MD Port P114 operation mode bit P115MD Port P115 operation mode bit P116MD Port P116 operation mode bit P117MD Port P117 operation mode bit Function 0: P110 1: TO0 0: P111 1: TO1 0: P112 1: TO2 0: P113 1: TO3 0: P114 1: TO4 0: P115 1: TO5 0: P116 1: TO6 0: P117 1: TO7 R R W W R R W W R R W W R R R W W W
P12 Operation Mode Register (P12MOD)
b0
0

6
P126MD 0
1
0
2
0
3
0
4
P124MD 0
5
P125MD 0
b7
P127MD 0
b 0-3 4 5 6 7 Bit Name No function assigned. Fix to "0". P124MD Port P124 operation mode bit P125MD Port P125 operation mode bit P126MD Port P126 operation mode bit P127MD Port P127 operation mode bit Note: * Ports P120-P123 are nonexistent. 0: P124 1: TCLK0 0: P125 1: TCLK1 0: P126 1: TCLK2 0: P127 1: TCLK3 R R W W R W Function R 0 R W 0 W
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P13 Operation Mode Register (P13MOD)
b8
P130MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P136MD 0
9
P131MD 0
10
P132MD 0
11
P133MD 0
12
P134MD 0
13
P135MD 0
b15
P137MD 0
b 8 9 10 11 12 13 14 15 Bit Name P130MD Port P130 operation mode bit P131MD Port P131 operation mode bit P132MD Port P132 operation mode bit P133MD Port P133 operation mode bit P134MD Port P134 operation mode bit P135MD Port P135 operation mode bit P136MD Port P136 operation mode bit P137MD Port P137 operation mode bit Note 1: TIN and PWMOFF inputs both are enabled. Function 0: P130 1: TIN16/PWMOFF0 (Note 1) 0: P131 1: TIN17/PWMOFF1 (Note 1) 0: P132 1: TIN18 0: P133 1: TIN19 0: P134 1: TIN20 0: P135 1: TIN21 0: P136 1: TIN22 0: P137 1: TIN23 R R W W R R W W R R W W R R R W W W
P14 Operation Mode Register (P14MOD)
b0
P140MD 0

6
P146MD 0
1
P141MD 0
2
P142MD 0
3
P143MD 0
4
P144MD 0
5
P145MD 0
b7
P147MD 0
b 0 1 2 3 4 5 6 7 Bit Name P140MD Port P140 operation mode bit P141MD Port P141 operation mode bit P142MD Port P142 operation mode bit P143MD Port P143 operation mode bit P144MD Port P144 operation mode bit P145MD Port P145 operation mode bit P146MD Port P146 operation mode bit P147MD Port P147 operation mode bit Function 0: P140 1: TIN8 0: P141 1: TIN9 0: P142 1: TIN10 0: P143 1: TIN11 0: P144 1: TIN12 0: P145 1: TIN13 0: P146 1: TIN14 0: P147 1: TIN15 R W R R W W R R W W R R W W R R W W
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P15 Operation Mode Register (P15MOD)
b8
P150MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P156MD 0
9
P151MD 0
10
P152MD 0
11
P153MD 0
12
P154MD 0
13
P155MD 0
b15
P157MD 0
b 8 9 10 11 12 13 14 15 Bit Name P150MD Port P150 operation mode bit P151MD Port P151 operation mode bit P152MD Port P152 operation mode bit P153MD Port P153 operation mode bit P154MD Port P154 operation mode bit P155MD Port P155 operation mode bit P156MD Port P156 operation mode bit P157MD Port P157 operation mode bit Function 0: P150 1: TIN0 0: P151 1: TIN1 0: P152 1: TIN2 0: P153 1: TIN3 0: P154 1: TIN4 0: P155 1: TIN5 0: P156 1: TIN6 0: P157 1: TIN7 R R W W R R W W R R W W R R R W W W
P16 Operation Mode Register (P16MOD)
b0
P160MD 0

6
P166MD 0
1
P161MD 0
2
P162MD 0
3
P163MD 0
4
P164MD 0
5
P165MD 0
b7
P167MD 0
b 0 1 2 3 4 5 6 7 Bit Name P160MD Port P160 operation mode bit P161MD Port P161 operation mode bit P162MD Port P162 operation mode bit P163MD Port P163 operation mode bit P164MD Port P164 operation mode bit P165MD Port P165 operation mode bit P166MD Port P166 operation mode bit P167MD Port P167 operation mode bit Function 0: P160 1: TO21 0: P161 1: TO22 0: P162 1: TO23 0: P163 1: TO24 0: P164 1: TO25 0: P165 1: TO26 0: P166 1: TO27 0: P167 1: TO28 R R W W R R W W R R R W W W R R W W
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P17 Operation Mode Register (P17MOD)
b8
0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P176MD 0
9
0
10
P172MD 0
11
P173MD 0
12
P174MD 0
13
P175MD 0
b15
P177MD 0
b 8,9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". P172MD Port P172 operation mode bit P173MD Port P173 operation mode bit P174MD Port P174 operation mode bit P175MD Port P175 operation mode bit P176MD Port P176 operation mode bit P177MD Port P177 operation mode bit Note: * Ports P170 and P171 are nonexistent. 0: P172 1: TIN24 0: P173 1: TIN25 0: P174 1: TXD2 0: P175 1: RXD2 0: P176 1: TXD3 0: P177 1: RXD3 R R W W R R W W Function R 0 R R W 0 W W
P18 Operation Mode Register (P18MOD)
b0
P180MD 0

6
P186MD 0
1
P181MD 0
2
P182MD 0
3
P183MD 0
4
P184MD 0
5
P185MD 0
b7
P187MD 0
b 0 1 2 3 4 5 6 7 Bit Name P180MD Port P180 operation mode bit P181MD Port P181 operation mode bit P182MD Port P182 operation mode bit P183MD Port P183 operation mode bit P184MD Port P184 operation mode bit P185MD Port P185 operation mode bit P186MD Port P186 operation mode bit P187MD Port P187 operation mode bit Function 0: P180 1: TO29 0: P181 1: TO30 0: P182 1: TO31 0: P183 1: TO32 0: P184 1: TO33 0: P185 1: TO34 0: P186 1: TO35 0: P187 1: TO36 R W R R W W R R W W R R R R W W W W
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P19 Operation Mode Register (P19MOD)
b8
P190MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P196MD 0
9
P191MD 0
10
P192MD 0
11
P193MD 0
12
P194MD 0
13
P195MD 0
b15
P197MD 0
b 8 9 10 11 12 13 14 15 Bit Name P190MD Port P190 operation mode bit P191MD Port P191 operation mode bit P192MD Port P192 operation mode bit P193MD Port P193 operation mode bit P194MD Port P194 operation mode bit P195MD Port P195 operation mode bit P196MD Port P196 operation mode bit P197MD Port P197 operation mode bit Note 1: TIN and PWMOFF inputs both are enabled. Function 0: P190 1: TIN26 0: P191 1: TIN27 0: P192 1: TIN28 0: P193 1: TIN29 0: P194 1: TIN30 0: P195 1: TIN31 0: P196 1: TIN32 0: P197 1: TIN33/PWMOFF2 (Note 1) R R W W R R W W R R W W R R R W W W
P20 Operation Mode Register (P20MOD)
b0
P200MD 0

6
0
1
P201MD 0
2
P202MD 0
3
P203MD 0
4
0
5
0
b7
0
b 0 1 2 3 4-7 Bit Name P200MD Port P200 operation mode bit P201MD Port P201 operation mode bit P202MD Port P202 operation mode bit P203MD Port P203 operation mode bit No function assigned. Fix to "0". Function 0: P200 1: TXD4 0: P201 1: RXD4 0: P202 1: TXD5 0: P203 1: RXD5 R 0 W 0 R R W W R R W W
Note: * Ports P204-P207 are nonexistent.
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P21 Operation Mode Register (P21MOD)
b8
P210MD 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers

14
P216MD 0
9
P211MD 0
10
P212MD 0
11
P213MD 0
12
P214MD 0
13
P215MD 0
b15
P217MD 0
b 8 9 10 11 12 13 14 15 Bit Name P210MD Port P210 operation mode bit P211MD Port P211 operation mode bit P212MD Port P212 operation mode bit P213MD Port P213 operation mode bit P214MD Port P214 operation mode bit P215MD Port P215 operation mode bit P216MD Port P216 operation mode bit P217MD Port P217 operation mode bit Function 0: P210 1: TO37 0: P211 1: TO38 0: P212 1: TO39 0: P213 1: TO40 0: P214 1: TO41 0: P215 1: TO42 0: P216 1: TO43 0: P217 1: TO44 R R W W R R W W R R W W R R R W W W
P22 Operation Mode Register (P22MOD)
b0
P220MD 0 0

6
P226MD 0
1
2
P222MD 0
3
P223MD 0
4
P224MD 0
5
P225MD 0
b7
P227MD 0
b 0 1 2 3 4 5 6 7 Bit Name P220MD Port P220 operation mode bit No function assigned. Fix to "0". P222MD Port P222 operation mode bit P223MD Port P223 operation mode bit P224MD Port P224 operation mode bit (Note 1) P225MD Port P225 operation mode bit (Note 1) P226MD Port P226 operation mode bit (Note 1) P227MD Port P227 operation mode bit (Note 1) 0: P222 1: CTX1 0: P223 1: CRX1 0: P224 1: A11/CS2# (Note 2) 0: P225 1: A12/CS3# (Note 2) 0: P226 1: CS2# 0: P227 1: CS3# R W R R W W R R W W Function 0: P220 1: CTX0 0 R 0 W R R W W
Note 1: Port P224-P227 operation mode bits are useful only when the CPU operates in external extension mode. Note 2: These functions are selected using the P22 Peripheral Output Select Register. Note: * P221 is the CAN input-only pin.
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b0
0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
8.3.4 Port Peripheral Output Select Registers
P10 Peripheral Output Select Register (P10SMOD)
1
P101 SMD 0

2
P102 SMD 0
3
0
4
0
5
0
6
0
b7
0
b 0 1 2 3-7 Bit Name No function assigned. Fix to "0". P101SMD Port P101 peripheral output select mode bit P102SMD Port P102 peripheral output select mode bit No function assigned. Fix to "0". 0: TO9 1: TXD3 0: TO10 1: CTX1 0 0 Function R 0 R R W 0 W W
P22 Peripheral Output Select Register (P22SMOD)
b0
0

1
0
2
0
3
0
4
P224 SMD 0
5
P225 SMD 0
6
0
b7
0
b 0-3 4 5 6-7 Bit Name No function assigned. Fix to "0". P224SMD Port P224 peripheral output select mode bit P225SMD Port P225 peripheral output select mode bit No function assigned. Fix to "0". 0: A11 1: CS2# 0: A12 1: CS3# R 0 W 0 Function R 0 R W 0 W
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b8
0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
8.3.5 Port Input Special Function Control Register
Port Input Special Function Control Register (PICNT)
9
0

10
0
11
XSTAT 0
12
0
13
0
14
PISEL 0
b15
PIEN0 0
b 8-10 11 12-13 14 15 Bit Name No function assigned. Fix to "0". XSTAT XIN oscillation status bit No function assigned. Fix to "0". PISEL Port input data select bit PIEN0 Port input enable bit 0: Content of port output latch 1: Port pin level 0: Disable input 1: Enable input R W 0: XIN oscillating 1: XIN inactive Function R 0 W 0
R(Note 1) 0 R 0 W
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
(1) XSTAT (XIN oscillation status) bit (Bit 11) 1) Conditions under which XSTAT is set to "1" XSTAT is set to "1" upon detecting that XIN oscillation has stopped. When XIN remains at the same level for a predetermined time (3 BCLK periods up to 4 BCLK periods), XIN oscillation is assumed to have stopped. When operating normally, XIN changes state (high or low) once every BCLK period. 2) Conditions under which XSTAT is cleared to "0" XSTAT is cleared to "0" by a system reset or by writing "0". If XSTAT is cleared at the same time it is set in (1) above, the former has priority. Writing "1" to XSTAT is ignored. 3) Method for using XSTAT to detect XIN oscillation stoppage Because the M32R/ECU internally contains a PLL, the internal clock remains active even when XIN oscillation has stopped. By reading XSTAT without clearing it never once after reset, it is possible to know whether XIN has ever stopped since the reset signal was deasserted. Similarly, by reading XSTAT after clearing it by writing "0", it is possible to know the current oscillating status of XIN. (However, there must be an interval of at least 5 BCLK periods (20 CPU clock periods) between read and write.)
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
(1) To know whether XIN oscillation has ever stopped after being reset
Read XSTAT
(2) To know the current status of XIN oscillation
Write XSTAT = 0 Wait before inspecting XSTAT Wait for 20 CPU clock periods or more
Read XSTAT
Figure 8.3.1 Procedure for Setting XSTAT (2) PISEL (Port input data select) bit (Bit 14) When the Port Direction Register is set for output, this bit selects the target data to be read from the Port Data Register. This bit is unaffected by the Port Operation Mode Register. Table 8.3.1 PISEL Bit Settings and the Target Data To Be Read from the Port Data Register
Direction Register 0 (input) 1 (output) PISEL Settings 0/1 0 1 Target Data to Be Read Port pin level Port output latch Port pin level
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(3) PIEN0 (Port input enable) bit (Bit 15)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.3 Input/Output Port Related Registers
This bit is used to prevent current from flowing into the port input pins. Because the input/output ports are disabled against input after reset, if any ports need to be used in input mode they must be enabled for input by setting this bit to "1". When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the low-level input on it. The following shows the procedure for selecting a peripheral input function. (1) Enable the port for input when its pin level is valid (high or low) (2) Select a function using the port operation mode bit During boot mode, the pins shared with serial I/O functions are enabled for input and can therefore be protected against current flowing in from the pins other than serial I/O functions during flash programming by clearing PIEN0. The table below lists the pins that can be controlled by the PIEN0 bit in each operation mode. Table 8.3.2 Pins Controllable by PIEN0 Bit
Mode Name Controllable Pins P00-P07, P10-P17, P20-P27 P30-P37, P41-P47, P61-P63 P65-P67, P70-P77, P82-P87 P93-P97, P100-P107, P110-P117 P124-P127, P130-P137, P140-P147 P150-P157, P160-P167, P172-P177 P180-P187, P190-P197, P200-P203 P210-P217, P220-P222, P224-P227 P61-P63, P65-P67, P70-P77 P82-P87, P93-P97, P100-P107 P110-P117, P124-P127, P130-P137 P140-P147, P150-P157, P160-P167 P172-P177, P180-P187, P190-P197 P200-P203, P210-P217, P220 P222 P00-P07, P10-P17, P20-P27 P30-P37, P41-P47, P61-P63 P67, P70-P77, P93-P97 P100, P102-P107, P110-P117, P124-P127 P130-P134, P137, P140-P147, P150-P157 P160-P167, P172-P173, P180-P187 P190-P197, P210-P217, P220 P222, P224-P227 Uncontrolled Pins P221, P223, FP, MOD0, MOD1, SBI#, RESET#
Single-chip
External extension Microprocessor
P00-P07, P10-P17 P20-P27, P30-P37 P41-P47, P221, P223-P227 FP, MOD0, MOD1, SBI#, RESET#
Boot (single-chip)
P65, P66, P82-P87, P101 P135-P136, P174-P177, P200-P203 P221, P223, FP, MOD0, MOD1, SBI#, RESET#
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INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.4 Port Input Level Switching Function
8.4 Port Input Level Switching Function
The port input level switching function allows the port threshold to be switched to one of three voltage levels (with or without Schmitt as selected) in units of the following port group. Group 0: P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, P70-P73, P224-P227 Group 1: P65-P67, P82-P87, P172-P177 Group 2: P160-P167, P210-P217 Group 3: P93-P97, P110-P117 Group 4: P124-P127, P140-P147, P190-P197 Group 5: P61-P63, SBI# Group 6: P74-P77, P180-P187, P100-P107 Group 7: P136, P220-P223 Group 8: P130-P135, P137, P150-P157, P200-P203
P174/TXD2 P175/RXD2 P176/TXD3 P177/RXD3 P173/TIN25 P172/TIN24 FP MOD0 MOD1 EXCVDD VSS EXCVCC VDDE VSS VCCE VCC-BUS P17/DB15 P16/DB14 P15/DB13 P14/DB12 P13/DB11 P12/DB10 P11/DB9 P10/DB8 P07/DB7 P06/DB6 P05/DB5 P04/DB4 P03/DB3 P02/DB2 P01/DB1 P00/DB0 VSS P73/HACK# P72/HREQ# P71/WAIT# P70/BCLK/WR# P43/RD# P42/BHW#/BHE# P41/BLW#/BLE# VCC-BUS VSS AD1IN15 AD1IN14 AD1IN13 AD1IN12 AD1IN11 AD1IN10 AD1IN9 AD1IN8 AVSS1 AD1IN7 AD1IN6 AD1IN5 AD1IN4 AD1IN3 AD1IN2 AD1IN1 AD1IN0 VREF1
180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
P82/TXD0 P83/RXD0 P84/SCLKI0/SCLKO0 P85/TXD1 P86/RXD1 P87/SCLKI1/SCLKO1 P65/SCLKI4/SCLKO4 P66/SCLKI5/SCLKO5 P67 P210/TO37 P211/TO38 P212/TO39 P213/TO40 P214/TO41 P215/TO42 P216/TO43 P217/TO44 P160/TO21 P161/TO22 P162/TO23 P163/TO24 P164/TO25 P165/TO26 P166/TO27 P167/TO28 VSS VCCE VCC-BUS P226/CS2# P227/CS3# P44/CS0# P45/CS1# P224/A11/CS2# P225/A12/CS3# P46/A13 P47/A14 P30/A15 P31/A16 P32/A17 P33/A18 P34/A19 P35/A20 P36/A21 P37/A22 VSS P20/A23 P21/A24 P22/A25 P23/A26 P24/A27 P25/A28 P26/A29 P27/A30 VCC-BUS VSS VCCE P93/TO16 P94/TO17 P95/TO18 P96/TO19
181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Port group 3
Port group 4
Port group 0
M32180F8VFP M32180F8TFP
Port group 0 Port group 5
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P97/TO20 P117/TO7 P116/TO6 P115/TO5 P114/TO4 P113/TO3 P112/TO2 P111/TO1 P110/TO0 P147/TIN15 P146/TIN14 P145/TIN13 P144/TIN12 P143/TIN11 P142/TIN10 P141/TIN9 P140/TIN8 P197/TIN33/PWMOFF2 P196/TIN32 P195/TIN31 P194/TIN30 P193/TIN29 P192/TIN28 P191/TIN27 P190/TIN26 P127/TCLK3 P126/TCLK2 P125/TCLK1 P124/TCLK0 EXCVCC VSS VCCE VSS VSS VSS SBI# P63 P62 P61 AD0IN15 AD0IN14 AD0IN13 AD0IN12 AD0IN11 AD0IN10 AD0IN9 AD0IN8 AVSS0 AD0IN7 AD0IN6 AD0IN5 AD0IN4 AD0IN3 AD0IN2 AD0IN1 AD0IN0 VREF0 AVCC0 VSS VCCE
Port group 2
Port group 0
Port group 1
Port group 7 Port group 8
Port group 8
Port group 7
Port group 6
Port group 0
Figure 8.4.1 Port Input Level Switching Groups
AVCC1 VSS VCCE P150/TIN0 P151/TIN1 P152/TIN2 P153/TIN3 P154/TIN4 P155/TIN5 P156/TIN6 P157/TIN7 P200/TXD4 P201/RXD4 P202/TXD5 P203/RXD5 P130/TIN16/PWMOFF0 P131/TIN17/PWMOFF1 P132/TIN18 P133/TIN19 P134/TIN20 P135/TIN21 P136/TIN22 P137/TIN23 P220/CTX0 P221/CRX0 P222/CTX1 P223/CRX1 VCCE OSC-VSS VCNT OSC-VCC XIN OSC-VSS XOUT RESET# P180/TO29 P181/TO30 P182/TO31 P183/TO32 P184/TO33 P185/TO34 P186/TO35 P187/TO36 P74/RTDTXD P75/RTDRXD P76/RTDACK P77/RTDCLK JTDI JTDO JTRST JTCK JTMS P100/TO8 P101/TO9/TXD3 P102/TO10/CTX1 P103/TO11 P104/TO12 P105/TO13 P106/TO14 P107/TO15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
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Port group 6
8
b0 0 1 0 2 0 3 1 4 0 5 0 6 0
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.4 Port Input Level Switching Function
Port Group 0,1 Input Level Setting Register (PG01LEV)
b7 1

WF0SEL PT0SEL VT0SEL0 VT0SEL1 WF1SEL PT1SEL VT1SEL0 VT1SEL1
Port Group 2,3 Input Level Setting Register (PG23LEV)
b8 0 9 0 10 0 11 1 12 0 13 0 14 0 b15 1

WF2SEL PT2SEL VT2SEL0 VT2SEL1 WF3SEL PT3SEL VT3SEL0 VT3SEL1
Port Group 4,5 Input Level Setting Register (PG45LEV)
b0 0 1 0 2 0 3 1 4 0 5 0 6 0 b7 1

WF4SEL PT4SEL VT4SEL0 VT4SEL1 WF5SEL PT5SEL VT5SEL0 VT5SEL1
Port Group 6,7 Input Level Setting Register (PG67LEV)
b8 0 9 0 10 0 11 1 12 0 13 0 14 0 b15 1

WF6SEL PT6SEL VT6SEL0 VT6SEL1 WF7SEL PT7SEL VT7SEL0 VT7SEL1
Port Group 8 Input Level Setting Register (PG8LEV)
b0
0

1
0
2
0
3
1
4
0
5
0
6
0
b7
0
WF8SEL PT8SEL VT8SEL0 VT8SEL1
Note: * The PG8LEV register bits 4-7 have no functions assigned.
b 0(4) 8(12) 1(5) 9(13) 2-3 (6-7) 10-11 (14-15) Bit Name WFnSEL Group n dual-function input select bit PTnSEL Group n port input select bit VTnSEL Group n input threshold select bit Function 0: Select standard input for each pin 1: Select threshold switching function 0: Select CMOS input 1: Select Schmitt input 00: Select 0.35 VCCE 01: Select 0.5 VCCE 10: Select 0.7 VCCE 11: Settings inhibited 00: VT+ = 0.5 VCCE VT- = 0.35 VCCE 01: Settings inhibited 10: VT+ = 0.7 VCCE VT- = 0.35 VCCE 11: VT+ = 0.7 VCCE VT- = 0.5VCCE Note: * The following ports operate with the VCC-BUS power supply, and not with the VCCE power supply. Therefore, the reference voltages for these ports are the VCC-BUS input voltage. P00-P07, P10-P17, P20-P27, P30-P37, P41-P47, P70-P73, P224-P227 R W R R R W W W
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0.7VCCE 0.5VCCE Pin
Input function enable
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.4 Port Input Level Switching Function
S S
VT+ Schmitt VTS Port input
0.35VCCE Threshold
S VTnSELL
CMOS
PTnSEL
Standard input level for each peripheral function pin
S WFnSEL
Peripheral function input
Figure 8.4.2 Port Level Switching Function
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8.5 Port Peripheral Circuits
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.5 Port Peripheral Circuits
Figures 8.5.1 through 8.5.4 show the peripheral circuit diagrams of the input/output ports described in the preceding pages.
P00-P07(DB0-DB7) P10-P17(DB8-DB15) P20-P27(A23-A30) P30-P37(A15-A22) P46, P47(A13, A14) P71(WAIT#) P73(HACK#) P74(RTDTXD) P76(RTDACK) P224(A11/CS2#) P225(A12/CS3#)
Direction register
Data bus
Port output latch Input data select bit
Operation mode register
(Note 1)
Port level switching function (Standard: peripheral TTL) Input function enable
Peripheral function input
P44(CS0#) P45(CS1#) P70(BCLK/WR#) P82(TXD0) P85(TXD1) P93-P97(TO16-TO20) P100(TO8) P103-P107(TO11-TO15) P110-P117(TO0-TO7) P166, P167(TO27, TO28) P174(TXD2) P176(TXD3) P186, P187(TO35, TO36) P200(TXD4) P202(TXD5) P216, P217(TO43, TO44) P220(CTX0) P222(CTX1) P226(CS2#) P227(CS3#)
Direction register
Data bus
Port output latch Input data select bit
Operation mode register
(Note 1)
Port level switching function (No peripheral input) Input function enable
Peripheral function input
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: * During processor mode, P00-P07, P10-P17, P20-P27, P30-P37, P45-P47, P224, and P225 are external bus interface control signal pins, but their functional description in this block diagram is omitted. * Although P224 and P225 serve triple functions, their functional description in this block diagram is omitted. * The circle denotes a pin. * The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. * The input capacitance of each pin is approximately 10 pF.
Figure 8.5.1 Port Peripheral Circuit Diagram (1)
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P101(TO9/TXD3) P102(TO10/CTX1) Data bus
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.5 Port Peripheral Circuits
Direction register
Port output latch Input data select bit
Operation mode register
(Note 1)
Peripheral output select register Input function enable Port level switching function (No peripheral input)
Peripheral function output 1 Peripheral function output 2
P72(HREQ#) P75(RTDRXD) P77(RTDCLK) P83(RXD0) P86(RXD1) P124-P127(TCLK0-TCLK3) P132-P137(TIN18-TIN23) P140-P147(TIN8-TIN15) P150-P157(TIN0-TIN7) P172, P173(TIN24, TIN25) P175(RXD2) P177(RXD3) P190, P196(TIN26, TIN32) P201(RXD4) P203(RXD5) P223(CRX1)
Direction register
Data bus
Port output latch Input data select bit
Operation mode register
Peripheral function input
Input function enable
(Note 1) Port level switching function (Standard: peripheral Schmitt)
P130(TIN16/PWMOFF0) P131(TIN17/PWMOFF1) P197(TIN33/PWMOFF2) Data bus
Direction register
Port output latch Input data select bit
Operation mode register
Peripheral function input 1 Peripheral function input 2
Input function enable
(Note 1) Port level switching function (Standard: peripheral Schmitt)
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: P223 is an input mode-only port. * The circle denotes a pin. * The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. * The input capacitance of each pin is approximately 10 pF.
Figure 8.5.2 Port Peripheral Circuit Diagram (2)
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P160-P165(TO21-TO26) P180-P185(TO29-TO34) P210-P215(TO37-TO42)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.5 Port Peripheral Circuits
PWM output disable Direction register
Data bus
Port output latch Input data select bit
Operation mode register
(Note 1)
Port level switching function (No peripheral input) Input function enable
Peripheral function output
P41(BLW#/BLE#) P42(BHW#/BHE#) P43(RD#) P61-P63 P67
Direction register
Data bus
Port output latch Input data select bit
(Note 1)
Port level switching function (No peripheral input) Input function enable
Direction register Data bus Port output latch Input data select bit P65(SCLKI4/SCLKO4) P66(SCLKI5/SCLKO5) P84(SCLKI0/SCLKO0) P87(SCLKI1/SCLKO1)
Operation mode register
UART/CSIO function select bit Internal/external clock select bit SCLKOi output SCLKIi input
Input function enable
(Note 1) Port level switching function (Standard: peripheral Schmitt)
Note 1: For details about the port level switching function, see Section 8.4, "Port Input Level Switching Function." Notes: * During processor and external extension modes, P41-P43 are external bus interface control signal pins, but their functional description in this block diagram is omitted. * The circle denotes a pin. * The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage. * The input capacitance of each pin is approximately 10 pF.
Figure 8.5.3 Port Peripheral Circuit Diagram (3)
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8
SBI# P221(CRX0) Data bus (DB0-DB15)
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.5 Port Peripheral Circuits
SBI#, CRX0
MOD0, MOD1
FP
JTDI, JTCK, JTMS
Output control JTDO
RESET#, XIN, JTRST
OSC-VCC, VCCE, VDDE VCC-BUS, EXCVCC, EXCVDD
Notes: * The circle denotes a pin. * The symbol denotes a parasitic diode. Make sure the voltage applied to each pin does not exceed the VCCE voltage.
Figure 8.5.4 Port Peripheral Circuit Diagram (4)
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8
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.6 Precautions on Input/Output Ports
8.6 Precautions on Input/Output Ports
* When using input/output ports in output mode Because the value of the Port Data Register is undefined after reset, the Port Data Register must have its initial value set in it before the Port Direction Register can be set for output. Conversely, if the Port Direction Register is set for output before setting data in the Port Data Register, the Port Data Register outputs an undefined value until any data is written into it. * About the port input disable function Because the input/output ports are disabled against input after reset, they must be enabled for input by setting the Port Input Enable (PIEN0) bit to "1" before their input functions can be used. When disabled against input, the input/output ports are in a state equivalent to a situation where the pin has a low-level input applied. Consequently, if a peripheral input function is selected for any port (uncontrolled pin) while disabled against input by using the Port Operation Mode Register, the port may operate unexpectedly due to the low-level input on it.
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8
INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.6 Precautions on Input/Output Ports
This page is blank for reasons of layout.
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CHAPTER 9 DMAC
9.1 9.2 9.3 9.4 Outline of the DMAC DMAC Related Registers Functional Description of the DMAC Precautions about the DMAC
9
9.1 Outline of the DMAC
DMAC
9.1 Outline of the DMAC
The microcomputer internally contains a 10-channel DMAC (Direction Memory Access Controller). It allows data to be transferred at high speed between internal peripheral I/Os, between internal RAM and internal peripheral I/O, or between internal RAMs, as initiated by a software trigger or requested from an internal peripheral I/O. Table 9.1.1 Outline of the DMAC
Item Number of channels Description 10 channels * Request from internal peripheral I/Os: A-D converter, multijunction timer, serial I/O (reception completed, transmit buffer empty) or CAN * DMA channels can be cascaded (Note 1) Maximum number of times transferred Transferable address space Transfer data size Transfer method Transfer mode Direction of transfer * 64 Kbytes (address space from H'0080 0000 to H'0080 FFFF) * Transfers between internal peripheral I/Os, between internal RAM and internal peripheral I/O, and between internal RAMs are supported. 16 or 8 bits Single transfer DMA (control of the internal bus is relinquished for each transfer performed), dualaddress transfer Single transfer mode One of three modes can be selected for the source and destination: * Address fixed * Address incremental * Ring buffered Channel priority Maximum transfer rate Interrupt request Transfer area DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 (Priority is fixed) 13.3 Mbytes per second (when internal peripheral clock BCLK = 20 MHz) Group interrupt request can be generated when each transfer count register underflows. 64 Kbytes from H'0080 0000 to H'0080 FFFF (Transferable in the entire RAM/SFR area) 65,536 times
Transfer request sources * Software trigger
Note 1: The DMA channels can be cascaded in the manner described below. * Start DMA transfer on DMA1 upon completion of one DMA transfer on DMA0 * Start DMA transfer on DMA5 upon completion of all DMA transfers on DMA0 (upon underflow of the transfer count register) * Start DMA transfer on DMA2 upon completion of one DMA transfer on DMA1 * Start DMA transfer on DMA0 upon completion of one DMA transfer on DMA2 * Start DMA transfer on DMA3 upon completion of one DMA transfer on DMA2 * Start DMA transfer on DMA4 upon completion of one DMA transfer on DMA3 * Start DMA transfer on DMA6 upon completion of one DMA transfer on DMA5 * Start DMA transfer on DMA7 upon completion of one DMA transfer on DMA6 * Start DMA transfer on DMA5 upon completion of one DMA transfer on DMA7 * Start DMA transfer on DMA8 upon completion of one DMA transfer on DMA7 * Start DMA transfer on DMA9 upon completion of one DMA transfer on DMA8
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Input event bus
3210
DMAC
9.1 Outline of the DMAC
Output event bus
0123
AD0 conversion completed TIO8_udf TIN0S
S
AD0 conversion completed TIO8_udf Software start
S
DMA0
udf end
TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf
S
TIN13S Software start
S
DMA1
udf end
CAN0_S1/S14 TID2_udf/ovf
S
TIN18S Software start
S
DMA2
udf end
TIN0S AD1 conversion completed
S
SIO0_TXD SIO1_RXD Software start
S
DMA3
udf end
TIN19S SIO0_TXD TOU1_7irq
S
SIO0_RXD Software start
S
DMA4
udf end
DMA0-4 interrupt
TIN20S TOU0_0irq TOU2_7irq
Software start
S
SIO2_RXD
S
DMA5
udf end
TOU0_1irq SIO1_RXD
S
SIO1_TXD TIN1S Software start
S
DMA6
udf end
SIO3_TXD TOU0_2irq
S
SIO2_TXD TIN2S Software start
S
DMA7
udf end
TOU0_6irq TIN7S
S
SIO3_RXD Software start
S
DMA8
udf end
AD1 conversion completed TOU0_7irq
S
SIO3_TXD TIN8S Software start
S
DMA9
udf end
DMA5-9 interrupt
0123
3210
Figure 9.1.1 Block Diagram of the DMAC
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9
9.2 DMAC Related Registers
The diagram below shows a memory map of the DMAC related registers. DMAC Related Register Map (1/2)
Address b0 H'0080 0400 +0 address b7 b8
DMAC
9.2 DMAC Related Registers
+1 address b15
See pages 9-24 9-25
|
H'0080 0408
DMA0-4 Interrupt Request Status Register DMA0-4 Interrupt Request Mask Register (DM04ITST) (DM04ITMK) (Use inhibited area) DMA5-9 Interrupt Request Status Register DMA5-9 Interrupt Request Mask Register (DM59ITST) (DM59ITMK) (Use inhibited area) DMA0 Channel Control Register 0 DMA0 Channel Control (DM0CNT0) (DM0CNT1) DMA0 Source Address Register (DM0SA) DMA0 Destination Address Register (DM0DA) DMA0 Transfer Count Register (DM0TCT) DMA5 Channel Control Register 0 DMA5 Channel Control (DM5CNT0) (DM5CNT1) DMA5 Source Address Register (DM5SA) DMA5 Destination Address Register (DM5DA) DMA5 Transfer Count Register (DM5TCT) DMA1 Channel Control Register 0 DMA1 Channel Control (DM1CNT0) (DM1CNT1) DMA1 Source Address Register (DM1SA) DMA1 Destination Address Register (DM1DA) DMA1 Transfer Count Register (DM1TCT) DMA6 Channel Control Register 0 DMA6 Channel Control (DM6CNT0) (DM6CNT1) DMA6 Source Address Register (DM6SA) DMA6 Destination Address Register (DM6DA) DMA6 Transfer Count Register (DM6TCT) DMA2 Channel Control Register 0 DMA2 Channel Control (DM2CNT0) (DM2CNT1) DMA2 Source Address Register (DM2SA) DMA2 Destination Address Register (DM2DA) DMA2 Transfer Count Register (DM2TCT) DMA7 Channel Control Register 0 DMA7 Channel Control (DM7CNT0) (DM7CNT1) DMA7 Source Address Register (DM7SA) DMA7 Destination Address Register (DM7DA) DMA7 Transfer Count Register (DM7TCT) Register 1
9-24 9-25
|
H'0080 0410 H'0080 0412 H'0080 0414 H'0080 0416 H'0080 0418 H'0080 041A H'0080 041C H'0080 041E H'0080 0420 H'0080 0422 H'0080 0424 H'0080 0426 H'0080 0428 H'0080 042A H'0080 042C H'0080 042E H'0080 0430 H'0080 0432 H'0080 0434 H'0080 0436 H'0080 0438 H'0080 043A H'0080 043C H'0080 043E
9-6 9-19 9-20 9-21
Register 1
9-11 9-19 9-20 9-21
Register 1
9-7 9-19 9-20 9-21
Register 1
9-12 9-19 9-20 9-21
Register 1
9-8 9-19 9-20 9-21
Register 1
9-13 9-19 9-20 9-21
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DMAC Related Register Map (2/2)
Address b0 H'0080 0440 H'0080 0442 H'0080 0444 H'0080 0446 H'0080 0448 H'0080 044A H'0080 044C H'0080 044E H'0080 0450 H'0080 0452 H'0080 0454 H'0080 0456 H'0080 0458 H'0080 045A H'0080 045C H'0080 045E H'0080 0460 H'0080 0462 H'0080 0464 H'0080 0466 H'0080 0468 +0 address b7 b8
DMAC
9.2 DMAC Related Registers
+1 address b15 Register 1
See pages 9-9 9-19 9-20 9-21 Register 1 9-14 9-19 9-20 9-21 Register 1 9-10 9-19 9-20 9-21 Register 1 9-15 9-19 9-20 9-21 9-18 9-18 9-18 9-18 9-18
|
H'0080 0470 H'0080 0472 H'0080 0474 H'0080 0476 H'0080 0478
DMA3 Channel Control Register 0 DMA3 Channel Control (DM3CNT0) (DM3CNT1) DMA3 Source Address Register (DM3SA) DMA3 Destination Address Register (DM3DA) DMA3 Transfer Count Register (DM3TCT) DMA8 Channel Control Register 0 DMA8 Channel Control (DM8CNT0) (DM8CNT1) DMA8 Source Address Register (DM8SA) DMA8 Destination Address Register (DM8DA) DMA8 Transfer Count Register (DM8TCT) DMA4 Channel Control Register 0 DMA4 Channel Control (DM4CNT0) (DM4CNT1) DMA4 Source Address Register (DM4SA) DMA4 Destination Address Register (DM4DA) DMA4 Transfer Count Register (DM4TCT) DMA9 Channel Control Register 0 DMA9 Channel Control (DM9CNT0) (DM9CNT1) DMA9 Source Address Register (DM9SA) DMA9 Destination Address Register (DM9DA) DMA9 Transfer Count Register (DM9TCT) DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 Software Request Generation Register (DM4SRI) (Use inhibited area) DMA5 Software Request Generation (DM5SRI) DMA6 Software Request Generation (DM6SRI) DMA7 Software Request Generation (DM7SRI) DMA8 Software Request Generation (DM8SRI) DMA9 Software Request Generation (DM9SRI) Register Register Register Register Register
9-18 9-18 9-18 9-18 9-18
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9.2.1 DMA Channel Control Registers
DMA0 Channel Control Register 0 (DM0CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL0 0
3
0
4
TENL0 0
5
0
6
0
MDSEL0 TREQF0
TSZSL0 SADSL0 DADSL0
b 0 1 2, 3 Bit Name MDSEL0 DMA0 transfer mode select bit TREQF0 DMA0 transfer request flag bit REQSL0 DMA0 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start or one DMA2 transfer completed 01: A-D0 conversion completed 10: MJT (TIO8_udf) 11: Extended DMA0 transfer request source select (DMA0 Channel Control Register 1) 4 5 6 7 TENL0 DMA0 transfer enable bit TSZSL0 DMA0 transfer size select bit SADSL0 DMA0 source address direction select bit DADSL0 DMA0 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA0 Channel Control Register 1 (DM0CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL0
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL0 Extended DMA0 transfer request source select bit 0000: MJT (input event bus 2) 0001: MJT (TID0_udf/ovf) 0010: CAN (CAN0_S0/S15) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA1 Channel Control Register 0 (DM1CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL1 0
3
0
4
TENL1 0
5
0
6
0
MDSEL1 TREQF1
TSZSL1 SADSL1 DADSL1
b 0 1 2, 3 Bit Name MDSEL1 DMA1 transfer mode select bit TREQF1 DMA1 transfer request flag bit REQSL1 DMA1 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: MJT (output event bus 0) 10: MJT (TIN13S) 11: Extended DMA1 transfer request source select (DMA1 Channel Control Register 1) 4 5 6 7 TENL1 DMA1 transfer enable bit TSZSL1 DMA1 transfer size select bit SADSL1 DMA1 source address direction select bit DADSL1 DMA1 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA1 Channel Control Register 1 (DM1CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL1
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL1 Extended DMA1 transfer request source select bit 0000: One DMA0 transfer completed 0001: MJT(TIN3S) 0010: MJT(TID1_udf/ovf) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA2 Channel Control Register 0 (DM2CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL2
3
0
4
TENL2
5
TSZSL2
6
0
MDSEL2 TREQF2
SADSL2 DADSL2
0
0
0
b 0 1 2, 3 Bit Name MDSEL2 DMA2 transfer mode select bit TREQF2 DMA2 transfer request flag bit REQSL2 DMA2 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: MJT (output event bus 1) 10: MJT (TIN18S) 11: Extended DMA2 transfer request source select (DMA2 Channel Control Register 1) 4 5 6 7 TENL2 DMA2 transfer enable bit TSZSL2 DMA2 transfer size select bit SADSL2 DMA2 source address direction select bit DADSL2 DMA2 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA2 Channel Control Register 1 (DM2CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL2
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL2 Extended DMA1 transfer request source select bit 0000: One DMA1 transfer completed 0001: MJT(TID2_udf/ovf) 0010: CAN(CAN0_S1/S14) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA3 Channel Control Register 0 (DM3CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL3 0
3
0
4
TENL3 0
5
TSZSL3 0
6
0
MDSEL3 TREQF3
SADSL3 DADSL3
b 0 1 2, 3 Bit Name MDSEL3 DMA3 transfer mode select bit TREQF3 DMA3 transfer request flag bit REQSL3 DMA3 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO0_TXD (transmit buffer empty) 10: SIO1_RXD 11: Extended DMA3 transfer request source select (DMA3 Channel Control Register 1) 4 5 6 7 TENL3 DMA3 transfer enable bit TSZSL3 DMA3 transfer size select bit SADSL3 DMA3 source address direction select bit DADSL3 DMA3 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA3 Channel Control Register 1 (DM3CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL3
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL3 Extended DMA3 transfer request source select bit 0000: MJT(TIN0) 0001: One DMA2 transfer completed 0010: AD1 conversion completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA4 Channel Control Register 0 (DM4CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL4
3
0
4
TENL4
5
TSZSL4
6
0
MDSEL4 TREQF4
SADSL4 DADSL4
0
0
0
b 0 1 2, 3 Bit Name MDSEL4 DMA4 transfer mode select bit TREQF4 DMA4 transfer request flag bit REQSL4 DMA4 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: One DMA3 transfer completed 10: SIO0_RXD 11: Extended DMA4 transfer request source select (DMA4 Channel Control Register 1) 4 5 6 7 TENL4 DMA4 transfer enable bit TSZSL4 DMA4 transfer size select bit SADSL4 DMA4 source address direction select bit DADSL4 DMA4 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA4 Channel Control Register 1 (DM4CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL4
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL4 Extended DMA4 transfer request source select bit 0000: MJT(TIN19S) 0001: SIO0_TXD (transmit buffer empty) 0010: MJT(TOU1_7irq) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA5 Channel Control Register 0 (DM5CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
DADSL5
1
0
2
REQSL5
3
0
4
TENL5
5
TSZSL5
6
SADSL5
MDSEL5 TREQF5
0
0
0
0
0
b 0 1 2, 3 Bit Name MDSEL5 DMA5 transfer mode select bit TREQF5 DMA5 transfer request flag bit REQSL5 DMA5 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start or one DMA7 transfer completed 01: All DMA0 transfers completed 10: SIO2_RXD 11: Extended DMA5 transfer request source select (DMA5 Channel Control Register 1) 4 5 6 7 TENL5 DMA5 transfer enable bit TSZSL5 DMA5 transfer size select bit SADSL5 DMA5 source address direction select bit DADSL5 DMA5 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA5 Channel Control Register 1 (DM5CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL5
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL5 Extended DMA5 transfer request source select bit 0000: MJT(TIN20S) 0001: MJT(TOU0_0irq) 0010: MJT(TOU2_7irq) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA6 Channel Control Register 0 (DM6CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL6
3
0
4
TENL6
5
0
6
0
MDSEL6 TREQF6
TSZSL6 SADSL6 DADSL6
0
0
b 0 1 2, 3 Bit Name MDSEL6 DMA6 transfer mode select bit TREQF6 DMA6 transfer request flag bit REQSL6 DMA6 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO1_TXD (transmit buffer empty) 10: MJT(TIN1S) 11: Extended DMA6 transfer request source select (DMA6 Channel Control Register 1) 4 5 6 7 TENL6 DMA6 transfer enable bit TSZSL6 DMA6 transfer size select bit SADSL6 DMA6 source address direction select bit DADSL6 DMA6 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA6 Channel Control Register 1 (DM6CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL6
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL6 Extended DMA6 transfer request source select bit 0000: One DMA5 transfer completed 0001: MJT(TOU0_1irq) 0010: SIO1_RXD 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA7 Channel Control Register 0 (DM7CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL7
3
0
4
TENL7
5
TSZSL7
6
0
MDSEL7 TREQF7
SADSL7 DADSL7
0
0
0
b 0 1 2, 3 Bit Name MDSEL7 DMA7 transfer mode select bit TREQF7 DMA7 transfer request flag bit REQSL7 DMA7 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO2_TXD (transmit buffer empty) 10: MJT(TIN2S) 11: Extended DMA7 transfer request source select (DMA7 Channel Control Register 1) 4 5 6 7 TENL7 DMA7 transfer enable bit TSZSL7 DMA7 transfer size select bit SADSL7 DMA7 source address direction select bit DADSL7 DMA7 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA7 Channel Control Register 1 (DM7CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL7
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL7 Extended DMA7 transfer request source select bit 0000: One DMA6 transfer completed 0001: MJT(TOU0_2irq) 0010: SIO3_TXD (transmit buffer empty) 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA8 Channel Control Register 0 (DM8CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL8
3
0
4
TENL8
5
TSZSL8
6
0
MDSEL8 TREQF8
SADSL8 DADSL8
0
0
0
b 0 1 2, 3 Bit Name MDSEL8 DMA8 transfer mode select bit TREQF8 DMA8 transfer request flag bit REQSL8 DMA8 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: MJT (input event bus 0) 10: SIO3_RXD 11: Extended DMA8 transfer request source select (DMA8 Channel Control Register 1) 4 5 6 7 TENL8 DMA8 transfer enable bit TSZSL8 DMA8 transfer size select bit SADSL8 DMA8 source address direction select bit DADSL8 DMA8 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA8 Channel Control Register 1 (DM8CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL8
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL8 Extended DMA8 transfer request source select bit 0000: MJT(TIN7S) 0001: MJT(TOU0_6irq) 0010: One DMA7 transfer completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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DMA9 Channel Control Register 0 (DM9CNT0)
b0
0
DMAC
9.2 DMAC Related Registers

b7
0
1
0
2
REQSL9
3
0
4
TENL9
5
0
6
0
MDSEL9 TREQF9
TSZSL9 SADSL9 DADSL9
0
0
b 0 1 2, 3 Bit Name MDSEL9 DMA9 transfer mode select bit TREQF9 DMA9 transfer request flag bit REQSL9 DMA9 transfer request source select bit Function 0: Normal mode 1: Ring buffer mode 0: Transfer not requested 1: Transfer requested 00: Software start 01: SIO3_TXD (transmit buffer empty) 10: MJT(TIN8S) 11: Extended DMA9 transfer request source select (DMA9 Channel Control Register 1) 4 5 6 7 TENL9 DMA9 transfer enable bit TSZSL9 DMA9 transfer size select bit SADSL9 DMA9 source address direction select bit DADSL9 DMA9 destination address direction select bit 0: Disable transfer 1: Enable transfer 0: 16 bits 1: 8 bits 0: Fixed 1: Increment 0: Fixed 1: Increment R R W W R R W W R W R R W W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA9 Channel Control Register 1 (DM9CNT1)
b8
0

b15
0
9
0
10
0
11
0
12
0
13
0
14
0
REQESEL9
b 8-11 12-15 Bit Name No function assigned. Fix to "0". REQESEL9 Extended DMA9 transfer request source select bit 0000: One DMA8 transfer completed 0001: MJT(TOU0_7irq) 0010: AD1 conversion completed 0011: Common 1) MJT (input event bus 1) 0100: Common 2) MJT (input event bus 3) 0101: Common 3) MJT (output event bus 2) 0110: Common 4) MJT (output event bus 3) 0111: Common 5) AD0 conversion completed 1000: Common 6) MJT (TIN0S) 1001: Common 7) MJT (TIO8_udf) 1010: Settings inhibited | | 1111: Settings inhibited Function R 0 R W 0 W
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[DMnCNT0 Register] (1) MDSELn (DMAn Transfer Mode Select) bit (Bit 0)
DMAC
9.2 DMAC Related Registers
The DMA Channel Control Register consists of the bits to select DMA transfer mode on each channel, set the DMA transfer request flag, select the cause or source of DMA request and enable DMA transfer, as well as those to set the transfer size and the source/destination address directions.
When performing DMA transfer in single transfer mode, this bit selects normal mode or ring buffer mode. Setting this bit to "0" selects normal mode and setting it to "1" selects ring buffer mode. In ring buffer mode, transfer begins from the transfer start address and after performing transfers 32 times, control is recycled back to the transfer start address, from which transfer operation is repeated. In this case, the Transfer Count Register counts in free-run mode, during which time transfer operation is continued until the transfer enable bit is reset to "0" (to disable transfer). In ring buffer mode, no interrupt is generated at completion of DMA transfer. (2) TREQFn (DMAn Transfer Request Flag) bit (Bit 1) This flag is set to "1" when a DMA transfer request occurs, and is cleared to "0" when the transfer for that transfer request is completed. Reading this flag helps to know DMA transfer requests on each channel. Writing "0" to this bit clears the generated DMA transfer request. Writing "1" has no effect; the bit retains the value it had before the write. If a new DMA transfer request occurs on a channel for which the DMA transfer request flag has already been set to "1", the next DMA transfer request is not accepted until the transfer being performed on that channel is completed. (3) REQSLn (DMAn Transfer Request Source Select) bits (Bits 2-3) These bits select the cause or source of DMA transfer request on each DMA channel. (4) TENLn (DMAn Transfer Enable) bit (Bit 4) Setting this bit to "1" enables transfer, and the channel is made ready for DMA transfer. When all transfers on that channel are completed (i.e., the Transfer Counter Register underflows), the bit is cleared to "0". Setting this bit to "0" disables transfer. However, if a transfer request has already been accepted, transfers on that channel are not disabled until after the requested transfer is completed. (5) TSZSLn (DMAn Transfer Size Select) bit (Bit 5) This bit selects the number of bits to be transferred in one DMA transfer operation (the unit of one transfer). The unit of one transfer is 16 bits when TSZSL = "0" or 8 bits when TSZSL = "1". (6) SADSLn (DMAn Source Address Direction Select) bit (Bit 6) This bit selects the direction in which the source address changes. This mode can be selected from two choices: Address fixed or Address incremental. (7) DADSLn (DMAn Destination Address Direction Select) bit (Bit 7) This bit selects the direction in which the destination address changes. This mode can be selected from two choices: Address fixed or Address incremental. [DMnCNT1 Register] (1) REQESELn (Extended DMAn Transfer Request Source Select) bits (Bits 12-15) These bits select the cause or source of extended DMA transfer request on each DMA channel. Note: * The extended DMA transfer request sources selected by the REQESELn (Extended DMAn Transfer Request Source Select) bits have no effect unless the "Extended" DMA transfer request source is selected with the DMA Channel Control Register's DMA Request Source Select (REQSLn) bits.
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DMAC
9.2 DMAC Related Registers
Extended DMA transfer request source selected
S
DMAn transfer request source
S
DMAn
Figure 9.2.1 Block Diagram of Extended DMAn Transfer Request Source Selection
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9.2.2 DMA Software Request Generation Registers
DMA0 Software Request Generation Register (DM0SRI) DMA1 Software Request Generation Register (DM1SRI) DMA2 Software Request Generation Register (DM2SRI) DMA3 Software Request Generation Register (DM3SRI) DMA4 DMA5 DMA6 DMA7 Software Software Software Software Request Request Request Request Generation Generation Generation Generation Register Register Register Register (DM4SRI) (DM5SRI) (DM6SRI) (DM7SRI)
DMAC
9.2 DMAC Related Registers
0470> 0472> 0474>
DMA8 Software Request Generation Register (DM8SRI) DMA9 Software Request Generation Register (DM9SRI)
b0 ? 1 ? 2 ? 3 ? 4 ? 5 ? 6 7 8 9 10 ? 11 ?

12 ? 13 ? 14 ? b15 ?
DM0SRI-DM9SRI ? ? ? ?
b 0-15 Bit Name DM0SRI-DM9SRI DMA software request generation bits Function DMA transfer request is generated by writing any data to these bits. R H W W
Note: * This register may be accessed in either bytes or halfwords.
The DMA Software Request Generation Register is used to generate DMA transfer requests in software. A DMA transfer request can be generated by writing any data to this register when "Software start" has been selected for the cause of DMA transfer request. (1) DM0SRI-DM9SRI (DMA Software Request Generation) bits A software DMA transfer request is generated by writing any data to this register in halfword (16 bits) or in byte (8 bits) beginning with an even or odd address when "Software start" is selected as the cause of DMA transfer request (by setting the DMAn Channel Control Register 0 bits 2-3 to `00').
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9.2.3 DMA Source Address Registers
DMA0 Source Address Register (DM0SA) DMA1 Source Address Register (DM1SA) DMA2 Source Address Register (DM2SA) DMA3 Source Address Register (DM3SA) DMA4 DMA5 DMA6 DMA7 Source Source Source Source Address Address Address Address Register Register Register Register (DM4SA) (DM5SA) (DM6SA) (DM7SA)
DMAC
9.2 DMAC Related Registers

6 ? 7 8 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ?
DMA8 Source Address Register (DM8SA) DMA9 Source Address Register (DM9SA)
b0 ? 1 ? 2 ? 3 ? 4 ? 5 ?
DM0SA-DM9SA ? ?
b 0-15 Bit Name DM0SA-DMA9SA Function Source address bits A16-A31 (A0-A15 are fixed to H'0080) Note: * This register must always be accessed in halfwords. R R W W
The DMA Source Address Register is used to set the source address of DMA transfer in such a way that bit 0 and bit 5 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same source address that was set in it before the DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Source Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0SA-DM9SA (Source Address bits A16-A31) Set this register to specify the source address of DMA transfer in the internal I/O or RAM space from the address H'0080 0000 to the address H'0080 FFFF. The 16 high-order source address bits (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order source address bits (with bit 0 corresponding to the source address A16, and bit 15 corresponding to the source address A31).
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9.2.4 DMA Destination Address Registers
DMA0 Destination Address Register (DM0DA) DMA1 Destination Address Register (DM1DA) DMA2 Destination Address Register (DM2DA) DMA3 Destination Address Register (DM3DA) DMA4 DMA5 DMA6 DMA7 Destination Destination Destination Destination Address Address Address Address Register Register Register Register (DM4DA) (DM5DA) (DM6DA) (DM7DA)
DMAC
9.2 DMAC Related Registers

6 ? 7 8 9 ? 10 ? 11 ? 12 ? 13 ? 14 ? b15 ?
DMA8 Destination Address Register (DM8DA) DMA9 Destination Address Register (DM9DA)
b0 ? 1 ? 2 ? 3 ? 4 ? 5 ?
DM0DA-DM9DA ? ?
b 0-15 Bit Name DM0DA-DM9DA Function Destination address bits A16-A31 (A0-A15 are fixed to H'0080) Note: * This register must always be accessed in halfwords R R W W
The DMA Destination Address Register is used to set the destination address of DMA transfer in such a way that bit 0 and bit 15 correspond to A16 and A31, respectively. Because this register is comprised of a current register, the values read from this register are always the current value. When DMA transfer finishes (i.e., the Transfer Count Register underflows), the value in this register if "Address fixed" is selected, is the same source address that was set in it before the DMA transfer began; if "Address incremental" is selected, the value in this register is the last transfer address + 1 (for 8-bit transfer) or the last transfer address + 2 (for 16-bit transfer). The DMA Destination Address Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined. (1) DM0DA-DM9DA (Destination Address bits A16-A31) Set this register to specify the destination address of DMA transfer in the internal I/O or RAM space from the address H'0080 0000 to the address H'0080 FFFF. The 16 high-order destination address bits (A0-A15) are always fixed to H'0080. Use this register to set the 16 low-order destination address bits (with bit 0 corresponding to the destination address A16, and bit 15 corresponding to the destination address A31).
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9.2.5 DMA Transfer Count Registers
DMA0 Transfer Count Register (DM0TCT) DMA1 Transfer Count Register (DM1TCT) DMA2 Transfer Count Register (DM2TCT) DMA3 Transfer Count Register (DM3TCT) DMA4 DMA5 DMA6 DMA7 Transfer Transfer Transfer Transfer Count Count Count Count Register Register Register Register (DM4TCT) (DM5TCT) (DM6TCT) (DM7TCT)
DMAC
9.2 DMAC Related Registers

6 7 8 9 10 ? 11 ? 12 ? 13 ? 14 ? b15 ?
DMA8 Transfer Count Register (DM8TCT) DMA9 Transfer Count Register (DM9TCT)
b0 ? 1 ? 2 ? 3 ? 4 ? 5 ?
DM0TCT-DM15TCT ? ? ? ?
b 0-15 Bit Name DM0TCT-DM9TCT (Has no effect during ring buffer mode) Note: * This register must always be accessed in halfwords. Function DMA transfer count R R W W
The DMA Transfer Count Register is used to set the number of times data is transferred on each channel. However, the value in this register has no effect during ring buffer mode. The transfer count is the (value set in the transfer count register + 1). Because the DMA Transfer Count Register is comprised of a current register, the values read from this register are always the current value. (However, if the register is read in a cycle immediately after transfer, the value obtained is one that was stored in the count register before the transfer began.) When transfer finishes, this count register underflows and the value read from it is H'FFFF. When transfer is enabled, this register is protected in hardware and cannot be accessed for write. During ring buffer mode, the transfer count register counts down in free-run mode and continues counting until transfer is disabled. No interrupt is generated at underflow. If any cascaded channel exists, each time one DMA transfer (byte or halfword) is completed or when all transfers on a channel are completed (i.e., the transfer count register underflows), transfer on the cascaded channel starts. The DMA Transfer Count Register must always be accessed in halfwords (16 bits) beginning with an even address. If accessed in bytes, the value in this register is undefined.
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9.2.6 DMA Interrupt Related Registers
DMAC
9.2 DMAC Related Registers
The DMA interrupt related registers are used to control the interrupt request signals sent from the DMAC to the Interrupt Controller. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupt requests within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests.
Group interrupt
Interrupt request from each peripheral function Set Data = 0 clear Interrupt request status
Data bus
F/F F/F
Interrupt request enabled To the Interrupt Controller
Figure 9.2.2 Interrupt Request Status and Mask Registers
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Example for clearing interrupt request status Interrupt request status
b4 5 0 6 0 b7 0
DMAC
9.2 DMAC Related Registers
Initial state
0
Interrupt request Event occurs on bit 6
0 0 1 0
Event occurs on bit 4 Write to the interrupt request status
b4 1 5 1 6 0 b7 1
1
0
1
0
1
0
0
0
Only bit 6 cleared Bit 4 data retained
Program example * To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
b4 5 0 6 1 b7 0
Event occurs on bit 6
0
Read
0 0 1 0
Event occurs on bit 4
1
0
1
0
Clear bit 6 (AND'ing with 1101)
0 0 0 0
0
0
0
0
Write Only bit 6 cleared Bit 4 also cleared
Figure 9.2.3 Example for Clearing Interrupt Request Status
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DMA0-4 Interrupt Request Status Register (DM04ITST)
b0
0
DMAC
9.2 DMAC Related Registers

1
0
2
0
3
0
4
0
5
0
6
0
b7
0
DMITST4 DMITST3 DMITST2 DMITST1 DMITST0
b 0-2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". DMITST4 (DMA4 interrupt request status bit) DMITST3 (DMA3 interrupt request status bit) DMITST2 (DMA2 interrupt request status bit) DMITST1 (DMA1 interrupt request status bit) DMITST0 (DMA0 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
DMA5-9 Interrupt Request Status Register (DM59ITST)
b0
0

1
0
2
0
3
0
4
0
5
0
6
0
b7
0
DMITST9 DMITST8 DMITST7 DMITST6 DMITST5
b 0-2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". DMITST9 (DMA9 interrupt request status bit) DMITST8 (DMA8 interrupt request status bit) DMITST7 (DMA7 interrupt request status bit) DMITST6 (DMA6 interrupt request status bit) DMITST5 (DMA5 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
The Interrupt Request Status Register helps to know the status of interrupt requests on each channel. If the DMAn interrupt request status bit (n = 0-9) is set to "1", it means that a DMA interrupt request on the corresponding channel has been generated. (1) DMITSTn (DMAn Interrupt Request Status) bit (n = 0-9) [Setting the DMAn interrupt request status bit] This bit is set in hardware, and cannot be set in software. [Clearing the DMAn interrupt request status bit] This bit is cleared by writing "0" in software. Note: * The DMAn interrupt request status bit cannot be cleared by writing "0" to the DMA Interrupt Control Register's "interrupt request bit" included in the Interrupt Controller. When writing to the DMA Interrupt Request Status Register, make sure only the bits to be cleared are set to "0" and all other bits are set to "1". Those bits that have been set to "1" are unaffected by writing in software and retain the value they had before the write.
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DMA0-4 Interrupt Request Mask Register (DM04ITMK)
b8
0
DMAC
9.2 DMAC Related Registers

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
DMITMK4 DMITMK3 DMITMK2 DMITMK1 DMITMK0
b 8-10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". DMITMK4 (DMA4 interrupt request mask bit) DMITMK3 (DMA3 interrupt request mask bit) DMITMK2 (DMA2 interrupt request mask bit) DMITMK1 (DMA1 interrupt request mask bit) DMITMK0 (DMA0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
DMA5-9 Interrupt Request Mask Register (DM59ITMK)
b8
0

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
DMITMK9 DMITMK8 DMITMK7 DMITMK6 DMITMK5
b 8-10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". DMITMK9 (DMA9 interrupt request mask bit) DMITMK8 (DMA8 interrupt request mask bit) DMITMK7 (DMA7 interrupt request mask bit) DMITMK6 (DMA6 interrupt request mask bit) DMITMK5 (DMA5 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
The DMA Interrupt Request Mask Register is used to mask interrupt requests on each DMA channel. (1) DMITMKn (DMAn Interrupt Request Mask) bit (n = 0-9) Setting the DMAn interrupt request mask bit to "1" masks the interrupt requests on DMAn channel. However, if an interrupt request occurs, the DMAn interrupt request status bit is always set to "1" irrespective of the contents of this mask register.
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DM04ITST (H'0080 0400) DM04ITMK (H'0080 0401) DMA4UDF Data bus b3 b11 DMA3UDF b4 b12 DMA2UDF b5 b13 DMA1UDF b6 b14 DMA0UDF b7 b15 DMITST0 F/F DMITMK0 F/F DMITST1 F/F DMITMK1 F/F DMITST2 F/F DMITMK2 F/F DMITST3 F/F DMITMK3 F/F DMITST4 F/F DMITMK4 F/F 5-source inputs (Level)
DMAC
9.2 DMAC Related Registers
DMA transfer interrupt request 0
Figure 9.2.4 Block Diagram of DMA Transfer Interrupt Request 0
DM59ITST (H'0080 0408) DM59ITMK (H'0080 0409) DMA9UDF Data bus b3 b11 DMA8UDF b4 b12 DMA7UDF b5 b13 DMA6UDF b6 b14 DMA5UDF b7 b15 DMITST5 F/F DMITMK5 F/F DMITST6 F/F DMITMK6 F/F DMITST7 F/F DMITMK7 F/F DMITST8 F/F DMITMK8 F/F DMITST9 F/F DMITMK9 F/F 5-source inputs (Level) DMA transfer interrupt request 1
Figure 9.2.5 Block Diagram of DMA Transfer Interrupt Request 1
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9.3 Functional Description of the DMAC
9.3.1 DMA Transfer Request Sources
DMAC
9.3 Functional Description of the DMAC
For each DMA channel (channels 0-9), DMA transfer can be requested from two or more sources. There are various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all transfers on another DMA channel (cascade mode). The causes or sources of DMA transfer requests are selected using the transfer request source select bits REQSLn on each channel (DMAn Channel Control Register 0 bits 2-3) or the extended transfer request source select bits REQESELn (DMAn Channel Control Register 1 bits 12-15). The tables below list the causes or sources of DMA transfer requests on each channel. Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0
REQSL0 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start or one DMA2 transfer completed A-D0 conversion completed MJT (TIO8_udf) Extended DMA0 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA0 Software Request Generation Register (software start) or when one DMA2 transfer is completed (cascade mode) When A-D0 conversion is completed When MJT TIO8 underflows The source selected by the DMA0 Channel Control Register 1 (DM0CNT1) REQESEL0 bits (see below)
REQESEL0 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (input event bus 2) MJT (TID0_udf/ovf) CAN (CAN0_S0/S15) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When MJT input event bus 2 signal is generated When MJT TID0 underflow/overflow occurs When CAN0 slot 0 transmission failed or slot 15 transmission reception finished When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
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REQSL1 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (output event bus 0) MJT (TIN13 input signal) Extended DMA1 transfer request source selected
DMAC
9.3 Functional Description of the DMAC
Table 9.3.2 DMA Transfer Request Sources and Generation Timings on DMA1
DMA Transfer Request Generation Timing When any data is written to the DMA1 Software Request Generation Register When MJT output event bus 0 signal is generated When MJT TIN13 input signal is generated The source selected by the DMA1 Channel Control Register 1 (DM1CNT1) REQESEL1 bits (see below)
REQESEL1 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA0 transfer completed MJT (TIN3 input signal) MJT (TID1_udf/ovf) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When one DMA0 transfer is completed (cascade mode) When MJT TIN3 input signal is generated When MJT TID1 underflow/overflow occurs When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
Table 9.3.3 DMA Transfer Request Sources and Generation Timings on DMA2
REQSL2 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (output event bus 1) MJT (TIN18 input signal) Extended DMA2 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA2 Software Request Generation Register When MJT output event bus 1 signal is generated When MJT TIN18 input signal is generated The source selected by the DMA2 Channel Control Register 1 (DM2CNT1) REQESEL2 bits (see below)
REQESEL2 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA0 transfer completed MJT(TID2_udf/ovf) CAN(CAN0_S1/S14) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When one DMA0 transfer is completed (cascade mode) When MJT TID2 underflow/overflow occurs When CAN0 slot 1 transmission failed or slot 14 transmission reception finished When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
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REQSL3 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start
DMAC
9.3 Functional Description of the DMAC
Table 9.3.4 DMA Transfer Request Sources and Generation Timings on DMA3
DMA Transfer Request Generation Timing When any data is written to the DMA3 Software Request Generation Register
Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty Serial I/O1 (reception completed) When serial I/O1 reception is completed Extended DMA3 transfer request source selected The source selected by the DMA3 Channel Control Register 1 (DM3CNT1) REQESEL3 bits (see below)
REQESEL3 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN0 input signal) One DMA2 transfer completed A-D1 conversion completed MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When MJT TIN0 input signal is generated When one DMA2 transfer is completed (cascade mode) When A-D1 conversion is completed When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
Table 9.3.5 DMA Transfer Request Sources and Generation Timings on DMA4
REQSL4 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start One DMA3 transfer completed Extended DMA4 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA4 Software Request Generation Register When one DMA3 transfer is completed (cascade mode) The source selected by the DMA4 Channel Control Register 1 (DM4CNT1) REQESEL4 bits (see below)
Serial I/O0 (reception completed) When serial I/O0 reception is completed
REQESEL4 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN19 input signal) MJT (TOU1_7irq) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When MJT TIN19 input signal is generated MJT TOU1_7 interrupt source When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
Serial I/O0 (transmit buffer empty) When serial I/O0 transmit buffer is empty
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REQSL5 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start or one DMA7 transfer completed All DMA0 transfers completed Extended DMA5 transfer request source selected
DMAC
9.3 Functional Description of the DMAC
Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5
DMA Transfer Request Generation Timing When any data is written to the DMA5 Software Request Generation Register (software start) or when one DMA7 transfer is completed (cascade mode) When all DMA0 transfers are completed (cascade mode) The source selected by the DMA5 Channel Control Register 1 (DM5CNT1) REQESEL5 bits (see below)
Serial I/O2 (reception completed) When serial I/O2 reception is completed
REQESEL5 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN20 input signal) MJT (TOU0_0irq) MJT (TOU2_7irq) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When MJT TIN20 input signal is generated MJT TOU0_0 interrupt source MJT TOU2_7 interrupt source When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6
REQSL6 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (TIN1 input signal) Extended DMA6 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA4 Software Request Generation Register When MJT TIN1 input signal is generated The source selected by the DMA6 Channel Control Register 1 (DM6CNT1) REQESEL6 bits (see below)
Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty
REQESEL6 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA5 transfer completed MJT (TOU0_1irq) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When one DMA5 transfer is completed (cascade mode) MJT TOU0_1 interrupt source When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
Serial I/O1 (reception completed) When serial I/O1 reception is completed
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REQSL7 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (TIN2 input signal) Extended DMA7 transfer request source selected
DMAC
9.3 Functional Description of the DMAC
Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7
DMA Transfer Request Generation Timing When any data is written to the DMA7 Software Request Generation Register When MJT TIN2 input signal is generated The source selected by the DMA7 Channel Control Register 1 (DM7CNT1) REQESEL7 bits (see below)
Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty
REQESEL7 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA6 transfer completed MJT (TOU0_2irq) MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When one DMA6 transfer is completed (cascade mode) MJT TOU0_2 interrupt source When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
Serial I/O3 (reception completed) When serial I/O3 reception is completed
Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8
REQSL8 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (input event bus 0) Extended DMA8 transfer request source selected DMA Transfer Request Generation Timing When any data is written to the DMA8 Software Request Generation Register When MJT input event bus 0 signal is generated The source selected by the DMA8 Channel Control Register 1 (DM8CNT1) REQESEL8 bits (see below)
Serial I/O3 (reception completed) When serial I/O3 reception is completed
REQESEL8 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited MJT (TIN7 input signal) MJT (TOU0_6irq) One DMA7 transfer completed MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When MJT TIN7 input signal is generated MJT TOU0_6 interrupt source When one DMA7 transfer is completed (cascade mode) When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
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REQSL9 0 0 1 1 0 1 0 1 DMA Transfer Request Source Software start MJT (TIN8 input signal) Extended DMA9 transfer request source selected
DMAC
9.3 Functional Description of the DMAC
Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9
DMA Transfer Request Generation Timing When any data is written to the DMA9 Software Request Generation Register When MJT TIN8 input signal is generated The source selected by the DMA9 Channel Control Register 1 (DM9CNT1) REQESEL9 bits (see below)
Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty
REQESEL9 DMA Transfer Request Source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 | 1111 Settings inhibited One DMA8 transfer completed MJT (TOU0_7irq) A-D0 conversion completed MJT (input event bus 1) MJT (input event bus 3) MJT (output event bus 2) MJT (output event bus 3) A-D0 conversion completed MJT (TIN0 input signal) MJT (TIO8_udf)
DMA Transfer Request Generation Timing When one DMA8 transfer is completed (cascade mode) MJT TOU0_7 interrupt source When A-D0 conversion is completed When MJT input event bus 1 signal is generated When MJT input event bus 3 signal is generated When MJT output event bus 2 signal is generated When MJT output event bus 3 signal is generated When A-D0 conversion is completed When MJT TIN0 input signal is generated When MJT TIO8 underflow occurs -
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9.3.2 DMA Transfer Processing Procedure
DMAC
9.3 Functional Description of the DMAC
Shown below is an example of how to control DMA transfer in cases when performing transfer on DMA channel 0.
DMA transfer processing starts
Setting interrupt controller-related registers
Set the interrupt controller's DMA0-4 Interrupt Control Register
* Interrupt priority level
Set DMA0 Channel Control Register 0
* Transfers disabled
Set DMA0-4 Interrupt Request Status Registers 0 and 1
* Interrupt request status bits cleared * Interrupt request enabled
Set DMA0-4 Interrupt Request Mask Register
Setting DMAC-related registers
Set DMA0 Source Address Register
* Source address of transfer
Set DMA0 Destination Address Register
* Destination address of transfer
Set DMA0 Count Register
* Number of times DMA transfer is performed * Transfer mode, request source, transfer size, address direction and transfer enable
Set DMA0 Channel Control Registers 0 and 1
Starting DMA transfer
DMA transfer starts as requested by internal peripheral I/O
Transfer count register underflows DMA transfer completed Interrupt request generated
DMA operation completed
Figure 9.3.1 Example of a DMA Transfer Processing Procedure
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9.3.3 Starting DMA
DMAC
9.3 Functional Description of the DMAC
Use the DMAn Channel Control Register 0 REQSL (DMA transfer request source select) and DMAn Channel Control Register 1 REQESEL (extended DMA transfer request source select) bits to set the cause or source of DMA transfer request. To enable DMA, set the TENL (DMA transfer enable) bit to "1". DMA transfer begins when the specified cause or source of DMA transfer request becomes effective after setting the TENL (DMA transfer enable) bit to "1". Note: * If the transfer request source selected by the REQSL (DMA transfer request source select) and REQESEL (extended DMA transfer request source select) bits is MJT (TIN input signal), the time required for DMA transfer to begin after detecting the rising or falling or both edges of the TIN input signal is three cycles (150 ns when the internal peripheral clock = 20 MHz) at the shortest. Or, depending on the preceding or following bus usage condition, up to five cycles (250 ns when the internal peripheral clock = 20 MHz) may be required. (However, this applies when the external bus, HOLD and the LOCK instruction all are unused.) To ensure that changes of the TIN input signal state will be detected correctly, make sure the TIN input signal is held active for a duration of more than 7tc (BCLK)/2. (For details, see Section 21.7, "AC Characteristics (when VCCE = 5 V)," and Section 21.8, "AC Characteristics (when VCCE = 3.3 V).")
9.3.4 DMA Channel Priority
DMA0 has the highest priority. The priority of this and other channels is shown below. DMA0 > DMA1 > DMA2 > DMA3 > DMA4 > DMA5 > DMA6 > DMA7 > DMA8 > DMA9 This order of priority is fixed and cannot be changed. Among channels on which DMA transfer is requested, the channel that has the highest priority is selected.
9.3.5 Gaining and Releasing Control of the Internal Bus
For any channel, control of the internal bus is gained and released in "single transfer DMA" mode. In single transfer DMA, the DMAC gains control of the internal bus (in one peripheral clock cycle) when DMA transfer request is accepted and after executing one DMA transfer (in one read and one write internal clock cycle), returns bus control to the CPU. The diagram below shows the operation in single transfer DMA.
Requested Internal bus arbitration (requests from the DMAC)
Gained
Requested
Gained
Requested
Gained
CPU Internal bus Released Released Released
DMAC
R
W
R
W
R
W
One DMA transfer
One DMA transfer R: Read W: Write
One DMA transfer
Figure 9.3.2 Gaining and Releasing Control of the Internal Bus
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9.3.6 Transfer Units
DMAC
9.3 Functional Description of the DMAC
Use the TSZSL (DMA transfer size select) bit to set for each channel the number of bits (8 or 16 bits) to be transferred in one DMA transfer.
9.3.7 Transfer Counts
Use the DMA Transfer Count Register to set transfer counts for each channel. Transfer can be performed up to 65,536 times. The value of the DMA Transfer Count Register is decremented by one every time one transfer unit is transferred. In ring buffer mode, the DMA Transfer Count Register operates in free-run mode, with the value set in it ignored.
9.3.8 Address Space
The address space in which data can be transferred by DMA is 64 Kbytes of internal peripheral I/O or RAM space (H'0080 0000 through H'0080 FFFF) for both source and destination. To set the source and destination addresses on each DMA channel, use the DMA Source Address Register and DMA Destination Address Register.
9.3.9 Transfer Operation
(1) Dual-address transfer Irrespective of the size of transfer unit, data is transferred in two bus cycles, one for source read access and one for destination write access. (The transfer data is taken into the DMAC's internal temporary register before being transferred.) (2) Bus protocol and bus timing Because the bus interface is shared with the CPU, DMA transfer is performed with the same bus protocol and the same bus timing as when peripheral modules are accessed by the CPU. (3) Transfer rate Transfer is performed using a total of three peripheral clock cycles, one cycle to gain control of the bus and one read and one write cycle to perform one transfer. Therefore, the maximum transfer rate is calculated by the equation below: 1 Maximum transfer rate [bytes per second] = 2 bytes x 1/f(BCLK) x 3 cycles (4) Address count direction and address changes The direction in which the source and destination addresses are counted as transfer proceeds ("Address fixed" or "Address incremental") is set for each channel using the SADSL (source address direction select) and DADSL (destination address direction select) bits. When the transfer size is 16 bits, the address is incremented by two for each DMA transfer performed; when the transfer size is 8 bits, the address is incremented by one. Table 9.3.11 Address Count Direction and Address Changes
Address Count Direction Address fixed Address incremental Transfer Unit 8 bits 16 bits 8 bits 16 bits Address Change for One DMA 0 0 +1 +2
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(5) Transfer count value (6) Transfer byte positions
DMAC
9.3 Functional Description of the DMAC
The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits).
When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination. (Therefore, in addition to data transfers between even addresses or between odd addresses, data may be transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus. The diagram below shows the valid byte positions in DMA transfer.
+0 b0 Source 8 bits b7 b8 8 bits +1 b15
+0 b0 b7 b8 16 bits +1 b15
Destination
8 bits
8 bits
16 bits
Figure 9.3.3 Transfer Byte Positions (7) Ring buffer mode When ring buffer mode is selected, transfer begins from the transfer start address and after performing transfers 32 times, control returns to the transfer start address, from which transfer operation is repeated. In this case, however, the five low-order bits of the ring buffer start address must always be B'00000 (if transfer size = 16 bits, the six low-order bits must be B'000000). The following describes how addresses are incremented in ring buffer mode. [1] When the transfer size is 8 bits The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented by one at a time. When as transfer proceeds the five low-order bits reach B'11111, they are recycled to B'00000 by the next increment operation, thus returning to the start address again. [2] When the transfer size is 16 bits The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented by two at a time. When as transfer proceeds the six low-order bits reach B'111110, they are recycled to B'000000 by the next increment operation, thus returning to the start address again. If the source address has been set to be incremented, it is the source address that recycles to the start address; if the destination address has been set to be incremented, it is the destination address that recycles to the start address. If both source and destination addresses have been set to be incremented, both addresses recycle to the start address. However, the start address on either side must have their five low-order bits initially set to B'00000 (if transfer size = 16 bits, the six low-order bits must be B'000000). During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer).
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Transfer count 1 2 3 Transfer address H'0080 1000 H'0080 1001 H'0080 1002
DMAC
9.3 Functional Description of the DMAC

Transfer count 1 2 3 Transfer address H'0080 1000 H'0080 1002 H'0080 1004
|
31 32 1 2
|
H'0080 101E H'0080 101F H'0080 1000 H'0080 1001
|
31 32 1 2
|
H'0080 103C H'0080 103E H'0080 1000 H'0080 1002
|
|
|
|
Figure 9.3.4 Example of How Addresses Are Incremented in 32-channel Ring Buffer Mode
9.3.10 End of DMA and Interrupt
In normal mode, DMA transfer is terminated by an underflow of the transfer count register. When transfer finishes, the transfer enable bit is cleared to "0" and transfers are thereby disabled. Also, an interrupt request is generated at completion of transfer. However, if interrupt requests on any channel have been masked by the DMA Interrupt Request Mask Register, no interrupt requests are generated on that channel. During ring buffer mode, the transfer count register operates in free-run mode, and transfer continues until the transfer enable bit is cleared to "0" (to disable transfer). In this case, therefore, no interrupt requests are generated at completion of DMA transfer. Nor are these DMA transfer-completed interrupt requests are generated even when transfer in ring buffer mode is terminated by clearing the transfer enable bit.
9.3.11 Each Register Status after Completion of DMA Transfer
When DMA transfer is completed, the status of the source and destination address registers becomes as follows: (1) Address fixed * The values set in the address registers before DMA transfer started remain intact (fixed). (2) Address incremental * For 8-bit transfer, the values of the address registers are the last transfer address + 1. * For 16-bit transfer, the values of the address registers are the last transfer address + 2. The transfer count register at completion of DMA transfer is in an underflow state (H'FFFF). Therefore, before another DMA transfer can be performed, the transfer count register must be set newly again, except when trying to perform transfers 65,536 times (H'FFFF).
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9.4 Precautions about the DMAC
* About writing to the DMAC related registers
DMAC
9.4 Precautions about the DMAC
Because DMA transfer involves exchanging data via the internal bus, the DMAC related registers basically can only be accessed for write immediately after reset or when transfer is disabled (transfer enable bit = "0"). When transfer is enabled, do not write to the DMAC related registers, except the DMA transfer enable bit, the transfer request flag and the DMA Transfer Count Register that is protected in hardware. This is a precaution necessary to ensure stable DMA operation. The table below lists the registers that can or cannot be accessed for write. Table 9.4.1 DMAC Related Registers That Can or Cannot Be Accessed for Write
Status Transfer enabled Transfer disabled Transfer enable bit Can be accessed Can be accessed Transfer request flag Can be accessed Can be accessed Other DMAC related registers Cannot be accessed Can be accessed
Even for registers that can exceptionally be written to while transfer is enabled, the following conditions must be observed: (1) DMA Channel Control Register 0 transfer enable bit and transfer request flag For all other bits in this register, be sure to write the same data that those bits had before the write. Note, however, that only writing "0" is effective for the transfer request flag. (2) DMA Transfer Count Register When transfer is enabled, this register is protected in hardware, so that any data rewritten to it is ignored. (3) Rewriting the DMA source and DMA destination addresses on different channels by DMA transfer Although this operation means accessing the DMAC related registers while DMA is enabled, there is no problem. Note, however, that no data can be transferred by DMA to the DMAC related registers on the currently active channel itself. * Manipulating the DMAC related registers by DMA transfer When manipulating the DMAC related registers by means of DMA transfer (e.g., reloading the DMAC related registers with the initial values by DMA transfer), do not write to the DMAC related registers on the currently active channel through that channel. (If this precaution is neglected, device operation cannot be guaranteed.) It is only the DMAC related registers on other channels that can be rewritten by means of DMA transfer. (For example, the DMAn Source Address and DMAn Destination Address Registers on channel 1 can be rewritten by DMA transfer through channel 0.) * About the DMA Interrupt Request Status Register When clearing the DMA Interrupt Request Status Register, be sure to write "1" to all bits, except those to be cleared. Writing "1" to any bits in this register has no effect, so that they retain the data they had before the write. * About the stable operation of DMA transfer To ensure the stable operation of DMA transfer, never rewrite the DMAC related registers, except the channel control register's transfer enable bit, unless transfer is disabled. One exception is that even when transfer is enabled, the DMA Source Address and DMA Destination Address Registers can be rewritten by DMA transfer from one channel to another.
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CHAPTER 10 MULTIJUNCTION TIMERS
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 Outline of Multijunction Timers Common Units of Multijunction Timers TOP (Output-Related 16-Bit Timer) TIO (Input/Output-Related 16-Bit Timer) TMS (Input-Related 16-Bit Timer) TML (Input-Related 32-Bit Timer) TID (Input-Related 16-Bit Timer) TOU (Output-Related 24-Bit Timer)
10
10.1 Outline of Multijunction Timers
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
The multijunction timers (abbreviated MJT) have input event and output event buses. Therefore, in addition to being used as a single unit, the timers can be internally connected to each other. This capability allows for highly flexible timer configuration, making it possible to meet various application needs. It is because the timers are connected to the internal event buses at multiple points that they are called the "multijunction" timers. The 32180 has six types of MJT as listed in the table below, providing a total of 64-channel timers. Table 10.1.1 Outline of MJT
Name TOP (Timer OutPut) Type Output-related 16-bit timer (down-counter) No. of Channels 11 Description One of three output modes can be selected by software. * Single-shot output mode * Delayed single-shot output mode * Continuous output mode TIO (Timer Input OutPut) Input/output-related 16-bit timer (down-counter) 10 One of three input modes or four output modes can be selected by software. * Measure clear input mode * Measure free-run input mode * Noise processing input mode * PWM output mode * Single-shot output mode * Delayed single-shot output mode * Continuous output mode TMS (Timer Measure Small) TML (Timer Measure Large) TID (Timer Input Derivation) TOU (Timer output Unification) Output-related 24-bit timer (down-counter) 24 Input-related 16-bit timer (up/down-counter)) 3 One of four input modes can be selected by software. * Fixed period mode * Event count mode * Multiply-by-4 event count mode * Up/down event count mode One of five output modes can be selected by software. * PWM output mode * Single-shot PWM mode * Delayed single-shot output mode * Single-shot output mode * Continuous output mode Input-related 32-bit timer (up-counter) 8 32-bit input measure timer Input-related 16-bit timer (up-counter) 8 16-bit input measure timer
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Table 10.1.2 Interrupt Generation Functions of MJT
Signal Name MJT Interrupt Request Source IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 TIO0-3 output TOP6, TOP7 output TOP0-5 output TIO8, TIO9 output TIO4-7 output TOP10 output TOP8, TOP9 output TMS0, TMS1 output TIN7-TIN11 input TIN0-TIN2 input TIN12-TIN19 input TIN20-TIN23 input TIN3-TIN6 input TOU0_0-TOU0_7 output TID0 output TID1 output TOU1_0-TOU1_7 output, TOU2_0-TOU2_7 output TID2 output TIN30-TIN33 input Source of Interrupt
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
No. of ICU Input Sources 4 2 6 2 4 1 2 2 5 3 8 4 4 8 1 1 16 1 4
TIO0-3 output interrupt TOP6, 7 output interrupt TOP0-5 output interrupt TIO8, 9 output interrupt TIO4-7 output interrupt TOP10 output interrupt TOP8, 9 output interrupt TMS0, 1 output interrupt TIN7-TIN11 input interrupt TIN0-2 input interrupt TIN12-19 input interrupt TIN20-23 input interrupt TIN3-6 input interrupt TOU0 output interrupt TID0 output interrupt TID1 output interrupt TOU1 + TOU2 output interrupt TID2 output interrupt TIN30-TIN33 input interrupt
Table 10.1.3 DMA Transfer Request Generation by MJT
Corresponding DMAC Channel No. DMA0 DMA Transfer Request Source TIO8_udf Input event bus 2 TID0_udf/ovf Common transfer request source (see Table 10.1.4) DMA1 Output event bus 0 TIN13 input signal TIN3 input signal TID1_udf/ovf Common transfer request source (see Table 10.1.4) DMA2 Output event bus 1 TIN18 input signal TID2_udf/ovf Common transfer request source (see Table 10.1.4) DMA3 DMA4 TIN0 input signal Common transfer request source (see Table 10.1.4) TIN19 input signal TOU1_7irq Common transfer request source (see Table 10.1.4) DMA5 TIN20 input signal TOU0_0irq TOU2_7irq Common transfer request source (see Table 10.1.4)
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DMA6 TIN1 input signal TOU0_1irq DMA7 TIN2 input signal TOU0_2irq
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
Common transfer request source (see Table 10.1.4)
Common transfer request source (see Table 10.1.4) DMA8 Input event bus 0 TIN7 input signal TOU0_6irq Common transfer request source (see Table 10.1.4) DMA9 TIN8 input signal TOU0_7irq Common transfer request source (see Table 10.1.4)
Table 10.1.4 DMA Transfer Request Generation by MJT (Common)
Corresponding DMAC Channel No. DMAn DMA Transfer Request Source Input event bus 1 Input event bus 3 Output event bus 2 Output event bus 3 TIN0 input signal TIO8_udf
Table 10.1.5 A-D Conversion Start Request by MJT
Signal Name AD0TRG AD1TRG A-D Conversion Start Request Source Input event bus 2, input event bus 3, output event bus 3, TIN23 Input event bus 2, input event bus 3, TID1udf/ovf, TIN23 Can be input to A-D1 conversion start trigger A-D Converter Can be input to A-D0 conversion start trigger
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Clock bus Input event bus
3210 3210
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
Output event bus
S TCLK0 (P124) TCLK0S
IRQ9
clk clk clk
IRQ2
0123
en en en en en en en en
TOP 0 TOP 1 TOP 2 TOP 3 TOP 4 TOP 5 TOP 6 TOP 7
udf
IRQ2
F/F0 F/F1
IRQ2
TO0 (P110) TO1 (P111) TO2 (P112) TO3 (P113) TO4 (P114) TO5 (P115) TO6 (P116) TO7 (P117)
udf udf
IRQ2
F/F2 F/F3
TIN0 (P150)
TIN0S
DMA3,DMA commom PRS0
S
clk clk clk
udf
IRQ2
udf
IRQ2
F/F4 F/F5
IRQ1
BCLK/2
PRS1 PRS2
udf udf
IRQ1
S
IRQ9
clk clk S
S S
IRQ6
F/F6 F/F7
TIN1 (P151)
TIN1S
DMA6
S
udf
IRQ9
S S
clk clk clk
en en en en/cap en/cap en/cap en/cap en/cap
TOP 8 TOP 9 TOP 10 TIO 0 TIO 1 TIO 2 TIO 3 TIO 4
udf udf udf
IRQ0 IRQ6
S S
IRQ5
F/F8 F/F9 F/F10 F/F11 F/F12 F/F13 F/F14 F/F15
TO8 (P100) TO9 (P101) TO10 (P102) TO11 (P103) TO12 (P104) TO13 (P105) TO14 (P106) TO15 (P107)
TIN2 (P152)
TIN2S
DMA7
S S
IRQ0
IRQ12
S S
clk clk S clk
udf udf
IRQ0
TIN3 (P153) TIN4 (P154) TIN5 (P155)
TIN3S TIN4S TIN5S
DMA1 IRQ12 IRQ12
S S
IRQ0
udf udf udf
S clk
IRQ12
S
IRQ4
S S
clk
S
TIN6 (P156)
TIN6S
S TCLK1 (P125) TIN7 (P157) TCLK2 (P126) TIN8 (P140) TCLK1S TIN7S TCLK2S TIN8S
DMA9 IRQ8 DMA8 IRQ8 IRQ4 IRQ8
S S
clk
en/cap
TIO 5
udf
IRQ4
S
F/F16
TO16 (P93)
S S
clk
en/cap
TIO 6
udf
IRQ4
S
F/F17
TO17 (P94)
S S
clk
TIN9 (P141)
TIN9S
IRQ8
en/cap
TIO 7
udf
DMA0 DMA common IRQ3
S
F/F18
TO18 (P95)
S S
clk
TIN10 (P142)
TIN10S
IRQ8
en/cap
TIO 8
udf
S
IRQ3
F/F19
TO19 (P96)
S S
3210 3210
clk
TIN11 (P143)
TIN11S
en/cap
TIO 9
udf
F/F20
TO20 (P97)
0123
PRS0-5 : Prescalers
F/F
: Output flip-flop
S : Selector
Notes: * IRQ0-18 denotes interrupt signals, of which the same number represents the same group of interrupts. * DMA0-9 and DMA common denote DMA request signals to the DMAC. * AD0TRGa and AD1TRG denote trigger signals to the A-D0 and A-D1 converters, respectively.
Figure 10.1.1 Block Diagram of MJT (1/4)
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Clock bus Input event bus
3210 3210
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
Output event bus
0123
TCLK3 (P127)
TCLK3S
IRQ10
S S
IRQ10
clk cap3
TMS 0 cap2 cap1
cap0
ovf
IRQ7
TIN12 (P144)
TIN12S
TIN13 (P145)
TIN13S
DMA1 IRQ10
S
TIN14 (P146)
TIN14S
IRQ10
S
TIN15 (P147)
TIN15S clk cap3 S
IRQ10
S
S
IRQ10
TMS 1 cap2 cap1
cap0
ovf
IRQ7
TIN16/PWMOFF0 (P130) TIN17/PWMOFF1 (P131) TIN18 (P132)
TIN16S
TIN17S
IRQ10
S
TIN18S
DMA2 IRQ10
S
TIN19 (P133)
TIN19S
DMA4
S
BCLK/2
IRQ11
S TIN20S
DMA5 IRQ11
clk cap3 S
TML 0(32-bit) cap2 cap1
cap0
TIN20 (P134)
TIN21 (P135)
TIN21S
IRQ11
S
TIN22 (P136)
TIN22S
IRQ11
S
TIN23 (P137)
TIN23S
S
(To A-D0 converter) AD0TRG (To A-D1 converter)AD1TRG
BCLK/2
IRQ18
S TIN30S
IRQ18
clk cap3 S
TML 1(32-bit) cap2 cap1
cap0
TIN30 (P194)
TIN31 (P195)
TIN31S
IRQ18
S
TIN32 (P196)
TIN32S
IRQ18
S
AD0TRG (to A-D0 converter)
TIN33/PWMOFF2 (P197)
TIN33S
S
AD0TRG (to A-D0 converter)/ AD1TRG (to A-D1 converter) AD0TRG (to A-D0 converter)/ AD1TRG (to A-D1 converter)
3210 3210
0123
Figure 10.1.2 Block Diagram of MJT (2/4)
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TIN16/PWMOFF0 (P130)
PWMOFF0S
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
Output event bus
0 IRQ13 PO0DOS
clk clk clk clk clk clk clk
IRQ11
en TOU0_0 (24-bit) en TOU0_1 (24-bit) en TOU0_2 (24-bit) en TOU0_3 (24-bit) en TOU0_4 (24-bit) en TOU0_5 (24-bit) en TOU0_6 (24-bit) en TOU0_7 (24-bit) CLK1 CLK2 TID 0 S
udf
DMA5 IRQ13
F/F21 F/F22
DMA6 IRQ13
TO21 (P160) TO22 (P161) TO23 (P162) TO24 (P163) TO25 (P164) TO26 (P165) TO27 (P166) TO28 (P167)
udf udf
DMA7 IRQ13
F/F23 F/F24
udf
IRQ13
udf
IRQ13
F/F25 F/F26
IRQ13
udf udf
DMA8 IRQ13
F/F27 F/F28
DMA9 IRQ14 DMA0
TIN24S BCLK/2 TIN24 (P172) TIN25 (P173) TIN25S TIN17/PWMOFF1 (P131)
PWMOFF1S
S
clk clk
udf ovf udf
PRS3
IRQ11
clk clk clk clk clk clk clk
IRQ11
IRQ16
PO1DIS
en TOU1_0 (24-bit) en TOU1_1 (24-bit) en TOU1_2 (24-bit) en TOU1_3 (24-bit) en TOU1_4 (24-bit) en TOU1_5 (24-bit) en TOU1_6 (24-bit) en TOU1_7 (24-bit) CLK1 CLK2 TID 1 S
udf
IRQ16
F/F29 F/F30
IRQ16
TO29 (P180) TO30 (P181) TO31 (P182) TO32 (P183) TO33 (P184) TO34 (P185) TO35 (P186) TO36 (P187)
udf udf
IRQ16
F/F31 F/F32
udf
IRQ16
udf
IRQ16
F/F33 F/F34
IRQ16
udf udf
IRQ16
F/F35 F/F36
DMA4
TIN26S BCLK/2 TIN26 (P190) TIN27 (P191) TIN27S TIN33/PWMOFF2 (P197)
PWMOFF2S
S
clk clk
udf ovf udf
PRS4
IRQ15, AD1TRG (to A-D0 converter) DMA1
IRQ11
clk clk clk clk clk clk clk
IRQ11
IRQ16
PO2DIS
en TOU2_0 (24-bit) en TOU2_1 (24-bit) en TOU2_2 (24-bit) en TOU2_3 (24-bit) en TOU2_4 (24-bit) en TOU2_5 (24-bit) en TOU2_6 (24-bit) en TOU2_7 (24-bit) CLK1 CLK2 TID 2 S
udf
IRQ16
F/F37 F/F38
IRQ16
TO37 (P210) TO38 (P211) TO39 (P212) TO40 (P213) TO41 (P214) TO42 (P215) TO43 (P216) TO44 (P217)
udf udf
IRQ16
F/F39 F/F40
udf
IRQ16
udf
IRQ16
F/F41 F/F42
IRQ16
udf udf
IRQ16
F/F43 F/F44
DMA5 IRQ17 DMA2
TIN28S BCLK/2 TIN28 (P192) TIN29 (P193) TIN29S
S
clk clk
udf ovf udf
PRS5
IRQ11
Figure 10.1.3 Block Diagram of MJT (3/4)
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Input event bus
3210
MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers
Output event bus
0123
AD0 conversion completed TIO8_udf TIN0S
S
AD0 conversion completed TIO8_udf Software start
S
DMA0
udf end
TID0_udf/ovf CAN0_S0/S15 TIN3S TID1_udf/ovf
S
TIN13S Software start
S
DMA1
udf end
CAN0_S1/S14 TID2_udf/ovf
S
TIN18S Software start
S
DMA2
udf end
TIN0S AD1 conversion completed
S
SIO0_TXD SIO1_RXD Software start
S
DMA3
udf end
TIN19S SIO0_TXD TOU1_7irq
S
SIO0_RXD Software start
S
DMA4
udf end
DMA0-4 interrupt
TIN20S TOU0_0irq TOU2_7irq
Software start
S
SIO2_RXD
S
DMA5
udf end
TOU0_1irq SIO1_RXD
S
SIO1_TXD TIN1S Software start
S
DMA6
udf end
SIO3_TXD TOU0_2irq
S
SIO2_TXD TIN2S
S
DMA7
udf end
TOU0_6irq TIN7S
S
SIO3_RXD Software start
S
DMA8
udf end
AD1 conversion completed TOU0_7irq
S
SIO3_TXD TIN8S Software start
S
DMA9
udf end
DMA5-9 interrupt
0123
3210
Figure 10.1.4 Block Diagram of MJT (4/4)
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The common units of MJT include the following:
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
10.2 Common Units of Multijunction Timers
* Prescaler Unit * Clock Bus and Input/Output Event Bus Control Unit * Input Processing Control Unit * Output Flip-flop Control Unit * Interrupt Control Unit
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10.2.1 MJT Common Unit Register Map
MJT Common Unit Register Map (1/2)
Address b0 H'0080 0200 H'0080 0202 H'0080 0204 (Use inhibited area) Prescaler Register 0 (PRS0) Prescaler Register 2 (PRS2) +0 address
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
The table below shows a common unit register map of MJT.
+1 address b7 b8 Clock Bus & Input Event Bus Control Register (CKIEBCR) Prescaler Register 1 (PRS1) Output Event Bus Control Register (OEBCR) (Use inhibited area) b15
See pages 10-16 10-12 10-12 10-17
|
H'0080 0210 H'0080 0212 H'0080 0214 H'0080 0216 H'0080 0218 H'0080 021A
|
H'0080 0220 H'0080 0222 H'0080 0224 H'0080 0226 H'0080 0228 H'0080 022A
TCLK Input Processing Control Register (TCLKCR) TIN0-4 Input Processing Control Register (TIN04CR) TIN5-8 Input Processing Control Register (TIN58CR) TIN9-11 Input Processing Control Register (TIN911CR) TIN12-19 Input Processing Control Register (TIN1219CR) TIN20-23, TIN30-33 Input Processing Control Register (TIN2023_3033CR) (Use inhibited area) F/F6-15 Source Select Register (FF615S) (Use inhibited area) F/F16-19 Source Select Register (FF1619S) F/F0-15 Protect Register (FF015P) F/F0-15 Data Register (FF015D) (Use inhibited area) F/F16-20 Protect Register (FF1620P) (Use inhibited area) F/F16-20 Data Register (FF1620D) (Use inhibited area) TOP0-5 Interrupt Request Status Register (TOP05IST) TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS) TIO0-3 Interrupt Request Mask & Status Register (TIO03IMS) TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS) TIN0-2 Interrupt Request Mask & Status Register (TIN02IMS) TIN7-11 Interrupt Request Status Register (TIN711IST) TIN12-19 Interrupt Request Status Register (TIN1219IST) TIN20-23 Interrupt Request Mask & Status Register (TIN2023IMS) TOP0-5 Interrupt Request Mask Register (TOP05IMA) TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS) TIO4-7 Interrupt Request Mask & Status Register (TIO47IMS) TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS) TIN3-6 Interrupt Request Mask & Status Register (TIN36IMS) TIN7-11 Interrupt Request Mask Register (TIN711IMA) TIN12-19 Interrupt Request Mask Register (TIN1219IMA) TIN30-33 Interrupt Request Mask & Status Register (TIN3033IMS)
10-20 10-21 10-22 10-23 10-24 10-24
10-28 10-29 10-30 10-32 10-30 10-32
|
H'0080 0230 H'0080 0232 H'0080 0234 H'0080 0236 H'0080 0238 H'0080 023A H'0080 023C H'0080 023E
10-39 10-41 10-42 10-43 10-44 10-45 10-46 10-47 10-48 10-49 10-51 10-53 10-57
|
H'0080 07D0 H'0080 07D2 H'0080 07D4 H'0080 07D6 Prescaler Register 3 (PRS3) TOU0 Interrupt Request Mask Register (TOU0IMA) (Use inhibited area) (Use inhibited area) TID0 Control & Prescaler 3 Enable Register (TID0PRS3EN) TOU0 Interrupt Request Status Register (TOU0IST) F/F21-28 Protect Register (FF2128P) F/F21-28 Data Register (FF2128D) 10-12 10-141 10-58 10-31 10-33
|
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MJT Common Unit Register Map (2/2)
Address b0 H'0080 07E0 H'0080 07E2 PWMOFF0 Input Processing Control Register (PWMOFF0CR) TIN24,25 Interrupt Request Mask Register (TIN2425IMA) +0 address
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
+1 address b7 b8 TIN24,25 Input Processing Control Register (TIN2425CR) TIN24,25 Interrupt Request Status Register (TIN2425IST) b15
See pages 10-171 10-25 10-53
|
H'0080 0BD0 H'0080 0BD2 H'0080 0BD4 H'0080 0BD6 Prescaler Register 4 (PRS4) TOU1 Interrupt Request Mask Register (TOU1IMA) (Use inhibited area) (Use inhibited area) TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN) TOU1 Interrupt Request Status Register (TOU1IST) F/F29-36 Protect Register (FF2936P) F/F29-36 Data Register (FF2936D) 10-12 10-142 10-60 10-31 10-33
|
H'0080 0BE0 H'0080 0BE2 PWMOFF1 Input Processing Control Register (PWMOFF1CR) TIN26,27 Interrupt Request Mask Register (TIN2627IMA) TIN26,27 Input Processing Control Register (TIN2627CR) TIN26,27 Interrupt Request Status Register (TIN2627IST) 10-171 10-25 10-54
|
H'0080 0CD0 H'0080 0CD2 H'0080 0CD4 H'0080 0CD6 Prescaler Register 5 (PRS5) TOU2 Interrupt Request Mask Register (TOU2IMA) (Use inhibited area) (Use inhibited area) TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN) TOU2 Interrupt Request Status Register (TOU2IST) F/F37-44 Protect Register (FF3744P) F/F37-44 Data Register (FF3744D) 10-12 10-143 10-61 10-31 10-34
|
H'0080 0CE0 H'0080 0CE2 PWMOFF2 Input Processing Control Register (PWMOFF2CR) TIN28,29 Interrupt Request Mask Register (TIN2829IMA) TIN28,29 Input Processing Control Register (TIN2829CR) TIN28,29 Interrupt Request Status Register (TIN2829IST) 10-172 10-25 10-54
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10.2.2 Prescaler Unit
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
The Prescalers PRS0-5 area an 8-bit counter, which generates clocks supplied to each timer (TOP, TIO, TMS, TML, TID and TOU) from the internal peripheral clock (BCLK) divided by 2 (10 MHz when f(BCLK) = 20 MHz). The values of prescaler registers are initialized to H'00 immediately after reset. When the set value of any prescaler register is rewritten, the prescaler starts operating with the new value at the same time it has underflowed. Values H'00 to H'FF can be set in the prescaler register. The prescaler's divide-by ratio is given by the equation below: 1 Prescaler divide-by ratio = prescaler set value + 1
Prescaler Register 0 (PRS0) Prescaler Register 1 (PRS1) Prescaler Register 2 (PRS2) Prescaler Register 3 (PRS3) Prescaler Register 4 (PRS4) Prescaler Register 5 (PRS5)
b0 b8 0 1 9 0 2 10 0 3 11 0 4 12 0 5 13 0 6 14 0 b7 b15 0

PRS0-PRS5
b 0-7 (8-15) Bit Name PRS0-PRS5 Prescaler Function Set the prescaler divide-by value R R W W
Prescaler Registers 0-2 start counting immediately after reset. Prescaler Registers 3-5 each are activated by setting the TID0 Control & Prescaler 3 Enable Register, TID1 Control & Prescaler 4 Enable Register or TID2 Control & Prescaler 5 Enable Register's prescaler-n enable (PRSnEN) bit to "1" (count start), upon which the prescaler register value is reloaded and the prescaler starts counting. For details, see Section 10.7, "TID (InputRelated 16-Bit Timer)." If the prescaler register is accessed for read during operation, the value written into it, not the current count, is read out.
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(1) Clock bus
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
10.2.3 Clock Bus and Input/Output Event Bus Control Unit
The clock bus is provided for supplying clock to each timer, and is comprised of four lines of clock bus 0-3. Each timer can use these clock bus signals as clock input signals. The table below lists the signals that can be fed into the clock bus. Table 10.2.1 Acceptable Clock Bus Signals
Clock Bus 3 2 1 0 Acceptable Signal TCLK0 input Internal prescaler (PRS2) or TCLK3 input Internal prescaler (PRS1) Internal prescaler (PRS0)
(2) Input event bus The input event bus is provided for supplying a count enable signal or measure capture signal to each timer, and is comprised of four lines of input event bus 0-3. Each timer can use these input event bus signals as enable (or capture) input. Furthermore, they can also be used as request signals to start A-D conversion or DMA transfer. The table below lists the signals that can be fed into the input event bus. Table 10.2.2 Connectable (Acceptable) Input Event Bus Signals
Input Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TIN3 input, output event bus 2 or TIO7 underflow signal TIN0 input, TIN2 input or TIN4 input TIO6 underflow signal TIO5 underflow signal
Note 1: For the destination (output) to which the input event bus signals are connected, see Figure 10.1.1, "Block Diagram of MJT."
(3) Output event bus The output event bus has the underflow signal from each timer connected to it, and is comprised of four lines of output event bus 0-3. Output event bus signals are connected to output flip-flops, and can also be connected to the A-D converter and DMAC. Furthermore, output event bus 2 can be connected to input event bus 3. The table below lists the signals that can be connected to the output event bus. Table 10.2.3 Connectable (Acceptable) Output Event Bus Signals
Input Event Bus 3 2 1 0 Connectable (Acceptable) Signal (Note 1) TOP8, TIO3, TIO4 or TIO8 underflow signal TOP9 or TIO2 underflow signal TOP7 or TIO1 underflow signal TOP6 or TIO0 underflow signal
Note 1: For the destination (output) to which the output event bus signals are connected, see Figure 10.1.1, "Block Diagram of MJT."
Note that the signals from each timer to the output event bus (and TIO5, 6 signals to the input event bus) are generated with the timing shown in Table 10.2.4, and not the timing at which signals are output from the timer to the output flip-flop.
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Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO(Note 1) Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML TID (16-bit measure input) (32-bit measure input) Fixed period mode Event count mode Multiply-by-4 event count mode Up/down event count mode TOU PWM output mode Single-shot PWM mode Delayed single-shot output mode Single-shot output mode Continuous output mode
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
Table 10.2.4 Timing at Which Signals are Generated to the Output Event Bus by Each Timer
Timing at which signals are generated to the output event bus When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows When the counter underflows No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated
Note 1: TIO5-7 output an underflow signal to the input event bus.
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Clock bus
3210 3210
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
Input event bus
Output event bus
0123
TCLK0 (P124) TIN0 (P150)
BCLK/2
TCLK0S
clk clk clk clk
en en en en
TOP 6 TOP 7 TOP 8 TOP 9
udf udf udf udf
TIN0S
PRS0 PRS1 PRS2
TIN2 (P152)
TIN2S TIO 0 udf udf udf udf udf
TIN3 (P153)
TIN3S TIO 1
TIN4 (P154)
TIN4S
TIO 2 TIO 3 TIO 4
TIN5 (P155)
TIN5S
TIN6 (P156)
TIN6S
S TIO 5 TCLK3 (P127) TCLK3S TIO 6
3210 3210
udf udf udf udf
0123
TIO 7 TIO 8
PRS0-2
: Prescaler
S : Selector
Figure 10.2.1 Conceptual Diagram of the Clock Bus and Input/Output Event Bus
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MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
The Clock Bus and Input/Output Event Bus Control Unit has the following registers: * Clock Bus & Input Event Bus Control Register (CKIEBCR) * Output Event Bus Control Register (OEBCR)
Clock Bus & Input Event Bus Control Register (CKIEBCR)
b8
IEB3S 0 0 0

9
10
11
0
12
IEB1S 0
13
IEB0S 0
14
0
b15
CKB2S 0
IEB2S
b 8, 9 Bit Name IEB3S Input event bus 3 input select bit Function 00: Select external input 3 (TIN3) 01: - ditto - 10: Select output event bus 2 11: Select TIO7 output 10, 11 IEB2S Input event bus 2 input select bit 00: Select external input 0 (TIN0) 01: Select external input 2 (TIN2) 10: Select external input 4 (TIN4) 11: - ditto - 12 13 14 15 IEB1S Input event bus 1 input select bit IEB0S Input event bus 0 input select bit No function assigned. Fix to "0". CKB2S Clock bus 2 input select bit 0: Select prescaler 2 1: Select external clock 3 (TCLK3) 0: Select external input 5 (TIN5) 1: Select TIO6 output 0: Select external input 6 (TIN6) 1: Select TIO5 output 0 R 0 W R R W W R W R R W W
The CKIEBCR register is used to select the clock source (external input or prescaler) supplied to the clock bus and the count enable/capture signal (external input or output event bus) supplied to the input event bus.
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Output Event Bus Control Register (OEBCR)
b8
OEB3S 0 0 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

b15
OEB0S 0 0
9
10
11
OEB2S 0
12
0
13
OEB1S 0
14
b 8, 9 Bit Name OEB3S Output event bus 3 input select bit Function 00: Select TOP8 output 01: Select TIO3 output 10: Select TIO4 output 11: Select TIO8 output 10 11 12 13 14 15 No function assigned. Fix to "0". OEB2S Output event bus 2 input select bit No function assigned. Fix to "0". OEB1S Output event bus 1 input select bit No function assigned. Fix to "0". OEB0S Output event bus 0 input select bit 0: Select TOP6 output 1: Select TIO0 output 0: Select TOP7 output 1: Select TIO1 output 0: Select TOP9 output 1: Select TIO2 output 0 R 0 R 0 W 0 W 0 R 0 W R R W W
The OEBCR register is used to select the timer (TOP or TIO) whose underflow signal is supplied to the output event bus.
10.2.4 Input Processing Control Unit
The Input Processing Control Unit processes TCLK and TIN input signals to the MJT. In TCLK input processing, it selects the source of TCLK signal, and for external input, it selects the active edge (rising or falling or both) or level (high or low) of the signal, at which to generate the clock signal supplied to the clock bus. In TIN input processing, the unit selects the active edge (rising or falling or both) or level (high or low) of the signal, at which to generate the enable, measure or count source signal for each timer or the signal supplied to each event bus. Following input processing registers are included: * TLCK Input Processing Control Register (TCLKCR) * TIN0-4 Input Processing Control Register (TIN04CR) * TIN5-8 Input Processing Control Register (TIN58CR) * TIN9-11 Input Processing Control Register (TIN911CR) * TIN12-19 Input Processing Control Register (TIN1219CR) * TIN20-23, TIN30-33 Input Processing Control Register (TIN2023_3033CR) * TIN24,25 Input Processing Control Register (TIN2425CR) * TIN26,27 Input Processing Control Register (TIN2627CR) * TIN28,29 Input Processing Control Register (TIN2829CR)
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Item BCLK/2
BCLK/2
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
(1) Functions of TCLK Input Processing Control Registers
Function
Count clock
Rising edge TCLK
Count clock Falling edge TCLK
Count clock Both edges TCLK
Count clock Low level TCLK
BCLK/2
Count clock High level TCLK
BCLK/2
Count clock
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Item Rising edge TIN
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
(2) Functions of TIN Input Processing Control Registers
Function
Internal edge signal Falling edge TIN
Internal edge signal Both edges TIN
Internal edge signal Low level TIN Prescaler output period or TCLK input period Internal edge signal High level TIN Prescaler output period or TCLK input period Internal edge signal
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TLCK Input Processing Control Register (TCLKCR)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

7
0
1
0
2
0
3
0
4
0
5
0
6
TCLK2S 0
8
0
9
0
10
TCLK1S 0
11
0
12
0
13
0
14
0
b15
0
TCLK3S
TCLK0S
b 0, 1 2, 3 Bit Name No function assigned. Fix to "0". TCLK3S TCLK3 input processing select bit 00: BCLK/2 01: Rising edge 10: Falling edge 11: Both edges 4 5-7 No function assigned. Fix to "0". TCLK2S TCLK2 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8 9-11 No function assigned. Fix to "0". TCLK1S TCLK1 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 12,13 14,15 No function assigned. Fix to "0". TCLK0S TCLK0 input processing select bit 00: BCLK/2 01: Rising edge 10: Falling edge 11: Both edges110 Note: * This register must always be accessed in halfwords. 0 R 0 W 0 R 0 W 0 R 0 W Function R 0 R W 0 W
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TIN0-4 Input Processing Control Register (TIN04CR)
b0 1 2 TIN4S 0 0 0 0 0 0 3 4 5 6 TIN3S 0 0 7
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

8 9 10 11 TIN2S 0 0 0 0 0 12 13 TIN1S 0 0 14 b15 TIN0S 0
b 0 1-3 Bit Name No function assigned. Fix to "0". TIN4S TIN4 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 4 5-7 No function assigned. Fix to "0". TIN3S TIN3 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8,9 10,11 No function assigned. Fix to "0". TIN2S TIN2 input processing select bit 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges 12,13 TIN1S TIN1 input processing select bit 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges 14,15 TIN0S TIN0 input processing select bit 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Note: * This register must always be accessed in halfwords. R W R W 0 R 0 W 0 R 0 W Function R 0 R W 0 W
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TIN5-8 Input Processing Control Register (TIN58CR)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

8
0
1
0
2 TIN8S
0
3
0
4
0
5
0
6 TIN7S
0
7
0
9
0
10 TIN6S
0
11
0
12
0
13
0
14 TIN5S
0
b15
0
b 0 1-3 Bit Name No function assigned. Fix to "0". TIN8S TIN8 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 4 5-7 No function assigned. Fix to "0". TIN7S TIN7 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8 9-11 No function assigned. Fix to "0". TIN6S TIN6 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 12 13-15 No function assigned. Fix to "0". TIN5S TIN5 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level Note: * This register must always be accessed in halfwords. 0 R 0 W 0 R 0 W 0 R 0 W Function R 0 R W 0 W
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TIN9-11 Input Processing Control Register (TIN911CR)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

8
0
1
0
2
0
3
0
4
0
5
0
6
TIN11S 0
7
0
9
0
10
TIN10S 0
11
0
12
0
13
0
14
TIN9S 0
b15
0
b 0-4 5-7 Bit Name No function assigned. Fix to "0". TIN11S TIN11 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 8 9-11 No function assigned. Fix to "0". TIN10S TIN10 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level 12 13-15 No function assigned. Fix to "0". TIN9S TIN9 input processing select bit 000: Disable input 001: Rising edge 010: Falling edge 011: Both edges 100: Low level 101: Low level 110: High level 111: High level Note: * This register must always be accessed in halfwords. 0 R 0 W 0 R 0 W Function R 0 R W 0 W
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

8
0
TIN12-19 Input Processing Control Register (TIN1219CR)
1
0
2
0
3
TIN18S 0
4
0
5
TIN17S 0
6
0
7
TIN16S 0
9
TIN15S 0
10
0
11
0
12
0
13
0
14
0
b15
0
TIN19S
TIN14S
TIN13S
TIN12S
b 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN19S (TIN19 input processing select bit) TIN18S (TIN18 input processing select bit) TIN17S (TIN17 input processing select bit) TIN16S (TIN16 input processing select bit) TIN15S (TIN15 input processing select bit) TIN14S (TIN14 input processing select bit) TIN13S (TIN13 input processing select bit) TIN12S (TIN12 input processing select bit) Function 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges R R W W
Note: * This register must always be accessed in halfwords.
TIN20-23, TIN30-33 Input Processing Control Register (TIN2023_3033CR)
b0
0

11
0
1
0
2
0
3
TIN32S 0
4
0
5
TIN31S 0
6
0
7
TIN30S 0
8
0
9
TIN23S 0
10
0
12
0
13
0
14
0
b15
0
TIN33S
TIN22S
TIN21S
TIN20S
b 0, 1 2, 3 4, 5 6, 7 8, 9 10, 11 12, 13 14, 15 Bit Name TIN33S (TIN33 input processing select bit) TIN32S (TIN32 input processing select bit) TIN31S (TIN31 input processing select bit) TIN30S (TIN30 input processing select bit) TIN23S (TIN23 input processing select bit) TIN22S (TIN22 input processing select bit) TIN21S (TIN21 input processing select bit) TIN20S (TIN20 input processing select bit) Function 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges R R W W
Note: * This register must always be accessed in halfwords.
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b8
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN24, 25 Input Processing Control Register (TIN2425CR)
9
0
10
0
11
0
12
0
13
0
14
0
b15 0
TIN25S
TIN24S
b 8-11 12, 13 14, 15 Bit Name No function assigned. Fix to "0". TIN25S (TIN25 input processing select bit) TIN24S (TIN24 input processing select bit) 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W
TIN26, 27 Input Processing Control Register (TIN2627CR)
b8
0

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TIN27S
TIN26S
b 8-11 12, 13 14, 15 Bit Name No function assigned. Fix to "0". TIN27S (TIN27 input processing select bit) TIN26S (TIN26 input processing select bit) 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W
TIN28, 29 Input Processing Control Register (TIN2829CR)
b8
0

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TIN29S
TIN28S
b 8-11 12, 13 14, 15 Bit Name No function assigned. Fix to "0". TIN29S (TIN29 input processing select bit) TIN28S (TIN28 input processing select bit) 00: Disable input 01: Rising edge 10: Falling edge 11: Both edges Function R 0 R W 0 W
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10.2.5 Output Flip-flop Control Unit
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
The Output Flip-flop Control Unit controls the flip-flops (F/F) provided for each timer. Following flip-flop control registers are included: * F/F6-15 Source Select Register (FF615S) * F/F16-19 Source Select Register (FF1619S) * F/F0-15 Protect Register (FF015P) * F/F16-20 Protect Register (FF1620P) * F/F21-28 Protect Register (FF2128P) * F/F29-36 Protect Register (FF2936P) * F/F37-44 Protect Register (FF3744P) * F/F0-15 Data Register (FF015D) * F/F16-20 Data Register (FF1620D) * F/F21-28 Data Register (FF2128D) * F/F29-36 Data Register (FF2936D) * F/F37-44 Data Register (FF3744D) The timing at which signals are generated to the output flip-flop by each timer are shown in Table 10.2.5. (Note that this timing is different from one at which signals are output from the timer to the output event bus.)
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Timer TOP Mode Single-shot output mode Delayed single-shot output mode Continuous output mode TIO Measure clear input mode Measure free-run input mode Noise processing input mode PWM output mode Single-shot output mode Delayed single-shot output mode Continuous output mode TMS TML TID (16-bit measure input) (32-bit measure input) Fixed period count mode Event count mode Multiply-by-4 event count mode Up/down event count mode TOU PWM output mode Single-shot PWM output mode Delayed single-shot output mode Single-shot output mode Continuous output mode
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
Table 10.2.5 Timing at Which Signals Are Generated to the Output Flip-Flop by Each Timer
Timing at which signals are generated to the output flip-flop When count is enabled or underflows When counter underflows When count is enabled or underflows When counter underflows When counter underflows When counter underflows When count is enabled or underflows When count is enabled or underflows When counter underflows When count is enabled or underflows No signals generated No signals generated No signals generated No signals generated No signals generated No signals generated When count is enabled or underflows When counter underflows When counter underflows When count is enabled or underflows When count is enabled or underflows
F/F source selection (FSn) TOP/TIO/TOU udf Output event bus 0 Output event bus 1 Output event bus 2 Output event bus 3 Data bus WR F/F protect (FPn) Data bus F/F
Port operation mode register (PnMOD) F/F
Internal edge signal
F/Fn output data (FDn) F/F Output control (ON/OFF) TOn
Figure 10.2.2 Configuration of the F/F Output Circuit
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F/F6-15 Source Select Register (FF615S)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

6
FS12 0
1
0
2
0
3
FS15 0
4
FS14 0
5
FS13 0
7
FS11 0
8
FS10 0
9
0
10
FS9 0
11
0
12
FS8 0
13
0
14
FS7 0
b15
FS6 0
b 0-2 3 4 5 6 7 8, 9 Bit Name No function assigned. Fix to "0". FS15 F/F15 source select bit FS14 F/F14 source select bit FS13 F/F13 source select bit FS12 F/F12 source select bit FS11 F/F11 source select bit FS10 F/F10 source select bit 0: TIO4 output 1: Output event bus 0 0: TIO3 output 1: Output event bus 0 0: TIO2 output 1: Output event bus 3 0: TIO1 output 1: Output event bus 2 0: TIO0 output 1: Output event bus 1 00: TOP10 output 01: TOP10 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS9 F/F9 source select bit 00: TOP9 output 01: TOP9 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS8 F/F8 source select bit 00: TOP8 output 01: Output event bus 0 10: Output event bus 1 11: Output event bus 2 14 15 FS7 F/F7 source select bit FS6 F/F6 source select bit Note: * This register must always be accessed in halfwords. 0: TOP7 output 1: Output event bus 0 0: TOP6 output 1: Output event bus 1 R R W W R W R W R R R W W W R R W W Function R 0 R W 0 W
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F/F16-19 Source Select Register (FF1619S)
b8
FS19 0 0 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

b15
FS16 0 0 0
9
10
FS18
11
0
12
FS17 0
13
14
b 8, 9 Bit Name FS19 F/F19 source select bit Function 00: TIO8 output 01: TIO8 output 10: Output event bus 0 11: Output event bus 1 10, 11 FS18 F/F18 source select bit 00: TIO7 output 01: TIO7 output 10: Output event bus 0 11: Output event bus 1 12, 13 FS17 F/F17 source select bit 00: TIO6 output 01: TIO6 output 10: Output event bus 0 11: Output event bus 1 14, 15 FS16 F/F16 source select bit 00: TIO5 output 01: Output event bus 0 10: Output event bus 1 11: Output event bus 3 R W R W R W R R W W
These registers select the signal source for each output F/F (flip-flop). This signal source can be chosen to be a signal from the internal output bus or an underflow output from each timer.
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F/F0-15 Protect Register (FF015P)
b0
FP15 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

5
FP10 0
1
FP14 0
2
FP13 0
3
FP12 0
4
FP11 0
6
FP9 0
7
FP8 0
8
FP7 0
9
FP6 0
10
FP5 0
11
FP4 0
12
FP3 0
13
FP2 0
14
FP1 0
b15
FP0 0
b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FP15 (F/F15 protect bit) FP14 (F/F14 protect bit) FP13 (F/F13 protect bit) FP12 (F/F12 protect bit) FP11 (F/F11 protect bit) FP10 (F/F10 protect bit) FP9 (F/F9 protect bit) FP8 (F/F8 protect bit) FP7 (F/F7 protect bit) FP6 (F/F6 protect bit) FP5 (F/F5 protect bit) FP4 (F/F4 protect bit) FP3 (F/F3 protect bit) FP2 (F/F2 protect bit) FP1 (F/F1 protect bit) FP0 (F/F0 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W
Note: * This register must always be accessed in halfwords.
F/F16-20 Protect Register (FF1620P)
b8
0

14
FP17 0
9
0
10
0
11
FP20 0
12
FP19 0
13
FP18 0
b15
FP16 0
b 8-10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". FP20 (F/F20 protect bit) FP19 (F/F19 protect bit) FP18 (F/F18 protect bit) FP17 (F/F17 protect bit) FP16 (F/F16 protect bit) 0: Enable write to F/F output bit 1: Disable write to F/F output bit Function R 0 R W 0 W
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F/F21-28 Protect Register (FF2128P)
b8
FP21 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

14
FP27 0
9
FP22 0
10
FP23 0
11
FP24 0
12
FP25 0
13
FP26 0
b15
FP28 0
b 8 9 10 11 12 13 14 15 Bit Name FP21 (F/F21 protect bit) FP22 (F/F22 protect bit) FP23 (F/F23 protect bit) FP24 (F/F24 protect bit) FP25 (F/F25 protect bit) FP26 (F/F26 protect bit) FP27 (F/F27 protect bit) FP28 (F/F28 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W
F/F29-36 Protect Register (FF2936P)
b8
FP29 0

14
FP35 0
9
FP30 0
10
FP31 0
11
FP32 0
12
FP33 0
13
FP34 0
b15
FP36 0
b 8 9 10 11 12 13 14 15 Bit Name FP29 (F/F29 protect bit) FP30 (F/F30 protect bit) FP31 (F/F31 protect bit) FP32 (F/F32 protect bit) FP33 (F/F33 protect bit) FP34 (F/F34 protect bit) FP35 (F/F35 protect bit) FP36 (F/F36 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W
F/F37-44 Protect Register (FF3744P)
b8
FP37 0

14
FP43 0
9
FP38 0
10
FP39 0
11
FP40 0
12
FP41 0
13
FP42 0
b15
FP44 0
b 8 9 10 11 12 13 14 15 Bit Name FP37 (F/F37 protect bit) FP38 (F/F38 protect bit) FP39 (F/F39 protect bit) FP40 (F/F40 protect bit) FP41 (F/F41 protect bit) FP42 (F/F42 protect bit) FP43 (F/F43 protect bit) FP44 (F/F44 protect bit) Function 0: Enable write to F/F output bit 1: Disable write to F/F output bit R R W W
These registers control write to each output F/F (flip-flop) by enabling or disabling. If write to any output F/F is disabled, writing to the F/F data register has no effect.
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F/F0-15 Data Register (FF015D)
b0
FD15 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

5
FD10 0
1
FD14 0
2
FD13 0
3
FD12 0
4
FD11 0
6
FD9 0
7
FD8 0
8
FD7 0
9
FD6 0
10
FD5 0
11
FD4 0
12
FD3 0
13
FD2 0
14
FD1 0
b15
FD0 0
b 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit Name FD15 (F/F15 output data bit) FD14 (F/F14 output data bit) FD13 (F/F13 output data bit) FD12 (F/F12 output data bit) FD11 (F/F11 output data bit) FD10 (F/F10 output data bit) FD9 (F/F9 output data bit) FD8 (F/F8 output data bit) FD7 (F/F7 output data bit) FD6 (F/F6 output data bit) FD5 (F/F5 output data bit) FD4 (F/F4 output data bit) FD3 (F/F3 output data bit) FD2 (F/F2 output data bit) FD1 (F/F1 output data bit) FD0 (F/F0 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W
Note: * This register must always be accessed in halfwords.
F/F16-20 Data Register (FF1620D)
b8
0

14
FD17 0
9
0
10
0
11
FD20 0
12
FD19 0
13
FD18 0
b15
FD16 0
b 8-10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". FD20 (F/F20 output data bit) FD19 (F/F19 output data bit) FD18 (F/F18 output data bit) FD17 (F/F17 output data bit) FD16 (F/F16 output data bit) 0: F/F output data = 0 1: F/F output data = 1 Function R 0 R W 0 W
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F/F21-28 Data Register (FF2128D)
b8
FD21 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

14
FD27 0
9
FD22 0
10
FD23 0
11
FD24 0
12
FD25 0
13
FD26 0
b15
FD28 0
b 8 9 10 11 12 13 14 15 Bit Name FD21 (F/F21 output data bit) FD22 (F/F22 output data bit) FD23 (F/F23 output data bit) FD24 (F/F24 output data bit) FD25 (F/F25 output data bit) FD26 (F/F26 output data bit) FD27 (F/F27 output data bit) FD28 (F/F28 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W
F/F29-36 Data Register (FF2936D)
b8
FD29 0

13 14
FD35 0
9
FD30 0
10
FD31 0
11
FD32 0
12
FD33 0
b15
FD36 0
FD34 0
b 8 9 10 11 12 13 14 15 Bit Name FD29 (F/F29 output data bit) FD30 (F/F30 output data bit) FD31 (F/F31 output data bit) FD32 (F/F32 output data bit) FD33 (F/F33 output data bit) FD34 (F/F34 output data bit) FD35 (F/F35 output data bit) FD36 (F/F36 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W
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F/F37-44 Data Register (FF3744D)
b8
FD37 0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

14
FD43 0
9
FD38 0
10
FD39 0
11
FD40 0
12
FD41 0
13
FD42 0
b15
FD44 0
b 8 9 10 11 12 13 14 15 Bit Name FD37 (F/F37 output data bit) FD38 (F/F38 output data bit) FD39 (F/F39 output data bit) FD40 (F/F40 output data bit) FD41 (F/F41 output data bit) FD42 (F/F42 output data bit) FD43 (F/F43 output data bit) FD44 (F/F44 output data bit) Function 0: F/F output data = 0 1: F/F output data = 1 R R W W
These registers are used to set data in each output F/F (flip-flop). Although F/F output normally changes with timer output, setting data 0 or 1 in this register allows to produce desired output from any F/F. The F/F data register can only be operated on when the F/F protect register described earlier is enabled for write.
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10.2.6 Interrupt Control Unit
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
The Interrupt Control Unit controls the interrupt request signals output to the Interrupt Controller by each timer. Following timer interrupt control registers are provided for each timer: * TOP0-5 Interrupt Request Status Register (TOP05IST) * TOP0-5 Interrupt Request Mask Register (TOP05IMA) * TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS) * TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS) * TIO0-3 Interrupt Request Mask & Status Register (TIO03IMS) * TIO4-7 Interrupt Request Mask & Status Register (TIO47IMS) * TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS) * TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS) * TIN0-2 Interrupt Request Mask & Status Register (TIN02IMS) * TIN3-6 Interrupt Request Mask & Status Register (TIN36IMS) * TIN7-11 Interrupt Request Status Register (TIN711IST) * TIN7-11 Interrupt Request Mask Register (TIN711IMA) * TIN12-19 Interrupt Request Status Register (TIN1219IST) * TIN12-19 Interrupt Request Mask Register (TIN1219IMA) * TIN20-23 Interrupt Request Mask & Status Register (TIN2023IMS) * TIN24,25 Interrupt Request Mask Register (TIN2425IMA) * TIN24,25 Interrupt Request Status Register (TIN2425IST) * TIN26,27 Interrupt Request Mask Register (TIN2627IMA) * TIN26,27 Interrupt Request Status Register (TIN2627IST) * TIN28,29 Interrupt Request Mask Register (TIN2829IMA) * TIN28,29 Interrupt Request Status Register (TIN2829IST) * TIN30-33 Interrupt Request Mask & Status Register (TIN3033IMS) * TOU0 Interrupt Request Mask Register (TOU0IMA) * TOU0 Interrupt Request Status Register (TOU0IST) * TOU1 Interrupt Request Mask Register (TOU1IMA) * TOU1 Interrupt Request Status Register (TOU1IST) * TOU2 Interrupt Request Mask Register (TOU2IMA) * TOU2 Interrupt Request Status Register (TOU2IST) For interrupts which have only one interrupt request source in the interrupt vector table, no interrupt control registers are included in the timer, and the interrupt request status flags are automatically managed within the Interrupt Controller. For details, see Chapter 5, "Interrupt Controller." * TOP10 * TID0 * TID1 * TID2 TOP10 Output Interrupt Request (IRQ5) TID0 Output Interrupt Request (IRQ14) TID1 Output Interrupt Request (IRQ15) TID2 Output Interrupt Request (IRQ17)
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MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
For interrupts which have two or more interrupt sources in the interrupt vector table, interrupt control registers are included, with which to control interrupt requests and determine interrupt input. Therefore, the status flags in the Interrupt Controller only serve as a bit to determine interrupt requests from interrupt-enabled sources and cannot be accessed for write. (1) Interrupt request status bit This status bit is used to determine whether there is an interrupt request. When an interrupt request occurs, this bit is set in hardware (cannot be set in software). The status bit is cleared by writing "0". Writing "1" has no effect; the bit retains the status it had before the write. Because this status bit is unaffected by the interrupt request mask bit, it can be used to inspect the operating status of peripheral functions. In interrupt handling, make sure that within the grouped interrupt request status, only the status bit for the interrupt request that has been serviced is cleared. If the status bit for any interrupt request that has not been serviced is cleared, the pending interrupt request is cleared simultaneously with its status bit. (2) Interrupt request mask bit This bit is used to disable unnecessary interrupts within the grouped interrupt request. Set this bit to "0" to enable interrupt requests or "1" to disable interrupt requests.
Group interrupt
Timer or TIN input interrupt request Set Data = 0 clear Interrupt request status
Data bus
F/F F/F
Interrupt request enabled To the Interrupt Controller
Figure 10.2.3 Interrupt Request Status and Mask Registers
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Example for clearing interrupt request status
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
Interrupt request status
b4 5 0 6 0 b7 0
Initial state
0
Interrupt request Event occurs on bit 6
0 0 1 0
Event occurs on bit 4 Write to the interrupt request status
b4 1 5 1 6 0 b7 1
1
0
1
0
1
0
0
0
Only bit 6 cleared Bit 4 data retained
Program example * To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time, avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
b4 5 0 6 1 b7 0
Event occurs on bit 6
0
Read
0 0 1 0
Event occurs on bit 4
1
0
1
0
Clear bit 6 (ANDing with 1101)
0 0 0 0
0
0
0
0
Write Only bit 6 cleared Bit 4 also cleared
Figure 10.2.4 Example for Clearing Interrupt Request Status
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MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
The table below shows the relationship between the interrupt request signals generated by multijunction timers and the interrupt sources input to the Interrupt Controller (ICU). Table 10.2.6 Interrupt Request Signals Generated by MJT
Signal Name IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ16 Generated by TIO0, TIO1, TIO2, TIO3 TOP6, TOP7 TOP0, TOP1, TOP2, TOP3, TOP4, TOP5 TIO8, TIO9 TIO4, TIO5, TIO6, TIO7 TOP8, TOP9 TMS0, TMS1 TIN7, TIN8, TIN9, TIN10, TIN11 TIN0, TIN1, TIN2 TIN12, TIN13, TIN14, TIN15, TIN16, TIN17, TIN18, TIN19 TIN20, TIN21, TIN22, TIN23, TIN24, TIN25 TIN26, TIN27, TIN28, TIN29 TIN3, TIN4, TIN5, TIN6 TOU0_0, TOU0_1, TOU0_2, TOU0_3 TOU0_4, TOU0_5, TOU0_6, TOU0_7 TOU1_0, TOU1_1, TOU1_2, TOU1_3 TOU1_4, TOU1_5, TOU1_6, TOU1_7 TOU2_0, TOU2_1, TOU2_2, TOU2_3 TOU2_4, TOU2_5, TOU2_6, TOU2_7 IRQ18 TIN30, TIN31, TIN32, TIN33 TIN30-33 input interrupt 4 Note 1: See Chapter 5, "Interrupt Controller (ICU)." Note: * TOP10 and TID0-2 have only one interrupt source in each interrupt group, so that their status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.) TOU1 + TOU2 output interrupt 16 TIN3-6 input interrupt TOU0 output interrupt 4 8 TIN20-29 input interrupt 10 Interrupt Request Source (Note 1) TIO0-3 output interrupt TOP6, 7 output interrupt TOP0-5 output interrupt TIO8, 9 output interrupt TIO4-7 output interrupt TOP8, 9 output interrupt TMS0, 1 output interrupt TIN7-11 input interrupt TIN0-2 input interrupt TIN12-19 input interrupt No. of ICU Input Sources 4 2 6 2 4 2 2 5 3 8
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TOP0-5 Interrupt Request Status Register (TOP05IST)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TOPIS5 TOPIS4 TOPIS3 TOPIS2 TOPIS1 TOPIS0
b 0, 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". TOPIS5 (TOP5 interrupt request status bit) TOPIS4 (TOP4 interrupt request status bit) TOPIS3 (TOP3 interrupt request status bit) TOPIS2 interrupt request status bit) TOPIS1 interrupt request status bit) TOPIS0 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TOP0-5 Interrupt Request Mask Register (TOP05IMA)
b8
0

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TOPIM5 TOPIM4 TOPIM3 TOPIM2 TOPIM1 TOPIM0
b 8, 9 10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". TOPIM5 (TOP5 interrupt request mask bit) TOPIM4 (TOP4 interrupt request mask bit) TOPIM3 (TOP3 interrupt request mask bit) TOPIM2 (TOP2 interrupt request mask bit) TOPIM1 (TOP1 interrupt request mask bit) TOPIM0 (TOP0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
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TOP05IST TOP05IMA TOP5udf Data bus b2 b10 TOP4udf b3 b11 TOP3udf b4 b12 TOP2udf b5 b13 TOP1udf b6 b14 TOP0udf b7 b15 TOPIS0 F/F TOPIM0 F/F TOPIS1 F/F TOPIM1 F/F TOPIS2 F/F TOPIM2 F/F TOPIS3 F/F TOPIM3 F/F TOPIS4 F/F TOPIM4 F/F TOPIS5 F/F TOPIM5 F/F
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
6-source inputs TOP0-5 output interrupt request IRQ2
(Level)
Figure 10.2.5 Block Diagram of TOP0-5 Output Interrupt Request
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TOP6,7 Interrupt Request Mask & Status Register (TOP67IMS)
1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TOPIS7 TOPIS6
TOPIM7 TOPIM6
b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0". TOPIS7 (TOP7 interrupt request status bit) TOPIS6 (TOP6 interrupt request status bit) No function assigned. Fix to "0". TOPIM7 (TOP7 interrupt request mask bit) TOPIM6 (TOP6 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TOP67IMS TOP7udf Data bus b2 b6 TOPIS7 F/F TOPIM7 F/F 2-source inputs TOP6,7 output interrupt request IRQ1
(Level)
TOP6udf b3 b7 TOPIS6 F/F TOPIM6 F/F
Figure 10.2.6 Block Diagram of TOP6,7 Output Interrupt Request
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b8
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TOP8,9 Interrupt Request Mask & Status Register (TOP89IMS)
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TOPIS9 TOPIS8
TOPIM9 TOPIM8
b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0". TOPIS9 (TOP9 interrupt request status bit) TOPIS8 (TOP8 interrupt request status bit) No function assigned. Fix to "0". TOPIM9 (TOP9 interrupt request mask bit) TOPIM8 (TOP8 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note: * TOP10 has only one interrupt source in the interrupt group, so that its status and mask registers are nonexistent in the MJT interrupt control registers. (They are controlled directly by the Interrupt Controller.)
TOP89IMS TOP9udf Data bus TOPIS9 b10 b14 TOP8udf b11 b15 TOPIS8 F/F TOPIM8 F/F F/F TOPIM9 F/F (Level) 2-source inputs TOP8,9 output interrupt request IRQ6
Figure 10.2.7 Block Diagram of TOP8,9 Output Interrupt Request
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIO0-3 Interrupt Request Mask & Status Register (TIO03IMS)
1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TIOIS3 TIOIS2 TIOIS1 TIOIS0 TIOIM3 TIOIM2 TIOIM1 TIOIM0
b 0 1 2 3 4 5 6 7 Bit Name TIOIS3 (TIO3 interrupt request status bit) TIOIS2 (TIO2 interrupt request status bit) TIOIS1 (TIO1 interrupt request status bit) TIOIS0 (TIO0 interrupt request status bit) TIOIM3 (TIO3 interrupt request mask bit) TIOIM2 (TIO2 interrupt request mask bit) TIOIM1 (TIO1 interrupt request mask bit) TIOIM0 (TIO0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIO03IMS TIO3udf Data bus b0 b4 TIO2udf b1 b5 TIO1udf b2 b6 TIO0udf b3 b7 TIOIS0 F/F TIOIM0 F/F TIOIS1 F/F TIOIM1 F/F TIOIS2 F/F TIOIM2 F/F TIOIS3 F/F TIOIM3 F/F 2-source inputs TIO0-3 output interrupt request IRQ0
(Level)
Figure 10.2.8 Block Diagram of TIO0-3 Output Interrupt Request
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b8 0 9 0 10 0 11 0 12 0 13 0 14 0 b15 0 TIOIS7 TIOIS6 TIOIS5 TIOIS4 TIOIM7 TIOIM6 TIOIM5 TIOIM4
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIO4-7 Interrupt Request Mask & Status Register (TIO47IMS)
b 8 9 10 11 12 13 14 15 Bit Name TIOIS7 (TIO7 interrupt request status bit) TIOIS6 (TIO6 interrupt request status bit) TIOIS5 (TIO5 interrupt request status bit) TIOIS4 (TIO4 interrupt request status bit) TIOIM7 (TIO7 interrupt request mask bit) TIOIM6 (TIO6 interrupt request mask bit) TIOIM5 (TIO5 interrupt request mask bit) TIOIM4 (TIO4 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIO47IMS TIO7udf Data bus b8 b12 TIO6udf b9 b13 TIO5udf b10 b14 TIO4udf b11 b15 TIOIS4 F/F TIOIM4 F/F TIOIS5 F/F TIOIM5 F/F TIOIS6 F/F TIOIM6 F/F TIOIS7 F/F TIOIM7 F/F 4-source inputs TIO4-7 output interrupt request IRQ4
(Level)
Figure 10.2.9 Block Diagram of TIO4-7 Output Interrupt Request
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b0 0 1 0 2 0 3 0 4 0 5 0 6 0 b7 0 TIOIS9 TIOIS8 TIOIM9 TIOIM8
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIO8,9 Interrupt Request Mask & Status Register (TIO89IMS)
b 0, 1 2 3 4, 5 6 7 Bit Name No function assigned. Fix to "0". TIOIS9 (TIO9 interrupt request status bit) TIOIS8 (TIO8 interrupt request status bit) No function assigned. Fix to "0". TIOIM9 (TIO9 interrupt request mask bit) TIOIM8 (TIO8 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIO89IMS TIO9udf Data bus b2 b6 TIO8udf TIOIS8 b3 b7 F/F TIOIM8 F/F TIOIS9 F/F TIOIM9 F/F (Level) 2-source inputs TIO8, 9 output interrupt request IRQ3
Figure 10.2.10 Block Diagram of TIO8,9 Output Interrupt Request
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b8
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TMS0,1 Interrupt Request Mask & Status Register (TMS01IMS)
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TMSIS1 TMSIS0
TMSIM1 TMSIM0
b 8, 9 10 11 12, 13 14 15 Bit Name No function assigned. Fix to "0". TMSIS1 (TMS1 interrupt request status bit) TMSIS0 (TMS0 interrupt request status bit) No function assigned. Fix to "0". TMSIM1 (TMS1 interrupt request mask bit) TMSIM0 (TMS0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0: Interrupt not requested 1: Interrupt requested 0 R 0 W Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TMS01IMS TMS1ovf Data bus b10 b14 TMS0ovf TMSIS0 b11 b15 F/F TMSIM0 F/F TMSIS1 F/F TMSIM1 F/F (Level) 2-source inputs TMS0, 1 output interrupt request IRQ7
Figure 10.2.11 Block Diagram of TMS0,1 Output Interrupt Request
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN0-2 Interrupt Request Mask & Status Register (TIN02IMS)
1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TINIS2 TINIS1 TINIS0
TINIM2 TINIM1 TINIM0
b 0 1 2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". TINIS2 (TIN2 interrupt request status bit) TINIS1 (TIN1 interrupt request status bit) TINIS0 (TIN0 interrupt request status bit) No function assigned. Fix to "0". TINIM2 (TIN2 interrupt request mask bit) TINIM1 (TIN1 interrupt request mask bit) TINIM0 (TIN0 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request 0 R 0 W 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIN02IMS TIN2edge Data bus b1 b5 TIN1edge TINIS1 b2 b6 TIN0edge b3 b7 TINIS0 F/F TINIM0 F/F F/F TINIM1 F/F TINIS2 F/F TINIM2 F/F (Level) 3-source inputs TIN0-2 input interrupt request IRQ9
Figure 10.2.12 Block Diagram of TIN0-2 Input Interrupt Request
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b8
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN3-6 Interrupt Request Mask & Status Register (TIN36IMS)
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TINIS6 TINIS5 TINIS4 TINIS3 TINIM6 TINIM5 TINIM4 TINIM3
b 8 9 10 11 12 13 14 15 Bit Name TINIS6 (TIN6 interrupt request status bit) TINIS5 (TIN5 interrupt request status bit) TINIS4 (TIN4 interrupt request status bit) TINIS3 (TIN3 interrupt request status bit) TINIM6 (TIN6 interrupt request mask bit) TINIM5 (TIN5 interrupt request mask bit) TINIM4 (TIN4 interrupt request mask bit) TINIM3 (TIN3 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIN36IMS TIN6edge Data bus b8 b12 TIN5edge TINIS5 b9 b13 TIN4edge b10 b14 TIN3edge b11 b15 TINIS3 F/F TINIM3 F/F TINIS4 F/F TINIM4 F/F F/F TINIM5 F/F TINIS6 F/F TINIM6 F/F (Level) 4-source inputs TIN3-6 input interrupt request IRQ12
Figure 10.2.13 Block Diagram of TIN3-6 Input Interrupt Request
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TIN7-11 Interrupt Request Status Register (TIN711IST)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TINIS11 TINIS10 TINIS9 TINIS8 TINIS7
b 0-2 3 4 5 6 7 Bit Name No function assigned. Fix to "0". TINIS11 (TIN11 interrupt request status bit) TINIS10 (TIN10 interrupt request status bit) TINIS9 (TIN9 interrupt request status bit) TINIS8 (TIN8 interrupt request status bit) TINIS7 (TIN7 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIN7-11 Interrupt Request Mask Register (TIN711IMA)
b8
0

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TINIM11 TINIM10 TINIM9 TINIM8 TINIM7
b 8-10 11 12 13 14 15 Bit Name No function assigned. Fix to "0". TINIM11 (TIN11 interrupt request mask bit) TINIM10 (TIN10 interrupt request mask bit) TINIM9 (TIN9 interrupt request mask bit) TINIM8 (TIN8 interrupt request mask bit) TINIM7 (TIN7 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
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TIN711IST TIN711IMA TIN11edge Data bus b3 b11 TIN10edge b4 b12 TIN9edge b5 b13 TIN8edge b6 b14 TIN7edge b7 b15 TINIS7 F/F TINIM7 F/F TINIS8 F/F TINIM8 F/F TINIS9 F/F TINIM9 F/F TINIS10 F/F TINIM4 F/F TINIS11 F/F TINIM11 F/F
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
5-source inputs TIN7-11 input interrupt request IRQ8
(Level)
Figure 10.2.14 Block Diagram of TIN7-11 Input Interrupt Request
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN12-19 Interrupt Request Status Register (TIN1219IST)
1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TINIS19 TINIS18 TINIS17 TINIS16 TINIS15 TINIS14 TINIS13 TINIS12
b 0 1 2 3 4 5 6 7 Bit Name TINIS19 (TIN19 interrupt request status bit) TINIS18 (TIN18 interrupt request status bit) TINIS17 (TIN17 interrupt request status bit) TINIS16 (TIN16 interrupt request status bit) TINIS15 (TIN15 interrupt request status bit) TINIS14 (TIN14 interrupt request status bit) TINIS13 (TIN13 interrupt request status bit) TINIS12 (TIN12 interrupt request status bit) Function 0: Interrupt not requested 1: Interrupt requested R W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIN12-19 Interrupt Request Mask Register (TIN1219IMA)
b8
0

9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TINIM19 TINIM18 TINIM17 TINIM16 TINIM15 TINIM14 TINIM13 TINIM12
b 8 9 10 11 12 13 14 15 Bit Name TINIM19 (TIN19 interrupt request mask bit) TINIM18 (TIN18 interrupt request mask bit) TINIM17 (TIN17 interrupt request mask bit) TINIM16 (TIN16 interrupt request mask bit) TINIM15 (TIN15 interrupt request mask bit) TINIM14 (TIN14 interrupt request mask bit) TINIM13 (TIN13 interrupt request mask bit) TINIM12 (TIN12 interrupt request mask bit) Function 0: Enable interrupt request 1: Mask (disable) interrupt request R R W W
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TIN1219IST TIN1219IMA TIN19edge Data bus b0 b8 TIN18edge TINIS18 b1 b9 TIN17edge b2 b10 TIN16edge b3 b11 TIN15edge b4 b12 TIN14edge TINIS14 b5 b13 TIN13edge TINIS13 b6 b14 TIN12edge b7 b15 TINIS12 F/F TINIM12 F/F F/F TINIM13 F/F F/F TINIM14 F/F TINIS15 F/F TINIM15 F/F TINIS16 F/F TINIM16 F/F TINIS17 F/F TINIM17 F/F F/F TINIM18 F/F TINIS19 F/F TINIM19 F/F
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
8-source inputs TIN12-19 input interrupt request IRQ10
(Level)
Figure 10.2.15 Block Diagram of TIN12-19 Input Interrupt Request
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN20-23 Interrupt Request Mask & Status Register (TIN2023IMS)
1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TINIS23 TINIS22 TINIS21 TINIS20 TINIM23 TINIM22 TINIM21 TINIM20
b 0 1 2 3 4 5 6 7 Bit Name TINIS23 (TIN23 interrupt request status bit) TINIS22 (TIN22 interrupt request status bit) TINIS21 (TIN21 interrupt request status bit) TINIS20 (TIN20 interrupt request status bit) TINIM23 (TIN23 interrupt request mask bit) TINIM22 (TIN22 interrupt request mask bit) TINIM21 (TIN21 interrupt request mask bit) TINIM20 (TIN20 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write.
TIN24, 25 Interrupt Request Mask Register (TIN2425IMA)
b0
0

1
0
2
0
3
0
4
0
5
0
6
TINIM24 0
b7
TINIM25 0
b 0-5 6 7 Bit Name No function assigned. Fix to "0". TINIM24 (TIN24 interrupt request mask bit) TINIM25 (TIN25 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
TIN24, 25 Interrupt Request Status Register (TIN2425IST)
b8
0

9
0
10
0
11
0
12
0
13
0
14
TINIS24 0
b15
TINIS25 0
b 8-13 14 15 Bit Name No function assigned. Fix to "0". TINIS24 (TIN24 interrupt request status bit) TINIS25 (TIN25 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
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b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN26, 27 Interrupt Request Mask Register (TIN2627IMA)
1
0
2
0
3
0
4
0
5
0
6
TINIM26 0
b7
TINIM27 0
b 0-5 6 7 Bit Name No function assigned. Fix to "0". TINIM26 (TIN26 interrupt request mask bit) TINIM27 (TIN27 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
TIN26, 27 Interrupt Request Status Register (TIN2627IST)
b8
0

9
0
10
0
11
0
12
0
13
0
14
TINIS26 0
b15
TINIS27 0
b 8-13 14 15 Bit Name No function assigned. Fix to "0". TINIS26 (TIN26 interrupt request status bit) TINIS27 (TIN27 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
TIN28, 29 Interrupt Request Mask Register (TIN2829IMA)
b0
0

1
0
2
0
3
0
4
0
5
0
6
TINIM28 0
b7
TINIM29 0
b 0-5 6 7 Bit Name No function assigned. Fix to "0". TINIM28 (TIN28 interrupt request mask bit) TINIM29 (TIN29 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request Function R 0 R W 0 W
TIN28, 29 Interrupt Request Status Register (TIN2829IST)
b8
0

9
0
10
0
11
0
12
0
13
0
14
TINIS28 0
b15
TINIS29 0
b 8-13 14 15 Bit Name No function assigned. Fix to "0". TINIS28 (TIN28 interrupt request status bit) TINIS29 (TIN29 interrupt request status bit) 0: Interrupt not requested 1: Interrupt requested Function R 0 W 0
R(Note 1)
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TIN2425IST TIN2425IMA TIN2627IST TIN2627IMA TIN2829IST TIN2829IMA TIN29edge Data bus b15 b7 TIN28edge TINIS28 b14 b6 TIN27edge b15 b7 TIN26edge b15 b6 TIN25edge b15 b7 TIN24edge b14 b6 TINIS24 F/F TINIM24 F/F TINIS25 F/F TINIM25 F/F TINIS26 F/F TINIM26 F/F TINIS27 F/F TINIM27 F/F F/F TINIM28 F/F TINIS29 F/F TINIM29 F/F
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
10-source inputs TIN20-29 input interrupt request IRQ11
(Level)
To the remaining 4-input sources in the next page
~
Figure 10.2.16 Block Diagram of TIN20-29 Input Interrupt Request (1/2)
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TIN2023IMS TIN23edge Data bus b0 b4 TIN22edge TINIS22 b1 b5 TIN21edge b2 b6 TIN20edge b3 b7 TINIS20 F/F TINIM20 F/F TINIS21 F/F TINIM21 F/F F/F TINIM22 F/F TINIS23 F/F TINIM23 F/F
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers
4-source inputs To the preceding page
Figure 10.2.17 Block Diagram of TIN20-29 Input Interrupt Request (2/2)
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b8
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

TIN30-33 Interrupt Request Mask & Status Register (TIN3033IMS)
9
0
10
0
11
0
12
0
13
0
14
0
b15
0
TINIS33 TINIS32 TINIS31 TINIS30 TINIM33 TINIM32 TINIM31 TINIM30
b 8 9 10 11 12 13 14 15 Bit Name TINIS33 (TIN33 interrupt request status bit) TINIS32 (TIN32 interrupt request status bit) TINIS31 (TIN31 interrupt request status bit) TINIS30 (TIN30 interrupt request status bit) TINIM33 (TIN33 interrupt request mask bit) TINIM32 (TIN32 interrupt request mask bit) TINIM31 (TIN31 interrupt request mask bit) TINIM30 (TIN30 interrupt request mask bit) 0: Enable interrupt request 1: Mask (disable) interrupt request R W Function 0: Interrupt not requested 1: Interrupt requested R W
R(Note 1)
Note 1: Only writing "0" is effective. Writing "1" has no effect; the bit retains the value it had before the write. Note: * TIN24-TIN29 do not have interrupt functions, so that their status and mask registers are nonexistent.
TIN3033IMS TIN33edge Data bus b8 b12 TIN32edge TINIS32 b9 b13 TIN31edge b10 b14 TIN30edge b11 b15 TINIS30 F/F TINIM30 F/F TINIS31 F/F TINIM31 F/F F/F TINIM32 F/F TINIS33 F/F TINIM33 F/F (Level) 4-source inputs TIN30-33 input interrupt request IRQ18
Figure 10.2.18 Block Diagram of TIN30-33 Input Interrupt Request
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TOU0 Interrupt Request Mask Register (TOU0IMA)
b0
0
MULTIJUNCTION TIMERS
10.2 Common Units of Multijunction Timers

1
0
2
0
3
0
4
0
5
0
6
0
b7
0
TOU0IM7 TOU0IM6 TOU0IM5 TOU0IM4 TOU0IM3 TOU0IM2 TOU0IM1 TOU0IM0
b 0 1 2 3 4 5 6 7 Bit Name TOU0IM7 (TOU0_7 interrupt request mask bit) TOU0IM6 (TOU0_6 interrupt request mask bit) TOU0IM5 (TOU0_5 interrupt request mask bit) TOU0IM4 (TOU0_4 interrupt request mask bit) TOU0IM3 (TOU0_3 interrupt request mask bit) TOU0IM2 (TOU0_2 interrupt request mask bit) TOU0IM1 (TOU0_1 interrupt request mask bit) TOU0IM0 (TOU0_0 interrupt request mask bit) Function 0: Enable interrupt request 1: Mask (disable) interrupt request R R W W
TOU0 Interrupt Request Status Register (TOU0IST)
b8
TOU0IS7 0

9
TOU0IS6 0
10
TOU0IS5 0
11
TOU0IS4 0
12
TOU0IS3 0
13
TOU0IS2 0
14
TOU0IS1 0
b15
TOU0IS0 0

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