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XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
AUG 2008 REV. V1.0.0
FEATURES * Performs clock and data recovery for selectable
data of 622.08 Mbps (STS-12/STM-4) or 155.52 Mbps (STS-3/STM-1) NRZ data
APPLICATIONS * SONET/SDH-based Transmission Systems * Add/Drop Multiplexers * Cross Connect Equipment * ATM and Multi-Service Switches, Routers and
Switch/Routers
* Meets Telcordia, ANSI and ITU-T G.783 and G.825
SDH jitter requirements including T1.105.03 - 2002 SONET Jitter Tolerance specification, and GR-253 CORE, GR-253 ILR SONET Jitter specifications.
* Lock output pin monitors data run length and
frequency drift from reference clock
* Data is resampled at the output * Active High Signal Detect (SIGD) LVPECL input * Low jitter, high-speed outputs support LVPECL and
low-power LVDS termination
* DSLAMS * SONET/SDH Test Equipment * DWDM Termination Equipment GENERAL DESCRIPTION
The XRT91L33 is a fully integrated multirate Clock and Data Recovery (CDR) device for SONET/SDH 622.08 Mbps STS-12/STM-4 or 155.52 Mbps STS-3/ STM-1 applications. The device provides Clock and Data Recovery (CDR) function by synchronizing its on-chip Voltage Controlled Oscillator (VCO) to the incoming serial scrambled non-return to zero (NRZ) data stream. Figure 1 shows the block diagram of the XRT91L33.
* 19.44 MHz reference frequency LVTTL input * Low power: 215 mW typical * 3.3V power supply * 20-pin TSSOP package * Requires one external capacitor * PLL bypass operation facilitates board debug
process
* ESD greater than 2kV on all pins
FIGURE 1. BLOCK DIAGRAM OF XRT91L33
STS12_MODE REFCK
19.44 MHz
CAP+ 1u F CAP+ TEST
RX LOOP FILTER
PLL
Differential Receiver
RXDIP RXDIN
External 100R termination Internal biasing RXDATAIN
RECVDDATAOUT
LVDS/LVPECL Output Drivers
STS-12/3 or STM-4/1 Clock and Data Recovery
CDR
0
RXDOP RXDON
1
RECVDCLKOUT
RXCLKOP RXCLKON
LOCK LCKTOREFN SIGD
MUTE RXDO
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT CLOCK AND DATA RECOVERY OVERVIEW The clock and data recovery (CDR) unit accepts high speed NRZ serial data from the Differential receiver and generates a clock with a frequency equal to that of the incoming data. The CDR block uses a reference clock to train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500 ppm, the clock recovery PLL will switch and lock back onto the local reference clock and declare a Loss of Lock. Whenever a Loss of Lock or a Loss of Signal event occurs, the CDR will continue to supply a recovered clock (based on the local reference) to the framer/mapper device. An LOS condition occurs when either SIGD or LCKTOREFN is low. In this case, the receive serial data output is forced to a logic zero state for the entire duration of the LOS condition. This acts as a receive data mute upon LOS function to prevent random noise from being misinterpreted as valid incoming data. When SIGD becomes active again, the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source and LOS is no longer declared, the clock recovery PLL will switch and lock back onto the incoming receive serial data stream.
REV. V1.0.0
FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW)
1 2 3 4 5 6 7 8 9 10
VDDA RXDIP RXDIN VSSA LOCK STS12_MODE REFCK LCKTOREFN VSS VDD
VDDA VSSA CAP+ CAPTEST SIGD RXDOP RXDON RXCLKOP RXCLKON
20 19 18 17 16 15 14 13 12 11
TABLE 1: ORDERING INFORMATION
PART NUMBER XRT91L33IG XRT91L33IG-F PACKAGE 20-pin TSSOP Package 20-Pin TSSOP Lead-Free Package OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C
2
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FEATURES......................................................................................................................... 1 APPLICATIONS ................................................................................................................. 1 GENERAL DESCRIPTION................................................................................................. 1
FIGURE 1. BLOCK DIAGRAM OF XRT91L33 ...................................................................................................................................... 1
CLOCK AND DATA RECOVERY OVERVIEW ....................................................................................................... 2
FIGURE 2. 20 PIN TSSOP OF XRT91L33 (TOP VIEW) .................................................................................................................... 2 TABLE 1: ORDERING INFORMATION................................................................................................................................................... 2
1.0 PIN DESCRIPTIONS .............................................................................................................................. 4
TABLE 2: PIN DESCRIPTION TABLE ................................................................................................................................................... 4
..................................................................................................................................................................... 5 2.0 FUNCTIONAL DESCRIPTION ............................................................................................................... 6
2.1 2.2 2.3 2.4 2.5 REFERENCE CLOCK INPUT ........................................................................................................................... RECEIVE CLOCK AND DATA RECOVERY .................................................................................................... EXTERNAL RECEIVE LOOP FILTER CAPACITOR ....................................................................................... STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ........................................................................... SIGNAL DETECTION ....................................................................................................................................... 6 6 6 6 6
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION ............................................................ 7
2.6 LOCK DETECTION ........................................................................................................................................... 7 2.7 PLL TEST OPERATION ................................................................................................................................... 7
TABLE 3: SIGNAL DETECT AND PLL TEST OPERATION CONTROL .................................................................................................... 8
3.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 9
3.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 9
TABLE 4: ABSOLUTE MAXIMUM RATINGS........................................................................................................................................... 9
3.2 OPERATING CONDITIONS .............................................................................................................................. 9
TABLE 5: RECOMMENDED OPERATING CONDITIONS .......................................................................................................................... 9
3.3 LVPECL SINGLE ENDED INPUT AND OUTPUT DC CHARACTERISTICS .................................................. 9
TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS................................................................................................................. 9
3.4 LVPECL DIFFERENTIAL INPUT AND OUTPUT DC CHARACTERISTICS ................................................. 10
TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUPUTS .................................................................................................................. 10 FIGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA ................................................... 10 TABLE 8: LVDS OUTPUTS............................................................................................................................................................. 10 TABLE 9: LVTTL INPUTS................................................................................................................................................................ 11
3.5 AC CHARACTERISTICS ................................................................................................................................ 11
TABLE 10: PERFORMANCE SPECIFICATIONS .................................................................................................................................... 11
4.0 JITTER PERFORMANCE .................................................................................................................... 12
4.1 SONET JITTER REQUIREMENTS ................................................................................................................. 12
4.1.1 RX JITTER TOLERANCE: .......................................................................................................................................... 12 FIGURE 5. GR-253/G.783 JITTER TOLERANCE MASK ..................................................................................................................... 12 FIGURE 6. XRT91L33 JITTER TOLERANCE AT 155 MBPS OC3/STM-1.......................................................................................... 13 FIGURE 7. XRT91L33 JITTER TOLERANCE AT 622 MBPS OC12/STM-4........................................................................................ 13 4.1.2 JITTER GENERATION................................................................................................................................................ 13
5.0 HIGH-SPEED OUTPUTS ..................................................................................................................... 14
FIGURE 8. HIGH SPEED OUTPUTS, LVDS TERMINATION.................................................................................................................. 14 FIGURE 9. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS ............................................................................................... 14
6.0 RESAMPLED DATA AND CLOCK OUTPUTS .................................................................................. 15
FIGURE 10. OUTPUT DATA AND CLOCK AFTER RESAMPLING............................................................................................................ 15 TABLE 11: OUTPUT TIMING ............................................................................................................................................................ 15
7.0 PACKAGE DIMENSIONS .................................................................................................................... 16
TABLE 12: REVISION HISTORY........................................................................................................................................................ 16
3
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT 1.0 PIN DESCRIPTIONS TABLE 2: PIN DESCRIPTION TABLE
NAME VDDA RXDIP LEVEL PWR LVDS/PECL TYPE PWR I PIN 1 2 3.3V Power supply Positive side of receive data input. The high-speed output clock (RXCLKOP/N) is recovered from this high-speed differential inupt data. Negative side of receive data input. The high-speed output clock (RXCLKOP/N) is recovered from this high-speed differential input data. Ground pin DESCRIPTION
REV. V1.0.0
RXDIN
LVDS/PECL
I
3
VSSA
PWR
PWR
4
LOCK
LVPECL
O
5
Active HIGH to indicate that the PLL is locked to serial data input and valid clock and data are present at the serial outputs (RXDOP/N and RXCLKOP/N). The LOCK will go inactive under the following conditions:
* If SIGD is set LOW * If LCKTOREFN is set LOW * If the VCO has drifted away from the local reference
clock, REFCK, by more than +/- 500 ppm
STS12_MODE REFCK LVTTL LVTTL I I 6 7 STS-12 or STS-3 mode selection. Set HIGH to select the STS-12 operation. Set LOW for STS-3 operation Local 19.44 MHz reference clock input for the CDR. REFCK is used for the PLL phase adjustment during power up. It also serves as a stable clock source in the absence of serial input data. Lock to REFCK input. When set LOW, this pin causes the output clock, RXCLKOP/N to be held within +/- 500ppm of the input reference clock REFCL and forces the RXDOP/N to a low state. Ground pin 3.3V power supply High-speed clock output, negative. This clock is recovered from the receive data input (RXDIP/N) and supports either LVDS or LVPECL termination High-speed clock output, positive This clock is recovered from the receive data input (RXDIP/N) and supports either LVDS or LVPECL. termination High-speed output, negative This is the retimed version of the recovered data stream from RXDIP/N and can be in either LVDS or LVPECL termination High-speed output, positive. This is the retimed version of the recovered data stream from RXDIP/N and can be in either LVDS or LVPECL termination
LCKTOREFN
LVTTL
I
8
VSS VDD RXCLKON
PWR PWR LVDS/ LVPECL LVDS/ LVPECL LVDS/ LVPECL LVDS/ LVPECL
PWR PWR O
9 10 11
RXCLKOP
O
12
RXDON
O
13
RXDOP
O
14
4
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
LEVEL LVPECL TYPE I PIN 15 DESCRIPTION Signal detect. SIGD should be connected to the SIGD output on the optical module. SIGD is active HIGH. When SIGD is set HIGH, it means there is sufficient optical power. When SIGD is LOW, this indicates an LOS condition, the RXCLKOP/N output signal will be held to within +/- 500 ppm of the REFCK input. Additionally, the RXDOP/N will be held in the LOW state. Used for production testing. Set to VSS for normal operation. Negative side of the external loop filter. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0 F +/- 10 % Positive side of the external loop filter. The loop filter capacitor should be connected to these pins. The capacitor value should be 1.0 F +/- 10 %. Ground pin 3.3V power supply
NAME SIGD
TEST CAP-
LVTTL Analog
I I
16 17
CAP+
Analog
I
18
VSSA VDDA
PWR PWR
PWR PWR
19 20
5
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT 2.0 FUNCTIONAL DESCRIPTION The XRT91L33 CDR is designed to operate with a SONET Framer/ASIC device and provide a high-speed serial clock and data recovery interface to optical networks. The CDR receives a differential NRZ serial bit stream running at STS-12/STM-4 or STS-3/STM-1 and generates recovered serial clock and data via differential LVDS/LVPECL drivers.
REV. V1.0.0
2.1
Reference Clock Input
The XRT91L33 accepts a 19.44 MHz LVTTL clock input at REFCK. The REFCK should be generated from a source that has a frequency accuracy better than 100ppm in order for the CDR Loss of Lock detector to have the necessary accuracy required for SONET systems.
2.2
Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high-speed NRZ serial data from the Differential receiver and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the reference clock from REFCK to train and monitor its clock recovery PLL. Upon startup, the PLL locks to the local reference clock. Once this is achieved, the PLL then attempts to lock onto the incoming receive serial data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by more than approximately 500ppm, the clock recovery PLL will switch to the local reference clock, declare a Loss of Lock and output a LOW level signal on the LOCK output pin. Whenever a Loss of Lock (LOL) or a Loss of Signal (LOS) event occurs, the CDR will continue to supply a receive clock (based on the local reference).
2.3
External Receive Loop Filter Capacitor
For STS12/STM4 and STS3/STM1 operation, the XRT91L33 uses a 1.0uF (or greater) external loop filter capacitor to achieve the required receiver jitter performance. It must be well isolated to prohibit noise entering the CDR block and should be placed as close to the pins as possible. The non-polarized capacitor should be of 10% tolerance. Use type X7R or X5R capacitors for improved stability over temperature.
2.4
STS-12/STM-4 and STS-3/STM-1 Mode of Operation
The VCO output signal is fed into a programmable frequency divider allowing to properly set the PLL operating frequency corresponding to the desired data rate. For 622.08 Mbps signal STS12_MODE is set HIGH and for 155.52 Mbps, STS12_MODE is set LOW.
2.5
Signal Detection
XRT91L33 has two control pins that are used to indicate an LOS condition (Loss Of Signal). The SIGD pin is a LVPECL input and the LCKTOREFN pin is a LVTTL input. They are internally connected as shown in Figure 3. If either of these two inputs goes LOW and TEST is LOW, XRT91L33 will enter a Loss of Signal (LOS) state, and will mute the RXDOP/N. During the LOS state, XRT91L33 will also maintain RXCLKOP/N within 500ppm of the input reference clock, REFCK. Most optical modules have an SIGD output. This SIGD output indicates that there is sufficient optical power and is typically active HIGH. If the SIGD output on the optical module is LVPECL, it should be connected directly to the SIGD input of XRT91L33, and the LCKTOREFN input should be tied HIGH. If the SIGD output is LVTTL, it should be connected directly to the LCKTOREFN input and the SIGD input should be tied HIGH. The SIGD and LCKTOREFN inputs also can be used for other applications when it is required to hold RXCLKOP/N output within 500ppm of the input reference clock and mute the serial data output lines.
6
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION
2 2
RXDIP/N
RXDOP/N
PLL Clock (Internal)
0
2 RXCLKOP/N
REFCK
1
STS12_MODE TEST LOS (Internal)
LCKTOREFN SIGD
2.6
Lock Detection
XRT91L33 features a PLL lock detection circuit. The lock detect (LOCK) output goes HIGH to indicate that the PLL is locked to the serial data input and valid data and clock are present at the high-speed differential output. The LOCK output will go LOW if either the LOCKTOREFN or the SIGD input is forced LOW. Additionally, LOCK will also go low if the incoming data frequency is more than +/-500ppm away from the reference clock frequency (REFCK x 32 in OC12 mode, REFCLK x 8 in OC3 mode). When LOCK output is driven LOW, the VCO is forced to lock to REFCK and then released to lock on the incoming data. If the incoming data frequency remains outside the +/-500ppm window, the training mode is repeated. Debounce logic stabilizes the LOCK output pin to stay LOW for incoming frequencies well beyond the +/-500ppm window.
2.7
PLL Test Operation
The TEST pin is intended for use in production test and should be set at logic LOW in normal operation. If both TEST and STS12_MODE pins are set to logic HIGH, XRT91L33 will bypass the PLL and present an inverted version of the REFCK to the clock output RXCLKOP/N. REFCK's rising edge is used to capture the input data and transmit data to RXDOP/N. This bypass test operation can be used to facilitate board level debugging process.
7
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT . TABLE 3: SIGNAL DETECT AND PLL TEST OPERATION CONTROL
STS12_MODE TEST LCKTOREFN SIGD RXDO RXCLKO
REV. V1.0.0
1 1 1 1 1 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
1 1 0 0 X 1 1 0 0 X
1 0 1 0 X 1 0 1 0 X
RXDI Muted Muted Muted RXDI RXDI Muted Muted Muted Not allowed
PLL clock PLL clock PLL clock PLL clock REFCK PLL clock PLL clock PLL clock PLL clock Not allowed
8
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
3.0 ELECTRICAL CHARACTERISTICS 3.1 Absolute Maximum RATINGS TABLE 4: ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD PARAMETER Power supply voltage, referenced to GND DC input voltage (LVPECL, LVTTL) Output current (LVDS or LVPECL) TS VESD Storage Temperature Electrostatic discharge voltage, human body model MINIMUM MAXIMUM UNIT -0.5 -0.5 -50 -65 -2000 4.0 VDD+0.5 +50 150 2000 V V mA C V
3.2
Operating Conditions TABLE 5: RECOMMENDED OPERATING CONDITIONS
SYMBOL VDD Temp IDD PD
PARAMETER Power supply voltage Operating Temperature under bias 1 Power supply current (outputs unterminated) Power dissipation (outputs unterminated)
MIN. 3.135 -40
TYP 3.3
MAX. 3.465 85
UNITS V C mA mW
65 215
80 277
1. Lower limit of specification is ambient temperature, and upper limit is case temperature. 3.3 LVPECL Single Ended Input and Output DC characteristics TABLE 6: LVPECL SINGLE ENDED INPUTS AND OUTPUTS
SYMBOL VIH VIL IIH IIL VOL VOH PARAMETER Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Output LOW voltage Output HIGH voltage MIN. VDD-1.125 VDD-2.0 -0.5 -0.5 VDD-2.0 VDD-1.25 TYP. MAX. VDD-0.5 VDD-1.5 10 10 VDD-1.8 VDD-0.67 UNITS V V A A V V CONDITIONS Guaranteed input HIGH voltage Guaranteed input LOW voltage VIN = VDD - 0.5V VIN=VDD-2.0V 50 to (VDD-2.0V) 50 to (VDD-2.0V)
9
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT 3.4 LVPECL Differential Input and Output DC characteristics TABLE 7: LVPECL DIFFERENTIAL INPUTS AND OUPUTS
SYMBOL VIH VIL IIH IIL VIDIFF VOCM VODIFF PARAMETER Input HIGH voltage Input LOW voltage Input HIGH current Input LOW current Input PECL Differential Voltage, peakto-peak swing (see Figure 4) Output Common-Mode Voltage Output LVPECL Differential Voltage, peak-to-peak swing (see Figure 4) MIN. VDD-1.75 VDD-2.0 -0.5 -0.5 250 TYP. MAX. VDD-0.4 VDD-0.7 10 10 UNITS V V A A mV 50 to (VDD-2.0V) 50 to (VDD-2.0V) CONDITIONS Guaranteed input HIGH voltage Guaranteed input LOW voltage VIN DIFF =0.5V VIN DIFF =0.5V
REV. V1.0.0
0.8 800
1.35
1.7 1700
V mV
FIGURE 4. DIFFERENTIAL VOLTAGE SWING DEFINITIONS (INPUT OR OUTPUT) FOR CLOCK AND DATA
V(+) V SING LE
V(-)
V DIFF = V(+)-V(-) 2 x V SINGLE 0V
TABLE 8: LVDS OUTPUTS
SYMBOL VOCM PARAMETER Output common-mode voltage MIN. 1.0 TYP. 1.35 MAX. 1.7 UNITS V CONDITIONS 100 between RXDOP/N and RXCLKP/N 100 between RXDOP/N and RXCLKP/N
VODIFF
Output LVDS Differential Voltage, peak-to-peak Swing (see Figure 4)
700
1700
mV
10
XRT91L33
REV. V1.0.0
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
TABLE 9: LVTTL INPUTS
SYMBOL VIH VIL IIH IIL PARAMETER Input HIGH voltage Input LOW voltage Input HIGH current MIN. 2.0 0 -50 TYP. MAX. VDD 0.8 50 UNITS V V A A VIN = 2.75 V, VDD = Maximum VIN = 0.5 V, VDD = Maximum CONDITIONS
Input LOW current
-50
50
3.5
AC Characteristics TABLE 10: PERFORMANCE SPECIFICATIONS
Test Condition: VDD = 3.3V + 5% unless otherwise specified SYMBOL f fTOL fTREF_CLK CLKOUTDC tLOCK PARAMETER VCO center frequency CDR's reference clock frequency OC-12/STS-12 capture range Clock output duty cycle OC-12/STS-12 acquisition lock time -250 -500 45 MIN TYP 622.08 250 500 55 16 MAX UNITS MHz ppm ppm % UI s with respect to the fixed reference frequency 20% minimum transition density Valid REFCK and device already powered up 10% to 90%, with 100 and 5 pF capacitive equivalent load CONDITIONS
tLOCK_R, tLOCK_F JGEN_CLCK JTOL
LOCK output rise and fall time
500
ps
RXCLKOP/N iitter generation OC-12/STS-12 jitter tolerance 0.40
0.005 0.5
0.01
UIrms UI Sinusoidal input jitter of RXDIP/N from 250 KHz to 5MHz
11
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT 4.0 JITTER PERFORMANCE 4.1 SONET Jitter Requirements
REV. V1.0.0
SONET receive equipment jitter requirements are specified jitter tolerance and jitter transfer. The definitions of each of these types of jitter are given below. 4.1.1 Rx Jitter Tolerance:
OC-3/STM-1, and OC-12/STM-4 category II SONET interfaces should tolerate, the input jitter applied according to the mask of Figure 6, with the corresponding specified parameters. Jitter measurements are done with standard SONET/SDH testers such as Acterna ANT20 as well as Agilent Omniber testers.
FIGURE 5. GR-253/G.783 JITTER TOLERANCE MASK
A3 slope= -20dB/decade Input Jitter Amplitude (UIpp) A2 slope= -20dB/decade
A1
f0
f1
f2
f3
f4
Jitter Frequency (Hz)
OC-N
STM-X LEVEL STM0 STM1
F0 (HZ) 10 10 10
F1 (HZ) 30 30 30
F2 (HZ) 300 300 300
F3 (HZ) 2K 6.5K 25K
F4 (HZ) 20K 65K 250K
A1 (UIPP) 0.15 0.15 0.15
A2 (UIPP) 1.5 1.5 1.5
A3 (UIPP) 15 15 15
OC1/STS1 1 OC3/STS3 3
OC12/STS12 STM4 12
12
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT FIGURE 6. XRT91L33 JITTER TOLERANCE AT 155 MBPS OC3/STM-1
XRT 91L33 Jitter Tolerance OC3
100.00 Jitter (UI) 10.00
1.00
0.10 0.01 0.10 1.00 10.00 100.00 Frequency (KHz) 1,000.00 10,000.00
Jitter Mask
FIGURE 7. XRT91L33 JITTER TOLERANCE AT 622 MBPS OC12/STM-4
XRT 91L33 Jitter Tolerance OC12
1,000.00 Jitter (UI) 100.00
10.00
1.00
0.10 0.01 0.10 1.00 10.00 100.00 Frequency (KHz) 1,000.00 10,000.00
Jitter Mask
4.1.2
Jitter Generation
Maximum jitter generation is less than 0.01 UI rms within the SONET/SDH band, when rms jitter of less than 14 ps (OC-12) or 56 ps (OC-3) is presented to the serial data inputs.
13
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT 5.0 HIGH-SPEED OUTPUTS The high-speed output buffers, RXDOP/N and RXCLKOP/N can be terminated as either LVDS or LVPECL outputs. In LVDS mode, the transmission lines must be routed with 100 differential impedance and terminated at the receive end with a line-to-line 100 resistor (See Figure 8). FIGURE 8. HIGH SPEED OUTPUTS, LVDS TERMINATION
XRT91L33 100 Ohm Receiver
REV. V1.0.0
For LVPECL conections, the transmission line must be terminated with 50 pull-down resistors near the receiving end or an equivalent circuit. (See Figure 9) FIGURE 9. HIGH-SPEED OUTPUTS, LVPECL TERMINATION OPTIONS
V DD - 2.0V 50 Ohm
XRT91L33
Receiver
V DD - 2.0V V DD
82 Ohm Creates 2V bias when V DD = 3.3V
XRT91L33
168 Ohm
50 Ohm
Receiver
V DD 82 Ohm 124 Ohm
V SS 168 Ohm
124 Ohm
(Unbiased and No internal termination)
V SS
XRT91L33
168 Ohm
Receiver
168 Ohm
(Baised with internal termination)
14
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
6.0 RESAMPLED DATA AND CLOCK OUTPUTS It is recommended that the retimed data output be captured with the rising edge of the clock output as shown in Figure 10. Data valid time is longer for OC-3/STS-3 mode of operation than that of OC-12/STS-12. Data valid time before the output clock's rising edge is the available setup time (tSU), while the data valid time after the clock's rising edge is the available hold time (tH). FIGURE 10. OUTPUT DATA AND CLOCK AFTER RESAMPLING
RXDOP/N
RXCLKOP/N
tH tSU
TABLE 11: OUTPUT TIMING
SYMBOL tSU PARAMETER Available setup time MINIMUM 450 2.0 tH Available hold time 650 3.0 MAXIMUM UNIT ps ns ps ns CONDITION STS-12 operation (622.08 MHz) STS-3 operation (155.52 MHz) STS-12 operation (622.08 MHz) STS-3 operation (155.52 MHz)
15
XRT91L33
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
REV. V1.0.0
7.0 PACKAGE DIMENSIONS 20 pin Surface mount TSSOP
TABLE 12: REVISION HISTORY
REVISION # V1.0.0 DATE Aug 2008 Product Release Datasheet DESCRIPTION
16

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