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HD74LVC574A Octal D-type Flip Flops with 3-state Outputs REJ03D0361-0400Z (Previous ADE-205-117B (Z)) Rev.4.00 Jul. 29, 2004 Description The HD74LVC574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low voltage and high-speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features * * * * * * * VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 24 mA (@VCC = 3.0 V to 5.5 V) Ordering Information Package Type SOP-20 pin (JEITA) TSSOP-20 pin Package Code FP-20DAV TTP-20DAV Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel) Part Name HD74LVC574AFPEL HD74LVC574ATELL Note: Please consult the sales office for the above package availability. Function Table Inputs OC L L L H H: L: X: Z: : Q0 : CK L X D H L X X Output Q H L Q0 Z High level Low level Immaterial High impedance Low to high transition Level of Q before the indicated steady input conditions were established. Rev.4.00 Jul. 29, 2004 page 1 of 7 HD74LVC574A Pin Arrangement OC 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 DQ CK DQ CK DQ CK DQ CK DQ CK DQ CK DQ CK DQ CK 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 CK (Top view) Absolute Maximum Ratings Item Supply voltage Input diode current Input voltage Output diode current Output voltage Output current VCC, GND current / pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC or IGND Tstg Ratings -0.5 to 6.0 -50 -0.5 to 6.0 -50 50 -0.5 to VCC +0.5 -0.5 to 6.0 50 100 -65 to +150 Unit V mA V mA V mA mA C Conditions VI = -0.5 V VO = -0.5 V VO = VCC+0.5 V Output "H" or "L" Output "Z" or VCC:OFF Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Rev.4.00 Jul. 29, 2004 page 2 of 7 HD74LVC574A Recommended Operating Conditions Item Supply voltage Input / output voltage Symbol VCC VI VO Ta IOH IOL Input rise / fall time *1 tr, tf Ratings 1.5 to 5.5 2.0 to 5.5 0 to 5.5 0 to VCC 0 to 5.5 -40 to 85 -12 -24*2 12 24*2 10 Unit V V V C mA mA ns/V Conditions Data hold At operation OC, CK, D Output "H" or "L" Output "Z" or VCC:OFF VCC = 2.7 V VCC = 3.0 V to 5.5 V VCC = 2.7 V VCC = 3.0 V to 5.5 V Operating temperature Output current Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. 2. Duty cycle 50% Electrical Characteristics Ta = -40 to 85C Item Input voltage Symbol VIH VIL Output voltage VOH VCC (V) 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 5.5 2.7 3.0 3.0 4.5 2.7 to 5.5 2.7 3.0 4.5 0 to 5.5 2.7 to 5.5 0 2.7 to 3.6 2.7 to 5.5 3.0 to 3.6 Min 2.0 VCCx0.7 -- -- VCC-0.2 2.2 2.4 2.2 3.8 -- -- -- -- -- -- -- -- -- -- Max -- -- 0.8 VCCx0.3 -- -- -- -- -- 0.2 0.4 0.55 0.55 5.0 5.0 20 10 10 500 Unit V V V IOH = -100 A IOH = -12 mA IOH = -24 mA V IOL = 100 A IOL = 12 mA IOL = 24 mA VIN = 5.5 V or GND VIN = VCC, GND VOUT = 5.5 V or GND VIN / VOUT = 5.5 V VIN / VOUT = 3.6 to 5.5 V VIN = VCC or GND VIN = one input at(VCC-0.6)V, other inputs at VCC or GND Test Conditions VOL Input current Off state output current Output leak current Quiescent supply current IIN IOZ IOFF ICC ICC A A A A A Rev.4.00 Jul. 29, 2004 page 3 of 7 HD74LVC574A Switching Characteristics Ta = -40 to 85C Item Maximum clock frequency Symbol fmax VCC (V) 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 3.30.3 5.00.5 2.7 2.7 Min 80.0 100.0 125.0 -- 1.5 -- -- 1.5 -- -- 1.5 -- 2.0 2.0 2.0 1.5 1.5 1.5 3.3 3.3 3.3 -- -- -- -- -- Typ -- 150.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 3.0 15.0 Max -- -- -- 9.5 8.5 7.0 9.5 8.5 7.0 8.5 7.5 6.5 -- -- -- -- -- -- -- -- -- -- 1.0 1.0 -- -- Unit MHz From (Input) To (Output) Propagation delay time tPLH tPHL tZH tZL tHZ tLZ tsu ns CK Q Output enable time ns OC Q Output disable time ns OC Q Setup time ns Hold time th ns Pulse width tw ns Between output pins skew *1 Input capacitance Output capacitance Note: tOSLH tOSHL CIN CO ns pF pF 1. This parameter is characterized but not tested. tosLH = | tPLHm - tPLHn|, tosHL = | tPHLm - tPHLn| Rev.4.00 Jul. 29, 2004 page 4 of 7 HD74LVC574A Test Circuit VCC VCC Output OC Input 1Q to 8Q CL = 50 pF 1D to 8D Symbol t PLH / t PHL CK t su / t h / t w t ZH/ t HZ t ZL / t LZ S1 Vcc=2.7V, 3.30.3V Vcc=5.00.5V 500 S1 450 50 Scope OPEN *1 See under table See Function Table GND Pulse generator Zout = 50 Input Pulse generator Zout = 50 OPEN GND 6V OPEN GND 2xVcc Note: 1. CL includes probe and jig capacitance. Waveforms - 1 tr Input CK 10 % tr Input D 90 % 10 % t PLH Output Q Vref 90 % 90 % Vref 10 % tf 90 % 10 % t PHL Vref VOL tf VIH Vref GND VIH GND VOH Rev.4.00 Jul. 29, 2004 page 5 of 7 HD74LVC574A Waveforms - 2 tr Input CK 10 % tw ts Input D Vref th VIH Vref GND 90 % 90 % Vref Vref 10 % tw tf VIH Vref GND Waveforms - 3 tf 90 % Vref 10 % t ZL Waveform - A t ZH Waveform - B Vref TEST VIH Vref VOH1 VOL1 Vref t HZ VOH - 0.3 V tr 90 % Vref 10 % t LZ VIH GND V OH1 VOL + 0.3 V VOL VOH V OL1 Vcc=2.7V, 3.30.3V Vcc=5.00.5V Input OC 2.7 V 1.5 V 3V GND Vcc 50%Vcc Vcc GND Notes: 1. tr = 2.5 ns, tf = 2.5 ns 2. Input waveform : PRR = 10 MHz, duty cycle 50% 3. Waveform - A shows input conditions such that the output is "L" level when enable by the output control. 4. Waveform - B shows input conditions such that the output is "H" level when enable by the output control. Rev.4.00 Jul. 29, 2004 page 6 of 7 HD74LVC574A Package Dimensions As of January, 2002 12.6 13 Max 20 Unit: mm 11 1 10 5.5 0.80 Max 2.20 Max *0.20 0.05 0.20 7.80 + 0.30 - 1.15 1.27 *0.40 0.06 0.10 0.10 0 - 8 0.70 0.20 0.15 0.12 M *Pd plating Package Code JEDEC JEITA Mass (reference value) FP-20DAV -- Conforms 0.31 g As of January, 2002 Unit: mm 6.50 6.80 Max 20 11 1 10 0.65 1.0 6.40 0.20 0.65 Max *0.20 0.05 0.13 M 4.40 *0.15 0.05 1.10 Max 0.10 0.07 +0.03 -0.04 0 - 8 0.50 0.10 *Pd plating Package Code JEDEC JEITA Mass (reference value) TTP-20DAV -- -- 0.07 g Rev.4.00 Jul. 29, 2004 page 7 of 7 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. 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The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. 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