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Ordering number : ENA1400
LC872G08A LC872G06A LC872G04A
Overview
CMOS IC 8K/6K/4K-byte ROM and 256-byte RAM integrated
8-bit 1-chip Microcontroller
The SANYO LC872G08A/06A/04A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 8K/6K/4K-byte ROM, 256-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), two 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-bit/8-bit 8-channel AD converter, a system clock frequency divider, an internal reset and a 18-source 10-vector interrupt feature.
Features
ROM * 8192 x 8 bits (LC872G08A) * 6144 x 8 bits (LC872G06A) * 4096 x 8 bits (LC872G04A) RAM * 256 x 9 bits (LC872G08A/06A/04A)
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver. 0.40
12109HKIM 20081216-S00009 No.A1400-1/27
LC872G08A/06A/04A
Minimum Bus Cycle * 83.3ns (12MHz at VDD=2.7V to 5.5V) * 100ns (10MHz at VDD=2.2V to 5.5V) * 250ns (4MHz at VDD=1.8V to 5.5V) Note: The bus cycle time here refers to the ROM read speed. Minimum Instruction Cycle Time * 250ns (12MHz at VDD=2.7V to 5.5V) * 300ns (10MHz at VDD=2.2V to 5.5V) * 750ns (4MHz at VDD=1.8V to 5.5V) Ports * Normal withstand voltage I/O ports Ports I/O direction can be designated in 1-bit units Ports I/O direction can be designated in 4-bit units * Dedicated oscillator ports/input ports * Reset pin * Power pins
11 (P1n, P20, P21, P70) 8 (P0n) 2 (CF1/XT1, CF2/XT2) 1 (RES) 2 (VSS1, VDD1)
Timers * Timer 0: 16-bit timer/counter with a capture register. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) * Timer 1: 16-bit timer/counter that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/ counter with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM) * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts are programmable in 5 different time schemes High-Speed Clock Counter * Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). * Can generate output real time. SIO * SIO0: 8-bit Synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3tCYC) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A1400-2/27
LC872G08A/06A/04A
UART * Full duplex * 7/8/9 bit data bits selectable * 1 stop bit (2 bits in continuous data transmission) * Built-in baudrate generator AD Converter: 12 bits/8 bits x 8 channels * 12 bits/8 bits AD converter resolution selectable Remote Control Receiver Circuit (sharing pins with P15, SCK1, INT3, and T0IN) * Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC) Clock Output Function * Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. * Can generate the source clock for the subclock Watchdog Timer * External RC watchdog timer * Interrupt and reset signals selectable Interrupts * 18 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/INT4 INT3/base timer T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC/T6/T7 Port 0 Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 128levels (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time)
No.A1400-3/27
LC872G08A/06A/04A
Oscillation Circuits * Internal oscillation circuits Low-speed RC oscillation circuit : For system clock (100kHz) Medium-speed RC oscillation circuit : For system clock (1MHz) Multifrequency RC oscillation circuit : For system clock (8MHz) * External oscillation circuits Hi-speed CF oscillation circuit: For system clock, with internal Rf Low speed crystal oscillation circuit: For low-speed system clock, with internal Rf 1) The CF and crystal oscillation circuits share the same pins. The active circuit is selected under program control. 2) Both the CF and crystal oscillator circuits stop operation on a system reset. When the reset is released, only the CF oscillation circuit resumes operation. System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). Internal Reset Function * Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 8 levels (1.67V, 1.97V, 2.07V, 2.37V, 2.57V, 2.87V, 3.86V, and 4.35V) through option configuration. * Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use/disuse of the LVD function and the low voltage threshold level (7 levels: 1.91V, 2.01V, 2.31V, 2.51V, 2.81V, 3.79V, 4.28V). Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the reset pin to the lower level. (2) System resetting by watchdog timer or low-voltage detection (3) Having an interrupt source established at either INT0, INT1, INT2 or INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0. * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The RC oscillator automatically stop operation. 2) The state of crystal oscillations established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level. (2) System resetting by watchdog timer or low-voltage detection. (3) Having an interrupt source established at either INT0, INT1, INT2 or INT4 * INT0 and INT1 HOLD mode reset is available only when level detection is set. (4) Having an interrupt source established at port 0. (5) Having an interrupt source established in the base timer circuit. Note: Available only when X'tal oscillation is selected.
No.A1400-4/27
LC872G08A/06A/04A
Package Form * MFP24S (300mil): Lead-free type * SSOP24 (225mil): Lead-free type (Development) Development Tools * On-chip debugger: TCB87 TypeB + LC87D2G08A TCB87 TypeB + LC87F2G08A Note: LC87F2G08A has an On-chip debugger but its function is limited. Flash ROM Version * LC87F2G08A
Package Dimensions
unit : mm (typ) 3112B
12.5 24 13
Package Dimensions
unit : mm (typ) 3287
6.5 24 13
5.4
7.6
4.4
0.63
6.4
1 1.0 (0.75) 0.35
12 0.15
1 0.5 (0.5)
1.7max
12 0.22 0.15
0.1
SANYO : MFP24S(300mil)
SANYO : SSOP24(225mil)
0.1
(1.3)
1.5max
(1.5)
0.5
No.A1400-5/27
LC872G08A/06A/04A
Pin Assignment
P70/INT0/T0LCP/AN8 RES VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20
P07/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4 P03/AN3 P02/AN2 P01/AN1 P00/AN0 P21/URX/INT4/T1IN P20/UTX/INT4/T1IN P17/T1PWMH/BUZ/INT1/T0HCP P16/T1PWML/INT2/T0IN
LC872G08A LC872G06A LC872G04A
19 18 17 16 15 14 13
Top view
SANYO: MFP24S (300mil) "Lead-free Type" SANYO: SSOP24 (225mil) "Lead-free Type" (Development)
MFP24S SSOP24 1 2 3 4 5 6 7 8 9 10 11 12
NAME P70/INT0/T0LCP/AN8 RES VSS1 CF1/XT1 CF2/XT2 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1/INT3/T0IN
MFP24S SSOP24 13 14 15 16 17 18 19 20 21 22 23 24
NAME P16/T1PWML/INT2/T0IN P17/T1PWMH/BUZ/INT1/T0HCP P20/UTX/INT4/T1IN P21/URX/INT4/T1IN P00/AN0 P01/AN1 P02/AN2 P03/AN3 P04/AN4 P05/AN5/CKO P06/AN6/T6O P07/T7O
No.A1400-6/27
LC872G08A/06A/04A
System Block Diagram
Interrupt control
IR
PLA
Standby control
Flash ROM
CF/ X'tal SRC RC MRC RES Reset control ACC Clock generator PC
WDT Reset circuit (LVD/POR)
B register
C register
SIO0
Bus interface
ALU
SIO1
Port 0
Timer 0
Port 1
PSW
Timer 1
Port 2
RAR
Timer 6
Port 7
RAM
Timer 7
ADC
Stack pointer
Base timer
INT0 to 2 INT3 (Noise filter)
UART1
Port 2 INT4
No.A1400-7/27
LC872G08A/06A/04A
Pin Description
Pin Name VSS1 VDD1 Port 0 P00 to P07 I/O I/O - Power supply pin + Power supply pin * 8-bit I/O port * I/O specifiable in 4-bit units * Pull-up resistors can be turned on and off in 4-bit units. * HOLD reset input * Port 0 interrupt input * Pin functions P05: System clock output P06: Timer 6 toggle output P07: Timer 7 toggle output P00(AN0) to P06(AN6): AD converter input Port 1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input / bus I/O P15: SIO1 clock I/O / INT3 input (with noise filter) / timer 0 event input / timer 0H capture input P16: Timer 1PWML output / INT2 input/HOLD reset input/timer 0 event input / timer 0L capture input P17: Timer 1PWMH output / beeper output / INT1 input / HOLD reset input / timer 0H capture input Interrupt acknowledge type Rising INT1 INT2 INT3 enable enable enable Falling enable enable enable Rising & Falling disable enable enable H level enable disable disable L level enable disable disable Yes Yes Description Option No No
Port 2 P20 to P21
I/O
* 2-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P20: UART transmit P21: UART receive P20 to P21: INT4 input / HOLD reset input / timer 1 event input / timer 0L capture input / timer 0H capture input Interrupt acknowledge types Rising INT4 enable Falling enable Rising & Falling enable H level disable L level disable Yes
Continued on next page.
No.A1400-8/27
LC872G08A/06A/04A
Continued from preceding page.
Pin Name Port 7 P70 I/O I/O * 1-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Pin functions P70: INT0 input / HOLD reset input / timer 0L capture input / watchdog timer output P70(AN8): AD converter input Interrupt acknowledge types Rising INT0 RES CF1/XT1 I/O I enable Falling enable Rising & Falling disable H level enable L level enable No Description Option
External reset input / internal reset output * Ceramic resonator or 32.768kHz crystal oscillator input pin * Pin function General-purpose input port
No No
CF2/XT2
I/O
* Ceramic resonator or 32.768kHz crystal oscillator output pin * Pin function General-purpose input port No
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port Name P00 to P07 Option selected in units of 1 bit Option type 1 2 P10 to P17 1 bit 1 2 P20 to P21 1 bit 1 2 P70 No CMOS Nch-open drain CMOS Nch-open drain CMOS Nch-open drain Nch-open drain Output type Pull-up resistor Programmable (Note 1) No Programmable Programmable Programmable Programmable Programmable
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low-and high-impedance pull-up connection is exercised in nibble (4-bit) units (P00 to 03 or P04 to 07).
User Option Table
Option Name Port output form Option Type P00 to P07 Mask Version *1 Flash Version Option Selected in Units of 1 bit Option Selection CMOS Nch-open drain P10 to P17 1 bit CMOS Nch-open drain P20 to P21 1 bit CMOS Nch-open drain Program start address Low-voltage detection reset function Power-on reset function Detect level Power-On reset level Detect function x *2 00000h 01E00h Enable:Use Disable:Not Used 7-level 8-level
*1: Mask option selection - No change possible after mask is completed. *2: Program start address of the mask version is 00000h.
No.A1400-9/27
LC872G08A/06A/04A
Recommended Unused Pin Connections
Recommended Unused Pin Connections Port Name Board P00 to P07 P10 to P17 P20 to P21 P70 CF1/XT1 CF2/XT2 Open Open Open Open Pulled low with a 100k resistor or less Pulled low with a 100k resistor or less Software Output low Output low Output low Output low General-purpose input port General-purpose input port
Notes on CF1/XT1 and CF2/XT2 pins * When using as general-purpose input ports Since the CF1/XT1 and CF2/XT2 pins are configured as CF oscillator pins at system reset time, it is necessary to add a current limiting resistor of 1k or greater to the CF2/XT2 pin in series when using them as general-purpose input pins. * Differences between flash and mask ROM version
System Reset Time State Flash ROM version LC87F2G08A Mask ROM version LC872G08A/06A/04A CF1/XT1 CF2/XT2 CF1/XT1 CF2/XT2 Set high via the internal Rf resistor Set high Set low via the internal Rf resistor Set low After System Reset is Released CF oscillation state CF oscillation state CF oscillation state CF oscillation state
Power Pin Treatment Recommendations (VDD1, VSS1)
Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: * Connect among the VDD1 and VSS1 pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (L1=L1', L2=L2'). * Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1F.
L2 L1 VSS1 C1 C2
VDD1 L1' L2'
No.A1400-10/27
LC872G08A/06A/04A
Absolute Maximum Ratings at Ta = 25C, VSS1 =0V
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output High level output current current Mean output current (Note 1-1) Total output current IOAH(1) IOAH(2) IOAH(3) Peak output current IOPL(2) Low level output current IOPL(3) Mean output current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) Power Dissipation Pd max(2) Pd max(1) IOML(1) IOPL(1) P10 to P14 Ports 0, 2 P15 to P17 Ports 0, 1, 2 P02 to P07 Ports 1, 2 P00, P01 P70 P02 to P07 Ports 1, 2 P00, P01 P70 P10 to P14 Port 0, 2, P15 to P17 Ports 0, 1, 2 P70 MFP24S(300mil) Total of all applicable pins Total of all applicable pins Ta=-40 to +85C Package only Ta=-40 to +85C Package with thermal resistance board (Note 1-2) Pd max(3) Pd max(4) SSOP24(225mil) Ta=-40 to +85C Package only Ta=-40 to +85C Package with thermal resistance board (Note 1-2) Operating ambient temperature Storage ambient temperature Tstg Topr -40 -55 +85 C +125 334 111 229 mW Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Total of all applicable pins Per 1 applicable pin Per 1 applicable pin Per 1 applicable pin Total of all applicable pins Per 1 applicable pin Total of all applicable pins Total of all applicable pins -20 -20 -25 20 30 10 15 20 7.5 50 60 70 7.5 129 mA IOMH Ports 0, 1, 2 IOPH VI VIO CF1, CF2 Ports 0, 1, 2, P70 Ports 0, 1, 2 CMOS output select Per 1 applicable pin CMOS output select Per 1 applicable pin -7.5 Symbol VDD max Pin/Remarks VDD1 Conditions VDD[V] min -0.3 -0.3 -0.3 -10 Specification typ max +6.5 VDD+0.3 VDD+0.3 V unit
Note 1-1: The mean output current is a mean value measured over 100ms. Note 1-2: SEMI standards thermal resistance board (size: 76.1x114.3x1.6tmm, glass epoxy) is used.
No.A1400-11/27
LC872G08A/06A/04A
Allowable Operating Conditions at Ta = -40C to +85C, VSS1 = 0V
Parameter Operating supply voltage Symbol VDD(1) VDD(2) VDD(3) Memory sustaining supply voltage High level input voltage VIH(2) VIH(3) VIH(4) Low level input voltage VIL(2) VIL(1) VIH(1) Ports 1, 2, P70 port input/ interrupt side Ports 0 Port 70 watchdog timer side CF1, RES Ports 1, 2, P70 port input/ interrupt side Ports 0 1.8 to 4.0 4.0 to 5.5 1.8 to 4.0 VIL(3) VIL(4) Instruction cycle time tCYC (Note 2-1) Port 70 watchdog timer side CF1, RES 1.8 to 5.5 1.8 to 5.5 2.7 to 5.5 2.2 to 5.5 1.8 to 5.5 External system clock frequency FEXCF CF1 * CF2 pin open * System clock frequency division ratio=1/1 * External system clock duty=505% * CF2 pin open * System clock frequency division ratio=1/2 * External system clock duty=505% Oscillation frequency range (Note 2-2) FmCF(3) CF1, CF2 FmCF(2) CF1, CF2 FmCF(1) CF1, CF2 12MHz ceramic oscillation. See Fig. 1. 10MHz ceramic oscillation. See Fig. 1. 4MHz ceramic oscillation. CF oscillation normal amplifier size selected. (CFLAMP=0) See Fig. 1. 4MHz ceramic oscillation. CF oscillation low amplifier size selected. (CFLAMP=1) See Fig. 1. FmMRC Frequency variable RC oscillation. 1/2 frequency division ratio. (RCCTD=0) (Note 2-3) FmRC FmSRC FsX'tal XT1, XT2 Internal medium-speed RC oscillation Internal low-speed RC oscillation 32.768kHz crystal oscillation See Fig. 1. 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 0.5 50 1.0 100 32.768 2.0 200 kHz 2.7 to 5.5 7.44 8.0 8.56 2.2 to 5.5 4 MHz 1.8 to 5.5 4 2.7 to 5.5 2.2 to 5.5 12 10 2.0 to 5.5 0.2 8 3.0 to 5.5 0.2 24.4 1.8 to 5.5 0.1 4 MHz 2.7 to 5.5 VSS VSS VSS VSS VSS 0.245 0.294 0.735 0.1 0.2VDD 0.15VDD+0.4 0.2VDD 0.8VDD-1.0 0.25VDD 200 200 200 12 s 1.8 to 5.5 1.8 to 5.5 1.8 to 5.5 4.0 to 5.5 0.3VDD+0.7 0.9VDD 0.75VDD VSS VDD VDD VDD 0.1VDD+0.4 V 1.8 to 5.5 0.3VDD+0.7 VDD VHD VDD1 Pin/Remarks VDD1 Conditions VDD[V] 0.245s tCYC 200s 0.294s tCYC 200s 0.735s tCYC 200s RAM and register contents sustained in HOLD mode. 1.6 min 2.7 2.2 1.8 Specification typ max 5.5 5.5 5.5 unit
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants. Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100s or longer after the multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A1400-12/27
LC872G08A/06A/04A
Electrical Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports 0, 1, 2, P70, RES Conditions VDD[V] Output disabled Pull-up resistor off VIN=VDD (Including output Tr's off leakage current) IIH(2) Low level input current IIL(1) CF1 Ports 0, 1, 2, P70, RES VIN=VDD Output disabled Pull-up resistor off VIN=VSS (Including output Tr's off leakage current) IIL(2) High level output voltage VOH(1) VOH(2) VOH(3) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Rpu(3) Ports 0, 1, 2 P70 Port 0 P00, P01 P70 Ports 0, 1, 2 CF1 Ports 0, 1, 2 VIN=VSS IOH=-1mA IOH=-0.35mA IOH=-0.15mA IOL=10mA IOL=1.4mA IOL=0.8mA IOL=1.4mA IOL=0.8mA IOL=25mA IOL=4mA IOL=2mA VOH=0.9VDD When Port 0 selected low-impedance pull-up. VOH=0.9VDD When Port 0 selected high-impedance pull-up. Hysteresis voltage VHYS(1) VHYS(2) Pin capacitance CP Ports 1, 2, P70, RES All pins For pins other than that under test: VIN=VSS f=1MHz Ta=25C 1.8 to 5.5 10 pF 2.7 to 5.5 1.8 to 2.7 0.1VDD 0.07VDD V 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 2.7 to 5.5 1.8 to 5.5 4.5 to 5.5 1.8 to 4.5 15 18 35 50 -15 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 0.4 0.4 0.4 1.5 0.4 0.4 80 230 k 1.8 to 5.5 100 210 400 V 1.8 to 5.5 -1 1.8 to 5.5 15 A 1.8 to 5.5 1 min Specification typ max unit
No.A1400-13/27
LC872G08A/06A/04A
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Output clock Frequency Low level pulse width High level pulse width Serial input Data setup time Data hold time Output delay Input clock time tdD0(2) tdD0(3) tsDI(1) thDI(1) tdD0(1) SO0(P10), SB0(P11) SB0(P11), SI0(P11) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 5. * Continuous data transmission/reception mode (Note 4-1-2) * Synchronous 8-bit mode (Note 4-1-2) Output clock (Note 4-1-2) 1.8 to 5.5 1.8 to 5.5 0.05 (1/3)tCYC +0.08 1tCYC +0.08 s 0.05 tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 5. 1.8 to 5.5 1/2 tSCK 1/2 tSCKH(1) Symbol tSCK(1) tSCKL(1) 1.8 to 5.5 Pin/ Remarks SCK0(P12) Conditions VDD[V] * See Fig. 5. min 2 1 tCYC 1 4/3 Specification typ max unit
Serial output
Serial clock
(1/3)tCYC +0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 5. 2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 5. 1.8 to 5.5 0.05 Output delay time Serial output tdD0(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 5. 1.8 to 5.5 (1/3)tCYC +0.08 s 0.05 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 5. 1.8 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) See Fig. 5. Conditions VDD[V] min 2 1.8 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Serial clock
No.A1400-14/27
LC872G08A/06A/04A
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pin/Remarks INT0(P70), INT1(P17), INT2(P16), INT4(P20 to P21) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P15) when noise filter time constant is 1/1 INT3(P15) when noise filter time constant is 1/32 INT3(P15) when noise filter time constant is 1/128 RES * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are nabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Resetting is enabled. 1.8 to 5.5 200 s 1.8 to 5.5 256 1.8 to 5.5 64 1.8 to 5.5 2 tCYC Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 or 1 are enabled. 1.8 to 5.5 1 min Specification typ max unit
No.A1400-15/27
LC872G08A/06A/04A
AD Converter Characteristics at VSS1 = 0V <12bits AD Converter Mode/Ta = -40C to +85C >
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN6(P06), AN8(P70) (Note 6-1) (Note 6-1) * See Conversion time calculation formulas. (Note 6-2) * See Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN Conditions VDD[V] 2.4 to 5.5 3.0 to 5.5 2.4 to 3.6 4.0 to 5.5 3.0 to 5.5 2.4 to 3.6 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 -1 32 64 410 VSS min Specification typ 12 max unit bit
16 20
115 115 425 VDD 1
LSB
s
V A
<8bits AD Converter Mode/Ta = -40C to +85C >
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol N ET Pin/Remarks AN0(P00) to AN6(P06) AN8(P70) * See Conversion time calculation formulas. (Note 6-2) * See Conversion time calculation formulas. (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (Note 6-1) Conditions VDD[V] 2.4 to 5.5 2.4 to 5.5 4.0 to 5.5 3.0 to 5.5 2.4 to 3.6 2.4 to 5.5 2.4 to 5.5 2.4 to 5.5 -1 20 40 250 VSS min Specification typ 8 1.5 90 90 265 VDD 1 V A s max unit bit LSB
Conversion time calculation formulas: 12bits AD Converter Mode: TCAD(Conversion time) = ((52/(AD division ratio))+2)x(1/3)xtCYC 8bits AD Converter Mode: TCAD(Conversion time) = ((32/(AD division ratio))+2)x(1/3)xtCYC
External oscillation (FmCF) CF-12MHz Operating supply voltage range (VDD) 4.0V to 5.5V 3.0V to 5.5V CF-10MHz 4.0V to 5.5V 3.0V to 5.5V CF-4MHz 3.0V to 5.5V 2.4V to 3.6V System division ratio (SYSDIV) 1/1 1/1 1/1 1/1 1/1 1/1 Cycle time (tCYC) 250ns 250ns 300ns 300ns 750ns 750ns AD division ratio (ADDIV) 1/8 1/16 1/8 1/16 1/8 1/32 12bit AD 34.8s 69.5s 41.8s 83.4s 104.5s 416.5s AD conversion time (TCAD) 8bit AD 21.5s 42.8s 25.8s 51.4s 64.5s 256.5s
Note 6-1: The quantization error (1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. The conversion time is 2 times the normal-time conversion time when: * The first AD conversion is performed in the 12-bit AD conversion mode after a system reset. * The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion mode.
No.A1400-16/27
LC872G08A/06A/04A
Power-on Reset (POR) Characteristics at Ta = -40C to +85C, VSS1 = 0V
Specification Parameter POR release voltage Symbol PORRL Pin/Remarks Conditions * Select from option. (Note 7-1) Option selected voltage 1.67V 1.97V 2.07V 2.37V 2.57V 2.87V 3.86V 4.35V Detection voltage unknown state Power supply rise time PORIS * Power supply rise time from 0V to 1.6V. 100 ms POUKS * See Fig. 7. (Note 7-2) 0.7 0.95 min 1.55 1.85 1.95 2.25 2.45 2.75 3.73 4.21 typ 1.67 1.97 2.07 2.37 2.57 2.87 3.86 4.35 max 1.79 2.09 2.19 2.49 2.69 2.99 3.99 4.49 V unit
Note7-1: The POR release level can be selected out of 8 levels only when the LVD reset function is disabled. Note7-2: POR is in an unknown state before transistors start operation.
Low Voltage Detection Reset (LVD) Characteristics at Ta = -40C to +85C, VSS1=0V
Specification Parameter LVD reset voltage (Note 8-2) Symbol LVDET Pin/Remarks Conditions * Select from option. (Note 8-1) (Note 8-3) * See Fig. 8. Option selected voltage 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V LVD hysteresys width LVHYS 1.91V 2.01V 2.31V 2.51V 2.81V 3.79V 4.28V Detection voltage unknown state Low voltage detection minimum width (Reply sensitivity) TLVDW LVUKS * See Fig. 8. (Note 8-4) * LVDET-0.5V * See Fig. 9. 0.2 ms 0.7 0.95 V min 1.81 1.91 2.21 2.41 2.71 3.69 4.18 typ 1.91 2.01 2.31 2.51 2.81 3.79 4.28 55 55 55 55 60 65 65 mV max 2.01 2.11 2.41 2.61 2.91 3.89 4.38 V unit
Note8-1: The LVD reset level can be selected out of 7 levels only when the LVD reset function is enabled. Note8-2: LVD reset voltage specification values do not include hysteresis voltage. Note8-3: LVD reset voltage may exceed its specification values when port output state changes and/or when a large current flows through port. Note8-4: LVD is in an unknown state before transistors start operation.
No.A1400-17/27
LC872G08A/06A/04A
Consumption Current Characteristics at Ta = -40C to +85C, VSS1 = 0V
Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 Conditions VDD[V] * FmCF=12MHz ceramic oscillation mode * System clock set to 12MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * CF1=24MHz external clock * System clock set to CF1 side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDOP(3) * FmCF=10MHz ceramic oscillation mode * System clock set to 10MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(4) * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(5) * CF oscillation low amplifier size selected. (CFLAMP=1) * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/4 frequency division ratio IDDOP(6) * FsX'tal=32.768kHz crystal oscillation mode * Internal low speed RC oscillation stopped. * System clock set to internal medium speed RC oscillation. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDOP(7) * FsX'tal=32.768kHz crystal oscillation mode * Internal low speed and medium speed RC oscillation stopped. * System clock set to 8MHz with frequency variable RC oscillation * 1/1 frequency division ratio IDDOP(8) * External FsX'tal and FmCF oscillation stopped. * System clock set to internal low speed RC oscillation. * Internal medium speed RC oscillation sopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDOP(9) * External FsX'tal and FmCF oscillation stopped. * System clock set to internal low speed RC oscillation. * Internal medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * Ta=-10 to +50C 2.5 23 64 3.3 33 90 5.0 55 153 A 1.8 to 3.6 33 108 1.8 to 5.5 55 197 2.7 to 3.6 2.6 5.0 2.7 to 5.5 4.2 8.8 1.8 to 3.6 0.3 0.6 1.8 to 5.5 0.5 1.3 2.2 to 3.6 0.5 1.0 2.2 to 5.5 0.9 2.2 1.8 to 3.6 1.3 2.7 mA 1.8 to 5.5 2.5 5.5 2.2 to 3.6 3.0 5.3 2.2 to 5.5 5.3 9.5 3.0 to 3.6 3.8 6.3 3.0 to 5.5 6.6 11.2 2.7 to 3.6 3.5 5.8 2.7 to 5.5 6.2 10.5 min Specification typ max unit
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1400-18/27
LC872G08A/06A/04A
Continued from preceding page.
Parameter Normal mode consumption current (Note 9-1) (Note 9-2) IDDOP(11) Symbol IDDOP(10) Pin/ Remarks VDD1 Conditions VDD[V] * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * Ta=-10 to +50C HALT mode consumption current (Note 9-1) (Note 9-2) IDDHALT(1) * HALT mode * FmCF=12MHz ceramic oscillation mode * System clock set to 12MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(2) * HALT mode * CF1=24MHz external clock * System clock set to CF1 side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDHALT(3) * HALT mode * FmCF=10MHz ceramic oscillation mode * System clock set to 10MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(4) * HALT mode * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(5) * HALT mode * CF oscillation low amplifier size selected. (CFLAMP=1) * FmCF=4MHz ceramic oscillation mode * System clock set to 4MHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/4 frequency division ratio IDDHALT(6) * HALT mode * FsX'tal=32.768kHz crystal oscillation mode * Internal low speed RC oscillation stopped. * System clock set to internal medium speed RC oscillation * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio 1.8 to 3.6 0.2 0.4 1.8 to 5.5 0.3 0.9 2.2 to 3.6 0.3 0.6 2.2 to 5.5 0.6 1.6 1.8 to 3.6 0.6 1.2 1.8 to 5.5 1.3 3.1 mA 2.2 to 3.6 1.1 1.9 2.2 to 5.5 2.2 3.9 3.0 to 3.6 1.6 2.6 3.0 to 5.5 2.8 4.8 2.7 to 3.6 1.3 2.1 2.7 to 5.5 2.5 4.4 2.5 6.1 15 3.3 12 27 5.0 33 68 A 1.8 to 3.6 12 41 1.8 to 5.5 33 101 min Specification typ max unit
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified.
Continued on next page.
No.A1400-19/27
LC872G08A/06A/04A
Continued from preceding page.
Parameter HALT mode consumption current (Note 9-1) (Note 9-2) Symbol IDDHALT(7) Pin/ remarks VDD1 * HALT mode * FsX'tal=32.768kHz crystal oscillation mode * Internal low speed and medium speed RC oscillation stopped. * System clock set to 8MHz with frequency variable RC oscillation * 1/1 frequency division ratio IDDHALT(8) * HALT mode * External FsX'tal and FmCF oscillation stopped. * System clock set to internal low speed RC oscillation. * Internal medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio IDDHALT(9) * HALT mode * External FsX'tal and FmCF oscillation stopped. * System clock set to internal low speed RC oscillation. * Internal medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/1 frequency division ratio * Ta=-10 to +50C IDDHALT(10) * HALT mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio IDDHALT(11) * HALT mode * FsX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal low speed and medium speed RC oscillation stopped. * Frequency variable RC oscillation stopped. * 1/2 frequency division ratio * Ta=-10 to +50C HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(3) IDDHOLD(2) IDDHOLD(1) HOLD mode * CF1=VDD or open (External clock mode) HOLD mode * CF1=VDD or open (External clock mode) * Ta=-10 to +50C HOLD mode * CF1=VDD or open (External clock mode) * LVD option selected IDDHOLD(4) HOLD mode * CF1=VDD or open (External clock mode) * Ta=-10 to +50C * LVD option selected Timer HOLD mode consumption current (Note 9-1) (Note 9-2) IDDHOLD(6) IDDHOLD(5) Timer HOLD mode * FsX'tal=32.768 kHz crystal oscillation mode Timer HOLD mode * FsX'tal=32.768kHz crystal oscillation mode * Ta=-10 to +50C 2.5 1.8 to 5.5 1.8 to 3.6 5.0 3.3 2.5 1.8 to 5.5 1.8 to 3.6 5.0 3.3 2.5 1.8 to 5.5 1.8 to 3.6 5.0 3.3 2.5 3.8 0.02 0.01 0.02 0.01 0.009 3.0 2.3 3.0 2.3 2.0 22 7.5 22 7.5 2.9 11 20 9.0 1.7 0.8 0.6 23 12 5.7 3.9 3.3 95 35 60 21 10 3.3 8.5 23 5.0 27 65 A 1.8 to 3.6 8.5 38 1.8 to 5.5 27 100 2.5 7.7 22 3.3 11 32 5.0 19 55 1.8 to 3.6 11 46 1.8 to 5.5 19 88 2.7 to 3.6 1.1 2.0 2.7 to 5.5 1.6 3.5 mA Conditions VDD[V] min Specification typ max unit
Note9-1: Values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. Note9-2: The consumption current values do not include operational current of LVD function if not specified.
No.A1400-20/27
LC872G08A/06A/04A
UART (Full Duplex) Operating Conditions at Ta = -40C to +85C, VSS1 = 0V
Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P20) URX(P21) Conditions VDD[V] 1.8 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC
Data length: Stop bits : Parity bits:
7/8/9 bits (LSB first) 1 bit (2-bit in continuous data transmission) None Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Start bit Stop bit Transmit data (LSB first) End of transmission
Start of transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Start bit Start of reception Receive data (LSB first)
Stop bit End of reception
UBR
No.A1400-21/27
LC872G08A/06A/04A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator * CF oscillation normal amplifier size selected (CFLAMP=0) MURATA
Nominal Frequency Circuit Constant Type Oscillator Name C1 [pF] 12MHz SMD CSTCE12M0G52-R0 (10) C2 [pF] (10) Rf [] Open Open SMD 10MHz LEAD CSTLS10M0G53-B0 (15) (15) CSTCE10M0G52-R0 (10) (10) Open Open Open Open SMD 8MHz LEAD CSTLS8M00G53-B0 (15) (15) CSTCE8M00G52-R0 (10) (10) Open Open Open Open SMD 6MHz LEAD CSTLS6M00G53-B0 (15) (15) CSTCR6M00G53-R0 (15) (15) Open Open Open Open SMD 4MHz LEAD CSTLS4M00G53-B0 (15) (15) CSTCR4M00G53-R0 (15) (15) Open Open Open Open Rd [] 680 1.0k 680 1.0k 680 1.0k 1.0k 1.5k 1.0k 1.5k 1.5k 2.2k 1.5k 2.2k 1.5k 3.3k 1.5k 3.3k Operating Voltage Range [V] 2.7 to 5.5 2.9 to 5.5 2.2 to 5.5 2.3 to 5.5 2.4 to 5.5 2.7 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 1.8 to 5.5 2.0 to 5.5 1.9 to 5.5 2.0 to 5.5 Oscillation Stabilization Time typ [ms] 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.2 0.2 0.2 0.2 max [ms] 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.6 0.6 0.6 0.6 Internal C1,C2 Remarks
* CF oscillation low amplifier size selected (CFLAMP=1) MURATA
Nominal Frequency Circuit Constant Type Oscillator Name C1 [pF] CSTCR4M00G53-R0 SMD CSTCR4M00G53095-R0 4MHz CSTLS4M00G53-B0 LEAD CSTLS4M00G53095-B0 (15) (15) (15) (15) (15) (15) (15) C2 [pF] (15) Rf [] Open Open Open Open Open Open Open Open Rd [] 1.0k 2.2k 1.0k 2.2k 1.0k 2.2k 1.0k 2.2k Operating Voltage Range [V] 2.2 to 5.5 2.3 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 2.3 to 5.5 2.2 to 5.5 2.2 to 5.5 Oscillation Stabilization Time typ [ms] 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 max [ms] 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 Internal C1,C2 Remarks
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 3) * Time till the oscillation gets stabilized after the CPU reset state is released * Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed * Till the oscillation gets stabilized after the HOLD mode is reset. * Till the oscillation gets stabilized after the X'tal HOLD mode is reset with CFSTOP (OCR register, bit 0) set to 0
No.A1400-22/27
LC872G08A/06A/04A
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator EPSON TOYOCOM
Nominal Frequency Type Oscillator Name C1 [pF] 32.768kHz SMD MC-306 9 Circuit Constant C2 [pF] 9 Rf [] Rd [] Operating Voltage Range [V] Oscillation Stabilization Time typ [s] max [s] Applicable CL value = 7.0pF Remarks
The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than minimum operating voltage. (See Fig. 3) * Till the oscillation gets stabilized after the instruction for starting the subclock oscillation circuit is executed * Till the oscillation starts and gets stabilized after the HOLD mode is reset when EXTOSC (OCR register, bit 6) is set to 1 and CFSTOP (OCR register, bit 0) is set to 1 (Notes on the implementation of the oscillator circuit) * Oscillation is influenced by the circuit pattern layout of printed circuit board. Place the oscillation-related components as close to the CPU chip and to each other as possible with the shortest possible pattern length. * Keep the signal lines whose state changes suddenly or in which large current flows as far away from the oscillator circuit as possible and make sure that they do not cross one another. * Be sure to insert a current limiting resistor (Rd) so that the oscillation amplitude never exceeds the input voltage level that is specified as the absolute maximum rating. * The oscillator circuit constants shown above are sample characteristic values that are measured using the SANYOdesignated oscillation evaluation board. Since the accuracy of the oscillation frequency and other characteristics vary according to the board on which the IC is installed, it is recommended that the user consult the resonator vendor for oscillation evaluation of the IC on a user's production board when using the IC for applications that require high oscillation accuracy. For further information, contact your resonator vendor or SANYO Semiconductor sales representative serving your locality. * It must be noted, when replacing the flash ROM version of a microcontroller with a mask ROM version, that their operating voltage ranges may differ even when the oscillation constant of the external oscillator is the same.
CF1/XT1 Rf
CF2/XT2
Rd
C1
CF/X'tal
C2
Figure 1 CF and XT Oscillator Circuit
0.5VDD
Figure 2 AC Timing Measurement Point
No.A1400-23/27
LC872G08A/06A/04A
VDD Power supply Operating VDD lower limit 0V Reset time RES
Internal Medium speed RC oscillation
tmsCF/tmsXtal CF1, CF2
Instruction execution (Note2) Operating mode Unpredictable Reset Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal valid
Internal Medium speed RC oscillation or Low speed RC oscillation tmsCF CF1, CF2 (Note1) tmsX'tal CF1, CF2 (Note2)
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time Note1: Mainclock oscillation circuit is selected. Note2: Subclock oscillation circuit is selected. Figure 3 Oscillation Stabilization Times
No.A1400-24/27
LC872G08A/06A/04A
VDD
RRES
RES CRES
Note: External circuits for reset may vary depending on the usage of POR and LVD. Please refer to the user's manual for more information.
Figure 4 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Figure 5 Serial I/O Output Waveforms
tPIL
tPIH
Figure 6 Pulse Input Timing Signal Waveform
No.A1400-25/27
LC872G08A/06A/04A
POR release voltage (PORRL)
(a)
(b)
VDD
Reset period Unknown-state (POUKS) RES
100s or longer
Reset period
Figure 7 Waveform observed when only POR is used (LVD not used) (RESET pin: Pull-up resistor RRES only) * The POR function generates a reset only when power is turned on starting at the VSS level. * No stable reset will be generated if power is turned on again when the power level does not go down to the VSS level as shown in (a). If such a case is anticipated, use the LVD function together with the POR function or implement an external reset circuit. * A reset is generated only when the power level goes down to the VSS level as shown in (b) and power is turned on again after this condition continues for 100s or longer.
LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS)
VDD LVD reset voltage (LVDET) Reset period Unknown-state (LVUKS) RES Reset period Reset period
Figure 8 Waveform observed when both POR and LVD functions are used (RESET pin: Pull-up resistor RRES only) * Resets are generated both when power is turned on and when the power level lowers. * A hysteresis width (LVHYS) is provided to prevent the repetitions of reset release and entry cycles near the detection level.
No.A1400-26/27
LC872G08A/06A/04A
VDD
LVD release voltage
LVD reset voltage
TLVDW
LVDET-0.5V
VSS
Figure 9 Low voltage detection minimum width (Example of momentary power loss/Voltage variation waveform)
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of December, 2008. Specifications and information herein are subject to change without notice.
PS No.A1400-27/27

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