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Section I. Stratix II Device Family Data Sheet
This section provides the data sheet specifications for Stratix(R) II devices. This section contains feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix II devices. This section contains the following chapters:

Chapter 1, Introduction Chapter 2, Stratix II Architecture Chapter 3, Configuration & Testing Chapter 4, Hot Socketing & Power-On Reset Chapter 5, DC & Switching Characteristics Chapter 6, Reference & Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
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Section I-1
Stratix II Device Family Data Sheet
Stratix II Device Handbook, Volume 1
Section I-2
Altera Corporation
1. Introduction
SII51001-4.2
Introduction
The Stratix(R) II FPGA family is based on a 1.2-V, 90-nm, all-layer copper SRAM process and features a new logic structure that maximizes performance, and enables device densities approaching 180,000 equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of on-chip, TriMatrixTM memory for demanding, memory intensive applications and has up to 96 DSP blocks with up to 384 (18-bit x 18-bit) multipliers for efficient implementation of high performance filters and other DSP functions. Various high-speed external memory interfaces are supported, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM. Stratix II devices support various I/O standards along with support for 1-gigabit per second (Gbps) source synchronous signaling with DPA circuitry. Stratix II devices offer a complete clock management solution with internal clock frequency of up to 550 MHz and up to 12 phase-locked loops (PLLs). Stratix II devices are also the industry's first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm to protect designs. The Stratix II family offers the following features:

Features

15,600 to 179,400 equivalent LEs; see Table 1-1 New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to 16 global clocks with 24 clocking resources per device region Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting
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1-1
Features

Support for numerous single-ended and differential I/O standards High-speed differential I/O support with DPA circuitry for 1-Gbps performance Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransportTM technology, and SFI-4 Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from Altera MegaCore(R) functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for design security using configuration bitstream encryption Support for remote configuration updates
Table 1-1. Stratix II FPGA Family Features Feature
ALMs Adaptive look-up tables (ALUTs) (1) Equivalent LEs (2) M512 RAM blocks M4K RAM blocks M-RAM blocks Total RAM bits DSP blocks 18-bit x 18-bit multipliers (3) Enhanced PLLs Fast PLLs Maximum user I/O pins Notes to Table 1-1:
(1) (2) (3) One ALM contains two ALUTs. The ALUT is the cell used in the Quartus(R) II software for logic synthesis. This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture). These multipliers are implemented using the DSP blocks.
EP2S15
6,240 12,480 15,600 104 78 0 419,328 12 48 2 4 366
EP2S30
13,552 27,104 33,880 202 144 1 1,369,728 16 64 2 4 500
EP2S60
24,176 48,352 60,440 329 255 2 2,544,192 36 144 4 8 718
EP2S90
36,384 72,768 90,960 488 408 4 4,520,488 48 192 4 8 902
EP2S130
53,016 106,032 132,540 699 609 6 6,747,840 63 252 4 8 1,126
EP2S180
71,760 143,520 179,400 930 768 9 9,383,040 96 384 4 8 1,170
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Altera Corporation May 2007
Introduction
Stratix II devices are available in space-saving FineLine BGA(R) packages (see Tables 1-2 and 1-3).
Table 1-2. Stratix II Package Options & I/O Pin Counts 484-Pin FineLine BGA
342 342 334 308
Notes (1), (2) 780-Pin FineLine BGA 1,020-Pin FineLine BGA 1,508-Pin FineLine BGA
Device
484-Pin Hybrid FineLine BGA
672-Pin FineLine BGA
366 500 492
EP2S15 EP2S30 EP2S60 (3) EP2S90 (3) EP2S130 (3) EP2S180 (3) Notes to Table 1-2:
(1) (2) (3)
718 534 534 758 742 742 902 1,126 1,170
All I/O pin counts include eight dedicated clock input pins (clk1p, clk1n, clk3p, clk3n, clk9p, clk9n, clk11p, and clk11n) that can be used for data inputs. The Quartus II software I/O pin counts include one additional pin, PLL_ENA, which is not available as generalpurpose I/O pins. The PLL_ENA pin can only be used to enable the PLLs within the device. The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and FPLL10CLKp/n) that can be used for data inputs.
Table 1-3. Stratix II FineLine BGA Package Sizes Dimension
Pitch (mm) Area (mm2) Length x width (mm x mm)
484 Pin
1.00 529 23 x 23
484-Pin Hybrid
1.00 729 27 x 27
672 Pin
1.00 729 27 x 27
780 Pin
1.00 841 29 x 29
1,020 Pin
1.00 1,089 33 x 33
1,508 Pin
1.00 1,600 40 x 40
All Stratix II devices support vertical migration within the same package (for example, you can migrate between the EP2S15, EP2S30, and EP2S60 devices in the 672-pin FineLine BGA package). Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. To ensure that a board layout supports migratable densities within one package offering, enable the applicable vertical migration path within the Quartus II software (Assignments menu > Device > Migration Devices).
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1-3 Stratix II Device Handbook, Volume 1
Features
After compilation, check the information messages for a full list of I/O, DQ, LVDS, and other pins that are not available because of the selected migration path. Table 1-4 lists the Stratix II device package offerings and shows the total number of non-migratable user I/O pins when migrating from one density device to a larger density device. Additional I/O pins may not be migratable if migrating from the larger device to the smaller density device. 1 When moving from one density to a larger density, the larger density device may have fewer user I/O pins. The larger device requires more power and ground pins to support the additional logic within the device. Use the Quartus II Pin Planner to determine which user I/O pins are migratable between the two devices.
Table 1-4. Total Number of Non-Migratable I/O Pins for Stratix II Vertical Migration Paths Vertical Migration Path
EP2S15 to EP2S30 EP2S15 to EP2S60 EP2S30 to EP2S60 EP2S60 to EP2S90 EP2S60 to EP2S130 EP2S60 to EP2S180 EP2S90 to EP2S130 EP2S90 to EP2S180 EP2S130 to EP2S180 Note to Table 1-4:
(1) Some of the DQ/DQS pins are not migratable. Refer to the Quartus II software information messages for more detailed information.
484-Pin FineLine BGA
0 (1) 8 (1) 8 (1)
672-Pin FineLine BGA
0 0 8
780-Pin FineLine BGA
1020-Pin FineLine BGA
1508-Pin FineLine BGA
0 0 0 0 (1) 16 16 0 17 0 0
1
To determine if your user I/O assignments are correct, run the I/O Assignment Analysis command in the Quartus II software (Processing > Start > Start I/O Assignment Analysis).
f
Refer to the I/O Management chapter in volume 2 of the Quartus II Handbook for more information on pin migration.
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Introduction
Stratix II devices are available in up to three speed grades, -3, -4, and -5, with -3 being the fastest. Table 1-5 shows Stratix II device speed-grade offerings.
Table 1-5. Stratix II Device Speed Grades Temperature Grade
Commercial Industrial EP2S30 Commercial Industrial EP2S60 Commercial Industrial EP2S90 Commercial Industrial EP2S130 Commercial Industrial EP2S180 Commercial Industrial -4, -5
Device
484-Pin FineLine BGA
-3, -4, -5 -4 -3, -4, -5 -4 -3, -4, -5 -4
484-Pin Hybrid FineLine BGA
672-Pin FineLine BGA
-3, -4, -5 -4 -3, -4, -5 -4 -3, -4, -5 -4
780-Pin FineLine BGA
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
EP2S15
-3, -4, -5 -4 -4, -5 -3, -4, -5 -4 -3, -4, -5 -4 -3, -4, -5 -4 -3, -4, -5 -4 -3, -4, -5 -4 -3, -4, -5 -4
-4, -5
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Document Revision History
Document Revision History
Table 1-6 shows the revision history for this chapter.
Table 1-6. Document Revision History Date and Document Version
May 2007, v4.2 April 2006, v4.1
Changes Made
Moved Document Revision History to the end of the chapter.

Summary of Changes
-- --
Updated "Features" section. Removed Note 4 from Table 1-2. Updated Table 1-4. Updated Tables 1-2, 1-4, and 1-5. Updated Figure 2-43. Added vertical migration information, including Table 1-4. Updated Table 1-5. Updated "Features" section. Updated Table 1-2.
December 2005, v4.0 July 2005, v3.1

-- --
May 2005, v3.0 March 2005, v2.1 January 2005, v2.0 October 2004, v1.2 July 2004, v1.1 February 2004, v1.0

-- -- -- -- -- --
Updated "Introduction" and "Features" sections. Added note to Table 1-2. Updated Tables 1-2, 1-3, and 1-5.

Updated Tables 1-1 and 1-2. Updated "Features" section.
Added document to the Stratix II Device Handbook.
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2. Stratix II Architecture
SII51002-4.3
Functional Description
Stratix(R) II devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provides signal interconnects between logic array blocks (LABs), memory block structures (M512 RAM, M4K RAM, and M-RAM blocks), and digital signal processing (DSP) blocks. Each LAB consists of eight adaptive logic modules (ALMs). An ALM is the Stratix II device family's basic building block of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 550 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 420 MHz. Several M-RAM blocks are located individually in the device's logic array. DSP blocks can implement up to either eight full-precision 9 x 9-bit multipliers, four full-precision 18 x 18-bit multipliers, or one full-precision 36 x 36-bit multiplier with add or subtract features. The DSP blocks support Q1.15 format rounding and saturation in the multiplier and accumulator stages. These blocks also contain shift registers for digital signal processing applications, including finite impulse response (FIR) and infinite impulse response (IIR) filters. DSP blocks are grouped into columns across the device and operate at up to 450 MHz.
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2-1
Functional Description
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR and DDR2 SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial interface channels with dynamic phase alignment (DPA) support data transfer at up to 1 Gbps using LVDS or HyperTransportTM technology I/O standards. Figure 2-1 shows an overview of the Stratix II device. Figure 2-1. Stratix II Block Diagram
M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers M4K RAM Blocks DSP Blocks for for True Dual-Port Multiplication and Full Memory & Other Embedded Implementation of FIR Filters Memory Functions IOEs Support DDR, PCI, PCI-X, SSTL-3, SSTL-2, HSTL-1, HSTL-2, LVDS, HyperTransport & other I/O Standards
IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs
LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs
LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs
LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs
LABs LABs LABs LABs LABs
M-RAM Block
LABs LABs LABs
DSP Block
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Stratix II Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device along with row and column numbers and M-RAM blocks. Table 2-1 lists the resources available in Stratix II devices.
Table 2-1. Stratix II Device Resources Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
M512 RAM Columns/Blocks
4 / 104 6 / 202 7 / 329 8 / 488 9 / 699 11 / 930
M4K RAM Columns/Blocks
3 / 78 4 / 144 5 / 255 6 / 408 7 / 609 8 / 768
M-RAM Blocks
0 1 2 4 6 9
DSP Block Columns/Blocks
2 / 12 2 / 16 3 / 36 3 / 48 3 / 63 4 / 96
LAB Columns
30 49 62 71 81 100
LAB Rows
26 36 51 68 87 96
Logic Array Blocks
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains, LAB control signals, local interconnect, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. Register chain connections transfer the output of an ALM register to the adjacent ALM register in an LAB. The Quartus(R) II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Figure 2-2 shows the Stratix II LAB structure.
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2-3 Stratix II Device Handbook, Volume 1
Logic Array Blocks
Figure 2-2. Stratix II LAB Structure
Row Interconnects of Variable Speed & Length
ALMs
Direct link interconnect from adjacent block Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
Local Interconnect
LAB
Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows
Column Interconnects of Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM blocks, or DSP blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 24 ALMs through fast local and direct link interconnects. Figure 2-3 shows the direct link connection.
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Stratix II Architecture
Figure 2-3. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output
ALMs
Direct link interconnect to left
Direct link interconnect to right
Local Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs. The control signals include three clocks, three clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, and synchronous load control signals. This gives a maximum of 11 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use three clocks and three clock enable signals. However, there can only be up to two unique clocks per LAB, as shown in the LAB control signal generation circuit in Figure 2-4. Each LAB's clock and clock enable signals are linked. For example, any ALM in a particular LAB using the labclk1 signal also uses labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. By default, the Quartus II software uses a NOT gate push-back technique to achieve preset. If you disable the NOT gate push-up option or assign a given register to power up high using the Quartus II software, the preset is achieved using the asynchronous load
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Adaptive Logic Modules
signal with asynchronous load data input tied high. When the asynchronous load/preset signal is used, the labclkena0 signal is no longer available. The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2-4 shows the LAB control signal generation circuit. Figure 2-4. LAB-Wide Control Signals
There are two unique clock signals per LAB.
6 Dedicated Row LAB Clocks 6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0 labclkena0 or asyncload or labpreset
labclk1 labclkena1
labclk2 labclkena2
syncload labclr0
labclr1 synclr
Adaptive Logic Modules
The basic building block of logic in the Stratix II architecture, the adaptive logic module (ALM), provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can implement various combinations of two functions. This adaptability allows the ALM to be
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Stratix II Architecture
completely backward-compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions. In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, the ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. Figure 2-5 shows a high-level block diagram of the Stratix II ALM while Figure 2-6 shows a detailed view of all the connections in the ALM. Figure 2-5. High-Level Block Diagram of the Stratix II ALM
carry_in shared_arith_in reg_chain_in To general or local routing adder0
D Q
dataf0 datae0 dataa datab datac datad datae1 dataf1 reg1 Combinational Logic adder1
D Q
To general or local routing
reg0
To general or local routing
To general or local routing carry_out shared_arith_out reg_chain_out
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shared_arith_in carry_in syncload ena[2..0]
Adaptive Logic Modules
reg_chain_in sclr asyncload
Local Interconnect
dataf0
Figure 2-6. Stratix II ALM Details
2-8 Stratix II Device Handbook, Volume 1
4-Input LUT Row, column & direct link routing
ENA CLRN PRN/ALD D Q ADATA
Local Interconnect
datae0
Local Interconnect 3-Input LUT
datac
Row, column & direct link routing Local Interconnect
Local Interconnect 3-Input LUT
dataa
Local Interconnect 4-Input LUT
datab
Local Interconnect
datad 3-Input LUT
PRN/ALD Q D ADATA ENA CLRN
Row, column & direct link routing Row, column & direct link routing Local Interconnect
3-Input LUT VCC
Local Interconnect
datae1
Local Interconnect
dataf1
carry_out shared_arith_out
reg_chain_out
clk[2..0] aclr[1..0]
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Stratix II Architecture
One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous load data. The asynchronous load data input comes from the datae or dataf input of the ALM, which are the same inputs that can be used for register packing. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of the ALM. Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers independently (see Figure 2-6). For each set of output drivers, two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output.
f
See the Performance & Logic Efficiency Analysis of Stratix II Devices White Paper for more information on the efficiencies of the Stratix II ALM and comparisons with previous architectures.
ALM Operating Modes
The Stratix II ALM can operate in one of the following modes:

Normal mode Extended LUT mode Arithmetic mode Shared arithmetic mode
Each mode uses ALM resources differently. In each mode, eleven available inputs to the ALM--the eight data inputs from the LAB local interconnect; carry-in from the previous ALM or LAB; the shared arithmetic chain connection from the previous ALM or LAB; and the register chain connection--are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear,
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Adaptive Logic Modules
synchronous load, and clock enable control for the register. These LABwide signals are available in all ALM modes. See the "LAB Control Signals" section for more information on the LAB-wide control signals. The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which ALM operating mode to use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and combinational functions. In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The normal mode allows two functions to be implemented in one Stratix II ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions which have common inputs. Figure 2-7 shows the supported LUT combinations in normal mode.
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Stratix II Architecture
Figure 2-7. ALM in Normal Mode Note (1)
dataf0 datae0 datac dataa datab datad datae1 dataf1
4-Input LUT
combout0
dataf0 datae0 datac dataa datab
5-Input LUT
combout0
4-Input LUT
combout1 datad datae1 dataf1
5-Input LUT
combout1
dataf0 datae0 datac dataa datab
5-Input LUT
combout0
datad datae1 dataf1
dataf0 datae0 dataa datab datac datad
6-Input LUT
combout0
3-Input LUT
combout1
dataf0 datae0 datac dataa datab
5-Input LUT
combout0
dataf0 datae0 dataa datab datac datad
6-Input LUT
combout0
datad datae1 dataf1
4-Input LUT
combout1
datae1 dataf1
6-Input LUT
combout1
Note to Figure 2-7:
(1) Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
The normal mode provides complete backward compatibility with fourinput LUT architectures. Two independent functions of four inputs or less can be implemented in one Stratix II ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs.
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Adaptive Logic Modules
For the packing of two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). In the case of implementing two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4 x 2 crossbar switch (two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one ALM, as shown in Figure 2-8. The shared inputs are dataa, datab, datac, and datad, while the unique select lines are datae0 and dataf0 for function0, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture. Figure 2-8. 4 x 2 Crossbar Switch Example
4 x 2 Crossbar Switch sel0[1..0] inputa inputb inputc inputd out1 sel1[1..0] datae1 dataf1 Six-Input LUT (Function1) out0 dataf0 datae0 dataa datab datac datad Implementation in 1 ALM
Six-Input LUT (Function0)
combout0
combout1
In a sparsely used device, functions that could be placed into one ALM may be implemented in separate ALMs. The Quartus II Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically utilizes the full potential of the Stratix II ALM. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments. Any six-input function can be implemented utilizing inputs dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1. If datae0 and dataf0 are utilized, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (see Figure 2-9). If
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Stratix II Architecture
datae1 and dataf1 are utilized, the output drives to register1 and/or bypasses register1 and drives to the interconnect using the bottom set of output drivers. The Quartus II Compiler automatically selects the inputs to the LUT. Asynchronous load data for the register comes from the datae or dataf input of the ALM. ALMs in normal mode support register packing. Figure 2-9. 6-Input Function in Normal Mode Notes (1), (2)
dataf0 datae0 dataa datab datac datad datae1 dataf1 (2) To general or local routing 6-Input LUT
D Q
To general or local routing
reg0
D
Q
To general or local routing
These inputs are available for register packing.
reg1
Notes to Figure 2-9:
(1) (2) If datae1 and dataf1 are used as inputs to the six-input function, then datae0 and dataf0 are available for register packing. The dataf1 input is available for register packing only if the six-input function is un-registered.
Extended LUT Mode
The extended LUT mode is used to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs. Figure 2-10 shows the template of supported seven-input functions utilizing extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the template shown in Figure 2-10 occur naturally in designs. These functions often appear in designs as "if-else" statements in Verilog HDL or VHDL code.
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Adaptive Logic Modules
Figure 2-10. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0 datac dataa datab datad dataf0 5-Input LUT combout0
D Q
To general or local routing To general or local routing
5-Input LUT datae1 dataf1 (1)
reg0
This input is available for register packing.
Note to Figure 2-10:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An ALM in arithmetic mode uses two sets of two four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. The four LUTs share the dataa and datab inputs. As shown in Figure 2-11, the carry-in signal feeds to adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs.
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Stratix II Architecture
Figure 2-11. ALM in Arithmetic Mode
carry_in
datae0 4-Input LUT
adder0
To general or local routing
D Q
dataf0 datac datab dataa
To general or local routing
4-Input LUT
reg0
adder1
datad datae1 4-Input LUT
D Q
To general or local routing To general or local routing
4-Input LUT dataf1 carry_out
reg1
While operating in arithmetic mode, the ALM can support simultaneous use of the adder's carry output along with combinational logic outputs. In this operation, the adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2-12. The equation for this example is: R = (X < Y) ? Y : X To implement this function, the adder is used to subtract `Y' from `X.' If `X' is less than `Y,' the carry_out signal is `1.' The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data `Y' drives the syncdata inputs to the registers. If `X' is greater than or equal to `Y,' the syncload signal is de-asserted and `X' drives the data port of the registers.
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Adaptive Logic Modules
Figure 2-12. Conditional Operation Example
Adder output is not used.
ALM 1 X[0] Y[0] Comb & Adder Logic X[0] R[0]
D Q
To general or local routing
syncdata
X[1] Y[1] Comb & Adder Logic X[1]
reg0 syncload
D
Q
R[1]
To general or local routing
reg1
Carry Chain
ALM 2 X[2] Y[2] Comb & Adder Logic
syncload
X[2]
D Q
R[2]
To general or local routing
reg0 syncload Comb & Adder Logic carry_out To local routing & then to LAB-wide syncload
The arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down and add/subtract control signals. These control signals are good candidates for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. Carry Chain The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. Carry chains can begin in either the first ALM or the fifth ALM in an LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.
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Stratix II Architecture
The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only utilize either the top half or the bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top four ALMs in the first LAB carry into the top half of the ALMs in the next LAB within the column. Carry chains that use the bottom four ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. Every other column of LABs is top-half bypassable, while the other LAB columns are bottom-half bypassable. See the "MultiTrack Interconnect" on page 2-22 section for more information on carry chain interconnect.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In this mode, the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in the LAB) via a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree. Figure 2-13 shows the ALM in shared arithmetic mode.
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Adaptive Logic Modules
Figure 2-13. ALM in Shared Arithmetic Mode
shared_arith_in carry_in
4-Input LUT
D Q
To general or local routing To general or local routing
datae0 datac datab dataa
4-Input LUT
reg0
datad datae1
4-Input LUT
D Q
To general or local routing To general or local routing
4-Input LUT
reg1
carry_out shared_arith_out
Note to Figure 2-13:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Adder trees can be found in many different applications. For example, the summation of the partial products in a logic-based multiplier can be implemented in a tree structure. Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure 2-14. The partial sum (S[2..0]) and the partial carry (C[2..0]) is obtained using the LUTs, while the result (R[2..0]) is computed using the dedicated adders.
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Stratix II Architecture
Figure 2-14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0' carry_in = '0' 3-Bit Add Example X2 X1 X0 Y2 Y1 Y0 + Z2 Z1 Z0 S2 S1 S0 + C2 C1 C0 R3 R2 R1 R0 X0 Y0 Z0 X1 Y1 Z1 ALM Implementation ALM 1
1st stage add is implemented in LUTs. 2nd stage add is implemented in adders.
3-Input LUT
S0 R0
3-Input LUT
C0
Binary Add 110 101 +010 001 +110 1101
Decimal Equivalents 6 5 +2 1 + 2x6 13
3-Input LUT
S1
R1 3-Input LUT ALM 2 3-Input LUT S2 R2 X2 Y2 Z2 3-Input LUT C2 C1
3-Input LUT
'0' R3
3-Input LUT
Shared Arithmetic Chain In addition to the dedicated carry chain routing, the shared arithmetic chain available in shared arithmetic mode allows the ALM to implement a three-input add. This significantly reduces the resources necessary to implement large adder trees or correlator functions. The shared arithmetic chains can begin in either the first or fifth ALM in an LAB. The Quartus II Compiler creates shared arithmetic chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long shared
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arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to the carry chains, the shared arithmetic chains are also top- or bottom-half bypassable. This capability allows the shared arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottomhalf bypassable. See the "MultiTrack Interconnect" on page 2-22 section for more information on shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in an LAB have register chain outputs. The register chain routing allows registers in the same LAB to be cascaded together. The register chain interconnect allows an LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between ALMs while saving local interconnect resources (see Figure 2-15). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance.
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Stratix II Architecture
Figure 2-15. Register Chain within an LAB Note (1)
From Previous ALM Within The LAB
reg_chain_in To general or local routing adder0
D Q
To general or local routing
reg0 Combinational Logic adder1
D Q
To general or local routing
reg1 To general or local routing
To general or local routing adder0
D Q
To general or local routing
reg0 Combinational Logic adder1
D Q
To general or local routing
reg1 To general or local routing
reg_chain_out
To Next ALM within the LAB
Note to Figure 2-15:
(1) The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
See the "MultiTrack Interconnect" on page 2-22 section for more information on register chain interconnect.
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MultiTrack Interconnect
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and load/preset signals. The ALM directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOTgate push-back technique. Stratix II devices support simultaneous asynchronous load/preset, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one load/preset signal. In addition to the clear and load/preset ports, Stratix II devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals.
MultiTrack Interconnect
In the Stratix II architecture, connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory in the same row. These row resources include:

Direct link interconnects between LABs and adjacent blocks R4 interconnects traversing four blocks to the right or left R24 row interconnects for high-speed access across the length of the device
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Stratix II Architecture
The direct link interconnect allows an LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself. This provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2-16 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 2-16. R4 Interconnect Connections Notes (1), (2), (3)
C4 and C16 Column Interconnects (1) R4 Interconnect Driving Right
Adjacent LAB can Drive onto Another LAB's R4 Interconnect R4 Interconnect Driving Left
LAB Neighbor
Primary LAB (2)
LAB Neighbor
Notes to Figure 2-16:
(1) (2) (3) C4 and C16 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row. The LABs in Figure 2-16 show the 16 possible logical outputs per LAB.
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MultiTrack Interconnect
R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect. These column resources include:

Shared arithmetic chain interconnects in an LAB Carry chain interconnects in an LAB and from LAB to LAB Register chain interconnects in an LAB C4 interconnects traversing a distance of four blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device
Stratix II devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These ALM to ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2-17 shows the shared arithmetic chain, carry chain and register chain interconnects.
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Stratix II Architecture
Figure 2-17. Shared Arithmetic Chain, Carry Chain & Register Chain Interconnects
Local Interconnect Routing Among ALMs in the LAB Carry Chain & Shared Arithmetic Chain Routing to Adjacent ALM
ALM 1
ALM 2
Register Chain Routing to Adjacent ALM's Register Inpu
Local Interconnect
ALM 3 ALM 4 ALM 5 ALM 6 ALM 7
ALM 8
The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2-18 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.
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MultiTrack Interconnect
Figure 2-18. C4 Interconnect Connections Note (1)
C4 Interconnect Drives Local and R4 Interconnects up to Four Rows
C4 Interconnect Driving Up
LAB
Row Interconnect
Adjacent LAB can drive onto neighboring LAB's C4 interconnect
Local Interconnect
C4 Interconnect Driving Down
Note to Figure 2-18:
(1) Each C4 interconnect can drive either up or down four rows.
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Stratix II Architecture
C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0]. Table 2-2 shows the Stratix II device's routing scheme.
Table 2-2. Stratix II Device Routing Scheme (Part 1 of 2) Destination Shared Arithmetic Chain Direct Link Interconnect Local Interconnect M512 RAM Block R24 Interconnect C16 Interconnect
M4K RAM Block
R4 Interconnect
C4 Interconnect
Register Chain
M-RAM Block
Carry Chain
Column IOE
DSP Blocks
Shared arithmetic chain Carry chain Register chain Local interconnect Direct link interconnect R4 interconnect R24 interconnect C4 interconnect C16 interconnect ALM M512 RAM block M4K RAM block M-RAM block DSP blocks
v v v vvvvvvv v v v vvvv vvvv v v v v v v vvvv vvvvvv vvv vvv vv
vvvv
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ALM
Source
Row IOE
TriMatrix Memory
Table 2-2. Stratix II Device Routing Scheme (Part 2 of 2) Destination Shared Arithmetic Chain Direct Link Interconnect Local Interconnect M512 RAM Block R24 Interconnect C16 Interconnect
M4K RAM Block
R4 Interconnect
C4 Interconnect
Register Chain
M-RAM Block
Carry Chain
Column IOE
DSP Blocks
Column IOE Row IOE
v
vv
vvvv
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2-3 shows the size and features of the different RAM blocks.
Table 2-3. TriMatrix Memory Features (Part 1 of 2) Memory Feature
Maximum performance True dual-port memory Simple dual-port memory Single-port memory Shift register ROM FIFO buffer Pack mode Byte enable Address clock enable Parity bits Mixed clock mode Memory initialization (.mif)
M512 RAM Block (32 x 18 Bits)
500 MHz
M4K RAM Block (128 x 36 Bits)
550 MHz
ALM
Source
M-RAM Block (4K x 144 Bits)
420 MHz
v v v v v v v v v v v v v v v v v v v v v
v v v
(1)
v v v v v v
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Row IOE
Stratix II Architecture
Table 2-3. TriMatrix Memory Features (Part 2 of 2) Memory Feature
Simple dual-port memory mixed width support True dual-port memory mixed width support Power-up conditions Register clears Outputs cleared Output registers
M512 RAM Block (32 x 18 Bits) v
M4K RAM Block (128 x 36 Bits) v v
Outputs cleared Output registers
M-RAM Block (4K x 144 Bits) v v
Outputs unknown Output registers
Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output Configurations 512 x 1 256 x 2 128 x 4 64 x 8 64 x 9 32 x 16 32 x 18 4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36 64K x 8 64K x 9 32K x 16 32K x 18 16K x 32 16K x 36 8K x 64 8K x 72 4K x 128 4K x 144
Notes to Table 2-3:
(1) The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The Stratix II device must write to the dual-port memory once and then disable the write-enable ports afterwards.
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient application support. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes. When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately.
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TriMatrix Memory
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:

Simple dual-port RAM Single-port RAM FIFO ROM Shift register Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies to both read and write operations.
1
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The six labclk signals or local interconnect can drive the inclock, outclock, wren, rden, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, ALMs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2-19 shows the M512 RAM block control signal generation logic. The RAM blocks in Stratix II devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. The M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through direct link interconnect. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2-20 shows the M512 RAM block to logic array interface.
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Stratix II Architecture
Figure 2-19. M512 RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 6
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect Local Interconnect inclock
inclocken
outclocken
wren outclr
outclock
rden
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Figure 2-20. M512 RAM Block LAB Row Interface
C4 Interconnect R4 Interconnect
Direct link interconnect to adjacent LAB
16
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M512 RAM Block clocks control signals
Direct link interconnect from adjacent LAB
datain
address
2 6
M512 RAM Block Local Interconnect Region
LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents.
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Stratix II Architecture
The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2-21. The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2-22 shows the M4K RAM block to logic array interface. Figure 2-21. M4K RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect 6
clock_b
clocken_b renwe_a
renwe_b aclr_a
aclr_b
clock_a
clocken_a
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Figure 2-22. M4K RAM Block LAB Row Interface
C4 Interconnect R4 Interconnect
Direct link interconnect to adjacent LAB
16 36 dataout
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB
M4K RAM Block datain control signals clocks byte enable
Direct link interconnect from adjacent LAB
address
6
M4K RAM Block Local Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO
You cannot use an initialization file to initialize the contents of an M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed.
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Stratix II Architecture
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M-RAM block registers (renwe, address, byte enable, datain, and output registers). The output register can be bypassed. The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 2-23. Figure 2-23. M-RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_a clocken_a renwe_a aclr_b renwe_b clocken_b clock_b 6
Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect
aclr_a
The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right or left side drive the M-RAM block local interconnect. Up to 16 direct link input connections to the M-RAM block are possible from the left adjacent LABs and another 16 possible from the right adjacent LAB. M-RAM block outputs can also connect to left and right LABs through direct link interconnect. Figure 2-24 shows an example floorplan for the EP2S130 device and the location of the M-RAM interfaces. Figures 2-25 and 2-26 show the interface between the M-RAM block and the logic array.
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TriMatrix Memory
Figure 2-24. EP2S130 Device with M-RAM Interface Locations Note (1)
M-RAM blocks interface to LABs on right and left sides for easy access to horizontal I/O pins
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M4K Blocks
M512 Blocks
DSP Blocks
LABs
DSP Blocks
Note to Figure 2-24:
(1) The device shown is an EP2S130 device. The number and position of M-RAM blocks varies in other devices.
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Figure 2-25. M-RAM Block LAB Row Interface Note (1)
Row Unit Interface Allows LAB Rows to Drive Port A Datain, Dataout, Address and Control Signals to and from M-RAM Block Row Unit Interface Allows LAB Rows to Drive Port B Datain, Dataout, Address and Control Signals to and from M-RAM Block
L0 L1 M-RAM Block L2 Port A
R0 R1
Port B R2 R3 R4 R5
L3 L4 L5
LAB Interface Blocks LABs in Row M-RAM Boundary LABs in Row M-RAM Boundary
Note to Figure 2-25:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
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TriMatrix Memory
Figure 2-26. M-RAM Row Unit Interface to Interconnect
C4 Interconnect R4 and R24 Interconnects
M-RAM Block
LAB
Up to 16 dataout_a[ ]
16
Direct Link Interconnects
Up to 28
datain_a[ ] addressa[ ] addr_ena_a renwe_a byteenaA[ ] clocken_a clock_a aclr_a
Row Interface Block
M-RAM Block to LAB Row Interface Block Interconnect Region
Table 2-4 shows the input and output data signal connections along with the address and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).
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Stratix II Architecture
Table 2-4. M-RAM Row Interface Unit Signals Unit Interface Block
L0 L1 L2
Input Signals
datain_a[14..0] byteena_a[1..0] datain_a[29..15] byteena_a[3..2] datain_a[35..30] addressa[4..0] addr_ena_a clock_a clocken_a renwe_a aclr_a addressa[15..5] datain_a[41..36] datain_a[56..42] byteena_a[5..4] datain_a[71..57] byteena_a[7..6] datain_b[14..0] byteena_b[1..0] datain_b[29..15] byteena_b[3..2] datain_b[35..30] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b addressb[15..5] datain_b[41..36] datain_b[56..42] byteena_b[5..4] datain_b[71..57] byteena_b[7..6]
Output Signals
dataout_a[11..0] dataout_a[23..12] dataout_a[35..24]
L3 L4 L5 R0 R1 R2
dataout_a[47..36] dataout_a[59..48] dataout_a[71..60] dataout_b[11..0] dataout_b[23..12] dataout_b[35..24]
R3 R4 R5
dataout_b[47..36] dataout_b[59..48] dataout_b[71..60]
f
See the TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on TriMatrix memory.
Altera Corporation May 2007
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Digital Signal Processing Block
Digital Signal Processing Block
The most commonly used DSP functions are FIR filters, complex FIR filters, IIR filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these use the multiplier as the fundamental building block. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Stratix II devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Stratix II device has from two to four columns of DSP blocks to efficiently implement DSP functions faster than ALM-based implementations. Stratix II devices have up to 24 DSP blocks per column (see Table 2-5). Each DSP block can be configured to support up to:

Eight 9 x 9-bit multipliers Four 18 x 18-bit multipliers One 36 x 36-bit multiplier
As indicated, the Stratix II DSP block can support one 36 x 36-bit multiplier in a single DSP block. This is true for any combination of signed, unsigned, or mixed sign multiplications. 1 This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions.
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Stratix II Architecture
Figure 2-27 shows one of the columns with surrounding LAB rows. Figure 2-27. DSP Blocks Arranged in Columns
DSP Block Column
4 LAB Rows
DSP Block
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Digital Signal Processing Block
Table 2-5 shows the number of DSP blocks in each Stratix II device.
Table 2-5. DSP Blocks in Stratix II Devices Note (1) Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180 Note to Table 2-5:
(1) Each device has either the numbers of 9 x 9-, 18 x 18-, or 36 x 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers.
DSP Blocks
12 16 36 48 63 96
Total 9 x 9 Multipliers
96 128 288 384 504 768
Total 18 x 18 Multipliers
48 64 144 192 252 384
Total 36 x 36 Multipliers
12 16 36 48 63 96
DSP block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on the configuration. This makes routing to ALMs easier, saves ALM routing resources, and increases performance, because all connections and blocks are in the DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications, and DSP blocks support Q1.15 format rounding and saturation. Figure 2-28 shows the top-level diagram of the DSP block configured for 18 x 18-bit multiplier mode.
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Stratix II Architecture
Figure 2-28. DSP Block Diagram for 18 x 18-Bit Configuration
Optional Serial Shift Register Inputs from Previous DSP Block
Adder Output Block
PRN D
Multiplier Block
Q PRN
Q1.15 Round/ Saturate
Output Selection Multiplexer
ENA CLRN
D
Q
From the row interface block
D
PRN Q
ENA CLRN
Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor
ENA CLRN
Adder/ Subtractor/ Accumulator 1
Q1.15 Round/ Saturate
D
PRN Q PRN
Q1.15 Round/ Saturate
ENA CLRN
D
Q
D
PRN Q
ENA CLRN Summation Block
Adder
D Q ENA CLRN
ENA CLRN
D
PRN Q PRN
Q1.15 Round/ Saturate
ENA CLRN
D
Q
PRN D Q ENA CLRN
ENA CLRN
Summation Stage for Adding Four Multipliers Together
Adder/ Subtractor/ Accumulator 2
Q1.15 Round/ Saturate
D
PRN Q PRN
Q1.15 Round/ Saturate
ENA CLRN
D
Q
Optional Serial Shift Register Outputs to Next DSP Block in the Column
D
PRN Q
ENA CLRN
Optional Pipline Register Stage
ENA CLRN
Optional Input Register Stage with Parallel Input or Shift Register Configuration
to MultiTrack Interconnect
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Digital Signal Processing Block
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:

Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder
Table 2-6 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication and many other functions. The DSP blocks also support mixed modes and mixed multiplier sizes in the same block. For example, half of one DSP block can implement one 18 x 18-bit multiplier in multiplyaccumulator mode, while the other half of the DSP block implements four 9 x 9-bit multipliers in simple multiplier mode.
Table 2-6. Multiplier Size & Configurations per DSP Block DSP Block Mode
Multiplier Multiply-accumulator Two-multipliers adder
9x9
Eight multipliers with eight product outputs Four two-multiplier adder (two 9 x 9 complex multiply) Two four-multiplier adder
18 x 18
Four multipliers with four product outputs Two 52-bit multiplyaccumulate blocks Two two-multiplier adder (one 18 x 18 complex multiply) One four-multiplier adder
36 x 36
One multiplier with one product output -
Four-multipliers adder
-
DSP Block Interface
Stratix II device DSP block input registers can generate a shift register that can cascade down in the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. You can cascade registers within multiple DSP blocks for 9 x 9- or 18 x 18-bit FIR filters larger than four taps, with additional adder stages implemented in ALMs. If the DSP block is configured as 36 x 36 bits, the adder, subtractor, or accumulator stages are implemented in ALMs. Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks.
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Stratix II Architecture
The DSP block is divided into four block units that interface with four LAB rows on the left and right. Each block unit can be considered one complete 18 x 18-bit multiplier with 36 inputs and 36 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 16 direct link interconnects from the LAB to the left or right of the DSP block in the same row. R4 and C4 routing resources can access the DSP block's local interconnect region. The outputs also work similarly to LAB outputs as well. Eighteen outputs from the DSP block can drive to the left LAB through direct link interconnects and eighteen can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing. Figures 2-29 and 2-30 show the DSP block interfaces to LAB rows. Figure 2-29. DSP Block Interconnect Interface
DSP Block
R4, C4 & Direct Link Interconnects
OA[17..0] OB[17..0] A1[17..0] B1[17..0]
R4, C4 & Direct Link Interconnects
OC[17..0] OD[17..0] A2[17..0] B2[17..0]
OE[17..0] OF[17..0]
A3[17..0] B3[17..0]
OG[17..0] OH[17..0]
A4[17..0] B4[17..0]
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Digital Signal Processing Block
Figure 2-30. DSP Block Interface to Interconnect
C4 Interconnect Direct Link Interconnect from Adjacent LAB R4 Interconnect Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB
36 DSP Block Row Structure
LAB 18
36
LAB
16
16
12 Control 36 A[17..0] B[17..0] OA[17..0] OB[17..0] 36
Row Interface Block
DSP Block to LAB Row Interface Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed/unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface.
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Stratix II Architecture
The LAB row source for control signals, data inputs, and outputs is shown in Table 2-7.
Table 2-7. DSP Block Signal Sources & Destinations LAB Row at Interface
0
Control Signals Generated
clock0 aclr0 ena0 mult01_saturate addnsub1_round/ accum_round addnsub1 signa sourcea sourceb clock1 aclr1 ena1 accum_saturate mult01_round accum_sload sourcea sourceb mode0 clock2 aclr2 ena2 mult23_saturate addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb clock3 aclr3 ena3 accum_saturate mult23_round accum_sload sourcea sourceb mode1
Data Inputs
A1[17..0] B1[17..0]
Data Outputs
OA[17..0] OB[17..0]
1
A2[17..0] B2[17..0]
OC[17..0] OD[17..0]
2
A3[17..0] B3[17..0]
OE[17..0] OF[17..0]
3
A4[17..0] B4[17..0]
OG[17..0] OH[17..0]
f
See the DSP Blocks in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook, for more information on DSP blocks.
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PLLs & Clock Networks
PLLs & Clock Networks
Stratix II devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix II devices provide 16 dedicated global clock networks and 32 regional clock networks (eight per device quadrant). These clocks are organized into a hierarchical clock structure that allows for up to 24 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains in Stratix II devices. There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figures 2-31 and 2-32. Internal logic and enhanced and fast PLL outputs can also drive the global and regional clock networks. Each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enables/disables the clock to reduce power consumption. Table 2-8 shows global and regional clock features.
Table 2-8. Global & Regional Clock Features Feature
Number per device Number available per quadrant Sources Dynamic clock source selection Dynamic enable/disable Note to Table 2-8:
(1) Dynamic source clock selection is supported for selecting between CLKp pins and PLL outputs only.
Global Clocks
16 16 CLK pins, PLL outputs, or internal logic
Regional Clocks
32 8 CLK pins, PLL outputs, or internal logic
v (1) v v
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources in the device-IOEs, ALMs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The
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Stratix II Architecture
global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2-31 shows the 16 dedicated CLK pins driving global clock networks. Figure 2-31. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[11..8]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks RCLK[7..0] in each quadrant of the Stratix II device that are driven by the dedicated CLK[15..0] input pins, by PLL outputs, or by internal logic. The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. The CLK clock pins symmetrically drive the RCLK networks in a particular quadrant, as shown in Figure 2-32.
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PLLs & Clock Networks
Figure 2-32. Regional Clocks
RCLK[31..28] RCLK[27..24]
CLK[15..12]
RCLK[3..0] CLK[3..0]
RCLK[23..20] CLK[11..8]
RCLK[7..4]
RCLK[19..16]
CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins, PLLs or Core Logic within that Quadrant RCLK[11..8] RCLK[15..12]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional clock by driving two regional clock network lines in adjacent quadrants (one from each quadrant). This allows logic that spans multiple quadrants to utilize the same low skew clock. The routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant. Internal logic-array routing can also drive a dual-regional clock. Clock pins and enhanced PLL outputs on the top and bottom can drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on the left and right can drive vertical dual-regional clocks, as shown in Figure 2-33. Corner PLLs cannot drive dual-regional clocks.
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Stratix II Architecture
Figure 2-33. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network Clock Pins or PLL Clock Outputs Can Drive Dual-Regional Network
CLK[15..12]
CLK[15..12]
CLK[3..0]
CLK[11..8]
CLK[3..0]
CLK[11..8]
PLLs
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources consisting of 16 global clock lines and eight regional clock lines. Multiplexers are used with these clocks to form busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select three of the six row clocks to feed the ALM registers in the LAB (see Figure 2-34). Figure 2-34. Hierarchical Clock Networks Per Quadrant
Clocks Available to a Quadrant or Half-Quadrant
Global Clock Network [15..0] Clock [23..0] Lab Row Clock [5..0] Regional Clock Network [7..0] Row I/O Cell IO_CLK[7..0] Column I/O Cell IO_CLK[7..0]
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PLLs & Clock Networks
IOE clocks have row and column block regions that are clocked by eight I/O clock signals chosen from the 24 quadrant clock resources. Figures 2-35 and 2-36 show the quadrant relationship to the I/O clock regions. Figure 2-35. EP2S15 & EP2S30 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0]
8
8
I/O Clock Regions
8
24 Clocks in the Quadrant
24 Clocks in the Quadrant
IO_CLKH[7:0]
8
IO_CLKC[7:0]
8
IO_CLKG[7:0]
24 Clocks in the Quadrant 24 Clocks in the Quadrant
IO_CLKD[7:0]
8
8
8
IO_CLKF[7:0]
IO_CLKE[7:0]
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Stratix II Architecture
Figure 2-36. EP2S60, EP2S90, EP2S130 & EP2S180 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0] IO_CLKC[7:0] IO_CLKD[7:0]
8
8
8
8
I/O Clock Regions
8
8
IO_CLKP[7:0]
24 Clocks in the Quadrant 8 24 Clocks in the Quadrant 8
IO_CLKE[7:0]
IO_CLKO[7:0]
IO_CLKF[7:0]
8
8
IO_CLKN[7:0]
24 Clocks in the Quadrant 8 24 Clocks in the Quadrant 8
IO_CLKG[7:0]
IO_CLKM[7:0]
IO_CLKH[7:0]
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
You can use the Quartus II software to control whether a clock input pin drives either a global, regional, or dual-regional clock network. The Quartus II software automatically selects the clocking resources if not specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its own clock control block. The control block has two functions:

Clock source selection (dynamic selection for global clocks) Clock power-down (dynamic clock enable/disable)
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PLLs & Clock Networks
1
When using the global or regional clock control blocks in Stratix II devices to select between multiple clocks or to enable and disable clock networks, be aware of possible narrow pulses or glitches when switching from one clock signal to another. A glitch or runt pulse has a width that is less than the width of the highest frequency input clock signal. To prevent logic errors within the FPGA, Altera recommends that you build circuits that filter out glitches and runt pulses.
Figures 2-37 through 2-39 show the clock control block for the global clock, regional clock, and PLL external clock output, respectively. Figure 2-37. Global Clock Control Blocks
CLKp Pins PLL Counter Outputs CLKSELECT[1..0] (1) 2 2 CLKn Pin 2 Internal Logic
This multiplexer supports User-Controllable Dynamic Switching
Static Clock Select (2)
Enable/ Disable Internal Logic GCLK
Notes to Figure 2-37:
(1) (2) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode. These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation.
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Stratix II Architecture
Figure 2-38. Regional Clock Control Blocks
CLKp Pin PLL Counter Outputs (3) 2 CLKn Pin (2) Internal Logic Static Clock Select (1)
Enable/ Disable Internal Logic RCLK
Notes to Figure 2-38:
(1) (2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. Only the CLKn pins on the top and bottom of the device feed to regional clock select blocks.The clock outputs from corner PLLs cannot be dynamically selected through the global clock control block. The clock outputs from corner PLLs cannot be dynamically selected through the global clock control block.
(3)
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PLLs & Clock Networks
Figure 2-39. External PLL Output Clock Control Blocks
PLL Counter Outputs (c[5..0]) 6 Static Clock Select (1)
Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1)
PLL_OUT Pin
Notes to Figure 2-39:
(1) (2) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation. The clock control block feeds to a multiplexer within the PLL_OUT pin's IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
For the global clock control block, the clock source selection can be controlled either statically or dynamically. The user has the option of statically selecting the clock source by using the Quartus II software to set specific configuration bits in the configuration file (.sof or .pof) or the user can control the selection dynamically by using internal logic to drive the multiplexor select inputs. When selecting statically, the clock source can be set to any of the inputs to the select multiplexor. When selecting the clock source dynamically, you can either select between two PLL outputs (such as the C0 or C1 outputs from one PLL), between two PLLs (such as the C0/C1 clock output of one PLL or the C0/C1 c1ock output of the other PLL), between two clock pins (such as CLK0 or CLK1), or between a combination of clock pins or PLL outputs. The clock outputs from corner PLLs cannot be dynamically selected through the global control block. For the regional and PLL_OUT clock control block, the clock source selection can only be controlled statically using configuration bits. Any of the inputs to the clock select multiplexor can be set as the clock source.
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Stratix II Architecture
The Stratix II clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device. The global and regional clock networks can be powered down statically through a setting in the configuration (.sof or .pof) file. Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the Quartus II software. The dynamic clock enable/disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and PLL_OUT pins. This function is independent of the PLL and is applied directly on the clock network or PLL_OUT pin, as shown in Figures 2-37 through 2-39. 1 The following restrictions for the input clock pins apply: * * * * CLK0 CLK1 CLK2 CLK3 pin pin pin pin -> -> -> -> inclk[0] inclk[1] inclk[0] inclk[1] of of of of CLKCTRL CLKCTRL CLKCTRL CLKCTRL
In general, even CLK numbers connect to the inclk[0] port of CLKCTRL, and odd CLK numbers connect to the inclk[1] port of CLKCTRL. Failure to comply with these restrictions will result in a no-fit error.
Enhanced & Fast PLLs
Stratix II devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clockfrequency synthesis. With features such as clock switchover, spread-spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the Stratix II device's enhanced PLLs provide you with complete control of clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Stratix II high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth.
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PLLs & Clock Networks
The Quartus II software enables the PLLs and their features without requiring any external devices. Table 2-9 shows the PLLs available for each Stratix II device and their type.
Table 2-9. Stratix II Device PLL Availability Fast PLLs Device 1
EP2S15 EP2S30 EP2S60 (1) EP2S90 (2) EP2S130 (3) EP2S180
Enhanced PLLs 8 9 10 5 v v 6 v v v v v v v v v v v v v v 11 12
2 v v v v v v
3 v v v v v v
4 v v v v v v
7
v v v v v v
v v v v
v v v v
v v v v
v v v v
v v v v
Notes to Table 2-9:
(1) (2) (3) EP2S60 devices in the 1020-pin package contain 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages contain fast PLLs 1-4 and enhanced PLLs 5 and 6. EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin packages contain fast PLLS 1-4 and enhanced PLLs 5 and 6. EP2S130 devices in the 1020-pin and 1508-pin packages contain 12PLLs. The EP2S130 device in the 780-pin package contains fast PLLs 1-4 and enhanced PLLs 5 and 6.
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Table 2-10 shows the enhanced PLL and fast PLL features in Stratix II devices.
Table 2-10. Stratix II PLL Features Feature
Clock multiplication and division Phase shift Clock switchover PLL reconfiguration Reconfigurable bandwidth Spread spectrum clocking Programmable duty cycle Number of internal clock outputs Number of external clock outputs Number of feedback clock inputs Notes to Table 2-10:
(1) (2) (3) (4) (5) (6) (7) (8) For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty cycle. For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4. The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8. For degree increments, Stratix II devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. Stratix II fast PLLs only support manual clock switchover. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin. Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Enhanced PLL
m/(n x post-scale counter) (1) Down to 125-ps increments (3), (4)
Fast PLL
m/(n x post-scale counter) (2) Down to 125-ps increments (3), (4)
v v v v v
6 Three differential/six single-ended One single-ended or differential (7), (8)
v (5) v v v
4 (6)
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PLLs & Clock Networks
Figure 2-40 shows a top-level diagram of the Stratix II device and PLL floorplan. Figure 2-40. PLL Locations
CLK[15..12] 11 5
FPLL7CLK
7
10
FPLL10CLK
CLK[3..0]
1 2
4 3
CLK[8..11]
PLLs
FPLL8CLK
8
9
FPLL9CLK
12
6
CLK[7..4]
Figures 2-41 and 2-42 shows the global and regional clocking from the fast PLL outputs and the side clock pins.
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Figure 2-41. Global & Regional Clock Connections from Center Clock Pins & Fast PLL Outputs Note (1)
CLK11 CLK10 CLK9 C2 C3 C0 C1 C2 Fast PLL 3 C3 CLK8
C0
C1
Fast PLL 4
RCK23 RCK21 RCK19 RCK17 GCK11 GCK9 Logic Array Signal Input To Clock Network GCK2 GCK0 RCK6 RCK4 RCK2 C0 C1 C2 C3 C0 C1 C2 Fast PLL 1 CLK0 CLK1 CLK2 Fast PLL 2
Notes to Figure 2-41:
(1) EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the connectivity from these four PLLs to the global and regional clock networks remains the same as shown. The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2)
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CLK3
C3
RCK0
RCK1
RCK3
RCK5
RCK7
GCK1
GCK3
GCK8
GCK10
RCK16
RCK18
RCK20
RCK22
PLLs & Clock Networks
Figure 2-42. Global & Regional Clock Connections from Corner Clock Pins & Fast PLL Outputs Note (1)
FPLL10CLK FPLL9CLK
Fast PLL 10
C0
C1
C2
C3
C0
C1
C2
Fast PLL 9 C3
RCK23
RCK22
RCK19 RCK17 GCK11 GCK9 GCK2 GCK0 RCK6 C0 C1 C2 C3 C0 C1 C2 Fast PLL 7
FPLL7CLK FPLL8CLK
RCK20
RCK21
RCK3
RCK2
RCK1
RCK0
Note to Figure 2-42:
(1) The corner fast PLLs can also be driven through the global or regional clock networks. The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
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Fast PLL 8
C3
RCK4
Altera Corporation May 2007
RCK5
RCK7
GCK1
GCK3
GCK8
GCK10
RCK16
RCK18
Stratix II Architecture
Figure 2-43 shows the global and regional clocking from enhanced PLL outputs and top and bottom CLK pins. The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs is shown in Table 2-11. The connections to the clocks from the bottom clock pins is shown in Table 2-12.
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PLLs & Clock Networks
Figure 2-43. Global & Regional Clock Connections from Top & Bottom Clock Pins & Enhanced PLL Outputs Notes (1), (2), and (3)
CLK13 CLK12 CLK15 CLK14
PLL11_FB
PLL5_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
PLL11_OUT[2..0]p PLL11_OUT[2..0]n
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p PLL5_OUT[2..0]n RCLK31 RCLK30 RCLK29 RCLK28
Regional Clocks
RCLK27 RCLK26 RCLK25 RCLK24 G15 G14 G13 G12
Global Clocks
G4 G5 G6 G7
Regional Clocks
RCLK8 RCLK9 RCLK10 RCLK11 RCLK12 RCLK13 RCLK14 RCLK15 PLL6_OUT[2..0]p PLL6_OUT[2..0]n
PLL12_OUT[2..0]p PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5 PLL 12
c0 c1 c2 c3 c4 c5
PLL 6
PLL12_FB CLK4 CLK5 CLK6 CLK7
PLL6_FB
Notes to Figure 2-43:
(1) (2) (3) EP2S15 and EP2S30 devices only have two enhanced PLLs (5 and 6), but the connectivity from these two PLLs to the global and regional clock networks remains the same as shown. If the design uses the feedback input, you lose one (or two, if FBIN is differential) external clock output pin. The enhanced PLLs can also be driven through the global or regional clock netowrks. The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
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Stratix II Architecture
Table 2-11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs of 2) DLLCLK RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 CLK12 CLK13 CLK14 Top Side Global & Regional Clock Network Connectivity
Clock pins CLK12p CLK13p CLK14p CLK15p CLK12n CLK13n CLK14n CLK15n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2 GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL 5 outputs c0 c1 c2 c3
(Part 1 RCLK30 v v v v v RCLK31 v v v v v
v v v v
v v
v v v v v v
CLK15
v v v v v
v
v v
v v v v v v v v
v v v v
v v v v v v v v v v v v v v v v v v v v v v v v
v v
v v
v v
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PLLs & Clock Networks
Table 2-11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs of 2) RCLK24 RCLK25 RCLK26 RCLK27 RCLK28 RCLK29 DLLCLK CLK12 CLK13 CLK14 Top Side Global & Regional Clock Network Connectivity
c4 c5 Enhanced PLL 11 outputs c0 c1 c2 c3 c4 c5
(Part 2 RCLK30 v v v RCLK14 v v RCLK31 v v v v v RCLK15
v v v v v v v v v v
CLK15
v v v v
v v
v v v v
v v v v v v v v
Table 2-12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL Outputs (Part 1 of 2) Bottom Side Global & Regional Clock Network Connectivity
Clock pins CLK4p CLK5p CLK6p CLK7p CLK4n CLK5n CLK6n CLK7n Drivers from internal logic GCLKDRV0 GCLKDRV1 GCLKDRV2
RCLK10
RCLK11
RCLK12 v v
v v v v
v v
v v v v v v
v v v v v v v v v v
v
v v
v
v v v
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RCLK13
DLLCLK
RCLK8
RCLK9
CLK4
CLK5
CLK6
CLK7
Stratix II Architecture
Table 2-12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL Outputs (Part 2 of 2) Bottom Side Global & Regional Clock Network Connectivity
GCLKDRV3 RCLKDRV0 RCLKDRV1 RCLKDRV2 RCLKDRV3 RCLKDRV4 RCLKDRV5 RCLKDRV6 RCLKDRV7 Enhanced PLL 6 outputs c0 c1 c2 c3 c4 c5 Enhanced PLL 12 outputs c0 c1 c2 c3 c4 c5
DLLCLK
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14 v v v v v v
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
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RCLK15
RCLK8
RCLK9
CLK4
CLK5
CLK6
CLK7
PLLs & Clock Networks
Enhanced PLLs
Stratix II devices contain up to four enhanced PLLs with advanced clock management features. Figure 2-44 shows a diagram of the enhanced PLL. Figure 2-44. Stratix II Enhanced PLL Note (1)
VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL Post-Scale Counters
Clock Switchover Circuitry INCLK[3..0] 4 /n
Phase Frequency Detector
Spread Spectrum
/c0
/c1 4 PFD Charge Pump Loop Filter 8 VCO /c2 6 /c3 6 /m (2) /c5 FBIN Lock Detect & Filter to I/O or general routing /c4 I/O Buffers (3) 8 Regional Clocks Global Clocks
Global or Regional Clock (4)
Shaded Portions of the PLL are Reconfigurable
VCO Phase Selection Affecting All Outputs
Notes to Figure 2-44:
(1) (2) (3) (4) Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL. If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin. Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs. The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
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Stratix II Architecture
Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial interfacing ability. Figure 2-45 shows a diagram of the fast PLL. Figure 2-45. Stratix II Device Fast PLL Notes (1), (2), (3)
VCO Phase Selection Selectable at each PLL Output Port Post-Scale Counters
Global or regional clock (1)
Clock Switchover Circuitry (4)
Phase Frequency Detector
diffioclk0 (2) /c0 load_en0 (3)
(5)
Clock Input 4 /n PFD Charge Pump Loop Filter VCO /k 8 /c1 4 /c2
Global or regional clock (1)
load_en1 (3) diffioclk1 (2) Global clocks 4 8 Regional clocks
/c3 /m 8 to DPA block
Shaded Portions of the PLL are Reconfigurable
Notes to Figure 2-45:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL. In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a differential I/O SERDES control signal. Stratix II fast PLLs only support manual clock switchover. If the design enables this /2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
(2) (3) (4) (5)
f
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on enhanced and fast PLLs. See "High-Speed Differential I/O with DPA Support" on page 2-96 for more information on high-speed differential I/O support. The Stratix II IOEs provide many features, including:

I/O Structure
Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support On-chip driver series termination On-chip parallel termination On-chip termination for differential standards Programmable pull-up during configuration
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I/O Structure

Output drive strength control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double data rate (DDR) registers
The IOE in Stratix II devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 2-46 shows the Stratix II IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.
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Stratix II Architecture
Figure 2-46. Stratix II IOE Structure
Logic Array OE Register OE
D Q
OE Register
D Q
Output Register Output A
D Q
CLK
Output Register Output B
D Q
Input Register
D Q
Input A Input B Input Register
D Q
Input Latch
D ENA Q
The IOEs are located in I/O blocks around the periphery of the Stratix II device. There are up to four IOEs per row I/O block and four IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2-47 shows how a row I/O block connects to the logic array. Figure 2-48 shows how a column I/O block connects to the logic array.
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I/O Structure
Figure 2-47. Row I/O Block Connection to the Interconnect Note (1)
R4 & R24 Interconnects
C4 Interconnect I/O Block Local Interconnect
32 Data & Control Signals from Logic Array (1)
LAB 32 Horizontal I/O Block
io_dataina[3..0] io_datainb[3..0]
Direct Link Interconnect to Adjacent LAB LAB Local Interconnect
Direct Link Interconnect to Adjacent LAB
io_clk[7:0]
Horizontal I/O Block Contains up to Four IOEs
Note to Figure 2-47:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0].
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Stratix II Architecture
Figure 2-48. Column I/O Block Connection to the Interconnect Note (1)
32 Data & Control Signals from Logic Array (1)
Vertical I/O Block
Vertical I/O Block Contains up to Four IOEs
32
IO_dataina[3:0] IO_datainb[3:0]
io_clk[7..0]
I/O Block Local Interconnect
R4 & R24 Interconnects
LAB
LAB
LAB
LAB Local Interconnect
C4 & C16 Interconnects
Note to Figure 2-48:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0].
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I/O Structure
There are 32 control and data signals that feed each row or column I/O block. These control and data signals are driven from the logic array. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from global or regional clocks (see the "PLLs & Clock Networks" section). Figure 2-49 illustrates the signal paths through the I/O block. Figure 2-49. Signal Path through the I/O Block
Row or Column io_clk[7..0]
To Other IOEs
To Logic Array
io_dataina io_datainb oe ce_in ce_out io_ce_in io_ce_out io_aclr Control Signal Selection aclr/apreset sclr/spreset clk_in io_sclr clk_out io_clk io_dataouta io_dataoutb IOE
io_oe
From Logic Array
Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out. Figure 2-50 illustrates the control signal selection.
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Stratix II Architecture
Figure 2-50. Control Signal Selection per IOE
Dedicated I/O Clock [7..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect io_oe
io_sclr
io_aclr
io_ce_out
io_ce_in
io_clk
clk_out
ce_out
sclr/spreset
clk_in
ce_in
aclr/apreset
oe
Notes to Figure 2-50:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives the control selection multiplexers.
In normal bidirectional operation, the input register can be used for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects.
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I/O Structure
Figure 2-51 shows the IOE in bidirectional configuration. Figure 2-51. Stratix II IOE in Bidirectional I/O Configuration Note (1)
ioe_clk[7..0] Column, Row, or Local Interconnect
oe OE Register
D Q
clkout
ENA CLRN/PRN OE Register tCO Delay VCCIO
ce_out
PCI Clamp (2)
VCCIO
aclr/apreset Chip-Wide Reset Output Register
D Q
Programmable Pull-Up Resistor
Output Pin Delay
On-Chip Termination
sclr/spreset
Drive Strength Control ENA Open-Drain Output CLRN/PRN Input Pin to Logic Array Delay
Input Pin to Input Register Delay
Input Register clkin
D Q
Bus-Hold Circuit
ce_in
ENA CLRN/PRN
Notes to Figure 2-51:
(1) (2) All input signals to the IOE can be inverted at the IOE. The optional PCI clamp is only available on column I/O pins.
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Stratix II Architecture
The Stratix II device IOE includes programmable delays that can be activated to ensure input IOE register-to-logic array register transfers, input pin-to-logic array register transfers, or output IOE register-to-pin transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output and/or output enable registers. Programmable delays are no longer required to ensure zero hold times for logic array register-to-IOE register transfers. The Quartus II Compiler can create the zero hold time for these transfers. Table 2-13 shows the programmable delays for Stratix II devices.
Table 2-13. Stratix II Programmable Delay Chain Programmable Delays
Input pin to logic array delay Input pin to input register delay Output pin delay Output enable register tCO delay
Quartus II Logic Option
Input delay from pin to internal cells Input delay from pin to input register Delay from output register to output pin Delay to output enable pin
The IOE registers in Stratix II devices share the same source for clear or preset. You can program preset or clear for each individual IOE. You can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers.
Double Data Rate I/O Pins
Stratix II devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix II devices support DDR inputs, DDR outputs, and bidirectional DDR modes.
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I/O Structure
When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used in the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times. This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2-52 shows an IOE configured for DDR input. Figure 2-53 shows the DDR input timing diagram. Figure 2-52. Stratix II IOE in DDR Input I/O Configuration Notes (1), (2), (3)
ioe_clk[7..0] Column, Row, or Local Interconnect To DQS Logic Block (3) VCCIO
PCI Clamp (4)
VCCIO
DQS Local Bus (2)
Programmable Pull-Up Resistor
Input Pin to Input RegisterDelay sclr/spreset Input Register
D Q
On-Chip Termination
clkin ce_in aclr/apreset
ENA CLRN/PRN
Bus-Hold Circuit
Chip-Wide Reset Input Register
D Q D
Latch
Q
ENA CLRN/PRN
ENA CLRN/PRN
Notes to Figure 2-52:
(1) (2) (3) (4) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only. The optional PCI clamp is only available on column I/O pins.
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Stratix II Architecture
Figure 2-53. Input Timing Diagram in DDR Mode
Data at input pin B0 A0 B1 A1 B2 A2 B3 A3 B4
CLK
A0
A1
A2
A3
Input To Logic Array
B0 B1 B2 B3
When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from ALMs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a x2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2-54 shows the IOE configured for DDR output. Figure 2-55 shows the DDR output timing diagram.
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I/O Structure
Figure 2-54. Stratix II IOE in DDR Output I/O Configuration Notes (1), (2)
ioe_clk[7..0] Column, Row, or Local Interconnect
oe OE Register
D Q
clkout
ENA CLRN/PRN
ce_out
OE Register tCO Delay
aclr/apreset
VCCIO
PCI Clamp (3)
Chip-Wide Reset OE Register
D Q
VCCIO
sclr/spreset
ENA CLRN/PRN
Used for DDR, DDR2 SDRAM
Programmable Pull-Up Resistor
Output Register
D Q
Output Pin Delay clk Drive Strength Control Open-Drain Output
On-Chip Termination
ENA CLRN/PRN
Output Register
D Q
ENA CLRN/PRN
Bus-Hold Circuit
Notes to Figure 2-54:
(1) (2) All input signals to the IOE can be inverted at the IOE. The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port. Similarly, the aclr and apreset signals are also active-high at the input ports of the DDIO megafunction. The optional PCI clamp is only available on column I/O pins.
(3)
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Stratix II Architecture
Figure 2-55. Output TIming Diagram in DDR Mode
CLK
A1
A2
A3
A4
From Internal Registers
B1 B2 B3 B4
DDR output
B1
A1
B2
A2
B3
A3
B4
A4
The Stratix II IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom (banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of x4, x8/x9, x16/x18, or x32/x36. Table 2-14 shows the number of DQ and DQS buses that are supported per device.
Table 2-14. DQS & DQ Bus Mode Support (Part 1 of 2) Device
EP2S15
Note (1) Number of x8/x9 Groups
4 8 4 8 4 8 18
Package
484-pin FineLine BGA 672-pin FineLine BGA
Number of x4 Groups
8 18 8 18 8 18 36
Number of Number of x16/x18 Groups x32/x36 Groups
0 4 0 4 0 4 8 0 0 0 0 0 0 4
EP2S30
484-pin FineLine BGA 672-pin FineLine BGA
EP2S60
484-pin FineLine BGA 672-pin FineLine BGA 1,020-pin FineLine BGA
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I/O Structure
Table 2-14. DQS & DQ Bus Mode Support (Part 2 of 2) Device
EP2S90
Note (1) Number of x8/x9 Groups
4 8 18 18 8 18 18 18 18
Package
484-pin Hybrid FineLine BGA 780-pin FineLine BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA
Number of x4 Groups
8 18 36 36 18 36 36 36 36
Number of Number of x16/x18 Groups x32/x36 Groups
0 4 8 8 4 8 8 8 8 0 0 4 4 0 4 4 4 4
EP2S130 780-pin FineLine BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA EP2S180 1,020-pin FineLine BGA 1,508-pin FineLine BGA Notes to Table 2-14:
(1)
Check the pin table for each DQS/DQ group in the different modes.
A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. The Stratix II device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom. Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits. Figure 2-56 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.
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Figure 2-56. DQS Phase-Shift Circuitry Notes (1), (2), (3), (4)
From PLL 5 (3) DQSn Pin DQS Pin DQSn Pin DQS Pin CLK[15..12]p (2) DQS Pin DQSn Pin DQS Pin DQSn Pin
t
t
t
t
DQS Phase-Shift Circuitry
t
t
t
t
DQS Logic Blocks
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
Notes to Figure 2-56:
(1) (2) (3) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry. The t module represents the DQS logic block. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phaseshift circuitry. You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom of the device.
(4)
These dedicated circuits combined with enhanced PLL clocking and phase-shift ability provide a complete hardware solution for interfacing to high-speed memory.
f
For more information on external memory interfaces, refer to the External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook.
Programmable Drive Strength
The output buffer for each Stratix II device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of drive strength that the user can control. The default setting used in the Quartus II software is the maximum current strength setting that is used to achieve maximum I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
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Table 2-15 shows the possible settings for the I/O standards with drive strength control.
Table 2-15. Programmable Drive Strength Note (1) I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II HSTL-18 Class I HSTL-18 Class II HSTL-15 Class I HSTL-15 Class II Note to Table 2-15:
(1) The Quartus II software default current setting is the maximum setting for each I/O standard.
IOH / IOL Current Strength Setting (mA) for Column I/O Pins
24, 20, 16, 12, 8, 4 24, 20, 16, 12, 8, 4 16, 12, 8, 4 12, 10, 8, 6, 4, 2 8, 6, 4, 2 12, 8 24, 20, 16 12, 10, 8, 6, 4 20, 18, 16, 8 12, 10, 8, 6, 4 20, 18, 16 12, 10, 8, 6, 4 20, 18, 16
IOH / IOL Current Strength Setting (mA) for Row I/O Pins
12, 8, 4 8, 4 12, 8, 4 8, 6, 4, 2 4, 2 12, 8 16 10, 8, 6, 4 12, 10, 8, 6, 4 8, 6, 4 -
Open-Drain Output
Stratix II devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices.
Bus Hold
Each Stratix II device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its last-driven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, you do not need an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.
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The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when the I/O pin has been configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to weakly pull the signal level to the last-driven state. See the DC & Switching Characteristics chapter in the Stratix II Device Handbook, Volume 1, for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
Programmable Pull-Up Resistor
Each Stratix II device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor (typically 25 k) weakly holds the output to the VCCIO level of the output pin's bank. Programmable pull-up resistors are only supported on user I/O pins, and are not supported on dedicated configuration pins, JTAG pins or dedicated clock pins.
Advanced I/O Standard Support
Stratix II device IOEs support the following I/O standards:

3.3-V LVTTL/LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL (on input and output clocks only) HyperTransport technology Differential 1.5-V HSTL Class I and II Differential 1.8-V HSTL Class I and II Differential SSTL-18 Class I and II Differential SSTL-2 Class I and II
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1.5-V HSTL Class I and II 1.8-V HSTL Class I and II 1.2-V HSTL SSTL-2 Class I and II SSTL-18 Class I and II
Table 2-16 describes the I/O standards supported by Stratix II devices.
Table 2-16. Stratix II Supported I/O Standards (Part 1 of 2) I/O Standard
LVTTL LVCMOS 2.5 V 1.8 V 1.5-V LVCMOS 3.3-V PCI 3.3-V PCI-X mode 1 LVDS LVPECL (1)
Type
Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential
Input Reference Output Supply Board Termination Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
0.75 0.90 0.90 1.25 0.6 0.75 0.9 0.90 3.3 3.3 2.5 1.8 1.5 3.3 3.3 2.5 (3) 3.3 2.5 1.5 1.8 1.8 2.5 1.2 1.5 1.8 1.8 0.75 0.90 0.90 1.25 0.6 0.75 0.9 0.90
HyperTransport technology Differential Differential 1.5-V HSTL Class I and II (2) Differential 1.8-V HSTL Class I and II (2) Differential SSTL-18 Class I and II (2) Differential SSTL-2 Class I and II (2) 1.2-V HSTL(4) 1.5-V HSTL Class I and II 1.8-V HSTL Class I and II SSTL-18 Class I and II Differential Differential Differential Differential Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced
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Table 2-16. Stratix II Supported I/O Standards (Part 2 of 2) I/O Standard
SSTL-2 Class I and II Notes to Table 2-16:
(1) (2) (3) This I/O standard is only available on input and output column clock pins. This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock pins in I/O banks 9,10, 11, and 12. VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 9, 10, 11, and 12). The clock input pins supporting LVDS on banks 3, 4, 7, and 8 use VCCINT for LVDS input operations and have no dependency on the VCCIO level of the bank. 1.2-V HSTL is only supported in I/O banks 4,7, and 8.
Type
Voltage-referenced
Input Reference Output Supply Board Termination Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
1.25 2.5 1.25
(4)
f
For more information on I/O standards supported by Stratix II I/O banks, refer to the Selectable I/O Standards in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook. Stratix II devices contain eight I/O banks and four enhanced PLL external clock output banks, as shown in Figure 2-57. The four I/O banks on the right and left of the device contain circuitry to support high-speed differential I/O for LVDS and HyperTransport inputs and outputs. These banks support all Stratix II I/O standards except PCI or PCI-X I/O pins, and SSTL-18 Class II and HSTL outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, enhanced PLL external clock output banks allow clock output capabilities such as differential support for SSTL and HSTL.
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Figure 2-57. Stratix II I/O Banks Notes (1), (2), (3), (4)
DQS8T VREF0B3 DQS7T VREF1B3 DQS6T VREF3B3 DQS5T VREF4B3 VREF2B3
PLL11
Bank 11
PLL5
Bank 9
DQS4T VREF0B4
DQS3T VREF1B4
DQS2T VREF2B4
DQS1T VREF3B4
DQS0T VREF4B4
PLL7 Bank 3
VREF 4B2
PLL10 Bank 4
VREF 0B5
Bank 2
Bank 5
PLL4 PLL3
VR EF2B2
VR EF1B2
VREF 0B2
PLL1
PLL2
VR EF4B1
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS, 2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I, HSTL-18 Class I, HSTL-15 Class I, LVDS, and HyperTransport standards for input and output operations. HSTL-18 Class II, HSTL-15-Class II, SSTL-18 Class II standards are only supported for input operations.
VR EF3B1
Bank 1
Bank 6
PLL9
VREF 2B1
This I/O bank supports LVDS and LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations.
This I/O bank supports LVDS and LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations.
VREF 1B1
VREF 0B1
Bank 8 PLL8
VREF4B8 DQS8B VREF3B8 VREF2B8 VREF1B8 VREF0B8 DQS5B DQS7B DQS6B
Bank 12
Bank 10
VREF4B7 DQS4B VREF3B7 DQS3B
Bank 7
VREF2B7 DQS2B VREF1B7 DQS1B VREF0B7 DQS0B
PLL12
PLL6
Notes to Figure 2-57:
(1) (2) (3) Figure 2-57 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. Depending on the size of the device, different device members have different numbers of VREF groups. Refer to the pin list and the Quartus II software for exact locations. Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank 10, the voltage level at VREFB7 is the reference voltage level for the SSTL input. Horizontal I/O banks feature SERDES and DPA circuitry for high speed differential I/O standards. See the High Speed Differential I/O Interfaces in Stratix II & Stratix II GX Devices chapter of the Stratix II Device Handbook, Volume 2 or the Stratix II GX Device Handbook, Volume 2 for more information on differential I/O standards.
(4)
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VREF 4B6
VREF 3B6
VREF 2B6
I/O banks 7, 8, 10 & 12 support all single-ended I/O standards and differential I/O standards except for HyperTransport technology for both input and output operations.
VR EF1B6
VR EF0B6
VREF 4B5
VR EF3B5
VR EF2B5
This I/O bank supports LVDS and LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations.
I/O banks 3, 4, 9 & 11 support all single-ended I/O standards and differential I/O standards except for HyperTransport technology for both input and output operations.
This I/O bank supports LVDS and LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations.
VR EF3B 2
VR EF1B 5
Stratix II Architecture
Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different VCCIO level independently. Each bank also has dedicated VREF pins to support the voltage-referenced standards (such as SSTL-2). The PLL banks utilize the adjacent VREF group when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank 10, the voltage level at VREFB7 is the reference voltage level for the SSTL input. I/O pins that reside in PLL banks 9 through 12 are powered by the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are powered by the VCCIO3 pin, and any I/O pins that reside in bank 12 are powered by the VCCIO8 pin. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one VREF voltage level. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.
On-Chip Termination
Stratix II devices provide differential (for the LVDS or HyperTransport technology I/O standard), series, and parallel on-chip termination to reduce reflections and maintain signal integrity. On-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. Stratix II devices provide four types of termination:

Differential termination (RD) Series termination (RS) without calibration Series termination (RS) with calibration Parallel termination (RT) with calibration
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Table 2-17 shows the Stratix II on-chip termination support per I/O bank.
Table 2-17. On-Chip Termination Support by I/O Banks (Part 1 of 2) On-Chip Termination Support
Series termination without calibration
I/O Standard Support
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVTTL 1.5-V LVCMOS SSTL-2 Class I and II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.2-V HSTL
Top & Bottom Banks v v v v v v v v v v v v v v v
Left & Right Banks v v v v v v v v v v v v
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Table 2-17. On-Chip Termination Support by I/O Banks (Part 2 of 2) On-Chip Termination Support
Series termination with calibration
I/O Standard Support
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL 2.5-V LVCMOS 1.8-V LVTTL 1.8-V LVCMOS 1.5-V LVTTL 1.5-V LVCMOS SSTL-2 Class I and II SSTL-18 Class I and II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.2-V HSTL
Top & Bottom Banks v v v v v v v v v v v v v v v v v v v v
Left & Right Banks
Parallel termination with calibration
SSTL-2 Class I and II SSTL-18 Class I and II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I and II 1.2-V HSTL
Differential termination (1)
LVDS HyperTransport technology
v v
Note to Table 2-17:
(1) Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip termination. Clock pins CLK0, CLK2, CLK8, and CLK10 do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
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Differential On-Chip Termination
Stratix II devices support internal differential termination with a nominal resistance value of 100 for LVDS or HyperTransport technology input receiver buffers. LVPECL input signals (supported on clock pins only) require an external termination resistor. Differential on-chip termination is supported across the full range of supported differential data rates as shown in the DC & Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook.
f
For more information on differential on-chip termination, refer to the High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook. For more information on tolerance specifications for differential on-chip termination, refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook.
f
On-Chip Series Termination Without Calibration
Stratix II devices support driver impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, reflections can be significantly reduced. Stratix II devices support on-chip series termination for single-ended I/O standards with typical RS values of 25 and 50 Once matching impedance is selected, current drive strength is . no longer selectable. Table 2-17 shows the list of output standards that support on-chip series termination without calibration.
On-Chip Series Termination with Calibration
Stratix II devices support on-chip series termination with calibration in column I/O pins in top and bottom banks. There is one calibration circuit for the top I/O banks and one circuit for the bottom I/O banks. Each on-chip series termination calibration circuit compares the total impedance of each I/O buffer to the external 25- or 50- resistors connected to the RUP and RDN pins, and dynamically enables or disables the transistors until they match. Calibration occurs at the end of device configuration. Once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers.
f
For more information on series on-chip termination supported by Stratix II devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook.
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f
For more information on tolerance specifications for on-chip termination with calibration, refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook.
On-Chip Parallel Termination with Calibration
Stratix II devices support on-chip parallel termination with calibration for column I/O pins only. There is one calibration circuit for the top I/O banks and one circuit for the bottom I/O banks. Each on-chip parallel termination calibration circuit compares the total impedance of each I/O buffer to the external 50- resistors connected to the RUP and RDN pins and dynamically enables or disables the transistors until they match. Calibration occurs at the end of device configuration. Once the calibration circuit finds the correct impedance, it powers down and stops changing the characteristics of the drivers. 1 On-chip parallel termination with calibration is only supported for input pins.
f
For more information on on-chip termination supported by Stratix II devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook. For more information on tolerance specifications for on-chip termination with calibration, refer to the DC & Switching Characteristics chapter in volume 1 of the Stratix II Device Handbook.
f
MultiVolt I/O Interface
The Stratix II architecture supports the MultiVolt I/O interface feature that allows Stratix II devices in all packages to interface with systems of different supply voltages. The Stratix II VCCINT pins must always be connected to a 1.2-V power supply. With a 1.2-V VCCINT level, input pins are 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-, 1.8-, 2.5-, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). The Stratix II VCCPD power pins must be connected to a 3.3-V power supply. These power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. The VCCPD pins also power configuration input pins and JTAG input pins.
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Table 2-18 summarizes Stratix II MultiVolt I/O support.
Table 2-18. Stratix II MultiVolt I/O Support Note (1) Input Signal (V) VCCIO (V)
1.2 1.5 1.8 2.5 3.3
(1) (2)
Output Signal (V) 3.3
v (2) v (2) v (2) v v
1.2
(4) (4) (4) (4) (4)
1.5
v (2) v v
1.8
v (2) v v
2.5
v (2) v (2) v (2) v v
1.2
v (4) v (3) v (3) v (3) v (3)
1.5
v v (3) v (3) v (3)
1.8
2.5
3.3
5.0
v v (3) v (3) v v (3) v v
Notes to Table 2-18:
To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and LVCMOS input levels to overdrive input buffer option in the Quartus II software. The pin current may be slightly higher than the default value. You must verify that the driving device's VO L maximum and VO H minimum voltages do not violate the applicable Stratix II VI L maximum and VI H minimum voltage specifications. Although VCCIO specifies the voltage necessary for the Stratix II device to drive out, a receiving device powered at a different level can still interface with the Stratix II device if it has inputs that tolerate the VCCIO value. Stratix II devices do not support 1.2-V LVTTL and 1.2-V LVCMOS. Stratix II devices support 1.2-V HSTL.
(3) (4)
The TDO and nCEO pins are powered by VCCIO of the bank that they reside in. TDO is in I/O bank 4 and nCEO is in I/O bank 7. Ideally, the VCC supplies for the I/O buffers of any two connected pins are at the same voltage level. This may not always be possible depending on the VCCIO level of TDO and nCEO pins on master devices and the configuration voltage level chosen by VCCSEL on slave devices. Master and slave devices can be in any position in the chain. Master indicates that it is driving out TDO or nCEO to a slave device. For multi-device passive configuration schemes, the nCEO pin of the master device drives the nCE pin of the slave device. The VCCSEL pin on the slave device selects which input buffer is used for nCE. When VCCSEL is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When VCCSEL is logic low it selects the 3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the VCCIO of the nCEO bank in a master device match the VCCSEL settings for the nCE input buffer of the slave device it is connected to, but that may not be possible depending on the application. Table 2-19 contains board design recommendations to ensure that nCEO can successfully drive nCE for all power supply combinations.
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Table 2-19. Board Design Recommendations for nCEO Stratix II nCEO VCCIO Voltage Level in I/O Bank 7 nCE Input Buffer Power in I/O Bank 3
VCCSEL high (VC C I O Bank 3 = 1.5 V) VCCSEL high (VC C I O Bank 3 = 1.8 V) VCCSEL low (nCE Powered by VC C P D = 3.3V)
Notes to Table 2-19:
(1) (2) (3) (4) (5) (6) Input buffer is 3.3-V tolerant. The nCEO output buffer meets VO H (MIN) = 2.4 V. Input buffer is 2.5-V tolerant. The nCEO output buffer meets VOH (MIN) = 2.0 V. Input buffer is 1.8-V tolerant. An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
VC C I O = 3.3 V v(1), (2) v (1), (2) v
VC C I O = 2.5 V v (3), (4) v (3), (4) v (4)
VC C I O = 1.8 V v (5) v v (6)
VC C I O = 1.5 V v v
Level shifter required
VC C I O = 1.2 V v
Level shifter required Level shifter required
For JTAG chains, the TDO pin of the first device drives the TDI pin of the second device in the chain. The VCCSEL input on JTAG input I/O cells (TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the VCCIO of the TDO bank from the first device to match the VCCSEL settings for TDI on the second device, but that may not be possible depending on the application. Table 2-20 contains board design recommendations to ensure proper JTAG chain operation.
Table 2-20. Supported TDO/TDI Voltage Combinations (Part 1 of 2) Device
Stratix II
Stratix II TDO VC C I O Voltage Level in I/O Bank 4 TDI Input Buffer Power V C C I O = 3.3 V VC C I O = 2.5 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V
Always VC C P D (3.3V)
v (1)
v (2)
v (3)
Level shifter required
Level shifter required
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Table 2-20. Supported TDO/TDI Voltage Combinations (Part 2 of 2) Device Stratix II TDO VC C I O Voltage Level in I/O Bank 4 TDI Input Buffer Power V C C I O = 3.3 V VC C I O = 2.5 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V v (1) v (1), (4) v (1), (4) v (1), (4) v (2) v (2) v (2), (5) v (2), (5) v (3) v (3) v v (6)
Level shifter required Level shifter required Level shifter required Level shifter required Level shifter required Level shifter required
Non-Stratix II VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V VCC = 1.5 V Notes to Table 2-20:
(1) (2) (3) (4) (5) (6)
v
v
The TDO output buffer meets VOH (MIN) = 2.4 V. The TDO output buffer meets VOH (MIN) = 2.0 V. An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal. Input buffer must be 3.3-V tolerant. Input buffer must be 2.5-V tolerant. Input buffer must be 1.8-V tolerant.
High-Speed Differential I/O with DPA Support
Stratix II devices contain dedicated circuitry for supporting differential standards at speeds up to 1 Gbps. The LVDS and HyperTransport differential I/O standards are supported in the Stratix II device. In addition, the LVPECL I/O standard is supported on input and output clock pins on the top and bottom I/O banks. The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications:

SPI-4 Phase 2 (POS-PHY Level 4) SFI-4 Parallel RapidIO HyperTransport technology
There are four dedicated high-speed PLLs in the EP2S15 to EP2S30 devices and eight dedicated high-speed PLLs in the EP2S60 to EP2S180 devices to multiply reference clocks and drive high-speed differential SERDES channels. Tables 2-21 through 2-26 show the number of channels that each fast PLL can clock in each of the Stratix II devices. In Tables 2-21 through 2-26 the first row for each transmitter or receiver provides the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 484-pin FineLine BGA EP2S15
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device, PLL 1 can drive a maximum of 10 transmitter channels in I/O bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The Quartus II software may also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels.
Table 2-21. EP2S15 Device Differential Channels Package
484-pin FineLine BGA
Note (1) Center Fast PLLs PLL 1
10 19 11 21 10 19 11 21
Transmitter/ Receiver
Transmitter
Total Channels
38 (2) (3)
PLL 2
9 19 10 21 9 19 10 21
PLL 3
9 19 10 21 9 19 10 21
PLL 4
10 19 11 21 10 19 11 21
Receiver
42 (2) (3)
672-pin FineLine BGA
Transmitter
38 (2) (3)
Receiver
42 (2) (3)
Table 2-22. EP2S30 Device Differential Channels Package
484-pin FineLine BGA
Note (1) Center Fast PLLs PLL 1
10 19 11 21 16 29 17 31
Transmitter/ Receiver
Transmitter
Total Channels
38 (2) (3)
PLL 2
9 19 10 21 13 29 14 31
PLL 3
9 19 10 21 13 29 14 31
PLL 4
10 19 11 21 16 29 17 31
Receiver
42 (2) (3)
672-pin FineLine BGA
Transmitter
58 (2) (3)
Receiver
62 (2) (3)
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High-Speed Differential I/O with DPA Support
Table 2-23. EP2S60 Differential Channels Package
484-pin FineLine BGA
Note (1) Corner Fast PLLs (4) PLL 7
10 11 16 17 21 21 -
Center Fast PLLs Transmitter/ Total Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
Transmitter 38 (2) (3) Receiver 42 (2) (3) 10 19 11 21 16 29 17 31 21 42 21 42 9 19 10 21 13 29 14 31 21 42 21 42 9 19 10 21 13 29 14 31 21 42 21 42 10 19 11 21 16 29 17 31 21 42 21 42
PLL 8
9 10 13 14 21 21 -
PLL 9 PLL 10
9 10 13 14 21 21 10 11 16 17 21 21 -
672-pin FineLine BGA
Transmitter
58 (2) (3)
Receiver
62 (2) (3)
1,020-pin FineLine BGA
Transmitter
84 (2) (3)
Receiver
84 (2) (3)
Table 2-24. EP2S90 Differential Channels Package
Note (1) Corner Fast PLLs (4) PLL 7
23 23 30 30 -
Center Fast PLLs Transmitter/ Total Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
38 (2) (3) 42 (2) (3) 10 19 11 21 16 32 17 34 23 45 23 46 30 59 30 59 9 19 10 21 16 32 17 34 22 45 24 46 29 59 29 59 9 19 10 21 16 32 17 34 22 45 24 46 29 59 29 59 10 19 11 21 16 32 17 34 23 45 23 46 30 59 30 59
PLL 8
22 24 29 29 -
PLL 9 PLL 10
22 24 29 29 23 23 30 30 -
484-pin Hybrid Transmitter FineLine BGA Receiver
780-pin FineLine BGA
Transmitter
64 (2) (3)
Receiver
68 (2) (3)
1,020-pin FineLine BGA
Transmitter
90 (2) (3)
Receiver
94 (2) (3)
1,508-pin FineLine BGA
Transmitter
118 (2) (3)
Receiver
118 (2) (3)
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Stratix II Architecture
Table 2-25. EP2S130 Differential Channels Package
780-pin FineLine BGA
Note (1) Corner Fast PLLs (4) PLL 7
22 23 37 37 -
Center Fast PLLs Transmitter/ Total Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
Transmitter 64 (2) (3) Receiver 68 (2) (3) 16 32 17 34 22 44 23 46 37 78 37 78 16 32 17 34 22 44 23 46 41 78 41 78 16 32 17 34 22 44 23 46 41 78 41 78 16 32 17 34 22 44 23 46 37 78 37 78
PLL 8
22 23 41 41 -
PLL 9 PLL 10
22 23 41 41 22 23 37 37 -
1,020-pin FineLine BGA
Transmitter
88 (2) (3)
Receiver
92 (2) (3)
1,508-pin FineLine BGA
Transmitter
156 (2) (3)
Receiver
156 (2) (3)
Table 2-26. EP2S180 Differential Channels Package
1,020-pin FineLine BGA
Note (1) Corner Fast PLLs (4) PLL 7
22 23 37 37 -
Center Fast PLLs Transmitter/ Total Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
Transmitter 88 (2) (3) Receiver 92 (2) (3) 22 44 23 46 37 78 37 78 22 44 23 46 41 78 41 78 22 44 23 46 41 78 41 78 22 44 23 46 37 78 37 78
PLL 8
22 23 41 41 -
PLL 9 PLL 10
22 23 41 41 22 23 37 37 -
1,508-pin FineLine BGA
Transmitter
156 (2) (3)
Receiver
156 (2) (3)
Notes to Tables 2-21 to 2-26:
(1) (2) (3) (4) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels. This is the maximum number of channels the PLLs can directly drive. This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL. The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL. Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and 4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
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High-Speed Differential I/O with DPA Support
Dedicated Circuitry with DPA Support
Stratix II devices support source-synchronous interfacing with LVDS or HyperTransport signaling at up to 1 Gbps. Stratix II devices can transmit or receive serial channels along with a low-speed or high-speed clock. The receiving device PLL multiplies the clock by an integer factor W = 1 through 32. For example, a HyperTransport technology application where the data rate is 1,000 Mbps and the clock rate is 500 MHz would require that W be set to 2. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL clock-multiplication W value. A design using the dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the Stratix II device bypasses the SERDES block. For a J factor of 2, the Stratix II device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. Figure 2-58 shows the block diagram of the Stratix II transmitter channel. Figure 2-58. Stratix II Transmitter Channel
Data from R4, R24, C4, or direct link interconnect
+ - 10 10
Up to 1 Gbps
Local Interconnect
Dedicated Transmitter Interface
diffioclk refclk Fast PLL load_en Regional or global clock
Each Stratix II receiver channel features a DPA block for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic sourcesynchronous operation of the channel. In addition, you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array. Figure 2-59 shows the block diagram of the Stratix II receiver channel.
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Stratix II Architecture
Figure 2-59. Stratix II Receiver Channel
Data to R4, R24, C4, or direct link interconnect Up to 1 Gbps
+ - D Q
Data Realignment Circuitry
10
data
retimed_data DPA DPA_clk Synchronizer
Dedicated Receiver Interface
Eight Phase Clocks
8
diffioclk refclk Fast PLL load_en Regional or global clock
An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. In addition, eight phase-shifted clocks from the VCO can feed to the DPA circuitry.
f
For more information on the fast PLL, see the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook. The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data. This allows the source-synchronous circuitry to capture incoming data correctly regardless of the channel-tochannel or clock-to-channel skew. The DPA block locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used to write the data into the synchronizer. The synchronizer sits between the DPA block and the data realignment and SERDES circuitry. Since every channel utilizing the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry.
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High-Speed Differential I/O with DPA Support
For high-speed source synchronous interfaces such as POS-PHY 4, Parallel RapidIO, and HyperTransport, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. The Stratix II device's high-speed differential I/O circuitry provides dedicated data realignment circuitry for usercontrolled byte boundary shifting. This simplifies designs while saving ALM resources. You can use an ALM-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment.
Fast PLL & Channel Layout
The receiver and transmitter channels are interleaved such that each I/O bank on the left and right side of the device has one receiver channel and one transmitter channel per LAB row. Figure 2-60 shows the fast PLL and channel layout in the EP2S15 and EP2S30 devices. Figure 2-61 shows the fast PLL and channel layout in the EP2S60 to EP2S180 devices. Figure 2-60. Fast PLL & Channel Layout in the EP2S15 & EP2S30 Devices Note (1)
4 LVDS Clock 4 2 Fast PLL 1 Fast PLL 4 2 DPA Clock Quadrant Quadrant DPA Clock LVDS Clock 4
4
2
Fast PLL 2
Fast PLL 3
2
4
LVDS Clock
DPA Clock
Quadrant
Quadrant
DPA Clock
LVDS Clock
4
Note to Figure 2-60:
(1) See Table 2-21 for the number of channels each device supports.
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Stratix II Architecture
Figure 2-61. Fast PLL & Channel Layout in the EP2S60 to EP2S180 Devices Note (1)
Fast PLL 7 2 4 LVDS Clock 4 2 Fast PLL 1 Fast PLL 4 2 DPA Clock Quadrant Quadrant DPA Clock LVDS Clock 4 Fast PLL 10 2
4
2
Fast PLL 2
Fast PLL 3
2
4
LVDS Clock
DPA Clock
Quadrant
Quadrant
DPA Clock
LVDS Clock
4
2 Fast PLL 8 Fast PLL 9
2
Note to Figure 2-61:
(1) See Tables 2-22 through 2-26 for the number of channels each device supports.
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Document Revision History
Document Revision History
Table 2-27 shows the revision history for this chapter.
Table 2-27. Document Revision History (Part 1 of 2) Date and Document Version Changes Made Summary of Changes
-- -- -- --
May 2007, v4.3 Updated "Clock Control Block" section. Updated note in the "Clock Control Block" section. Deleted Tables 2-11 and 2-12. Updated notes to: Figure 2-41 Figure 2-42 Figure 2-43 Figure 2-45
Updated notes to Table 2-18. Moved Document Revision History to end of the chapter. August 2006, v4.2 April 2006, v4.1 Updated Table 2-18 with note.

-- -- --
Updated Table 2-13. Removed Note 2 from Table 2-16. Updated "On-Chip Termination" section and Table 2-19 to include parallel termination with calibration information. Added new "On-Chip Parallel Termination with Calibration" section. Updated Figure 2-44.
Added parallel onchip termination description and specification. Changed RCLK names to match the Quartus II software in Table 2-13. -- --
December 2005, v4.0 July 2005, v3.1
Updated "Clock Control Block" section.

Updated HyperTransport technology information in Table 2-18. Updated HyperTransport technology information in Figure 2-57. Added information on the asynchronous clear signal. Updated "Functional Description" section. Updated Table 2-3. Updated "Clock Control Block" section. Updated Tables 2-17 through 2-19. Updated Tables 2-20 through 2-22. Updated Figure 2-57. Updated "Functional Description" section. Updated Table 2-3.
May 2005, v3.0

--
March 2005, 2.1

--
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Stratix II Architecture
Table 2-27. Document Revision History (Part 2 of 2) Date and Document Version
January 2005, v2.0 October 2004, v1.2 July 2004, v1.1

Changes Made
Updated the "MultiVolt I/O Interface" and "TriMatrix Memory" sections. Updated Tables 2-3, 2-17, and 2-19. Updated Tables 2-9, 2-16, 2-26, and 2-27. Updated note to Tables 2-9 and 2-16. Updated Tables 2-16, 2-17, 2-18, 2-19, and 2-20. Updated Figures 2-41, 2-42, and 2-57. Removed 3 from list of SERDES factor J. Updated "High-Speed Differential I/O with DPA Support" section. In "Dedicated Circuitry with DPA Support" section, removed XSBI and changed RapidIO to Parallel RapidIO.
Summary of Changes
--
-- --

February 2004, Added document to the Stratix II Device Handbook. v1.0
--
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Document Revision History
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3. Configuration & Testing
SII51003-4.2
IEEE Std. 1149.1 JTAG BoundaryScan Support
All Stratix(R) II devices provide Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Stratix II devices can also use the JTAG port for configuration with the Quartus(R) II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Stratix II devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode through the CONFIG_IO instruction. You can use this capability for JTAG testing before configuration when some of the Stratix II pins drive or receive from other devices on the board using voltage-referenced standards. Because the Stratix II device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows you to fully test I/O connections to other devices. A device operating in JTAG mode uses four required pins, TDI,TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI,TMS and TRST pins have weak internal pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The TDO output pin is powered by the VCCIO power supply of bank 4. Stratix II devices also use the JTAG port to monitor the logic operation of the device with the SignalTap(R) II embedded logic analyzer. Stratix II devices support the JTAG instructions shown in Table 3-1. 1 Stratix II, Stratix, Cyclone(R) II, and Cyclone devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix II, Stratix, Cyclone II, or Cyclone devices are in the 18th of further position, they fail configuration. This does not affect SignalTap II.
The Stratix II device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables 3-2 and 3-3 show the boundary-scan register length and device IDCODE information for Stratix II devices.
Altera Corporation May 2007
3-1
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3-1. Stratix II JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
00 0000 0101
Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Used when configuring a Stratix II device via the JTAG port with a USB Blaster, MasterBlasterTM, ByteBlasterMVTM, or ByteBlaster II download cable, or when using a .jam or .jbc via an embedded processor or JRunner.
EXTEST(1)
00 0000 1111
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE HIGHZ (1)
00 0000 0110 00 0000 1011
CLAMP (1)
00 0000 1010
ICR instructions
PULSE_NCONFIG CONFIG_IO (2)
00 0000 0001 00 0000 1101
Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, during, or after configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction holds nSTATUS low to reset the configuration device. nSTATUS is held low until the IOE configuration register is loaded and the TAP controller state machine transitions to the UPDATE_DR state. Monitors internal device operation with the SignalTap II embedded logic analyzer.
SignalTap II instructions Notes to Table 3-1:
(1) (2)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST. For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for Altera Devices White Paper.
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Configuration & Testing
The Quartus II software has an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. Turn on the Auto Usercode option by clicking Device & Pin Options, then General, in the Settings dialog box (Assignments menu).
Table 3-2. Stratix II Boundary-Scan Register Length Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Boundary-Scan Register Length
1,140 1,692 2,196 2,748 3,420 3,948
Table 3-3. 32-Bit Stratix II Device IDCODE IDCODE (32 Bits) (1) Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180 Notes to Table 3-3:
(1) (2) The most significant bit (MSB) is on the left. The IDCODE's least significant bit (LSB) is always 1.
Version (4 Bits)
0000 0000 0001 0000 0000 0000
Part Number (16 Bits)
0010 0000 1001 0001 0010 0000 1001 0010 0010 0000 1001 0011 0010 0000 1001 0100 0010 0000 1001 0101 0010 0000 1001 0110
Manufacturer Identity (11 LSB (1 Bit) (2) Bits)
000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 1 1 1 1 1 1
1
Stratix, Stratix II, Cyclone, and Cyclone II devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Stratix II, Cyclone, and Cyclone II devices are in the 18th or after they fail configuration. This does not affect SignalTap II.
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SignalTap II Embedded Logic Analyzer
f
For more information on JTAG, see the following documents:
The IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices chapter of the Stratix II Device Handbook, Volume 2 or the Stratix II GX Device Handbook, Volume 2 Jam Programming & Test Language Specification
SignalTap II Embedded Logic Analyzer
Stratix II devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA(R) packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Stratix II architecture are configured with CMOS SRAM elements. Altera(R) FPGA devices are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification. Stratix II devices are configured at system power-up with data stored in an Altera configuration device or provided by an external controller (e.g., a MAX(R) II device or microprocessor). Stratix II devices can be configured using the fast passive parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous (PPA), and JTAG configuration schemes. The Stratix II device's optimized interface allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Stratix II devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. In addition to the number of configuration methods supported, Stratix II devices also offer the design security, decompression, and remote system upgrade features. The design security feature, using configuration bitstream encryption and AES technology, provides a mechanism to protect your designs. The decompression feature allows Stratix II FPGAs to receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. The remote system upgrade feature allows real-time system upgrades from remote locations of your Stratix II designs. For more information, see "Configuration Schemes" on page 3-7.
Configuration
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Configuration & Testing
Operating Modes
The Stratix II architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow Stratix II devices to be reconfigured in-circuit by loading new configuration data into the device. With realtime reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely. PORSEL is a dedicated input pin used to select POR delay times of 12 ms or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms; when the PORSEL pin is connected to VCC, the POR time is 12 ms. The nIO PULLUP pin is a dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-ups, while a logic low turns them on. Stratix II devices also offer a new power supply, VCCPD, which must be connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input pins and JTAG pins. VCCPD applies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and the configuration input pins when VCCSEL is connected to ground. See Table 3-4 for more information on the pins affected by VCCSEL. The VCCSEL pin allows the VCCIO setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. Therefore, when selecting the VCCIO, the VIL and VIH levels driven to the configuration inputs do not have to be a concern.
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Configuration
The PLL_ENA pin and the configuration input pins (Table 3-4) have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input buffer is used. The 3.3V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by VCCIO. Table 3-4 shows the pins affected by VCCSEL.
Table 3-4. Pins Affected by the Voltage Level at VCCSEL Pin
nSTATUS (when used as an input) nCONFIG CONF_DONE
(when used as an input)
VCCSEL = LOW (connected to GND)
VCCSEL = HIGH (connected to VCCPD)
DATA[7..0] nCE DCLK (when used as an input) CS nWS nRS nCS CLKUSR DEV_OE DEV_CLRn RUnLU PLL_ENA
3.3/2.5-V input buffer is selected. Input buffer is powered by VC C P D . 1.8/1.5-V input buffer is selected. Input buffer is powered by VC C I O of the I/O bank.
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting cannot change on the fly or during a reconfiguration. The VCCSEL input buffer is powered by VCCINT and must be hardwired to VCCPD or ground. A logic high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the logic levels driven out of the configuration device or MAX(R) II/microprocessor. If you need to support configuration input voltages of 3.3 V/2.5 V, you should set the VCCSEL to a logic low; you can set the VCCIO of the I/O bank that contains the configuration inputs to any supported voltage. If
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Configuration & Testing
you need to support configuration input voltages of 1.8 V/1.5 V, you should set the VCCSEL to a logic high and the VCCIO of the bank that contains the configuration inputs to 1.8 V/1.5 V.
f
For more information on multi-volt support, including information on using TDO and nCEO in multi-volt systems, refer to the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Configuration Schemes
You can load the configuration data for a Stratix II device with one of five configuration schemes (see Table 3-5), chosen on the basis of the target application. You can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix II device. A configuration device can automatically configure a Stratix II device at system power-up. You can configure multiple Stratix II devices in any of the five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Stratix II FPGAs offer the following:

Configuration data decompression to reduce configuration file storage Design security using configuration data encryption to protect your designs Remote system upgrades for remotely updating your Stratix II designs
Table 3-5 summarizes which configuration features can be used in each configuration scheme.
Table 3-5. Stratix II Configuration Features (Part 1 of 2) Configuration Scheme
FPP
Configuration Method
MAX II device or microprocessor and flash device Enhanced configuration device
Design Security Decompression v (1) v (1) v (2) v v v v v v v v
Remote System Upgrade v v v (3) v v
AS PS
Serial configuration device MAX II device or microprocessor and flash device Enhanced configuration device Download cable (4)
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Configuration
Table 3-5. Stratix II Configuration Features (Part 2 of 2) Configuration Scheme
PPA JTAG
Configuration Method
MAX II device or microprocessor and flash device Download cable (4) MAX II device or microprocessor and flash device
Design Security Decompression
Remote System Upgrade v
Notes for Table 3-5:
(1) (2) (3) (4) In these modes, the host system must send a DCLK that is 4x the data rate. The enhanced configuration device decompression feature is available, while the Stratix II decompression feature is not available. Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported. The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable, MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the ByteBlasterMV parallel port download cable.
f
See the Configuring Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information about configuration schemes in Stratix II and Stratix II GX devices.
Device Security Using Configuration Bitstream Encryption
Stratix II FPGAs are the industry's first FPGAs with the ability to decrypt a configuration bitstream using the Advanced Encryption Standard (AES) algorithm. When using the design security feature, a 128-bit security key is stored in the Stratix II FPGA. To successfully configure a Stratix II FPGA that has the design security feature enabled, it must be configured with a configuration file that was encrypted using the same 128-bit security key. The security key can be stored in non-volatile memory inside the Stratix II device. This non-volatile memory does not require any external devices, such as a battery back-up, for storage.
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Configuration & Testing
1
An encryption configuration file is the same size as a nonencryption configuration file. When using a serial configuration scheme such as passive serial (PS) or active serial (AS), configuration time is the same whether or not the design security feature is enabled. If the fast passive parallel (FPP) scheme us used with the design security or decompression feature, a 4x DCLK is required. This results in a slower configuration time when compared to the configuration time of an FPGA that has neither the design security, nor decompression feature enabled. For more information about this feature, refer to AN 341: Using the Design Security Feature in Stratix II Devices. Contact your local Altera sales representative to request this document.
Device Configuration Data Decompression
Stratix II FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory, and transmit this compressed bit stream to Stratix II FPGAs. During configuration, the Stratix II FPGA decompresses the bit stream in real time and programs its SRAM cells. Stratix II FPGAs support decompression in the FPP (when using a MAX II device/microprocessor and flash memory), AS and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by modern system designers. Stratix II devices can help effectively deal with these challenges with their inherent re-programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life. Stratix II FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios(R) processor or user logic) implemented in the Stratix II device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides
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Configuration
error status information. This dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades. RSC is supported in the following Stratix II configuration schemes: FPP, AS, PS, and PPA. RSC can also be implemented in conjunction with advanced Stratix II features such as real-time decompression of configuration data and design security using AES for secure and efficient field upgrades.
f
See the Remote System Upgrades With Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information about remote configuration in Stratix II devices.
Configuring Stratix II FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including Stratix II FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the Windows NT operating system (OS), but can be customized to run on other platforms.
f
For more information on the JRunner software driver, see the JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com).
Programming Serial Configuration Devices with SRunner
A serial configuration device can be programmed in-system by an external microprocessor using SRunner. SRunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit in different embedded systems. SRunner is able to read a .rpd file (Raw Programming Data) and write to the serial configuration devices. The serial configuration device programming time using SRunner is comparable to the programming time when using the Quartus II software.
f
For more information about SRunner, see the SRunner: An Embedded Solution for EPCS Programming White Paper and the source code on the Altera web site at www.altera.com. For more information on programming serial configuration devices, see the Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet in the Configuration Handbook.
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Configuration & Testing
Configuring Stratix II FPGAs with the MicroBlaster Driver
The MicroBlasterTM software driver supports an RBF programming input file and is ideal for embedded FPP or PS configuration. The source code is developed for the Windows NT operating system, although it can be customized to run on other operating systems. For more information on the MicroBlaster software driver, see the Configuring the MicroBlaster Fast Passive Parallel Software Driver White Paper or the Configuring the MicroBlaster Passive Serial Software Driver White Paper on the Altera web site (www.altera.com).
PLL Reconfiguration
The phase-locked loops (PLLs) in the Stratix II device family support reconfiguration of their multiply, divide, VCO-phase selection, and bandwidth selection settings without reconfiguring the entire device. You can use either serial data from the logic array or regular I/O pins to program the PLL's counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL.
f
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook for more information on Stratix II PLLs. Stratix II devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device. These devices steer bias current through the Stratix II diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). The external device's output represents the junction temperature of the Stratix II device and can be used for intelligent power management. The diode requires two pins (tempdiodep and tempdioden) on the Stratix II device to connect to the external temperature-sensing device, as shown in Figure 3-1. The temperature sensing diode is a passive element and therefore can be used before the Stratix II device is powered.
Temperature Sensing Diode (TSD)
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3-11 Stratix II Device Handbook, Volume 1
Temperature Sensing Diode (TSD)
Figure 3-1. External Temperature-Sensing Diode
Stratix II Device Temperature-Sensing Device
tempdiodep
tempdioden
Table 3-6 shows the specifications for bias voltage and current of the Stratix II temperature sensing diode.
Table 3-6. Temperature-Sensing Diode Electrical Characteristics Parameter
IBIAS high IBIAS low VBP - VBN VBN Series resistance
Minimum
80 8 0.3
Typical
100 10
Maximum
120 12 0.9
Unit
A A V V
0.7 3
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Configuration & Testing
The temperature-sensing diode works for the entire operating range, as shown in Figure 3-2. Figure 3-2. Temperature vs. Temperature-Sensing Diode Voltage
0.95 0.90 0.85 0.80 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -55 -30 -5 20 45 70 95 120 100 A Bias Current 10 A Bias Current
Temperature (C)
The temperature sensing diode is a very sensitive circuit which can be influenced by noise coupled from other traces on the board, and possibly within the device package itself, depending on device usage. The interfacing device registers temperature based on milivolts of difference as seen at the TSD. Switching I/O near the TSD pins can affect the temperature reading. Altera recommends you take temperature readings during periods of no activity in the device (for example, standby mode where no clocks are toggling in the device), such as when the nearby I/Os are at a DC state, and disable clock networks in the device.
Automated Single Event Upset (SEU) Detection
Stratix II devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. Some applications that require the device to operate error free at high elevations or in close proximity to Earth's North or South Pole require periodic checks to ensure continued data integrity. The error detection cyclic redundancy check (CRC) feature controlled by
Altera Corporation May 2007
3-13 Stratix II Device Handbook, Volume 1
Document Revision History
the Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU. You can implement the error detection CRC feature with existing circuitry in Stratix II devices, eliminating the need for external logic. For Stratix II devices, CRC is computed by the device during configuration and checked against an automatically computed CRC during normal operation. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix II devices to perform error detection automatically. This error detection circuitry in Stratix II devices constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a re-configuration cycle. You can select the desired time between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the automated error detection CRC feature in the Device & Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, refer to AN 357: Error Detection Using CRC in Altera FPGA Devices.
Document Revision History
Table 3-7 shows the revision history for this chapter.
Table 3-7. Document Revision History (Part 1 of 2) Date and Document Version Changes Made Summary of Changes
-- --
May 2007, v4.2 Moved Document Revision History section to the end of the chapter. Updated the "Temperature Sensing Diode (TSD)" section.
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Configuration & Testing
Table 3-7. Document Revision History (Part 2 of 2) Date and Document Version
April 2006, v4.1 December 2005, v4.0 May 2005, v3.0
Changes Made
Updated "Device Security Using Configuration Bitstream Encryption" section. Updated "Software Interface" section.

Summary of Changes
-- -- --
Updated "IEEE Std. 1149.1 JTAG Boundary-Scan Support" section. Updated "Operating Modes" section.
January 2005, v2.1 January 2005, v2.0 July 2004, v1.1
Updated JTAG chain device limits. Updated Table 3-3.

-- -- --
Added "Automated Single Event Upset (SEU) Detection" section. Updated "Device Security Using Configuration Bitstream Encryption" section. Updated Figure 3-2.
February 2004, Added document to the Stratix II Device Handbook. v1.0
--
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Document Revision History
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4. Hot Socketing & Power-On Reset
SII51004-3.2
Stratix(R) II devices offer hot socketing, which is also known as hot plug-in or hot swap, and power sequencing support without the use of any external devices. You can insert or remove a Stratix II board in a system during system operation without causing undesirable effects to the running system bus or the board that was inserted into the system. The hot socketing feature also removes some of the difficulty when you use Stratix II devices on printed circuit boards (PCBs) that also contain a mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- and 1.2-V devices. With the Stratix II hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board. The Stratix II hot socketing feature provides:

Board or device insertion and removal without external components or board manipulation Support for any power-up sequence Non-intrusive I/O buffers to system buses during hot insertion
This chapter also discusses the power-on reset (POR) circuitry in Stratix II devices. The POR circuitry keeps the devices in the reset state until the VCC is within operating range.
Stratix II Hot-Socketing Specifications
Stratix II devices offer hot socketing capability with all three features listed above without any external components or special design requirements. The hot socketing feature in Stratix II devices allows:

The device can be driven before power-up without any damage to the device itself. I/O pins remain tri-stated during power-up. The device does not drive out before or during power-up, thereby affecting other buses in operation. Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies. External input signals to I/O pins of the device do not internally power the VCCIO or VCCINT power supplies of the device via internal paths within the device.
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4-1
Stratix II Hot-Socketing Specifications
Devices Can Be Driven Before Power-Up
You can drive signals into the I/O pins, dedicated input pins and dedicated clock pins of Stratix II devices before or during power-up or power-down without damaging the device. Stratix II devices support any power-up or power-down sequence (VCCIO, VCCINT, and VCCPD) in order to simplify system level design.
I/O Pins Remain Tri-Stated During Power-Up
A device that does not support hot-socketing may interrupt system operation or cause contention by driving out before or during power-up. In a hot socketing situation, Stratix II device's output buffers are turned off during system power-up or power-down. Stratix II device also does not drive out until the device is configured and has attained proper operating conditions.
Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power Supplies
Devices that do not support hot-socketing can short power supplies together when powered-up through the device signal pins. This irregular power-up can damage both the driving and driven devices and can disrupt card power-up. Stratix II devices do not have a current path from I/O pins, dedicated input pins, or dedicated clock pins to the VCCIO, VCCINT, or VCCPD pins before or during power-up. A Stratix II device may be inserted into (or removed from) a powered-up system board without damaging or interfering with system-board operation. When hot-socketing, Stratix II devices may have a minimal effect on the signal integrity of the backplane. 1 You can power up or power down the VCCIO, VCCINT, and VCCPD pins in any sequence. The power supply ramp rates can range from 100 s to 100 ms. All VCC supplies must power down within 100 ms of each other to prevent I/O pins from driving out. During hot socketing, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF. Stratix II devices meet the following hot socketing specification. The hot socketing DC specification is: | IIOPIN | < 300 A. The hot socketing AC specification is: | IIOPIN | < 8 mA for 10 ns or less.

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Hot Socketing & Power-On Reset
IIOPIN is the current at any user I/O pin on the device. This specification takes into account the pin capacitance, but not board trace and external loading capacitance. Additional capacitance for trace, connector, and loading needs must be considered separately. For the AC specification, the peak current duration is 10 ns or less because of power-up transients. For more information, refer to the Hot-Socketing & Power-Sequencing Feature & Testing for Altera Devices white paper. A possible concern regarding hot-socketing is the potential for latch-up. Latch-up can occur when electrical subsystems are hot-socketed into an active system. During hot-socketing, the signal pins may be connected and driven by the active system before the power supply can provide current to the device's VCC and ground planes. This condition can lead to latch-up and cause a low-impedance path from VCC to ground within the device. As a result, the device extends a large amount of current, possibly causing electrical damage. Nevertheless, Stratix II devices are immune to latch-up when hot-socketing.
Hot Socketing Feature Implementation in Stratix II Devices
The hot socketing feature turns off the output buffer during the power-up event (either VCCINT, VCCIO, or VCCPD supplies) or power down. The hotsocket circuit will generate an internal HOTSCKT signal when either VCCINT, VCCIO, or VCCPD is below threshold voltage. The HOTSCKT signal will cut off the output buffer to make sure that no DC current (except for weak pull up leaking) leaks through the pin. When VCC ramps up very slowly, VCC is still relatively low even after the POR signal is released and the configuration is finished. The CONF_DONE, nCEO, and nSTATUS pins fail to respond, as the output buffer can not flip from the state set by the hot socketing circuit at this low VCC voltage. Therefore, the hot socketing circuit has been removed on these configuration pins to make sure that they are able to operate during configuration. It is expected behavior for these pins to drive out during power-up and power-down sequences. Each I/O pin has the following circuitry shown in Figure 4-1.
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Hot Socketing Feature Implementation in Stratix II Devices
Figure 4-1. Hot Socketing Circuit Block Diagram for Stratix II Devices
Power On Reset Monitor
Output
Weak Pull-Up Resistor
PAD
R Output Enable
Voltage Tolerance Control
Hot Socket
Output Pre-Driver
Input Buffer to Logic Array
The POR circuit monitors VCCINT voltage level and keeps I/O pins tristated until the device is in user mode. The weak pull-up resistor (R) from the I/O pin to VCCIO is present to keep the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V before VCCIO and/or VCCINT and/or VCCPD are powered, and it prevents the I/O pins from driving out when the device is not in user mode. The hot socket circuit prevents I/O pins from internally powering VCCIO, VCCINT, and VCCPD when driven by external signals before the device is powered. Figure 4-2 shows a transistor level cross section of the Stratix II device I/O buffers. This design ensures that the output buffers do not drive when VCCIO is powered before VCCINT or if the I/O pad voltage is higher than VCCIO. This also applies for sudden voltage spikes during hot insertion. There is no current path from signal I/O pins to VCCINT or VCCIO or VCCPD during hot insertion. The VPAD leakage current charges the 3.3-V tolerant circuit capacitance.
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Hot Socketing & Power-On Reset
Figure 4-2. Transistor Level Diagram of FPGA Device I/O Buffers
Logic Array Signal VPAD
(1)
VCCIO
(2)
n+ p-well
n+
p+
p+ n-well
n+
p-substrate
Notes to Figure 4-2:
(1) (2) This is the logic array signal or the larger of either the VCCIO or VPAD signal. This is the larger of either the VCCIO or VPAD signal.
Power-On Reset Circuitry
Stratix II devices have a POR circuit to keep the whole device system in reset state until the power supply voltage levels have stabilized during power-up. The POR circuit monitors the VCCINT, VCCIO, and VCCPD voltage levels and tri-states all the user I/O pins while VCC is ramping up until normal user levels are reached. The POR circuitry also ensures that all eight I/O bank VCCIO voltages, VCCPD voltage, as well as the logic array VCCINT voltage, reach an acceptable level before configuration is triggered. After the Stratix II device enters user mode, the POR circuit continues to monitor the VCCINT voltage level so that a brown-out condition during user mode can be detected. If there is a VCCINT voltage sag below the Stratix II operational level during user mode, the POR circuit resets the device. When power is applied to a Stratix II device, a power-on-reset event occurs if VCC reaches the recommended operating range within a certain period of time (specified as a maximum VCC rise time). The maximum VCC rise time for Stratix II device is 100 ms. Stratix II devices provide a dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms. When the PORSEL pin is connected to VCC, the POR time is 12 ms.
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Document Revision History
Document Revision History
Table 4-1 shows the revision history for this chapter.
Table 4-1. Document Revision History Date and Document Version Changes Made Summary of Changes
--
May 2007, v3.2 Moved the Document Revision History section to the end of the chapter. April 2006, v3.1 May 2005, v3.0
Updated "Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power Supplies" section. Updated "Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power Supplies" section. Removed information on ESD protection.
Updated hot socketing AC specification. --

January 2005, v2.1 January 2005, v2.0 July 2004, v1.1
Updated input rise and fall time. Updated the "Hot Socketing Feature Implementation in Stratix II Devices", "ESD Protection", and "Power-On Reset Circuitry" sections.

-- --
Updated all tables. Added tables.
-- --
February 2004, Added document to the Stratix II Device Handbook. v1.0
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5. DC & Switching Characteristics
SII51005-4.3
Operating Conditions
Stratix(R) II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 (fastest), -4, -5 speed grades. Tables 5-1 through 5-32 provide information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Stratix II devices.
Absolute Maximum Ratings
Table 5-1 contains the absolute maximum ratings for the Stratix II device family.
Table 5-1. Stratix II Device Absolute Maximum Ratings Symbol
VCCINT VCCIO VCCPD VCCA VCCD VI IOUT TSTG TJ
(1) (2) (3) (4)
Notes (1), (2), (3) Minimum
-0.5 -0.5 -0.5 -0.5 -0.5 -0.5 -25
Parameter
Supply voltage Supply voltage Supply voltage Analog power supply for PLLs
Conditions
With respect to ground With respect to ground With respect to ground With respect to ground
Maximum
1.8 4.6 4.6 1.8 1.8 4.6 40 150 125
Unit
V V V V V V mA C C
Digital power supply for PLLs With respect to ground DC input voltage (4) DC output current, per pin Storage temperature Junction temperature No bias BGA packages under bias
-65 -55
Notes to Tables 5-1
See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 5-1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. During transitions, the inputs may overshoot to the voltage shown in Table 5-2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
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5-1
Operating Conditions
Table 5-2. Maximum Duty Cycles in Voltage Transitions Symbol
VI
Parameter
Maximum duty cycles in voltage transitions
Condition
VI = 4.0 V VI = 4.1 V VI = 4.2 V VI = 4.3 V VI = 4.4 V VI = 4.5 V
Maximum Duty Cycles
100 90 50 30 17 10
Unit
% % % % % %
Recommended Operating Conditions
Table 5-3 contains the Stratix II device family recommended operating conditions.
Table 5-3. Stratix II Device Recommended Operating Conditions (Part 1 of 2) Symbol
VCCINT VCCIO
Note (1) Maximum Unit
1.25 3.465 (3.60) 2.625 1.89 1.575 1.26 3.465 V V V V V V V
Parameter
Supply voltage for internal logic Supply voltage for input and output buffers, 3.3-V operation Supply voltage for input and output buffers, 2.5-V operation Supply voltage for input and output buffers, 1.8-V operation
Conditions
100 s risetime 100 ms (3) 100 s risetime 100 ms (3), (6) 100 s risetime 100 ms (3) 100 s risetime 100 ms (3)
Minimum
1.15 3.135 (3.00) 2.375 1.71 1.425 1.14 3.135
Supply voltage for output buffers, 100 s risetime 100 ms (3) 1.5-V operation Supply voltage for input and output buffers, 1.2-V operation VCCPD Supply voltage for pre-drivers as well as configuration and JTAG I/O buffers. Analog power supply for PLLs Digital power supply for PLLs Input voltage (see Table 5-2) Output voltage 100 s risetime 100 ms (3) 100 s risetime 100 ms (4)
VCCA VCCD VI VO
100 s risetime 100 ms (3) 100 s risetime 100 ms (3) (2), (5)
1.15 1.15 -0.5 0
1.25 1.25 4.0 VCCIO
V V V V
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DC & Switching Characteristics
Table 5-3. Stratix II Device Recommended Operating Conditions (Part 2 of 2) Symbol
TJ
Note (1) Maximum Unit
85 100 C C
Parameter
Operating junction temperature
Conditions
For commercial use For industrial use
Minimum
0 -40
Notes to Table 5-3:
(1) (2) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply. During transitions, the inputs may overshoot to the voltage shown in Table 5-2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns. Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VC C . VCCPD must ramp-up from 0 V to 3.3 V within 100 s to 100 ms. If VC C P D is not ramped up within this specified time, your Stratix II device does not configure successfully. If your system does not allow for a VCCPD ramp-up time of 100 ms or less, you must hold nCONFIG low until all power supplies are reliable. All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIO are powered. VC C I O maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
(3) (4)
(5) (6)
DC Electrical Characteristics
Table 5-4 shows the Stratix II device family DC electrical characteristics.
Table 5-4. Stratix II Device DC Operating Conditions (Part 1 of 2) Symbol
II IOZ IC C I N T 0
Note (1) Minimum Typical Maximum Unit
-10 -10 0.25 0.30 0.50 0.62 0.82 1.12 2.2 2.7 3.6 4.3 5.4 6.8 10 10 (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) (3) A A A A A A A A mA mA mA mA mA mA
Parameter
Conditions
VO = VCCIOmax to 0 V (2) VI = ground, no load, no toggling inputs TJ = 25 C EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Input pin leakage current VI = VCCIOmax to 0 V (2) Tri-stated I/O pin leakage current VCCINT supply current (standby)
ICCPD0
VCCPD supply current (standby)
VI = ground, no load, no toggling inputs TJ = 25 C, VCCPD = 3.3V
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
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Operating Conditions
Table 5-4. Stratix II Device DC Operating Conditions (Part 2 of 2) Symbol
ICCI00
Note (1) Minimum Typical Maximum Unit
4.0 4.0 4.0 4.0 4.0 4.0 10 15 30 40 50 25 35 50 75 90 1 (3) (3) (3) (3) (3) (3) 50 70 100 150 170 2 mA mA mA mA mA mA k k k k k k
Parameter
VCCIO supply current (standby)
Conditions
VI = ground, no load, no toggling inputs TJ = 25 C EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
RCONF (4) Value of I/O pin pull-up resistor before and during configuration
Vi = 0; VCCIO = 3.3 V Vi = 0; VCCIO = 2.5 V Vi = 0; VCCIO = 1.8 V Vi = 0; VCCIO = 1.5 V Vi = 0; VCCIO = 1.2 V
Recommended value of I/O pin external pull-down resistor before and during configuration Notes to Table 5-4:
(1) (2) (3)
(4)
Typical values are for TA = 25C, VCCINT = 1.2 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay Early Power Estimator (available at www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum values. See the section "Power Consumption" on page 5-20 for more information. Pin pull-up resistance values are lower if an external source drives the pin higher than VCCIO.
I/O Standard Specifications
Tables 5-5 through 5-32 show the Stratix II device family I/O standard specifications.
Table 5-5. LVTTL Specifications (Part 1 of 2) Symbol
VCCIO (1) VI H VIL VOH
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage
Conditions
Minimum
3.135 1.7 -0.3
Maximum
3.465 4.0 0.8
Unit
V V V V
IOH = -4 mA (2)
2.4
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DC & Switching Characteristics
Table 5-5. LVTTL Specifications (Part 2 of 2) Symbol
VOL
(1) (2)
Parameter
Low-level output voltage
Conditions
IOL = 4 mA (2)
Minimum
Maximum
0.45
Unit
V
Notes to Tables 5-5:
Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. This specification is supported across all the programmable drive strength settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-6. LVCMOS Specifications Symbol
VCCIO (1) VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.135 1.7 -0.3
Maximum
3.465 4.0 0.8
Unit
V V V V
VCCIO = 3.0, IOH = -0.1 mA (2) VCCIO = 3.0, IOL = 0.1 mA (2)
VCCIO - 0.2 0.2
V
Notes to Table 5-6:
(1) (2) Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B. This specification is supported across all the programmable drive strength available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-7. 2.5-V I/O Specifications Symbol
VCCIO (1) VIH VIL VOH VOL
(1) (2)
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 1.7 -0.3
Maximum
2.625 4.0 0.7
Unit
V V V V
IOH = -1mA (2) IOL = 1 mA (2)
2.0 0.4
V
Notes to Table 5-7:
Stratix II devices VC C I O voltage level support of 2.5 -5% is narrower than defined in the Normal Range of the EIA/JEDEC standard. This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
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Operating Conditions
Table 5-8. 1.8-V I/O Specifications Symbol
VCCIO (1) VI H VIL VOH VOL
(1) (2)
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.65 x VCCIO -0.30
Maximum
1.89 2.25 0.35 x VCCIO
Unit
V V V V
IOH = -2 mA (2) IOL = 2 mA (2)
VCCIO - 0.45 0.45
V
Notes to Table 5-8:
The Stratix II device family's VC C I O voltage level support of 1.8 -5% is narrower than defined in the Normal Range of the EIA/JEDEC standard. This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-9. 1.5-V I/O Specifications Symbol
VCCIO (1) VI H VIL VOH VOL
(1) (2)
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.425 0.65 x VCCIO -0.30 0.75 x VCCIO
Maximum
1.575 VCCIO + 0.30 0.35 x VCCIO 0.25 x VCCIO
Unit
V V V V V
IOH = -2 mA (2) IOL = 2 mA (2)
Notes to Table 5-9:
The Stratix II device family's VC C I O voltage level support of 1.5 -5% is narrower than defined in the Normal Range of the EIA/JEDEC standard. This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Figures 5-1 and 5-2 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, LVPECL, and HyperTransport technology).
5-6 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Figure 5-1. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground
Differential Waveform
VID p-n=0V VID
Figure 5-2. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground
Differential Waveform
VOD p-n=0V VOD
Altera Corporation May 2007
5-7 Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5-10. 2.5-V LVDS I/O Specifications Symbol
VCCIO
Parameter
I/O supply voltage for left and right I/O banks (1, 2, 5, and 6) Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input discrete resistor (external to Stratix II devices)
Conditions
Minimum
2.375
Typical
2.500
Maximum
2.625
Unit
V
VID VICM VOD VOCM RL
100 200 RL = 100 RL = 100 250 1.125 90
350 1,250
900 1,800 450 1.375
mV mV mV V
100
110
Table 5-11. 3.3-V LVDS I/O Specifications Symbol
VCCIO (1)
Parameter
I/O supply voltage for top and bottom PLL banks (9, 10, 11, and 12) Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input discrete resistor (external to Stratix II devices)
Conditions
Minimum
3.135
Typical
3.300
Maximum
3.465
Unit
V
VID VICM VOD VOCM RL
100 200 RL = 100 RL = 100 250 840 90
350 1,250
900 1,800 710 1,570
mV mV mV mV
100
110
Note to Table 5-11:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.
5-8 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-12. LVPECL Specifications Symbol
VCCIO (1) VID VICM VOD VOCM RL
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input resistor
Conditions
Minimum
3.135 300 1.0
Typical
3.300 600
Maximum
3.465 1,000 2.5 970 2,250
Unit
V mV V mV mV
RL = 100 RL = 100
525 1,650 90 100
110
Note to Table 5-12:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.
Table 5-13. HyperTransport Technology Specifications Symbol
VCCIO VID VICM VOD VOD VOCM VOCM RL
Parameter
I/O supply voltage for left and right I/O banks (1, 2, 5, and 6)
Conditions
Minimum
2.375 300 385 400
Typical
2.500 600 600 600
Maximum
2.625 900 845 820 75
Unit
V mV mV mV mV mV mV
Input differential voltage swing RL = 100 (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VOD between high and low RL = 100 RL = 100 RL = 100
Output common mode voltage RL = 100 Change in VOCM between high and low Receiver differential input resistor RL = 100
440
600
780 50
90
100
110
Table 5-14. 3.3-V PCI Specifications (Part 1 of 2) Symbol
VCCIO VIH
Parameter
Output supply voltage High-level input voltage
Conditions
Minimum
3.0 0.5 x VCCIO
Typical
3.3
Maximum
3.6 VCCIO + 0.5
Unit
V V
Altera Corporation May 2007
5-9 Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5-14. 3.3-V PCI Specifications (Part 2 of 2) Symbol
VIL VOH VOL
Parameter
Low-level input voltage High-level output voltage Low-level output voltage
Conditions
IOUT = -500 A IOUT = 1,500 A
Minimum
-0.3 0.9 x VCCIO
Typical
Maximum
0.3 x VCCIO 0.1 x VCCIO
Unit
V V V
Table 5-15. PCI-X Mode 1 Specifications Symbol
VCCIO VIH VIL VIPU VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.30 0.7 x VCCIO
Typical
Maximum
3.6 VCCIO + 0.5 0.35 x VCCIO
Unit
V V V V V
IOUT = -500 A IOUT = 1,500 A
0.9 x VCCIO 0.1 x VCCIO
V
Table 5-16. SSTL-18 Class I Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
(1)
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.855 VREF - 0.04 VREF + 0.125
Typical
1.80 0.900 VREF
Maximum
1.89 0.945 VREF + 0.04
Unit
V V V V
VREF - 0.125 VREF + 0.25 VREF - 0.25 IOH = -6.7 mA (1) IOL = 6.7 mA (1) VTT + 0.475 VTT - 0.475
V V V V V
Note to Table 5-16:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5-10 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-17. SSTL-18 Class II Specifications Symbol
VCCIO VREF VTT
Parameter
Output supply voltage Reference voltage Termination voltage
Conditions
Minimum
1.71 0.855 VREF - 0.04 VREF + 0.125
Typical
1.80 0.900 VREF
Maximum
1.89 0.945 VREF + 0.04
Unit
V V V V
VIH (DC) High-level DC input voltage VIL (DC) Low-level DC input voltage VIH (AC) High-level AC input voltage VIL (AC) Low-level AC input voltage VOH VOL
(1)
VREF - 0.125 VREF + 0.25 VREF - 0.25 IOH = -13.4 mA (1) IOL = 13.4 mA (1) VCCIO - 0.28 0.28
V V V V V
High-level output voltage Low-level output voltage
Note to Table 5-17:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-18. SSTL-18 Class I & II Differential Specifications Symbol
VCCIO VSWING (DC)
Parameter
Output supply voltage DC differential input voltage
Conditions
Minimum
1.71 0.25 (VCCIO/2) - 0.175 0.5
Typical
1.80
Maximum
1.89
Unit
V V
VX (AC) AC differential input cross point voltage VSWING (AC) VISO VISO VOX (AC) AC differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation AC differential cross point voltage
(VCCIO/2) + 0.175
V V
0.5 x VCCIO 200 (VCCIO/2) - 0.125 (VCCIO/2) + 0.125
V mV V
Altera Corporation May 2007
5-11 Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5-19. SSTL-2 Class I Specifications Symbol
VCCIO VTT VREF VIH (DC) VIL (DC) VI H (AC) VI L (AC) VOH VOL
(1)
Parameter
Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF - 0.04 1.188 VREF + 0.18 -0.30 VR E F + 0.35
Typical
2.500 VREF 1.250
Maximum
2.625 VREF + 0.04 1.313 3.00 VREF - 0.18
Unit
V V V V V V
VR E F - 0.35 IOH = -8.1 mA (1) IOL = 8.1 mA (1) VTT + 0.57 VTT - 0.57
V V V
Note to Table 5-19:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-20. SSTL-2 Class II Specifications Symbol
VCCIO VTT VREF VIH (DC) VIL (DC) VI H (AC) VI L (AC) VOH VOL
(1)
Parameter
Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF - 0.04 1.188 VREF + 0.18 -0.30 VR E F + 0.35
Typical
2.500 VREF 1.250
Maximum
2.625 VREF + 0.04 1.313 VCCIO + 0.30 VREF - 0.18
Unit
V V V V V V
VR E F - 0.35 IOH = -16.4 mA (1) IOL = 16.4 mA (1) VTT + 0.76 VTT - 0.76
V V V
Note to Table 5-20:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5-12 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-21. SSTL-2 Class I & II Differential Specifications Symbol
VCCIO VSWING (DC)
Parameter
Output supply voltage DC differential input voltage
Conditions
Minimum
2.375 0.36 (VCCIO/2) - 0.2 0.7
Typical
2.500
Maximum
2.625
Unit
V V
VX (AC) AC differential input cross point voltage VSWING (AC) VISO VISO VOX (AC) AC differential input voltage Input clock signal offset voltage Input clock signal offset voltage variation AC differential output cross point voltage
(VCCIO/2) + 0.2
V V
0.5 x VCCIO 200 (VCCIO/2) - 0.2 (VCCIO/2) + 0.2
V mV V
Table 5-22. 1.2-V HSTL Specifications Symbol
VCCIO VR E F
Parameter
Output supply voltage Reference voltage
Conditions
Minimum
1.14 0.48 x VC C I O VR E F + 0.08 -0.15 VR E F + 0.15 -0.24
Typical
1.20 0.50 x VC C I O
Maximum
1.26 0.52 x VC C I O VC C I O + 0.15 VR E F - 0.08 VC C I O + 0.24 VR E F - 0.15 VC C I O + 0.15 VR E F - 0.15
Unit
V V V V V V V V
VIH (DC) High-level DC input voltage VIL (DC) Low-level DC input voltage VIH (AC) High-level AC input voltage VIL (AC) Low-level AC input voltage VOH VOL High-level output voltage Low-level output voltage IO H = 8 mA IO H = -8 mA
VR E F + 0.15 -0.15
Altera Corporation May 2007
5-13 Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5-23. 1.5-V HSTL Class I Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
(1)
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.425 0.713 0.713 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.500 0.750 0.750
Maximum
1.575 0.788 0.788
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = 8 mA (1) IOH = -8 mA (1) VCCIO - 0.4 0.4
V V V
Note to Table 5-23:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-24. 1.5-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
(1)
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.425 0.713 0.713 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.500 0.750 0.750
Maximum
1.575 0.788 0.788
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = 16 mA (1) IOH = -16 mA (1) VCCIO - 0.4 0.4
V V V
Note to Table 5-24:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5-14 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-25. 1.5-V HSTL Class I & II Differential Specifications Symbol
VCCIO VDIF (DC) VCM (DC) VDIF (AC) VOX (AC)
Parameter
I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage AC differential cross point voltage
Conditions
Minimum
1.425 0.2 0.68 0.4 0.68
Typical
1.500
Maximum
1.575
Unit
V V
0.90
V V
0.90
V
Table 5-26. 1.8-V HSTL Class I Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
(1)
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.85 0.85 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.80 0.90 0.90
Maximum
1.89 0.95 0.95
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = 8 mA (1) IOH = -8 mA (1) VCCIO - 0.4 0.4
V V V
Note to Table 5-26:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Altera Corporation May 2007
5-15 Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5-27. 1.8-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
(1)
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 0.85 0.85 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.80 0.90 0.90
Maximum
1.89 0.95 0.95
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = 16 mA (1) IOH = -16 mA (1) VCCIO - 0.4 0.4
V V V
Note to Table 5-27:
This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5-28. 1.8-V HSTL Class I & II Differential Specifications Symbol
VCCIO VDIF (DC) VCM (DC) VDIF (AC) VOX (AC)
Parameter
I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage AC differential cross point voltage
Conditions
Minimum
1.71 0.2 0.78 0.4 0.68
Typical
1.80
Maximum
1.89 VCCIO + 0.6 V 1.12 VCCIO + 0.6 V 0.90
Unit
V V V V V
5-16 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Bus Hold Specifications
Table 5-29 shows the Stratix II device family bus hold specifications.
Table 5-29. Bus Hold Parameters VCCIO Level Parameter Conditions 1.2 V Min
Low sustaining current High sustaining current Low overdrive current High overdrive current Bus-hold trip point VIN > VIL (maximum) VIN < VIH (minimum) 0 V < VIN < VCCIO 0 V < VIN < VCCIO 0.45 22.5
1.5 V Min
25.0
1.8 V Min
30.0
2.5 V Min
50.0
3.3 V Min
70.0
Unit
Max
Max
Max
Max
Max
A
-22.5
-25.0
-30.0
-50.0
-70.0
A
120
160
200
300
500
A
-120
-160
-200
-300
-500
A
0.95
0.50
1.00
0.68
1.07
0.70
1.70
0.80
2.00
V
On-Chip Termination Specifications
Tables 5-30 and 5-31 define the specification for internal termination resistance tolerance when using series or differential on-chip termination.
Table 5-30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2) Notes (1), 2 Resistance Tolerance Symbol
25- RS 3.3/2.5
Description
Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting)
Conditions
VC C I O = 3.3/2.5 V VC C I O = 3.3/2.5 V
Commercial Max
5 30
Industrial Max
10 30
Unit
% %
Altera Corporation May 2007
5-17 Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5-30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2) Notes (1), 2 Resistance Tolerance Symbol
50- RS 3.3/2.5
Description
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
Conditions
VC C I O = 3.3/2.5 V VC C I O = 3.3/2.5 V VC C I O = 1.8 V VC C I O = 1.8 V VC C I O = 1.8 V VC C I O = 1.8 V VC C I O = 1.8 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.5 V VC C I O = 1.5 V VC C I O = 1.2 V VC C I O = 1.2 V VC C I O = 1.2 V
Commercial Max
5 30 30 5 30 5 30 10 8 36 10 8 50 10
Industrial Max
10 30 30 10 30 10 30 15 10 36 15 10 50 15
Unit
% % % % % % % % % % % % % %
50- RT 2.5 25- RS 1.8
Internal parallel termination with calibration (50- setting) Internal series termination with calibration (25- setting) Internal series termination without calibration (25- setting)
50- RS 1.8
Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
50- RT 1.8 50- RS 1.5
Internal parallel termination with calibration (50- setting) Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
50- RT 1.5 50- RS 1.2
Internal parallel termination with calibration (50- setting) Internal series termination with calibration (50- setting) Internal series termination without calibration (50- setting)
50- RT 1.2
(1) (2)
Internal parallel termination with calibration (50- setting)
Notes for Table 5-30:
The resistance tolerances for calibrated SOCT and POCT are for the moment of calibration. If the temperature or voltage changes over time, the tolerance may also change. On-chip parallel termination with calibration is only supported for input pins.
5-18 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-31. Series & Differential On-Chip Termination Specification for Left & Right I/O Banks Resistance Tolerance Symbol
25- RS 3.3/2.5 50- RS 3.3/2.5/1.8 50- RS 1.5 RD
Description
Internal series termination without calibration (25- setting) Internal series termination without calibration (50- setting) Internal series termination without calibration (50- setting)
Conditions
VC C I O = 3.3/2.5 V VC C I O = 3.3/2.5/1.8 V VC C I O = 1.5 V
Commercial Industrial Max Max
30 30 36 20 30 30 36 25
Unit
% % % %
VC C I O = 2.5 V Internal differential termination for LVDS or HyperTransport technology (100- setting)
Pin Capacitance
Table 5-32 shows the Stratix II device family pin capacitance.
Table 5-32. Stratix II Device Capacitance Symbol
CI O T B CI O L R CC L K T B CC L K L R CC L K L R + CO U T F B
Note (1) Parameter Typical
5.0 6.1 6.0 6.1 3.3 6.7
Unit
pF pF pF pF pF pF
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8. Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including highspeed differential receiver and transmitter pins. Input capacitance on top/bottom clock input pins: CLK[4..7] and
CLK[12..15].
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK8, CLK10. Input capacitance on left/right clock inputs: CLK1, CLK3, CLK9, and
CLK11.
Input capacitance on dual-purpose clock output/feedback pins in PLL banks 9, 10, 11, and 12.
Note to Table 5-32:
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5pF
Altera Corporation May 2007
5-19 Stratix II Device Handbook, Volume 1
Power Consumption
Power Consumption
Altera(R) offers two ways to calculate power for a design: the Excel-based PowerPlay Early Power Estimator power calculator and the Quartus(R) II PowerPlay Power Analyzer feature. The interactive Excel-based PowerPlay Early Power Estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-androute is complete. The Power Analyzer can apply a combination of userentered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates. In both cases, these calculations should only be used as an estimation of power, not as a specification.
f
For more information on PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Early Power Estimator and PowerPlay Power Analyzer chapters in volume 3 of the Quartus II Handbook. The PowerPlay Early Power Estimator is available on the Altera web site at www.altera. com. See Table 5-4 on page 5-3 for typical ICC standby specifications.
Timing Model
The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix II device densities and speed grades. This section describes and specifies the performance, internal timing, external timing, and PLL, high-speed I/O, external memory interface, and JTAG timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions. 1 The timing numbers listed in the tables of this section are extracted from the Quartus II software version 5.0 SP1.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 5-33 shows the status of the Stratix II device timing models.
5-20 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions.
Table 5-33. Stratix II Device Timing Model Status Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Preliminary
Final v v v v v v
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum voltage, and maximum temperature for input register setup time (tSU) and hold time (tH). The Quartus II software uses the following equations to calculate tSU and tH timing for Stratix II devices input signals. tSU = + data delay from input pin to input register + micro setup time of the input register - clock delay from input pin to input register tH = - data delay from input pin to input register + micro hold time of the input register + clock delay from input pin to input register Figure 5-3 shows the setup and hold timing diagram for input registers.
Altera Corporation May 2007
5-21 Stratix II Device Handbook, Volume 1
Timing Model
Figure 5-3. Input Register Setup & Hold Timing Diagram
Input Data Delay
micro tSU micro tH Input Clock Delay
For output timing, different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards. The following measurements are made during device characterization. Altera measures clock-to-output delays (tCO) at worst-case process, minimum voltage, and maximum temperature (PVT) for default loading conditions shown in Table 5-34. Use the following equations to calculate clock pin to output pin timing for Stratix II devices. tCO from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay txz/tzx from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay + output enable pin delay Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook. 1. Simulate the output driver of choice into the generalized test setup, using values from Table 5-34. Record the time to VMEAS. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load.
Altera Corporation May 2007
2. 3.
5-22 Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
4. 5.
Record the time to VMEAS. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in Table 5-34 using the above equation. Figure 5-4 shows the model of the circuit that is represented by the output timing of the Quartus II software. Figure 5-4. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT VCCIO RT Output Buffer
Output
Outputp RD
RS CL
GND
VMEAS
Outputn
GND
Notes to Figure 5-4:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations. VCCPD is 3.085 V unless otherwise specified. VCCINT is 1.12 V unless otherwise specified.
(2) (3)
Figures 5-5 and 5-6 show the measurement setup for output disable and output enable timing.
Altera Corporation May 2007
5-23 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-34. Output Timing Measurement Methodology for Output Pins Loading and Termination I/O Standard RS ()
LVTTL (4) LVCMOS (4) 2.5 V (4) 1.8 V (4) 1.5 V (4) PCI (5) PCI-X (5) SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.2-V HSTL with OCT Differential SSTL-2 Class I Differential SSTL-2 Class II Differential SSTL-18 Class I Differential SSTL-18 Class II 1.5-V Differential HSTL Class I 1.5-V Differential HSTL Class II 1.8-V Differential HSTL Class I 1.8-V Differential HSTL Class II LVDS HyperTransport LVPECL Notes to Table 5-34:
(1) (2) (3) (4) (5)
Notes (1), (2), (3) Measurement Point VTT (V) CL (pF)
0 0 0 0 0 10 10 1.123 1.123 0.790 0.790 0.790 0.790 0.648 0.648 0 0 0 0 0 0 0 0 0 1.123 1.123 0.790 0.790 0.648 0.648 0.790 0.790 0 0 0 0 0 0 0 0 0 0 0
RD ()
RT ()
VCCIO (V)
3.135 3.135 2.375 1.710 1.425 2.970 2.970
VMEAS (V)
1.5675 1.5675 1.1875 0.855 0.7125 1.485 1.485 1.1625 1.1625 0.83 0.83 0.83 0.83 0.6875 0.6875 0.570 1.1625 1.1625 0.83 0.83 0.6875 0.6875 0.83 0.83 1.1625 1.1625 1.5675
25 25 25 25 50 25 50
50 25 50 25 50 25 50 25
2.325 2.325 1.660 1.660 1.660 1.660 1.375 1.375 1.140
50 50 25 50 25 50 50 25 50 25 50 25 50 25 100 100 100 50 25
2.325 2.325 1.660 1.660 1.375 1.375 1.660 1.660 2.325 2.325 3.135
Input measurement point at internal node is 0.5 x VCCINT. Output measuring point for VMEAS at buffer output is 0.5 x VCCIO. Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer. Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
5-24 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Figure 5-5. Measurement Setup for txz
Note (1)
tXZ, Driving High to Tristate Enable OE Dout Din Din OE Disable 1/2 VCCINT "1" 100 mv Dout thz GND
100
tXZ, Driving Low to Tristate Enable OE 100 OE Dout Din Dout Din tlz "0" VCCIO 100 mv Disable 1/2 VCCINT
Note to Figure 5-5:
(1) VCCINT is 1.12 V for this measurement.
Altera Corporation May 2007
5-25 Stratix II Device Handbook, Volume 1
Timing Model
Figure 5-6. Measurement Setup for tzx
tZX, Tristate to Driving High Disable OE Dout Din 1 M Dout tzh 1/2 VCCIO Din "1" OE Enable 1/2 VCCINT
tZX, Tristate to Driving Low Disable OE 1 M OE Dout Din Dout tzl Din "0" 1/2 VCCIO Enable 1/2 VCCINT
Table 5-35 specifies the input timing measurement setup.
Table 5-35. Timing Measurement Methodology for Input Pins (Part 1 of 2) Measurement Conditions I/O Standard VCCIO (V)
LVTTL (5) LVCMOS (5) 2.5 V (5) 1.8 V (5) 1.5 V (5) PCI (6) PCI-X (6) SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 3.135 3.135 2.375 1.710 1.425 2.970 2.970 2.325 2.325 1.660 1.660 1.660 1.163 1.163 0.830 0.830 0.830
Notes (1)-(4) Measurement Point VM E A S (V)
1.5675 1.5675 1.1875 0.855 0.7125 1.485 1.485 1.1625 1.1625 0.83 0.83 0.83
VREF (V)
Edge Rate (ns)
3.135 3.135 2.375 1.710 1.425 2.970 2.970 2.325 2.325 1.660 1.660 1.660
5-26 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-35. Timing Measurement Methodology for Input Pins (Part 2 of 2) Measurement Conditions I/O Standard VCCIO (V)
1.8-V HSTL Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.2-V HSTL with OCT Differential SSTL-2 Class I Differential SSTL-2 Class II Differential SSTL-18 Class I Differential SSTL-18 Class II 1.5-V Differential HSTL Class I 1.5-V Differential HSTL Class II 1.8-V Differential HSTL Class I 1.8-V Differential HSTL Class II LVDS HyperTransport LVPECL Notes to Table 5-35:
(1) (2) (3) (4) (5) (6)
Notes (1)-(4) Measurement Point VM E A S (V)
0.83 0.6875 0.6875 0.570 1.1625 1.1625 0.83 0.83 0.6875 0.6875 0.83 0.83 1.1625 1.1625 1.5675
VREF (V)
0.830 0.688 0.688 0.570 1.163 1.163 0.830 0.830 0.688 0.688 0.830 0.830
Edge Rate (ns)
1.660 1.375 1.375 1.140 2.325 2.325 1.660 1.660 1.375 1.375 1.660 1.660 0.100 0.400 0.100
1.660 1.375 1.375 1.140 2.325 2.325 1.660 1.660 1.375 1.375 1.660 1.660 2.325 2.325 3.135
Input buffer sees no load at buffer input. Input measuring point at buffer input is 0.5 x VCCIO. Output measuring point is 0.5 x VCC at internal node. Input edge rate is 1 V/ns. Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
Performance
Table 5-36 shows Stratix II performance for some common designs. All performance values were obtained with the Quartus II software compilation of library of parameterized modules (LPM), or MegaCore(R) functions for the finite impulse response (FIR) and fast Fourier transform (FFT) designs.
Altera Corporation May 2007
5-27 Stratix II Device Handbook, Volume 1
Timing Model
1
The performance numbers in Table 5-36 are extracted from the Quartus II software version 5.1 SP1.
Table 5-36. Stratix II Performance Notes (Part 1 of 6) Resources Used Applications ALUTs TriMatrix Memory Blocks
0 0 0 0 1 1 1 1 1 1 1
Note (1) Performance -3 Speed Grade (2)
654.87 519.21 566.57 244.31 500.00 500.00 540.54 540.54 530.22 475.28 475.28
DSP Blocks
0 0 0 0 0 0 0 0 0 0 0
-3 Speed Grade (3)
625.0 473.26 538.79 232.07 476.19 476.19 515.46 515.46 499.00 453.30 453.30
-4 Speed Grade
523.83 464.25 489.23 209.11 434.02 434.78 469.48 469.48 469.48 413.22 413.22
-5 Speed Grade
460.4 384.17 421.05 181.38 373.13 373.13 401.60 401.60 401.60 354.10 354.10
Unit
LE
16-to-1 multiplexer (4) 32-to-1 multiplexer (4) 16-bit counter 64-bit counter
21 38 16 64 0 22 0 0 22 0 0
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
TriMatrix Memory M512 block TriMatrix Memory M4K block
Simple dual-port RAM 32 x 18 bit FIFO 32 x 18 bit Simple dual-port RAM 128 x 36 bit (8) True dual-port RAM 128 x 18 bit (8) FIFO 128 x 36 bit Simple dual-port RAM 128 x 36 bit (9) True dual-port RAM 128 x 18 bit (9)
5-28 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-36. Stratix II Performance Notes (Part 2 of 6) Resources Used Applications ALUTs TriMatrix Memory Blocks
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Note (1) Performance -3 Speed Grade (2)
349.65 420.16 349.65 354.60 420.16 349.65 364.96 420.16 359.71 364.96 420.16 359.71 364.96 420.16 359.71
DSP Blocks
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
-3 Speed Grade (3)
333.33 400.00 333.33 337.83 400.00 333.33 347.22 400.00 342.46 347.22 400.0 342.46 347.22 400.0 342.46
-4 Speed Grade
303.95 364.96 303.95 307.69 364.96 303.95 317.46 364.96 313.47 317.46 364.96 313.47 317.46 364.96 313.47
-5 Speed Grade
261.09 313.47 261.09 263.85 313.47 261.09 271.73 313.47 268.09 271.73 313.47 268.09 271.73 313.47 268.09
Unit
TriMatrix Memory M-RAM block
Single port RAM 4K x 144 bit Simple dual-port RAM 4K x 144 bit True dual-port RAM 4K x 144 bit Single port RAM 8K x 72 bit Simple dual-port RAM 8K x 72 bit True dual-port RAM 8K x 72 bit Single port RAM 16K x 36 bit Simple dual-port RAM 16K x 36 bit True dual-port RAM 16K x 36 bit Single port RAM 32K x 18 bit Simple dual-port RAM 32K x 18 bit True dual-port RAM 32K x 18 bit Single port RAM 64K x 9 bit Simple dual-port RAM 64K x 9 bit True dual-port RAM 64K x 9 bit
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation May 2007
5-29 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-36. Stratix II Performance Notes (Part 3 of 6) Resources Used Applications ALUTs TriMatrix Memory Blocks
0 0 0 0 0 0 0 22
Note (1) Performance -3 Speed Grade (2)
430.29 410.17 450.04 250.00 410.17 410.17 259.06 398.72
DSP Blocks
1 1 1 1 1 1 4 9
-3 Speed Grade (3)
409.16 390.01 428.08 238.15 390.01 390.01 240.61 364.03
-4 Speed Grade
373.13 356.12 391.23 217.48 356.12 356.12 217.15 355.23
-5 Speed Grade
320.10 305.06 335.12 186.60 305.06 305.06 185.01 306.37
Unit
DSP block
9 x 9-bit multiplier (5) 18 x 18-bit multiplier (5) 18 x 18-bit multiplier (7) 36 x 36-bit multiplier (5) 36 x 36-bit multiplier (6) 18-bit, four-tap FIR filter
0 0 0 0 0 0 58 2976
MHz MHz MHz MHz MHz MHz MHz MHz
Larger designs
8-bit,16-tap parallel FIR filter 8-bit, 1024-point, streaming, three multipliers and five adders FFT function 8-bit, 1024-point, streaming, four multipliers and two adders FFT function 8-bit, 1024-point, single output, one parallel FFT engine, burst, three multipliers and five adders FFT function 8-bit, 1024-point, single output, one parallel FFT engine, burst, four multipliers and two adders FFT function
2781
22
12
398.56
409.16
347.22
311.13
MHz
984
5
3
425.17
365.76
346.98
292.39
MHz
919
5
4
427.53
378.78
357.14
307.59
MHz
5-30 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-36. Stratix II Performance Notes (Part 4 of 6) Resources Used Applications ALUTs TriMatrix Memory Blocks
10
Note (1) Performance -3 Speed Grade (2)
430.29
DSP Blocks
6
-3 Speed Grade (3)
401.92
-4 Speed Grade
373.13
-5 Speed Grade
319.08
Unit
Larger designs
8-bit, 1024-point, single output, two parallel FFT engines, burst, three multiplier and five adders FFT function 8-bit, 1024-point, single output, two parallel FFT engines, burst, four multipliers and two adders FFT function 8-bit, 1024-point, quadrant output, one parallel FFT engine, burst, three multipliers and five adders FFT function 8-bit, 1024-point, quadrant output, one parallel FFT engine, burst, four multipliers and two adders FFT function 8-bit, 1024-point, quadrant output, two parallel FFT engines, burst, three multipliers and five adders FFT function 8-bit, 1024-point, quadrant output, two parallel FFT engines, burst, four multipliers and two adders FFT function
1725
MHz
1594
10
8
422.65
407.33
373.13
329.10
MHz
2361
10
9
315.45
342.81
325.73
284.25
MHz
2165
10
12
373.13
369.54
317.96
256.14
MHz
3996
14
18
378.50
367.10
332.33
288.68
MHz
3604
14
24
391.38
361.14
340.25
280.89
MHz
Altera Corporation May 2007
5-31 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-36. Stratix II Performance Notes (Part 5 of 6) Resources Used Applications ALUTs TriMatrix Memory Blocks
28
Note (1) Performance -3 Speed Grade (2)
334.11
DSP Blocks
36
-3 Speed Grade (3)
345.66
-4 Speed Grade
308.54
-5 Speed Grade
276.31
Unit
Larger designs
8-bit, 1024-point, quadrant output, four parallel FFT engines, burst, three multipliers and five adders FFT function 8-bit, 1024-point, quadrant output, four parallel FFT engines, burst, four multipliers two adders FFT function 8-bit, 1024-point, quadrant output, one parallel FFT engine, buffered burst, three multipliers and adders FFT function 8-bit, 1024-point, quadrant output, one parallel FFT engine, buffered burst, four multipliers and two adders FFT function 8-bit, 1024-point, quadrant output, two parallel FFT engines, buffered burst, three multipliers five adders FFT function 8-bit, 1024-point, quadrant output, two parallel FFT engines, buffered burst four multipliers and two adders FFT function
6850
MHz
6067
28
48
367.91
349.04
327.33
268.24
MHz
2730
18
9
387.44
388.34
364.56
306.84
MHz
2534
18
12
419.28
369.66
364.96
307.88
MHz
4358
30
18
396.51
378.07
340.13
291.29
MHz
3966
30
24
389.71
398.08
356.53
280.74
MHz
5-32 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-36. Stratix II Performance Notes (Part 6 of 6) Resources Used Applications ALUTs TriMatrix Memory Blocks
60
Note (1) Performance -3 Speed Grade (2)
359.58
DSP Blocks
36
-3 Speed Grade (3)
352.98
-4 Speed Grade
312.01
-5 Speed Grade
278.00
Unit
Larger designs
8-bit, 1024-point, quadrant output, four parallel FFT engines, buffered burst, three multipliers five adders FFT function 8-bit, 1024-point, quadrant output, four parallel FFT engines, buffered burst, four multipliers and two adders FFT function
7385
MHz
6601
60
48
371.88
355.74
327.86
277.62
MHz
Notes for Table 5-36:
(1) (2) (3) (4) (5) (6) (7) (8) (9) These design performance numbers were obtained using the Quartus II software version 5.0 SP1. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. This application uses registered inputs and outputs. This application uses registered multiplier input and output stages within the DSP block. This application uses registered multiplier input, pipeline, and output stages within the DSP block. This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or subtractor within the DSP block. This application uses the same clock source that is globally routed and connected to ports A and B. This application uses locally routed clocks or differently sourced clocks for ports A and B.
Altera Corporation May 2007
5-33 Stratix II Device Handbook, Volume 1
Timing Model
Internal Timing Parameters
See Tables 5-37 through 5-42 for internal timing parameters.
Table 5-37. LE_FF Internal Timing Microparameters -3 Speed Grade (1) Symbol Parameter Min (3)
tS U tH tC O tC L R tP R E tC L K L tC L K H tL U T tA D D E R Notes to Table 5-37:
(1) (2) (3) (4) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
-3 Speed Grade (2) Min (3)
95 157
-4 Speed Grade Min (4)
104 104 172 172
-5 Speed Grade Unit Min (3)
121 200
Max
Max
Max
Max
ps ps 127 ps ps ps ps ps 507 829 ps ps
LE register setup time before clock LE register hold time after clock LE register clock-to-output delay Minimum clear pulse width Minimum preset pulse width Minimum clock low time Minimum clock high time
90 149 62 204 204 612 612 162 354 378 619 94
62 214 214 642 642 162 354
99
59 62 234 234 234 234 703 703 703 703
109
62 273 273 820 820
397 650
162 170 354 372
435 712
162 354
5-34 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-38. IOE Internal Timing Microparameters -3 Speed Grade (1) Symbol Parameter Min (3)
tS U IOE input and output register setup time before clock IOE input and output register hold time after clock IOE input and output register clock-tooutput delay 122
-3 Speed Grade (2) Min (3)
128
-4 Speed Grade Min (4)
140 140 82 82
-5 Speed Grade Unit Min (3)
163
Max
Max
Max
Max
ps
tH
72
75
96
ps
tC O
101
169
101
177
97 101 391 410 408 428
194
101
226
ps
tP I N 2 C O M B O U T _ R Row input pin to IOE combinational output tP I N 2 C O M B O U T _ C Column input pin to IOE combinational output tC O M B I N 2 P I N _ R Row IOE data input to combinational output pin Column IOE data input to combinational output pin Minimum clear pulse width Minimum preset pulse width Minimum clock low time Minimum clock high time
410 428
760 787
410 428
798 825
873 904
410 428
1,018 1,054
ps ps
1,101
2,026 1,101
2,127
1,049 2,329 1,101 944 991 229 229 229 229 690 690 690 690 2,131
1,101
2,439
ps
tC O M B I N 2 P I N _ C
991
1,854
991
1,946
991
2,246
ps
tC L R tP R E tC L K L tC L K H
200 200 600 600
210 210 630 630
268 268 804 804
ps ps ps ps
Notes to Table 5-38:
(1) (2) (3) (4) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
Altera Corporation May 2007
5-35 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-39. DSP Block Internal Timing Microparameters (Part 1 of 2) -3 Speed Grade (1) Symbol Parameter Min (3)
tS U Input, pipeline, and output register setup time before clock Input, pipeline, and output register hold time after clock Input, pipeline, and output register clockto-output delay Input register to DSP block pipeline register in 9 x 9-bit mode Input register to DSP block pipeline register in 18 x 18-bit mode Input register to DSP block pipeline register in 36 x 36-bit mode 50
-3 Speed Grade (2) Min (3)
52
-4 Speed Grade Min (4)
57 57 206 206
-5 Speed Grade Unit Min (3)
67
Max
Max
Max
Max
ps
tH
180
189
241
ps
tC O
0
0
0
0
0 0
0
0
0
ps
tI N R E G 2 P I P E 9
1,312 2,030 1,312 2,030 1,250 2,334 1,312 2,720 1,312 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 1,302 1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693 1,302 924 1,450 924 1,522 880 924 1,667 924 1,943
ps
tI N R E G 2 P I P E 1 8
ps
tI N R E G 2 P I P E 3 6
ps
tP I P E 2 O U T R E G 2 A D D DSP block pipeline register to output register delay in twomultipliers adder mode tP I P E 2 O U T R E G 4 A D D DSP block pipeline register to output register delay in fourmultipliers adder mode tP D 9 Combinational input to output delay for 9x9 Combinational input to output delay for 18 x 18 Combinational input to output delay for 36 x 36 Minimum clear pulse width
ps
1,134 1,850 1,134 1,942 1,080 2,127 1,134 2,479 1,134
ps
2,100 2,880 2,100 3,024 2,000 3,312 2,100 3,859 2,100 2,110 2,990 2,110 3,139 2,010 3,438 2,110 4,006 2,110 2,939 4,450 2,939 4,672 2,800 5,117 2,939 5,962 2,939 2,212 2,322 2,543 2,543 2,964
ps
tP D 1 8
ps
tP D 3 6
ps
tC L R
ps
5-36 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-39. DSP Block Internal Timing Microparameters (Part 2 of 2) -3 Speed Grade (1) Symbol Parameter Min (3)
tC L K L tC L K H Notes to Table 5-39:
(1) (2) (3) (4) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
-3 Speed Grade (2) Min (3)
1,249 1,249
-4 Speed Grade Min (4)
1,368 1,368 1,368 1,368
-5 Speed Grade Unit Min (3)
1,594 1,594
Max
Max
Max
Max
ps ps
Minimum clock low time Minimum clock high time
1,190 1,190
Table 5-40. M512 Block Internal Timing Microparameters (Part 1 of 2) -3 Speed Grade (2) Symbol Parameter Min (4)
tM 5 1 2 R C tM 5 1 2 W E R E S U tM 5 1 2 W E R E H tM 5 1 2 D ATA S U tM 5 1 2 D ATA H Synchronous read cycle time Write or read enable setup time before clock Write or read enable hold time after clock Data setup time before clock Data hold time after clock 2,089 22 203 22 203 22 203 22 203
Note (1) -4 Speed Grade Min (5) Max -5 Speed Grade Unit Min (4)
2,089 29 272 29 272 29 272 29 272
-3 Speed Grade (3) Min (4) Max
2.433
Max
Max
3,104 ps ps ps ps ps ps ps ps ps
2,318 2,089 23 213 23 213 23 213 23 213
1,989 2,664 2,089 25 25 233 233 25 25 233 233 25 25 233 233 25 25 233 233
tM 5 1 2 WA D D R S U Write address setup time before clock tM 5 1 2 WA D D R H tM 5 1 2 R A D D R S U tM 5 1 2 R A D D R H Write address hold time after clock Read address setup time before clock Read address hold time after clock
Altera Corporation May 2007
5-37 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-40. M512 Block Internal Timing Microparameters (Part 2 of 2) -3 Speed Grade (2) Symbol Parameter Min (4)
tM 5 1 2 D ATA C O 1 Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock low time 298
Note (1) -4 Speed Grade Min (5)
284 298 2,003 2,102 1,512 1,512 1,512 1,512 165 165
-3 Speed Grade (3) Min (4)
298
-5 Speed Grade Unit Min (4)
298
Max
478
Max
501
Max
548
Max
640 ps
tM 5 1 2 D ATA C O 2 tM 5 1 2 C L K L tM 5 1 2 C L K H tM 5 1 2 C L R
2,102 1,315
2,345 2,102 1,380 1,380 151
2,461
2,695
2,102 1,762 1,762 192
3,141
ps ps ps ps
Minimum clock high time 1,315 Minimum clear pulse width 144
Notes to Table 5-40:
(1) (2) (3) (4) (5) FMAX of M512 block obtained using the Quartus II software does not necessarily equal to 1/TM512RC. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
Table 5-41. M4K Block Internal Timing Microparameters (Part 1 of 2) -3 Speed Grade (2) Symbol Parameter Min (4)
tM 4 K R C tM 4 K W E R E S U tM 4 K W E R E H tM 4 K B E S U tM 4 K B E H Synchronous read cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock 1,462 22 203 22 203
Note (1) -4 Speed Grade Min (5)
1,393 1,462 25 25 233 233 25 25 233 233
-3 Speed Grade (3) Min (4)
1,462 23 213 23 213
-5 Speed Grade Unit Min (4) Max
ps ps ps ps ps
Max
2,240
Max
2,351
Max
2,575
1,462 3,000 29 272 29 272
5-38 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-41. M4K Block Internal Timing Microparameters (Part 2 of 2) -3 Speed Grade (2) Symbol Parameter Min (4)
tM 4 K D ATA A S U tM 4 K D ATA A H tM 4 K A D D R A S U tM 4 K A D D R A H tM 4 K D ATA B S U tM 4 K D ATA B H A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock B port data setup time before clock B port data hold time after clock 22 203 22 203 22 203 22 203 334 524
Note (1) -4 Speed Grade Min (5)
25 25 233 233 25 25 233 233 25 25 233 233 25 25 233 233
-3 Speed Grade (3) Min (4)
23 213 23 213 23 213 23 213 334 549
-5 Speed Grade Unit Min (4)
29 272 29 272 29 272 29 272
Max
Max
Max
Max
ps ps ps ps ps ps ps ps 701 ps
tM 4 K R A D D R B S U B port address setup time before clock tM 4 K R A D D R B H tM 4 K D ATA C O 1 B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers
319 334 1,540 1,616 1,437 1,437 1,437 1,437 165 165
601
334
tM 4 K D ATA C O 2 (6) tM 4 K C L K H tM 4 K C L K L tM 4 K C L R
1,616
2,453
1,616 1,312 1,312 151
2,574
2,820
1,616 3,286 1,675 1,675 192
ps ps ps ps
Minimum clock high time 1,250 Minimum clock low time Minimum clear pulse width 1,250 144
Notes to Table 5-41:
(1) (2) (3) (4) (5) (6) FMAX of M4K Block obtained using the Quartus II software does not necessarily equal to 1/TM4KRC. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices. Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes that use locally routed or non-identical sources for the A and B port registers.
Altera Corporation May 2007
5-39 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-42. M-RAM Block Internal Timing Microparameters (Part 1 of 2) -3 Speed Grade (2) Symbol Parameter Min (4)
tM E G A R C tM E G AW E R E S U tM E G AW E R E H tM E G A B E S U tM E G A B E H tM E G A D ATA A S U tM E G A D ATA A H Synchronous read cycle time Write or read enable setup time before clock Write or read enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock 1,866 144 39 50 39 50 243 589 241 50 243 589 241 480 715
Note (1) -4 Speed Grade -5 Speed Grade Unit Min (4)
1,777 1,866 192 52 67 52 67 325 789 322 67 325 789 322 821 480 957
-3 Speed Grade (3) Min (4)
1,866 151 40 52 40 52 255 618 253 52 255 618 253 480 749
Max
2,774
Max
2,911
Min (5)
1,777 1,866 165 165 44 44 57 57 44 44 57 57 279 279 677 677 277 277 57 57 279 279 677 677 277 277 457 480 1,857 1,950 1,437 1,437
Max
3,189
Max
3,716 ps ps ps ps ps ps ps ps ps ps ps ps ps ps
tM E G A A D D R A S U A port address setup time before clock tM E G A A D D R A H tM E G A D ATA B S U tM E G A D ATA B H A port address hold time after clock B port setup time before clock B port hold time after clock
tM E G A A D D R B S U B port address setup time before clock tM E G A A D D R B H tM E G A D ATA C O 1 B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Minimum clock low time
tM E G A D ATA C O 2 tM E G A C L K L
1,950 1,250
2,899
1,950 1,312
3,042
3,332
1,950 1,675
3,884
ps ps
5-40 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-42. M-RAM Block Internal Timing Microparameters (Part 2 of 2) -3 Speed Grade (2) Symbol Parameter Min (4)
tM E G A C L K H tM E G A C L R Minimum clock high time Minimum clear pulse width 1,250 144
Note (1) -4 Speed Grade -5 Speed Grade Unit Min (4)
1,675 192
-3 Speed Grade (3) Min (4)
1,312 151
Max
Max
Min (5)
1,437 1,437 165 165
Max
Max
ps ps
Notes to Table 5-42:
(1) (2) (3) (4) (5) FMAX of M-RAM Block obtained using the Quartus II software does not necessarily equal to 1/TMEGARC. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices. For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade. For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.
Stratix II Clock Timing Parameters
See Tables 5-43 through 5-67 for Stratix II clock timing parameters.
Table 5-43. Stratix II Clock Timing Parameters Symbol
tC I N tC O U T tP L L C I N tP L L C O U T
Parameter
Delay from clock pad to I/O input register Delay from clock pad to I/O output register Delay from PLL inclk pad to I/O input register Delay from PLL inclk pad to I/O output register
Altera Corporation May 2007
5-41 Stratix II Device Handbook, Volume 1
Timing Model
EP2S15 Clock Timing Parameters
Tables 5-44 though 5-47 show the maximum clock timing parameters for EP2S15 devices.
Table 5-44. EP2S15 Column Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.445 1.288 0.104 -0.053
Commercial
1.512 1.347 0.102 -0.063
-3 Speed Grade
2.487 2.245 0.336 0.094
-4 Speed Grade
2.848 2.570 0.373 0.095
-5 Speed Grade
3.309 2.985 0.424 0.1
Unit
ns ns ns ns
Table 5-45. EP2S15 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.419 1.262 0.094 -0.063
Commercial
1.487 1.322 0.092 -0.073
-3 Speed Grade
2.456 2.214 0.326 0.084
-4 Speed Grade
2.813 2.535 0.363 0.085
-5 Speed Grade
3.273 2.949 0.414 0.09
Unit
ns ns ns ns
Table 5-46. EP2S15 Row Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.232 1.237 -0.109 -0.104
Commercial
1.288 1.293 -0.122 -0.117
-3 Speed Grade
2.144 2.140 -0.007 -0.011
-4 Speed Grade
2.454 2.450 -0.021 -0.025
-5 Speed Grade
2.848 2.843 -0.037 -0.042
Unit
ns ns ns ns
5-42 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-47. EP2S15 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.206 1.211 -0.125 -0.12
Commercial
1.262 1.267 -0.138 -0.133
-3 Speed Grade
2.113 2.109 -0.023 -0.027
-4 Speed Grade
2.422 2.418 -0.038 -0.042
-5 Speed Grade
2.815 2.810 -0.056 -0.061
Unit
ns ns ns ns
EP2S30 Clock Timing Parameters
Tables 5-48 through 5-51 show the maximum clock timing parameters for EP2S30 devices.
Table 5-48. EP2S30 Column Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.553 1.396 0.114 -0.043
Commercial
1.627 1.462 0.113 -0.052
-3 Speed Grade
2.639 2.397 0.225 -0.017
-4 Speed Grade
3.025 2.747 0.248 -0.03
-5 Speed Grade
3.509 3.185 0.28 -0.044
Unit
ns ns ns ns
Table 5-49. EP2S30 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.539 1.382 0.101 -0.056
Commercial
1.613 1.448 0.098 -0.067
-3 Speed Grade
2.622 2.380 0.209 -0.033
-4 Speed Grade
3.008 2.730 0.229 -0.049
-5 Speed Grade
3.501 3.177 0.267 -0.057
Unit
ns ns ns ns
Altera Corporation May 2007
5-43 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-50. EP2S30 Row Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.304 1.309 -0.135 -0.13
Commercial
1.184 1.189 -0.158 -0.153
-3 Speed Grade
1.966 1.962 -0.208 -0.212
-4 Speed Grade
2.251 2.247 -0.254 -0.258
-5 Speed Grade
2.616 2.611 -0.302 -0.307
Unit
ns ns ns ns
Table 5-51. EP2S30 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.289 1.294 -0.14 -0.135
Commercial
1.352 1.357 -0.154 -0.149
-3 Speed Grade
2.238 2.234 -0.169 -0.173
-4 Speed Grade
2.567 2.563 -0.205 -0.209
-5 Speed Grade
2.990 2.985 -0.254 -0.259
Unit
ns ns ns ns
EP2S60 Clock Timing Parameters
Tables 5-52 through 5-55 show the maximum clock timing parameters for EP2S60 devices.
Table 5-52. EP2S60 Column Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.681 1.524 0.066 -0.091
Commercial
1.762 1.597 0.064 -0.101
-3 Speed Grade
2.945 2.703 0.279 0.037
-4 Speed Grade
3.381 3.103 0.311 0.033
-5 Speed Grade
3.931 3.607 0.348 0.024
Unit
ns ns ns ns
5-44 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-53. EP2S60 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.658 1.501 0.06 -0.097
Commercial
1.739 1.574 0.057 -0.108
-3 Speed Grade
2.920 2.678 0.278 0.036
-4 Speed Grade
3.350 3.072 0.304 0.026
-5 Speed Grade
3.899 3.575 0.355 0.031
Unit
ns ns ns ns
Table 5-54. EP2S60 Row Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.463 1.468 -0.153 -0.148
Commercial
1.532 1.537 -0.167 -0.162
-3 Speed Grade
2.591 2.587 -0.079 -0.083
-4 Speed Grade
2.972 2.968 -0.099 -0.103
-5 Speed Grade
3.453 3.448 -0.128 -0.133
Unit
ns ns ns ns
Table 5-55. EP2S60 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.439 1.444 -0.161 -0.156
Commercial
1.508 1.513 -0.174 -0.169
-3 Speed Grade
2.562 2.558 -0.083 -0.087
-4 Speed Grade
2.940 2.936 -0.107 -0.111
-5 Speed Grade
3.421 3.416 -0.126 -0.131
Unit
ns ns ns ns
Altera Corporation May 2007
5-45 Stratix II Device Handbook, Volume 1
Timing Model
EP2S90 Clock Timing Parameters
Tables 5-56 through 5-59 show the maximum clock timing parameters for EP2S90 devices.
Table 5-56. EP2S90 Column Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.768 1.611 -0.127 -0.284
Commercial
1.850 1.685 -0.117 -0.282
-3 Speed Grade
3.033 2.791 0.125 -0.117
-4 Speed Grade
3.473 3.195 0.129 -0.149
-5 Speed Grade
4.040 3.716 0.144 -0.18
Unit
ns ns ns ns
Table 5-57. EP2S90 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.783 1.626 -0.137 -0.294
Commercial
1.868 1.703 -0.127 -0.292
-3 Speed Grade
3.058 2.816 0.115 -0.127
-4 Speed Grade
3.502 3.224 0.119 -0.159
-5 Speed Grade
4.070 3.746 0.134 -0.19
Unit
ns ns ns ns
Table 5-58. EP2S90 Row Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.566 1.571 -0.326 -0.321
Commercial
1.638 1.643 -0.326 -0.321
-3 Speed Grade
2.731 2.727 -0.178 -0.182
-4 Speed Grade
3.124 3.120 -0.218 -0.222
-5 Speed Grade
3.632 3.627 -0.264 -0.269
Unit
ns ns ns ns
5-46 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-59. EP2S90 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.585 1.590 -0.341 -0.336
Commercial
1.658 1.663 -0.341 -0.336
-3 Speed Grade
2.757 2.753 -0.193 -0.197
-4 Speed Grade
3.154 3.150 -0.235 -0.239
-5 Speed Grade
3.665 3.660 -0.278 -0.283
Unit
ns ns ns ns
EP2S130 Clock Timing Parameters
Tables 5-60 through 5-63 show the maximum clock timing parameters for EP2S130 devices.
Table 5-60. EP2S130 Column Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.889 1.732 0.105 -0.052
Commercial
1.981 1.816 0.106 -0.059
-3 Speed Grade
3.405 3.151 0.226 -0.028
-4 Speed Grade
3.722 3.444 0.242 -0.036
-5 Speed Grade
4.326 4.002 0.277 -0.047
Unit
ns ns ns ns
Table 5-61. EP2S130 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.907 1.750 0.134 -0.023
Commercial
1.998 1.833 0.136 -0.029
-3 Speed Grade
3.420 3.166 0.276 0.022
-4 Speed Grade
3.740 3.462 0.296 0.018
-5 Speed Grade
4.348 4.024 0.338 0.014
Unit
ns ns ns ns
Altera Corporation May 2007
5-47 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-62. EP2S130 Row Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.680 1.685 -0.113 -0.108
Commercial
1.760 1.765 -0.124 -0.119
-3 Speed Grade
3.070 3.066 -0.12 -0.124
-4 Speed Grade
3.351 3.347 -0.138 -0.142
-5 Speed Grade
3.892 3.887 -0.168 -0.173
Unit
ns ns ns ns
Table 5-63. EP2S130 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.690 1.695 -0.087 -0.082
Commercial
1.770 1.775 -0.097 -0.092
-3 Speed Grade
3.075 3.071 -0.075 -0.079
-4 Speed Grade
3.362 3.358 -0.089 -0.093
-5 Speed Grade
3.905 3.900 -0.11 -0.115
Unit
ns ns ns ns
EP2S180 Clock Timing Parameters
Tables 5-64 through 5-67 show the maximum clock timing parameters for EP2S180 devices.
Table 5-64. EP2S180 Column Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 2.001 1.844 -0.307 -0.464
Commercial
2.095 1.930 -0.297 -0.462
-3 Speed Grade
3.643 3.389 0.053 -0.201
-4 Speed Grade
3.984 3.706 0.046 -0.232
-5 Speed Grade
4.634 4.310 0.048 -0.276
Unit
ns ns ns ns
5-48 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-65. EP2S180 Column Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 2.003 1.846 -0.3 -0.457
Commercial
2.100 1.935 -0.29 -0.455
-3 Speed Grade
3.652 3.398 0.053 -0.201
-4 Speed Grade
3.993 3.715 0.054 -0.224
-5 Speed Grade
4.648 4.324 0.058 -0.266
Unit
ns ns ns ns
Table 5-66. EP2S180 Row Pins Regional Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.759 1.764 -0.542 -0.537
Commercial
1.844 1.849 -0.541 -0.536
-3 Speed Grade
3.273 3.269 -0.317 -0.321
-4 Speed Grade
3.577 3.573 -0.353 -0.357
-5 Speed Grade
4.162 4.157 -0.414 -0.419
Unit
ns ns ns ns
Table 5-67. EP2S180 Row Pins Global Clock Timing Parameters Minimum Timing Parameter Industrial
tC I N tC O U T tP L L C I N tP L L C O U T 1.763 1.768 -0.542 -0.537
Commercial
1.850 1.855 -0.542 -0.537
-3 Speed Grade
3.285 3.281 -0.319 -0.323
-4 Speed Grade
3.588 3.584 -0.355 -0.359
-5 Speed Grade
4.176 4.171 -0.42 -0.425
Unit
ns ns ns ns
Altera Corporation May 2007
5-49 Stratix II Device Handbook, Volume 1
Timing Model
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks such as global and regional clocks. Therefore, intra-clock network skew adder is not specified. Table 5-68 specifies the clock skew between any two clock networks driving registers in the IOE.
Table 5-68. Clock Network Specifications Name
Clock skew adder EP2S15, EP2S30, EP2S60 (1) Clock skew adder EP2S90 (1) Clock skew adder EP2S130 (1) Clock skew adder EP2S180 (1) Note to Table 5-68:
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Description
Inter-clock network, same side Inter-clock network, entire chip Inter-clock network, same side Inter-clock network, entire chip Inter-clock network, same side Inter-clock network, entire chip Inter-clock network, same side Inter-clock network, entire chip
Min
Typ
Max
50 100 55 110 63 125 75 150
Unit
ps ps ps ps ps ps ps ps
5-50 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
IOE Programmable Delay
See Tables 5-69 and 5-70 for IOE programmable delay.
Table 5-69. Stratix II IOE Programmable Delay on Column Pins Minimum Timing (2) Parameter Paths Affected Available Settings
Note (1) -4 Speed Grade -5 Speed Grade
-3 Speed Grade (3)
Min Max Min Max Min Max Min Max Offset Offset Offset Offset Offset Offset Offset Offset (ps) (ps) (ps) (ps) (ps) (ps) (ps) (ps)
0 0 0 0 0 0 0 0 1,696 1,781 1,955 2,053 316 332 305 320 0 0 0 0 0 0 0 0 2,881 3,025 3,275 3,439 500 525 483 507 0 3,313 0 3,860
Input delay from Pad to I/O dataout to logic pin to internal array cells Input delay from Pad to I/O input register pin to input register Delay from output register to output pin Output enable pin delay
(1) (2) (3)
8
64
0
3,766
0
4,388
I/O output register to pad tX Z , tZ X
2
0
575
0
670
2
0
556
0
647
Notes to Table 5-69:
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest version of the Quartus II software. The first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices. The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number applies to -3 speed grade EP2S130 and EP2S180 devices.
Altera Corporation May 2007
5-51 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-70. Stratix II IOE Programmable Delay on Row Pins Minimum Timing (2) Parameter Paths Affected Available Settings
Note (1) -3 Speed Grade (3) -4 Speed Grade -5 Speed Grade
Min Max Min Max Min Max Min Max Offset Offset Offset Offset Offset Offset Offset Offset (ps) (ps) (ps) (ps) (ps) (ps) (ps) (ps)
0 0 0 0 0 0 0 0 1,697 1,782 1,956 2,054 316 332 305 320 0 0 0 0 0 0 0 0 2,876 3,020 3,270 3,434 525 525 507 507 0 3,308 0 3,853
Input delay from Pad to I/O dataout to logic pin to internal array cells Input delay from Pad to I/O input register pin to input register Delay from output register to output pin Output enable pin delay
(1) (2) (3)
8
64
0
3,761
0
4,381
I/O output register to pad tX Z , tZ X
2
0
575
0
670
2
0
556
0
647
Notes to Table 5-70:
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the latest version of the Quartus II software. The first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices. The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number applies to -3 speed grade EP2S130 and EP2S180 devices.
Default Capacitive Loading of Different I/O Standards
See Table 5-71 for default capacitive loading of different I/O standards.
Table 5-71. Default Loading of Different I/O Standards for Stratix II (Part 1 of 2) I/O Standard
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V PCI PCI-X SSTL-2 Class I
Capacitive Load
0 0 0 0 0 10 10 0
Unit
pF pF pF pF pF pF pF pF
5-52 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-71. Default Loading of Different I/O Standards for Stratix II (Part 2 of 2) I/O Standard
SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.2-V HSTL with OCT Differential SSTL-2 Class I Differential SSTL-2 Class II Differential SSTL-18 Class I Differential SSTL-18 Class II 1.5-V Differential HSTL Class I 1.5-V Differential HSTL Class II 1.8-V Differential HSTL Class I 1.8-V Differential HSTL Class II LVDS HyperTransport LVPECL
Capacitive Load
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Unit
pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF
Altera Corporation May 2007
5-53 Stratix II Device Handbook, Volume 1
Timing Model
I/O Delays
See Tables 5-72 through 5-76 for I/O delays.
Table 5-72. I/O Delay Parameters Symbol
tD I P tO P tP C O U T tP I
Parameter
Delay from I/O datain to output pad Delay from I/O output register to output pad Delay from input pad to I/O dataout to core Delay from input pad to I/O input register
Table 5-73. Stratix II I/O Input Delay for Column Pins (Part 1 of 3) Minimum Timing I/O Standard
LVTTL
Parameter Industrial
tP I tP C O U T 674 408 684 418 747 481 749 483 674 408 507 241 507 241 543 277 543 277 560 294
-3 Speed -3 Speed -4 Speed -5 Speed Grade Grade Grade Grade Commercial (2) (3)
707 428 717 438 783 504 786 507 707 428 530 251 530 251 569 290 569 290 587 308 1223 787 1210 774 1366 930 1436 1000 1223 787 818 382 818 382 898 462 898 462 993 557 1282 825 1269 812 1433 976 1506 1049 1282 825 857 400 857 400 941 484 941 484 1041 584 1405 904 1390 889 1570 1069 1650 1149 1405 904 939 438 939 438 1031 530 1031 530 1141 640 1637 1054 1619 1036 1829 1246 1922 1339 1637 1054 1094 511 1094 511 1201 618 1201 618 1329 746
Unit
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
2.5 V
tP I tP C O U T
1.8 V
tP I tP C O U T
1.5 V
tP I tP C O U T
LVCMOS
tP I tP C O U T
SSTL-2 Class I
tP I tP C O U T
SSTL-2 Class II
tP I tP C O U T
SSTL-18 Class I
tP I tP C O U T
SSTL-18 Class II
tP I tP C O U T
1.5-V HSTL Class I
tP I tP C O U T
5-54 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-73. Stratix II I/O Input Delay for Column Pins (Part 2 of 3) Minimum Timing I/O Standard
1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II PCI
Parameter Industrial
tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T 560 294 543 277 543 277 679 413 679 413 507 241 507 241 543 277 543 277 543 277 543 277 560 294 560 294
-3 Speed -3 Speed -4 Speed -5 Speed Grade Grade Grade Grade Commercial (2) (3)
587 308 569 290 569 290 712 433 712 433 530 251 530 251 569 290 569 290 569 290 569 290 587 308 587 308 993 557 898 462 898 462 1214 778 1214 778 818 382 818 382 898 462 898 462 898 462 898 462 993 557 993 557 1041 584 941 484 941 484 1273 816 1273 816 857 400 857 400 941 484 941 484 941 484 941 484 1041 584 1041 584 1141 640 1031 530 1031 530 1395 894 1395 894 939 438 939 438 1031 530 1031 530 1031 530 1031 530 1141 640 1141 640 1329 746 1201 618 1201 618 1625 1042 1625 1042 1094 511 1094 511 1201 618 1201 618 1201 618 1201 618 1329 746 1329 746
Unit
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
PCI-X
tP I tP C O U T
Differential SSTL-2 Class I (1) Differential SSTL-2 Class II (1) Differential SSTL-18 Class I (1) Differential SSTL-18 Class II (1) 1.8-V Differential HSTL Class I (1) 1.8-V Differential HSTL Class II (1) 1.5-V Differential HSTL Class I (1) 1.5-V Differential HSTL Class II (1)
tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T
Altera Corporation May 2007
5-55 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-73. Stratix II I/O Input Delay for Column Pins (Part 3 of 3) Minimum Timing I/O Standard
1.2-V HSTL
Parameter Industrial
tP I tP C O U T 645 379
-3 Speed -3 Speed -4 Speed -5 Speed Grade Grade Grade Grade Commercial (2) (3)
677 398 1194 758 1252 795 -
Unit
ps ps
Notes for Table 5-73:
(1) (2) (3) These I/O standards are only supported on DQS pins. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5-74. Stratix II I/O Input Delay for Row Pins (Part 1 of 2) Minimum Timing I/O Standard
LVTTL
Parameter Industrial
tP I tP C O U T 715 391 726 402 788 464 792 468 715 391 547 223 547 223 577 253 577 253 602 278
-3 Speed -3 Speed -4 Speed -5 Speed Grade Grade Grade Grade Commercial (1) (2)
749 410 761 422 827 488 830 491 749 410 573 234 573 234 605 266 605 266 631 292 1287 760 1273 746 1427 900 1498 971 1287 760 879 352 879 352 960 433 960 433 1056 529 1350 798 1335 783 1497 945 1571 1019 1350 798 921 369 921 369 1006 454 1006 454 1107 555 1477 873 1461 857 1639 1035 1720 1116 1477 873 1008 404 1008 404 1101 497 1101 497 1212 608 1723 1018 1704 999 1911 1206 2006 1301 1723 1018 1176 471 1176 471 1285 580 1285 580 1413 708
Unit
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
2.5 V
tP I tP C O U T
1.8 V
tP I tP C O U T
1.5 V
tP I tP C O U T
LVCMOS
tP I tP C O U T
SSTL-2 Class I
tP I tP C O U T
SSTL-2 Class II
tP I tP C O U T
SSTL-18 Class I
tP I tP C O U T
SSTL-18 Class II
tP I tP C O U T
1.5-V HSTL Class I
tP I tP C O U T
5-56 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-74. Stratix II I/O Input Delay for Row Pins (Part 2 of 2) Minimum Timing I/O Standard
1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II LVDS
Parameter Industrial
tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T 602 278 577 253 577 253 515 191 515 191
-3 Speed -3 Speed -4 Speed -5 Speed Grade Grade Grade Grade Commercial (1) (2)
631 292 605 266 605 266 540 201 540 201 1056 529 960 433 960 433 948 421 948 421 1107 555 1006 454 1006 454 994 442 994 442 1212 608 1101 497 1101 497 1088 484 1088 484 1413 708 1285 580 1285 580 1269 564 1269 564
Unit
ps ps ps ps ps ps ps ps ps ps
HyperTransport
tP I tP C O U T
Notes for Table 5-74:
(1) (2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 1 of 8) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 8 mA tO P tD I P 12 mA tO P tD I P 16 mA tO P tD I P 20 mA tO P tD I P 24 mA (1) tO P tD I P
Industrial
1178 1198 1041 1061 976 996 951 971 931 951 924 944
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
1236 1258 1091 1113 1024 1046 998 1020 976 998 969 991 2351 2417 2036 2102 2036 2102 1893 1959 1787 1853 1788 1854 2467 2537 2136 2206 2136 2206 1986 2056 1875 1945 1876 1946 2702 2778 2340 2416 2340 2416 2176 2252 2054 2130 2055 2131 2820 2910 2448 2538 2448 2538 2279 2369 2154 2244 2156 2246 ps ps ps ps ps ps ps ps ps ps ps ps
LVTTL
Altera Corporation May 2007
5-57 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 2 of 8) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 8 mA tO P tD I P 12 mA tO P tD I P 16 mA tO P tD I P 20 mA tO P tD I P 24 mA (1) 2.5 V 4 mA tO P tD I P tO P tD I P 8 mA tO P tD I P 12 mA tO P tD I P 16 mA (1) tO P tD I P
Industrial
1041 1061 952 972 926 946 933 953 921 941 909 929 1004 1024 955 975 934 954 918 938
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
1091 1113 999 1021 971 993 978 1000 965 987 954 976 1053 1075 1001 1023 980 1002 962 984 2036 2102 1786 1852 1720 1786 1693 1759 1677 1743 1659 1725 2063 2129 1841 1907 1742 1808 1679 1745 2136 2206 1874 1944 1805 1875 1776 1846 1759 1829 1741 1811 2165 2235 1932 2002 1828 1898 1762 1832 2340 2416 2053 2129 1977 2053 1946 2022 1927 2003 1906 1982 2371 2447 2116 2192 2002 2078 1929 2005 2448 2538 2153 2243 2075 2165 2043 2133 2025 2115 2003 2093 2480 2570 2218 2308 2101 2191 2027 2117 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
LVCMOS
5-58 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 3 of 8) Minimum Timing I/O Standard Drive Parameter Strength
2 mA tO P tD I P 4 mA tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA (1) 1.5 V 2 mA tO P tD I P tO P tD I P 4 mA tO P tD I P 6 mA tO P tD I P 8 mA (1) tO P tD I P SSTL-2 Class I 8 mA tO P tD I P 12 mA (1) SSTL-2 Class II 16 mA tO P tD I P tO P tD I P 20 mA tO P tD I P 24 mA (1) tO P tD I P
Industrial
1042 1062 1047 1067 974 994 976 996 933 953 934 954 1023 1043 963 983 966 986 926 946 913 933 896 916 876 896 877 897 872 892
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
1093 1115 1098 1120 1022 1044 1024 1046 978 1000 979 1001 1073 1095 1009 1031 1012 1034 971 993 957 979 940 962 918 940 919 941 915 937 2904 2970 2248 2314 2024 2090 1947 2013 1882 1948 1833 1899 2505 2571 2023 2089 1923 1989 1878 1944 1715 1781 1672 1738 1609 1675 1598 1664 1596 1662 3048 3118 2359 2429 2124 2194 2043 2113 1975 2045 1923 1993 2629 2699 2123 2193 2018 2088 1970 2040 1799 1869 1754 1824 1688 1758 1676 1746 1674 1744 3338 3414 2584 2660 2326 2402 2238 2314 2163 2239 2107 2183 2879 2955 2325 2401 2210 2286 2158 2234 1971 2047 1921 1997 1849 1925 1836 1912 1834 1910 3472 3562 2698 2788 2434 2524 2343 2433 2266 2356 2209 2299 3002 3092 2433 2523 2315 2405 2262 2352 2041 2131 1991 2081 1918 2008 1905 1995 1903 1993 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
1.8 V
Altera Corporation May 2007
5-59 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 4 of 8) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA (1) SSTL-18 Class II 8 mA tO P tD I P tO P tD I P 16 mA tO P tD I P 18 mA tO P tD I P 20 mA (1) 1.8-V HSTL Class I 4 mA tO P tD I P tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA (1) tO P tD I P
Industrial
909 929 914 934 894 914 898 918 891 911 883 903 894 914 890 910 890 910 912 932 917 937 896 916 900 920 892 912
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
953 975 958 980 937 959 942 964 936 958 925 947 937 959 933 955 933 955 956 978 962 984 940 962 944 966 936 958 1690 1756 1656 1722 1640 1706 1638 1704 1626 1692 1597 1663 1578 1644 1585 1651 1583 1649 1608 1674 1595 1661 1586 1652 1591 1657 1585 1651 1773 1843 1737 1807 1721 1791 1718 1788 1706 1776 1675 1745 1655 1725 1663 1733 1661 1731 1687 1757 1673 1743 1664 1734 1669 1739 1663 1733 1942 2018 1903 1979 1885 1961 1882 1958 1869 1945 1835 1911 1813 1889 1821 1897 1819 1895 1848 1924 1833 1909 1823 1899 1828 1904 1821 1897 2012 2102 1973 2063 1954 2044 1952 2042 1938 2028 1904 1994 1882 1972 1890 1980 1888 1978 1943 2033 1928 2018 1917 2007 1923 2013 1916 2006 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
SSTL-18 Class I
5-60 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 5 of 8) Minimum Timing I/O Standard Drive Parameter Strength
16 mA tO P tD I P 18 mA tO P tD I P 20 mA (1) 1.5-V HSTL Class I 4 mA tO P tD I P tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA (1) 1.5-V HSTL Class II 16 mA tO P tD I P tO P tD I P 18 mA tO P tD I P 20 mA (1) 1.2-V HSTL tO P tD I P tO P tD I P PCI tO P tD I P PCI-X tO P tD I P
Industrial
877 897 879 899 879 899 912 932 917 937 899 919 900 920 893 913 881 901 884 904 886 906 958 978 1028 1048 1028 1048
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
919 941 921 943 921 943 956 978 961 983 943 965 943 965 937 959 924 946 927 949 929 951 1004 1026 1082 1104 1082 1104 1385 1451 1394 1460 1402 1468 1607 1673 1588 1654 1590 1656 1592 1658 1590 1656 1431 1497 1439 1505 1450 1516 1602 1668 1956 2022 1956 2022 1453 1523 1462 1532 1471 1541 1686 1756 1666 1736 1668 1738 1670 1740 1668 1738 1501 1571 1510 1580 1521 1591 1681 1751 2051 2121 2051 2121 1591 1667 1602 1678 1611 1687 1847 1923 1825 1901 1827 1903 1829 1905 1827 1903 1644 1720 1654 1730 1666 1742 2244 2320 2244 2320 1680 1770 1691 1781 1700 1790 1942 2032 1920 2010 1922 2012 1924 2014 1922 2012 1734 1824 1744 1834 1757 1847 2070 2160 2070 2160 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
1.8-V HSTL Class II
Altera Corporation May 2007
5-61 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 6 of 8) Minimum Timing I/O Standard Drive Parameter Strength
8 mA tO P tD I P 12 mA tO P tD I P Differential 16 mA SSTL-2 Class II 20 mA tO P tD I P tO P tD I P 24 mA tO P tD I P Differential SSTL-18 Class I 4 mA tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA tO P tD I P Differential SSTL-18 Class II 8 mA tO P tD I P 16 mA tO P tD I P 18 mA tO P tD I P 20 mA tO P tD I P
Industrial
913 933 896 916 876 896 877 897 872 892 909 929 914 934 894 914 898 918 891 911 883 903 894 914 890 910 890 910
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
957 979 940 962 918 940 919 941 915 937 953 975 958 980 937 959 942 964 936 958 925 947 937 959 933 955 933 955 1715 1781 1672 1738 1609 1675 1598 1664 1596 1662 1690 1756 1656 1722 1640 1706 1638 1704 1626 1692 1597 1663 1578 1644 1585 1651 1583 1649 1799 1869 1754 1824 1688 1758 1676 1746 1674 1744 1773 1843 1737 1807 1721 1791 1718 1788 1706 1776 1675 1745 1655 1725 1663 1733 1661 1731 1971 2047 1921 1997 1849 1925 1836 1912 1834 1910 1942 2018 1903 1979 1885 1961 1882 1958 1869 1945 1835 1911 1813 1889 1821 1897 1819 1895 2041 2131 1991 2081 1918 2008 1905 1995 1903 1993 2012 2102 1973 2063 1954 2044 1952 2042 1938 2028 1904 1994 1882 1972 1890 1980 1888 1978 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Differential SSTL-2 Class I
5-62 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 7 of 8) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA tO P tD I P 1.8-V Differential HSTL Class II 16 mA tO P tD I P 18 mA tO P tD I P 20 mA tO P tD I P 1.5-V Differential HSTL Class I 4 mA tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA tO P tD I P
Industrial
912 932 917 937 896 916 900 920 892 912 877 897 879 899 879 899 912 932 917 937 899 919 900 920 893 913
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
956 978 962 984 940 962 944 966 936 958 919 941 921 943 921 943 956 978 961 983 943 965 943 965 937 959 1608 1674 1595 1661 1586 1652 1591 1657 1585 1651 1385 1451 1394 1460 1402 1468 1607 1673 1588 1654 1590 1656 1592 1658 1590 1656 1687 1757 1673 1743 1664 1734 1669 1739 1663 1733 1453 1523 1462 1532 1471 1541 1686 1756 1666 1736 1668 1738 1670 1740 1668 1738 1848 1924 1833 1909 1823 1899 1828 1904 1821 1897 1591 1667 1602 1678 1611 1687 1847 1923 1825 1901 1827 1903 1829 1905 1827 1903 1943 2033 1928 2018 1917 2007 1923 2013 1916 2006 1680 1770 1691 1781 1700 1790 1942 2032 1920 2010 1922 2012 1924 2014 1922 2012 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
1.8-V Differential HSTL Class I
Altera Corporation May 2007
5-63 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-75. Stratix II I/O Output Delay for Column Pins (Part 8 of 8) Minimum Timing I/O Standard Drive Parameter Strength
16 mA tO P tD I P 18 mA tO P tD I P 20 mA tO P tD I P Notes to Table 5-75:
(1) (2) (3) (4) This is the default setting in the Quartus II software. These I/O standards are only supported on DQS pins. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Industrial
881 901 884 904 886 906
-3 -3 -4 -5 Speed Speed Speed Speed Unit Commercial Grade Grade Grade Grade (3) (4)
924 946 927 949 929 951 1431 1497 1439 1505 1450 1516 1501 1571 1510 1580 1521 1591 1644 1720 1654 1730 1666 1742 1734 1824 1744 1834 1757 1847 ps ps
1.5-V Differential HSTL Class II
Table 5-76. Stratix II I/O Output Delay for Row Pins (Part 1 of 3) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 8 mA tO P tD I P 12 mA (1) LVCMOS 4 mA tO P tD I P tO P tD I P 8 mA (1) tO P tD I P
Industrial
1267 1225 1144 1102 1091 1049 1144 1102 1044 1002
-3 -3 -4 -5 Speed Speed Speed Speed Commercial Grade Grade Grade Grade (2) (3)
1328 1285 1200 1157 1144 1101 1200 1157 1094 1051 2655 2600 2113 2058 2081 2026 2113 2058 1853 1798 2786 2729 2217 2160 2184 2127 2217 2160 1944 1887 3052 2989 2429 2366 2392 2329 2429 2366 2130 2067 3189 3116 2549 2476 2512 2439 2549 2476 2243 2170
Unit
LVTTL
ps ps ps ps ps ps ps ps ps ps
5-64 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-76. Stratix II I/O Output Delay for Row Pins (Part 2 of 3) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 8 mA tO P tD I P 12 mA (1) 1.8 V 2 mA tO P tD I P tO P tD I P 4 mA tO P tD I P 6 mA tO P tD I P 8 mA (1) tO P tD I P 1.5 V 2 mA tO P tD I P 4 mA tO P tD I P SSTL-2 Class I 8 mA tO P tD I P SSTL-2 Class II 16 mA (1) SSTL-18 Class I 4 mA tO P tD I P tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA (1) tO P tD I P
Industrial
1128 1086 1030 988 1012 970 1196 1154 1184 1142 1079 1037 1049 1007 1158 1116 1055 1013 1002 960 947 905 990 948 994 952 970 928 974 932
-3 -3 -4 -5 Speed Speed Speed Speed Commercial Grade Grade Grade Grade (2) (3)
1183 1140 1080 1037 1061 1018 1253 1210 1242 1199 1131 1088 1100 1057 1213 1170 1106 1063 1050 1007 992 949 1038 995 1042 999 1018 975 1021 978 2091 2036 1872 1817 1775 1720 2954 2899 2294 2239 2039 1984 1942 1887 2530 2475 2020 1965 1759 1704 1581 1526 1709 1654 1648 1593 1633 1578 1615 1560 2194 2137 1964 1907 1862 1805 3100 3043 2407 2350 2140 2083 2038 1981 2655 2598 2120 2063 1846 1789 1659 1602 1793 1736 1729 1672 1713 1656 1694 1637 2403 2340 2152 2089 2040 1977 3396 3333 2637 2574 2344 2281 2232 2169 2908 2845 2322 2259 2022 1959 1817 1754 1964 1901 1894 1831 1877 1814 1856 1793 2523 2450 2265 2192 2151 2078 3542 3469 2763 2690 2462 2389 2348 2275 3041 2968 2440 2367 2104 2031 1897 1824 2046 1973 1975 1902 1958 1885 1937 1864
Unit
2.5 V
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Altera Corporation May 2007
5-65 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-76. Stratix II I/O Output Delay for Row Pins (Part 3 of 3) Minimum Timing I/O Standard Drive Parameter Strength
4 mA tO P tD I P 6 mA tO P tD I P 8 mA tO P tD I P 10 mA tO P tD I P 12 mA (1) 1.5-V HSTL Class I 4 mA tO P tD I P tO P tD I P 6 mA tO P tD I P 8 mA (1) tO P tD I P LVDS tO P tD I P HyperTransport tO P tD I P Notes to Table 5-76:
(1) (2) (3) This is the default setting in the Quartus II software. These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Industrial
972 930 975 933 958 916 962 920 953 911 970 928 974 932 960 918 1018 976 1005 963
-3 -3 -4 -5 Speed Speed Speed Speed Commercial Grade Grade Grade Grade (2) (3)
1019 976 1022 979 1004 961 1008 965 999 956 1018 975 1021 978 1006 963 1067 1024 1053 1010 1610 1555 1580 1525 1576 1521 1567 1512 1566 1511 1591 1536 1579 1524 1572 1517 1723 1668 1723 1668 1689 1632 1658 1601 1653 1596 1644 1587 1643 1586 1669 1612 1657 1600 1649 1592 1808 1751 1808 1751 1850 1787 1816 1753 1811 1748 1801 1738 1800 1737 1828 1765 1815 1752 1807 1744 1980 1917 1980 1917 1956 1883 1920 1847 1916 1843 1905 1832 1904 1831 1933 1860 1919 1846 1911 1838 2089 2016 2089 2016
Unit
1.8-V HSTL Class I
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Maximum Input & Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency achievable for a clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated clock I/O pin.
5-66 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
The maximum clock toggle rate is different from the maximum data bit rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same I/O pin. Table 5-77 specifies the maximum input clock toggle rates. Table 5-78 specifies the maximum output clock toggle rates at 0pF load. Table 5-79 specifies the derating factors for the output clock toggle rate for a non 0pF load. To calculate the output toggle rate for a non 0pF load, use this formula: The toggle rate for a non 0pF load = 1000 / (1000/ toggle rate at 0pF load + derating factor * load value in pF /1000) For example, the output toggle rate at 0pF load for SSTL-18 Class II 20mA I/O standard is 550 MHz on a -3 device clock output pin. The derating factor is 94ps/pF. For a 10pF load the toggle rate is calculated as: 1000 / (1000/550 + 94 x 10 /1000) = 363 (MHz) Tables 5-77 through 5-79 show the I/O toggle rates for Stratix II devices.
Table 5-77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2) Column I/O Pins (MHz) Input I/O Standard -3
LVTTL 2.5-V LVTTL/CMOS 1.8-V LVTTL/CMOS 1.5-V LVTTL/CMOS LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 500 500 500 500 500 500 500 500 500 500 500 500
Row I/O Pins (MHz) -3
500 500 500 500 500 500 500 500 500 500 500 500
Dedicated Clock Inputs (MHz) -3
500 500 500 500 500 500 500 500 500 500 500 500
-4
500 500 500 500 500 500 500 500 500 500 500 500
-5
450 450 450 450 450 500 500 500 500 500 500 500
-4
500 500 500 500 500 500 500 500 500 500 500 500
-5
450 450 450 450 450 500 500 500 500 500 500 500
-4
500 500 500 500 500 500 500 500 500 500 500 500
-5
400 400 400 400 400 500 500 500 500 500 500 500
Altera Corporation May 2007
5-67 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2) Column I/O Pins (MHz) Input I/O Standard -3
1.8-V HSTL Class II PCI (1) PCI-X (1) 1.2-V HSTL (2) Differential SSTL-2 Class I (1), (3) Differential SSTL-2 Class II (1), (3) Differential SSTL-18 Class I (1), (3) Differential SSTL-18 Class II (1), (3) 1.8-V Differential HSTL Class I (1), (3) 1.8-V Differential HSTL Class II (1), (3) 1.5-V Differential HSTL Class I (1), (3) 1.5-V Differential HSTL Class II (1), (3) HyperTransport technology (4) LVPECL (1) LVDS (5) LVDS (6) Notes to Table 5-77:
(1) (2) (3) (4) (5) (6) Row clock inputs don't support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards. 1.2-V HSTL is only supported on column I/O pins. Differential HSTL and SSTL standards are only supported on column clock and DQS inputs. HyperTransport technology is only supported on row I/O and row dedicated clock input pins. These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks. These numbers apply to dedicated clock pins in the top and bottom I/O banks.
Row I/O Pins (MHz) -3
500 520 520 -
Dedicated Clock Inputs (MHz) -3
500 500 500 280 500 500 500 500 500 500 500 500 717 450 717 450
-4
500 500 500 500 500 500 500 500 500 500 500 -
-5
500 450 450 500 500 500 500 500 500 500 500 -
-4
500 520 520 -
-5
500 420 420 -
-4
500 500 500 500 500 500 500 500 500 500 500 717 450 717 450
-5
500 400 400 500 500 500 500 500 500 500 500 640 400 640 400
500 500 500 280 500 500 500 500 500 500 500 500 -
5-68 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-78. Maximum Output Toggle Rate on Stratix II Devices (Part 1 of 5) I/O Standard
3.3-V LVTTL
Note (1) Clock Outputs (MHz) -3
270 435 580 720 875 1,030 290 565 790 1,020 1,066
Drive Strength
4 mA 8 mA 12 mA 16 mA 20 mA 24 mA
Column I/O Pins (MHz) -3
270 435 580 720 875 1,030 290 565 790 1,020 1,066 1,100 230 430 630 930 120 285 450 660 905 1,131 244 470 550 625 400 400 350 400 400
Row I/O Pins (MHz) -3
270 435 580 290 565 230 430 630 120 285 450 660 244 470 400 350 -
-4
225 355 475 594 700 794 250 480 710 925 985 1,040 194 380 575 845 109 250 390 570 805 1,040 200 370 430 495 300 400 350 350 400
-5
210 325 420 520 610 670 230 440 670 875 935 1,000 180 380 550 820 104 230 360 520 755 990 180 325 375 420 300 350 300 350 350
-4
225 355 475 250 480 194 380 575 109 250 390 570 200 370 350 350 -
-5
210 325 420 230 440 180 380 550 104 230 360 520 180 325 350 300 -
-4
225 355 475 594 700 794 250 480 710 925 985
-5
210 325 420 520 610 670 230 440 670 875 935 1,000 180 380 550 820 104 230 360 520 755 990 180 325 375 420 300 350 300 350 350
3.3-V LVCMOS
4 mA 8 mA 12 mA 16 mA 20 mA 24 mA
1,100 1,040 230 430 630 930 120 285 450 660 905 194 380 575 845 109 250 390 570 805
2.5-V LVTTL/LVCMOS
4 mA 8 mA 12 mA 16 mA
1.8-V LVTTL/LVCMOS
2 mA 4 mA 6 mA 8 mA 10 mA 12 mA
1,131 1,040 244 470 550 625 400 400 350 400 400 200 370 430 495 300 400 350 350 400
1.5-V LVTTL/LVCMOS
2 mA 4 mA 6 mA 8 mA
SSTL-2 Class I
8 mA 12 mA
SSTL-2 Class II
16 mA 20 mA 24 mA
Altera Corporation May 2007
5-69 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-78. Maximum Output Toggle Rate on Stratix II Devices (Part 2 of 5) I/O Standard
SSTL-18 Class I
Note (1) Clock Outputs (MHz) -3
200 350 450 500 650 200 400 450 550 300 500 650 700 700 500 550 550 350 500 700 700 700 600 650 700 400 400 350 400 400
Drive Strength
4 mA 6 mA 8 mA 10 mA 12 mA
Column I/O Pins (MHz) -3
200 350 450 500 700 200 400 450 550 300 500 650 700 700 500 550 650 350 500 700 700 700 600 650 700 400 400 350 400 400
Row I/O Pins (MHz) -3
200 350 450 500 300 500 650 700 700 350 500 700 400 400 350 350 -
-4
150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 300 400 350 350 400
-5
150 200 300 400 400 150 350 400 450 300 450 600 600 650 450 500 550 300 450 600 650 700 550 600 600 300 350 300 350 350
-4
150 250 300 400 300 450 600 650 700 300 500 650 300 400 350 350 -
-5
150 200 300 400 300 450 600 600 650 300 450 600 300 350 300 297 -
-4
150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 300 400 350 350 400
-5
150 200 300 400 400 150 350 400 450 300 450 600 600 650 450 500 550 300 450 600 650 700 550 600 600 300 350 300 350 350
SSTL-18 Class II
8 mA 16 mA 18 mA 20 mA
1.8-V HSTL Class I
4 mA 6 mA 8 mA 10 mA 12 mA
1.8-V HSTL Class II
16 mA 18 mA 20 mA
1.5-V HSTL Class I
4 mA 6 mA 8 mA 10 mA 12 mA
1.5-V HSTL Class II
16 mA 18 mA 20 mA
Differential SSTL-2 Class I (3) Differential SSTL-2 Class II (3)
8 mA 12 mA 16 mA 20 mA 24 mA
5-70 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-78. Maximum Output Toggle Rate on Stratix II Devices (Part 3 of 5) I/O Standard
Differential SSTL-18 Class I (3)
Note (1) Clock Outputs (MHz) -3
200 350 450 500 650 200 400 450 550 300 500 650 700 700 500 550 550 350 500 700 700 700 600 650 700 1,000 1,000 450 450 400 350
Drive Strength
4 mA 6 mA 8 mA 10 mA 12 mA
Column I/O Pins (MHz) -3
200 350 450 500 700 200 400 450 550 300 500 650 700 700 500 550 650 350 500 700 700 700 600 650 700 1,000 1,000 -
Row I/O Pins (MHz) -3
200 350 450 500 350 500 500
-4
150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 790 790 -
-5
150 200 300 400 400 150 350 400 450 300 450 600 600 650 450 500 550 300 450 600 650 700 550 600 600 670 670 -
-4
150 250 300 400 350 500 500 400 350
-5
150 200 300 400 297 500 500 350 300
-4
150 250 300 400 550 200 350 400 500 300 450 600 650 700 500 500 550 300 500 650 700 700 600 600 650 790 790 400 400 400 350
-5
150 200 300 400 400 150 350 400 450 300 450 600 600 650 450 500 550 300 450 600 650 700 550 600 600 670 670 300 300 350 300
Differential SSTL-18 Class II (3)
8 mA 16 mA 18 mA 20 mA
1.8-V Differential HSTL Class I (3)
4 mA 6 mA 8 mA 10 mA 12 mA
1.8-V Differential HSTL Class II (3)
16 mA 18 mA 20 mA
1.5-V Differential HSTL Class I (3)
4 mA 6 mA 8 mA 10 mA 12 mA
1.5-V Differential HSTL Class II (3)
16 mA 18 mA 20 mA
3.3-V PCI 3.3-V PCI-X LVDS (6) HyperTransport technology (4), (6) LVPECL (5) 3.3-V LVTTL 2.5-V LVTTL OCT 50 OCT 50
400 350
400 350
350 300
400 350
Altera Corporation May 2007
5-71 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-78. Maximum Output Toggle Rate on Stratix II Devices (Part 4 of 5) I/O Standard
1.8-V LVTTL 3.3-V LVCMOS 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V HSTL (2) 1.5-V HSTL Class I 1.8-V HSTL Class I 1.8-V HSTL Class II Differential SSTL-2 Class I Differential SSTL-2 Class II Differential SSTL-18 Class I Differential SSTL-18 Class II 1.8-V Differential HSTL Class I 1.8-V Differential HSTL Class II 1.5-V Differential HSTL Class I
Note (1) Clock Outputs (MHz) -3
700 350 550 600 600 450 550 280 600 650 500 600 600 560 550 650 500 600
Drive Strength
OCT 50 OCT 50 OCT 50 OCT 50 OCT 25 OCT 50 OCT 25 OCT 50 OCT 50 OCT 50 OCT 25 OCT 50 OCT 25 OCT 50 OCT 25 OCT 50 OCT 25 OCT 50
Column I/O Pins (MHz) -3
700 350 550 600 600 560 550 280 600 650 500 600 600 560 550 650 500 600
Row I/O Pins (MHz) -3
700 350 550 600 600 590 600 650 600 600 590 650 600
-4
550 350 450 500 550 400 500 550 600 500 500 550 400 500 600 500 550
-5
450 300 400 500 500 350 450 500 600 450 500 500 350 450 600 450 500
-4
550 350 450 500 550 400 550 600 500 550 400 600 550
-5
450 300 400 500 500 350 500 600 500 500 350 600 500
-4
550 350 450 500 550 400 500 550 600 500 500 550 400 500 600 500 550
-5
450 300 400 500 500 350 450 500 600 450 500 500 350 450 600 450 500
5-72 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-78. Maximum Output Toggle Rate on Stratix II Devices (Part 5 of 5) I/O Standard
1.2-V Differential HSTL Notes to Table 5-78:
(1)
Note (1) Clock Outputs (MHz) -3
280
Drive Strength
OCT 50
Column I/O Pins (MHz) -3
280
Row I/O Pins (MHz) -3
-
-4
-
-5
-
-4
-
-5
-
-4
-
-5
-
(2) (3) (4) (5) (6)
The toggle rate applies to 0-pF output load for all I/O standards except for LVDS and HyperTransport technology on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from 0 to 5pF. 1.2-V HSTL is only supported on column I/O pins in I/O banks 4, 7, and 8. Differential HSTL and SSTL is only supported on column clock and DQS outputs. HyperTransport technology is only supported on row I/O and row dedicated clock input pins. LVPECL is only supported on column clock pins. Refer to Tables 5-81 through 5-91 if using SERDES block. Use the toggle rate values from the clock output column for PLL output.
Table 5-79. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5) Maximum Output Clock Toggle Rate Derating Factors (ps/pF) I/O Standard Drive Strength
4 mA 8 mA 12 mA 16 mA 20 mA 24 mA 3.3-V LVCMOS 4 mA 8 mA 12 mA 16 mA 20 mA 24 mA 2.5-V LVTTL/LVCMOS 4 mA 8 mA 12 mA 16 mA
Column I/O Pins -3 -4
510 333 247 197 187 177 391 212 145 111 88 72 427 224 203 182
Row I/O Pins -3
478 260 213 377 206 387 163 142 -
Dedicated Clock Outputs -5
510 333 247 391 212 427 224 203 -
-5
510 333 247 197 187 177 391 212 145 111 88 72 427 224 203 182
-4
510 333 247 391 212 427 224 203 -
-3
466 291 211 166 154 143 377 178 115 86 79 74 391 170 152 134
-4
510 333 247 197 187 177 391 212 145 111 88 72 427 224 203 182
-5
510 333 247 197 187 177 391 212 145 111 88 72 427 224 203 182
3.3-V LVTTL
478 260 213 136 138 134 377 206 141 108 83 65 387 163 142 120
Altera Corporation May 2007
5-73 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-79. Maximum Output Clock Toggle Rate Derating Factors (Part 2 of 5) Maximum Output Clock Toggle Rate Derating Factors (ps/pF) I/O Standard Drive Strength
2 mA 4 mA 6 mA 8 mA 10 mA 12 mA 1.5-V LVTTL/LVCMOS 2 mA 4 mA 6 mA 8 mA SSTL-2 Class I 8 mA 12 mA SSTL-2 Class II 16 mA 20 mA 24 mA SSTL-18 Class I 4 mA 6 mA 8 mA 10 mA 12 mA SSTL-18 Class II 8 mA 16 mA 18 mA 20 mA SSTL-2 Class I 8 mA 12 mA SSTL-2 Class II 16 mA 20 mA 24 mA
Column I/O Pins -3 -4
1421 516 325 274 236 209 963 347 247 194 680 207 147 122 116 570 380 282 220 175 206 160 130 127 680 207 147 122 116
Row I/O Pins -3
951 405 261 223 652 333 364 163 118 458 305 225 167 364 163 118 -
Dedicated Clock Outputs -5 -3
904 393 253 224 199 180 618 270 198 155 350 188 94 87 85 505 336 248 190 148 155 140 110 94 350 188 94 87 85
-5
1421 516 325 274 236 209 963 347 247 194 680 207 147 122 116 570 380 282 220 175 206 160 130 127 680 207 147 122 116
-4
1421 516 325 274 963 347 680 207 147 570 380 282 220 680 207 147 -
-4
1421 516 325 274 236 209 963 347 247 194 680 207 147 122 116 570 380 282 220 175 206 160 130 127 680 207 147 122 116
-5
1421 516 325 274 236 209 963 347 247 194 680 207 147 122 116 570 380 282 220 175 206 160 130 127 680 207 147 122 116
1.8-V LVTTL/LVCMOS
951 405 261 223 194 174 652 333 182 135 364 163 118 99 91 458 305 225 167 129 173 150 120 109 364 163 118 99 91
1421 516 325 274 963 347 680 207 147 570 380 282 220 680 207 147 -
5-74 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-79. Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 5) Maximum Output Clock Toggle Rate Derating Factors (ps/pF) I/O Standard Drive Strength
4 mA 6 mA 8 mA 10 mA 12 mA SSTL-18 Class II 8 mA 16 mA 18 mA 20 mA 1.8-V HSTL Class I 4 mA 6 mA 8 mA 10 mA 12 mA 1.8-V HSTL Class II 16 mA 18 mA 20 mA 1.5-V HSTL Class I 4 mA 6 mA 8 mA 10 mA 12 mA 1.5-V HSTL Class II 16 mA 18 mA 20 mA Differential SSTL-2 Class II (3) 8 mA 12 mA 16 mA 20 mA 24 mA
Column I/O Pins -3 -4
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 680 207 147 122 116
Row I/O Pins -3
458 305 225 167 245 164 123 110 97 168 112 84 -
Dedicated Clock Outputs -5
570 380 282 220 282 188 140 124 110 196 131 99 -
-5
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 680 207 147 122 116
-4
570 380 282 220 282 188 140 124 110 196 131 99 -
-3
505 336 248 190 148 155 140 110 94 229 153 114 108 104 99 93 88 188 125 95 90 87 96 101 104 350 188 94 87 85
-4
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 680 207 147 122 116
-5
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 680 207 147 122 116
SSTL-18 Class I
458 305 225 167 129 173 150 120 109 245 164 123 110 97 101 98 93 168 112 84 87 86 95 95 94 364 163 118 99 91
Altera Corporation May 2007
5-75 Stratix II Device Handbook, Volume 1
Timing Model
Table 5-79. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5) Maximum Output Clock Toggle Rate Derating Factors (ps/pF) I/O Standard Drive Strength
4 mA 6 mA 8 mA 10 mA 12 mA Differential SSTL-18 Class II (3) 8 mA 16 mA 18 mA 20 mA 1.8-V Differential HSTL Class I (3) 4 mA 6 mA 8 mA 10 mA 12 mA 1.8-V Differential HSTL Class II (3) 16 mA 18 mA 20 mA 1.5-V Differential HSTL Class I (3) 4 mA 6 mA 8 mA 10 mA 12 mA 1.5-V Differential HSTL Class II (3) 16 mA 18 mA 20 mA 3.3-V PCI 3.3-V PCI-X LVDS HyperTransport technology LVPECL (4)
Column I/O Pins -3 -4
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 177 177 -
Row I/O Pins -3
155 (1) 155 (1) -
Dedicated Clock Outputs -5
155 (1) 155 (1) -
-5
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 177 177 -
-4
155 (1) 155 (1) -
-3
505 336 248 190 148 155 140 110 94 229 153 114 108 104 99 93 88 188 125 95 90 87 96 101 104 143 143 134 134
-4
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 177 177 134 134
-5
570 380 282 220 175 206 160 130 127 282 188 140 124 110 104 102 99 196 131 99 98 98 101 100 101 177 177 134 134
Differential SSTL-18 Class I (3)
458 305 225 167 129 173 150 120 109 245 164 123 110 97 101 98 93 168 112 84 87 86 95 95 94 134 134 -
5-76 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-79. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5) Maximum Output Clock Toggle Rate Derating Factors (ps/pF) I/O Standard Drive Strength
OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 OCT 50 OCT 25 OCT 50 OCT 25 OCT 50
Column I/O Pins -3 -4
152 274 165 316 171 134 101 123 110 -
Row I/O Pins -3
133 207 151 300 157 121 56 100 -
Dedicated Clock Outputs -5
152 274 165 316 171 134 101 123 -
-5
152 274 165 316 171 134 101 123 110 -
-4
152 274 165 316 171 134 101 123 -
-3
147 235 153 263 174 77 58 106 59 -
-4
152 274 165 316 171 134 101 123 110 -
-5
152 274 165 316 171 134 101 123 110 95
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 3.3-V LVCMOS 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.2-V HSTL (2) Notes to Table 5-79:
(1)
133 207 151 300 157 121 56 100 61 95
(2) (3) (4)
For LVDS and HyperTransport technology output on row I/O pins, the toggle rate derating factors apply to loads larger than 5 pF. In the derating calculation, subtract 5 pF from the intended load value in pF for the correct result. For a load less than or equal to 5 pF, refer to Table 5-78 for output toggle rates. 1.2-V HSTL is only supported on column I/O pins in I/O banks 4,7, and 8. Differential HSTL and SSTL is only supported on column clock and DQS outputs. LVPECL is only supported on column clock outputs.
Duty Cycle Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a clock is off from its ideal position. The ideal position is when both the clock high time (CLKH) and the clock low time (CLKL) equal half of the clock period (T), as shown in Figure 5-7. DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as D1 for the falling edge A and D2 for the falling edge B (Figure 5-7). The maximum DCD for a clock is the larger value of D1 and D2.
Altera Corporation May 2007
5-77 Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Figure 5-7. Duty Cycle Distortion
Ideal Falling Edge CLKH = T/2 D1 D2 CLKL = T/2
Falling Edge A
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in Figure 5-7, is clock-period independent. DCD can also be expressed as a percentage, and the percentage number is clock-period dependent. DCD as a percentage is defined as (T/2 - D1) / T (the low percentage boundary) (T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the corresponding I/O element (IOE) block. When the output is a single data rate signal (non-DDIO), only one edge of the register input clock (positive or negative) triggers output transitions (Figure 5-8). Therefore, any DCD present on the input clock signal or caused by the clock input buffer or different input I/O standard does not transfer to the output signal. Figure 5-8. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
IOE
NOT
inst1 clk INPUT VCC
DFF PRN
D Q
OUTPUT
output
CLRN inst
5-78 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
However, when the output is a double data rate input/output (DDIO) signal, both edges of the input clock signal (positive and negative) trigger output transitions (Figure 5-9). Therefore, any distortion on the input clock and the input clock buffer affect the output DCD. Figure 5-9. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
IOE VCC INPUT VCC DFF PRN
D Q
clk
CLRN inst2 OUTPUT output
DFF PRN GND
NOT D Q
inst8
CLRN inst3
When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block. As the PLL only monitors the positive edge of the reference clock input and internally re-creates the output clock signal, any DCD present on the reference clock is filtered out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than the DCD for a DDIO output without PLL in the clock path. Tables 5-80 through 5-87 give the maximum DCD in absolution derivation for different I/O standards on Stratix II devices. Examples are also provided that show how to calculate DCD as a percentage.
Table 5-80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 1 of 2) Note (1) Row I/O Output Standard
3.3-V LVTTTL 3.3-V LVCMOS 2.5 V
Maximum DCD for Non-DDIO Output -3 Devices
245 125 105
-4 & -5 Devices
275 155 135
Unit
ps ps ps
Altera Corporation May 2007
5-79 Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5-80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 2 of 2) Note (1) Row I/O Output Standard
1.8 V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I 1.8-V HSTL Class I 1.5-V HSTL Class I LVDS/ HyperTransport technology Note to Table 5-80:
(1) The DCD specification is based on a no logic array noise condition.
Maximum DCD for Non-DDIO Output -3 Devices
180 165 115 95 55 80 85 55
-4 & -5 Devices
180 195 145 125 85 100 115 80
Unit
ps ps ps ps ps ps ps ps
Here is an example for calculating the DCD as a percentage for a non-DDIO output on a row I/O on a -3 device: If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 95 ps (see Table 5-80). If the clock frequency is 267 MHz, the clock period T is: T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps To calculate the DCD as a percentage: (T/2 - DCD) / T = (3745ps/2 - 95ps) / 3745ps = 47.5% (for low boundary) (T/2 + DCD) / T = (3745ps/2 + 95ps) / 3745ps = 52.5% (for high boundary)
5-80 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II non-DDIO row output clock on a -3 device ranges from 47.5% to 52.5%.
Table 5-81. Maximum DCD for Non-DDIO Output on Column I/O Pins Note (1) Column I/O Output Standard I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5 V 1.8 V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.2-V HSTL (2) LVPECL Note to Table 5-81:
(1) (2) The DCD specification is based on a no logic array noise condition. 1.2-V HSTL is only supported in -3 devices.
Maximum DCD for Non-DDIO Output Unit -3 Devices
190 140 125 80 185 105 100 90 70 80 80 85 50 170 55
-4 & -5 Devices
220 175 155 110 215 135 130 115 100 110 110 115 80 80 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Altera Corporation May 2007
5-81 Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5-82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices Notes (1), (2) Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port (No PLL in Clock Path) Row DDIO Output I/O Standard TTL/CMOS 3.3 & 2.5 V
3.3-V LVTTL 3.3-V LVCMOS 2.5 V 1.8 V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I 1.8-V HSTL Class I 1.5-V HSTL Class I LVDS/ HyperTransport technology Notes to Table 5-82:
(1) (2) The information in Table 5-82 assumes the input clock has zero DCD. The DCD specification is based on a no logic array noise condition.
SSTL-2 2.5 V
145 100 85 85 140 65 60 55 60 55 180
SSTL/HSTL 1.8 & 1.5 V
145 100 85 85 140 65 60 50 60 55 180
LVDS/ HyperTransport Technology 3.3 V
110 65 75 120 105 70 75 90 95 90 180
Unit
1.8 & 1.5 V
380 330 315 265 370 295 290 275 270 270 180
260 210 195 150 255 175 170 155 150 150 180
ps ps ps ps ps ps ps ps ps ps ps
Here is an example for calculating the DCD in percentage for a DDIO output on a row I/O on a -3 device: If the input I/O standard is SSTL-2 and the DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 60 ps (see Table 5-82). If the clock frequency is 267 MHz, the clock period T is: T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps Calculate the DCD as a percentage: (T/2 - DCD) / T = (3745ps/2 - 60ps) / 3745ps = 48.4% (for low boundary) (T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high boundary)
5-82 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO row output clock on a -3 device ranges from 48.4% to 51.6%.
Table 5-83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5 Devices Notes (1), (2) Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port (No PLL in the Clock Path) Row DDIO Output I/O Standard TTL/CMOS 3.3/2.5 V
3.3-V LVTTL 3.3-V LVCMOS 2.5 V 1.8 V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I 1.8-V HSTL Class I 1.5-V HSTL Class I LVDS/ HyperTransport technology Note to Table 5-83:
(1) (2) Table 5-83 assumes the input clock has zero DCD. The DCD specification is based on a no logic array noise condition.
SSTL-2 2.5 V
170 120 105 90 160 85 80 65 60 60 180
SSTL/HSTL 1.8/1.5 V
160 110 95 100 155 75 70 65 70 70 180
LVDS/ HyperTransport Technology 3.3 V
105 75 90 135 100 85 90 105 110 105 180
Unit
1.8/1.5 V
495 450 430 385 490 410 405 390 385 390 180
440 390 375 325 430 355 350 335 330 330 180
ps ps ps ps ps ps ps ps ps ps ps
Table 5-84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 1 of 2) Notes (1), (2) Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port (No PLL in the Clock Path) DDIO Column Output I/O Standard TTL/CMOS 3.3/2.5 V
3.3-V LVTTL 3.3-V LVCMOS 2.5 V 260 210 195
SSTL-2 2.5 V
145 100 85
SSTL/HSTL 1.8/1.5 V
145 100 85
1.2-V HSTL 1.2 V
145 100 85
Unit
1.8/1.5 V
380 330 315
ps ps ps
Altera Corporation May 2007
5-83 Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5-84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 2 of 2) Notes (1), (2) Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port (No PLL in the Clock Path) DDIO Column Output I/O Standard TTL/CMOS 3.3/2.5 V
1.8 V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.2-V HSTL LVPECL Note to Table 5-84:
(1) (2) Table 5-84 assumes the input clock has zero DCD. The DCD specification is based on a no logic array noise condition.
SSTL-2 2.5 V
85 140 65 60 55 70 60 60 55 85 155 180
SSTL/HSTL 1.8/1.5 V
85 140 65 60 50 70 60 60 55 85 155 180
1.2-V HSTL 1.2 V
85 140 65 60 50 70 60 60 55 85 155 180
Unit
1.8/1.5 V
265 370 295 290 275 260 270 270 270 240 360 180
150 255 175 170 155 140 150 150 150 125 240 180
ps ps ps ps ps ps ps ps ps ps ps ps
Table 5-85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5 Devices (Part 1 of 2) Notes (1), (2) Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port (No PLL in the Clock Path) TTL/CMOS 3.3/2.5 V
3.3-V LVTTL 3.3-V LVCMOS 2.5 V 1.8 V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II 440 390 375 325 430 355 350
DDIO Column Output I/O Standard
SSTL-2 2.5 V
170 120 105 90 160 85 80
SSTL/HSTL 1.8/1.5 V
160 110 95 100 155 75 70
Unit
1.8/1.5 V
495 450 430 385 490 410 405
ps ps ps ps ps ps ps
5-84 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5 Devices (Part 2 of 2) Notes (1), (2) Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port (No PLL in the Clock Path) TTL/CMOS 3.3/2.5 V
SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.2-V HSTL LVPECL Note to Table 5-85:
(1) (2) Table 5-85 assumes the input clock has zero DCD. The DCD specification is based on a no logic array noise condition.
DDIO Column Output I/O Standard
SSTL-2 2.5 V
65 70 60 60 60 90 155 180
SSTL/HSTL 1.8/1.5 V
65 80 70 70 70 100 165 180
Unit
1.8/1.5 V
390 375 385 385 390 360 470 180
335 320 330 330 330 330 420 180
ps ps ps ps ps ps ps ps
Table 5-86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the Clock Path (Part 1 of 2) Note (1) Row DDIO Output I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5V 1.8V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I 1.8-V HSTL Class I 1.5-V HSTL Class I
Maximum DCD (PLL Output Clock Feeding DDIO Clock Port) -3 Device
110 65 75 85 105 65 60 50 50 55
Unit
ps ps ps ps ps ps ps ps ps ps
-4 & -5 Device
105 75 90 100 100 75 70 65 70 70
Altera Corporation May 2007
5-85 Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5-86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the Clock Path (Part 2 of 2) Note (1) Row DDIO Output I/O Standard
LVDS/ HyperTransport technology Note to Table 5-86:
(1) The DCD specification is based on a no logic array noise condition.
Maximum DCD (PLL Output Clock Feeding DDIO Clock Port) -3 Device
180
Unit
ps
-4 & -5 Device
180
Table 5-87. Maximum DCD for DDIO Output on Column I/O with PLL in the Clock Path Note (1) Column DDIO Output I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5V 1.8V 1.5-V LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.2-V HSTL LVPECL Note to Table 5-87:
(1) (2) The DCD specification is based on a no logic array noise condition. 1.2-V HSTL is only supported in -3 devices.
Maximum DCD (PLL Output Clock Feeding DDIO Clock Port) -3 Device
145 100 85 85 140 65 60 50 70 60 60 55 85 155 180
Unit
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
-4 & -5 Device
160 110 95 100 155 75 70 65 80 70 70 70 100 180
5-86 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
High-Speed I/O Specifications
Table 5-88 provides high-speed timing specifications definitions.
Table 5-88. High-Speed Timing Specifications & Definitions High-Speed Timing Specifications
tC fH S C L K J W tR I S E tF A L L Timing unit interval (TUI)
Definitions
High-speed receiver/transmitter input and output clock period. High-speed receiver/transmitter input and output clock frequency. Deserialization factor (width of parallel data bus). PLL multiplication factor. Low-to-high transmission time. High-to-low transmission time. The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency x Multiplication Factor) = tC /w). Maximum/minimum LVDS data transfer rate (fH S D R = 1/TUI), non-DPA. Maximum/minimum LVDS data transfer rate (fH S D R D PA = 1/TUI), DPA. The timing difference between the fastest and slowest output edges, including tC O variation and clock skew. The clock is included in the TCCS measurement. The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window. Peak-to-peak input jitter on high-speed PLLs. Peak-to-peak output jitter on high-speed PLLs. Duty cycle on high-speed transmitter output clock. Lock time for high-speed transmitter and receiver PLLs.
fH S D R fH S D R D P A Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter Output jitter tDUTY tL O C K
Table 5-89 shows the high-speed I/O timing specifications for -3 speed grade Stratix II devices.
Table 5-89. High-Speed I/O Specifications for -3 Speed Grade (Part 1 of 2) Symbol
fH S C L K (clock frequency) fH S C L K = f H S D R / W
Notes (1), (2) -3 Speed Grade Unit
Conditions Min
W = 2 to 32 (LVDS, HyperTransport technology) (3) W = 1 (SERDES bypass, LVDS only) W = 1 (SERDES used, LVDS only) 16 16 150
Typ
Max
520 500 717 MHz MHz MHz
Altera Corporation May 2007
5-87 Stratix II Device Handbook, Volume 1
High-Speed I/O Specifications
Table 5-89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2) Symbol
fH S D R (data rate)
Notes (1), (2) -3 Speed Grade Unit
Conditions Min
J = 4 to 10 (LVDS, HyperTransport technology) J = 2 (LVDS, HyperTransport technology) J = 1 (LVDS only) 150 (4) (4) 150 330
Typ
Max
1,040 760 500 1,040 200 190 Mbps Mbps Mbps Mbps ps ps ps ps ps % UI UI Number of repetitions
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) TCCS SW Output jitter Output tR I S E Output tFA L L tDUTY DPA run length DPA jitter tolerance DPA lock time Data channel peak-to-peak jitter Standard SPI-4 Parallel Rapid I/O Training Pattern 0000000000 1111111111 00001111 10010000 Miscellaneous 10101010 01010101 Notes to Table 5-89:
(1) (2) (3) (4)
All differential standards All differential standards
All differential I/O standards All differential I/O standards 45 50
160 180 55 6,400 0.44 Transition Density 10% 25% 50% 100% 256 256 256 256 256
When J = 4 to 10, the SERDES block is used. When J = 1 or 2, the SERDES block is bypassed. The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 input clock frequency x W 1,040. The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
5-88 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-90 shows the high-speed I/O timing specifications for -4 speed grade Stratix II devices.
Table 5-90. High-Speed I/O Specifications for -4 Speed Grade Symbol
fH S C L K (clock frequency) fH S C L K = f H S D R / W
Notes (1), (2) -4 Speed Grade Unit Min Typ Max
520 500 717 1,040 760 500 1,040 200 190 MHz MHz MHz Mbps Mbps Mbps Mbps ps ps ps ps ps % UI UI Number of repetitions 256 256 256 256 256 16 16 150 150 (4) (4) 150 330
Conditions
W = 2 to 32 (LVDS, HyperTransport technology) (3) W = 1 (SERDES bypass, LVDS only) W = 1 (SERDES used, LVDS only)
fH S D R (data rate)
J = 4 to 10 (LVDS, HyperTransport technology) J = 2 (LVDS, HyperTransport technology) J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) TCCS SW Output jitter Output tR I S E Output tFA L L tDUTY DPA run length DPA jitter tolerance DPA lock time Data channel peak-to-peak jitter Standard SPI-4 Parallel Rapid I/O Training Pattern 0000000000 1111111111 00001111 10010000 Miscellaneous 10101010 01010101 Notes to Table 5-90:
(1) (2) (3) (4)
All differential standards All differential standards
All differential I/O standards All differential I/O standards 45 50
160 180 55 6,400 0.44 Transition Density 10% 25% 50% 100%
When J = 4 to 10, the SERDES block is used. When J = 1 or 2, the SERDES block is bypassed. The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 input clock frequency x W 1,040. The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
Altera Corporation May 2007
5-89 Stratix II Device Handbook, Volume 1
High-Speed I/O Specifications
Table 5-91 shows the high-speed I/O timing specifications for -5 speed grade Stratix II devices.
Table 5-91. High-Speed I/O Specifications for -5 Speed Grade Symbol
fH S C L K (clock frequency) fH S C L K = f H S D R / W
Notes (1), (2) -5 Speed Grade Unit Min Typ Max
420 500 640 840 700 500 840 200 190 MHz MHz MHz Mbps Mbps Mbps Mbps ps ps ps ps ps % UI UI Number of repetitions 256 256 256 256 256 16 16 150 150 (4) (4) 150 440
Conditions
W = 2 to 32 (LVDS, HyperTransport technology) (3) W = 1 (SERDES bypass, LVDS only) W = 1 (SERDES used, LVDS only)
fH S D R (data rate)
J = 4 to 10 (LVDS, HyperTransport technology) J = 2 (LVDS, HyperTransport technology) J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology) TCCS SW Output jitter Output tR I S E Output tFA L L tDUTY DPA run length DPA jitter tolerance DPA lock time Data channel peak-to-peak jitter Standard SPI-4 Parallel Rapid I/O Training Pattern 0000000000 1111111111 00001111 10010000 Miscellaneous 10101010 01010101 Notes to Table 5-91:
(1) (2) (3) (4)
All differential I/O standards All differential I/O standards
All differential I/O standards All differential I/O standards 45 50
290 290 55 6,400 0.44 Transition Density 10% 25% 50% 100%
When J = 4 to 10, the SERDES block is used. When J = 1 or 2, the SERDES block is bypassed. The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 input clock frequency x W 1,040. The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not have a minimum toggle rate.
5-90 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
PLL Timing Specifications
Tables 5-92 and 5-93 describe the Stratix II PLL specifications when operating in both the commercial junction temperature range (0 to 85 C) and the industrial junction temperature range (-40 to 100 C).
Table 5-92. Enhanced PLL Specifications (Part 1 of 2) Name
fI N fI N P F D fI N D U T Y fE I N D U T Y tI N J I T T E R
Description
Input clock frequency Input frequency to the PFD Input clock duty cycle External feedback input clock duty cycle Input or external feedback clock input jitter tolerance in terms of period jitter. Bandwidth 0.85 MHz Input or external feedback clock input jitter tolerance in terms of period jitter. Bandwidth > 0.85 MHz
Min
2 2 40 40
Typ
Max
500 420 60 60
Unit
MHz MHz % % ns (p-p)
0.5
1.0
ns (p-p)
tO U T J I T T E R tF C O M P fO U T
Dedicated clock output period jitter External feedback compensation time Output frequency for internal global or regional clock Duty cycle for external clock output (when set to 50%). Scanclk frequency Time required to reconfigure scan chains for enhanced PLLs PLL external clock output frequency 1.5 (2) 174/fS C A N C L K 1.5 (2) 45 50
250 ps for 100 MHz outclk ps or mUI (p-p) 25 mUI for < 100 MHz outclk 10 550.0 ns MHz
tO U T D U T Y
55
%
fS C A N C L K tC O N F I G P L L
100
MHz ns
fO U T _ E X T
550.0 (1)
MHz
Altera Corporation May 2007
5-91 Stratix II Device Handbook, Volume 1
PLL Timing Specifications
Table 5-92. Enhanced PLL Specifications (Part 2 of 2) Name
tL O C K
Description
Time required for the PLL to lock from the time it is enabled or the end of device configuration Time required for the PLL to lock dynamically after automatic clock switchover between two identical clock frequencies Frequency range where the clock switchover performs properly PLL closed-loop bandwidth PLL VCO operating range for -3 and -4 speed grade devices PLL VCO operating range for -5 speed grade devices
Min
Typ
0.03
Max
1
Unit
ms
tD L O C K
1
ms
fS W I T C H OV E R
4
500
MHz
fC L B W fV C O
0.13 300
1.20
16.90 1,040
MHz MHz
300
840
MHz
fS S % spread
Spread-spectrum modulation frequency Percent down spread for a given clock frequency Accuracy of PLL phase shift Minimum pulse width on areset signal. Minimum pulse width on the areset signal when using PLL reconfiguration. Reset the PLL after scandone goes high.
100 0.4 0.5
500 0.6
kHz %
tP L L _ P S E R R tA R E S E T tA R E S E T _ R E C O N F I G
15 10 500
ps ns ns
Notes to Table 5-92:
(1) (2) Limited by I/O fM A X . See Table 5-78 on page 5-69 for the maximum. Cannot exceed fO U T specification. If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
5-92 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-93. Fast PLL Specifications Name
fI N
Description
Input clock frequency (for -3 and -4 speed grade devices) Input clock frequency (for -5 speed grade devices)
Min
16.08 16.08 16.08 40
Typ
Max
717 640 500 60
Unit
MHz MHz MHz % ns (p-p) ns (p-p)
fI N P F D fI N D U T Y tI N J I T T E R
Input frequency to the PFD Input clock duty cycle Input clock jitter tolerance in terms of period jitter. Bandwidth 2 MHz Input clock jitter tolerance in terms of period jitter. Bandwidth > 2 MHz
0.5 1.0 300 300 150 150 4.6875 150 4.6875 1,040 840 520 420 550 1,040 (1) 100 75/fS C A N C L K 1.16 5.00 0.03 28.00 1.00
fV C O
Upper VCO frequency range for -3 and -4 speed grades Upper VCO frequency range for -5 speed grades Lower VCO frequency range for -3 and -4 speed grades Lower VCO frequency range for -5 speed grades
MHz MHz MHz MHz MHz MHz MHz MHz ns MHz ms
fO U T
PLL output frequency to GCLK or RCLK PLL output frequency to LVDS or DPA clock
fO U T _ I O fS C A N C L K tC O N F I G P L L fC L B W tL O C K
PLL clock output frequency to regular I/O pin Scanclk frequency Time required to reconfigure scan chains for fast PLLs PLL closed-loop bandwidth Time required for the PLL to lock from the time it is enabled or the end of the device configuration Accuracy of PLL phase shift Minimum pulse width on areset signal.
tP L L _ P S E R R tA R E S E T
15 10 500
ps ns ns
tA R E S E T _ R E C O N F I G Minimum pulse width on the areset signal when using PLL reconfiguration. Reset the PLL after scandone goes high. Notes to Table 5-93:
(1)
Limited by I/O fM A X . See Table 5-77 on page 5-67 for the maximum.
Altera Corporation May 2007
5-93 Stratix II Device Handbook, Volume 1
External Memory Interface Specifications
External Memory Interface Specifications
Tables 5-94 through 5-101 contain Stratix II device specifications for the dedicated circuitry used for interfacing with external memory devices.
Table 5-94. DLL Frequency Range Specifications Frequency Mode
0 1 2 3
Frequency Range
100 to 175 150 to 230 200 to 310 240 to 400 (-3 speed grade) 240 to 350 (-4 and -5 speed grades)
Resolution (Degrees)
30 22.5 30 36 36
Table 5-95 lists the maximum delay in the fast timing model for the Stratix II DQS delay buffer. Multiply the number of delay buffers that you are using in the DQS logic block to get the maximum delay achievable in your system. For example, if you implement a 90 phase shift at 200 MHz, you use three delay buffers in mode 2. The maximum achievable delay from the DQS block is then 3 x .416 ps = 1.248 ns.
Table 5-95. DQS Delay Buffer Maximum Delay in Fast Timing Model Frequency Mode
0 1, 2, 3
Maximum Delay Per Delay Buffer (Fast Timing Model)
0.833 0.416
Unit
ns ns
Table 5-96. DQS Period Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) Note (1) Number of DQS Delay Buffer Stages (2)
1 2 3 4 Notes to Table 5-96:
(1) (2) Peak-to-peak period jitter on the phase shifted DQS clock. Delay stages used for requested DQS phase shift are reported in your project's Compilation Report in the Quartus II software.
Commercial
80 110 130 160
Industrial
110 130 180 210
Unit
ps ps ps ps
5-94 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-97. DQS Phase Jitter Specifications for DLL-Delayed Clock (tDQS PHASE_JITTER) Note (1) Number of DQS Delay Buffer Stages (2)
1 2 3 4 Notes to Table 5-97:
(1) (2) Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused by DLL tracking). Delay stages used for requested DQS phase shift are reported in your project's Compilation Report in the Quartus II software.
DQS Phase Jitter
30 60 90 120
Unit
ps ps ps ps
Table 5-98. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) Number of DQS Delay Buffer Stages (2) -3 Speed Grade
1 2 3 4 Note to Table 5-98:
(1) (2)
(1) Unit
ps ps ps ps
-4 Speed Grade
30 60 90 120
-5 Speed Grade
35 70 105 140
25 50 75 100
This error specification is the absolute maximum and minimum error. For example, skew on three delay buffer stages in a C3 speed grade is 75 ps or 37.5 ps. Delay stages used for requested DQS phase shift are reported in your project's Compilation Report in the Quartus II software.
Table 5-99. DQS Bus Clock Skew Adder Specifications (tDQS_CLOCK_SKEW_ADDER) Mode
x4 DQ per DQS x9 DQ per DQS x18 DQ per DQS x36 DQ per DQS Note to Table 5-99:
(1) This skew specification is the absolute maximum and minimum skew. For example, skew on a x4 DQ group is 40 ps or 20 ps.
DQS Clock Skew Adder
40 70 75 95
Unit
ps ps ps ps
Altera Corporation May 2007
5-95 Stratix II Device Handbook, Volume 1
JTAG Timing Specifications
Table 5-100. DQS Phase Offset Delay Per Stage Speed Grade
-3 -4 -5 Notes to Table 5-100:
(1) (2) (3)
Notes (1), (2), (3) Max
14 14 15
Min
9 9 9
Unit
ps ps ps
The delay settings are linear. The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to +31 for frequency modes 1, 2, and 3. The typical value equals the average of the minimum and maximum values.
Table 5-101. DDIO Outputs Half-Period Jitter Name
tO U T H A L F J I T T E R
(1) (2)
Notes (1), (2) Max
200
Description
Half-period jitter (PLL driving DDIO outputs)
Unit
ps
Notes to Table 5-101:
The worst-case half period is equal to the ideal half period subtracted by the DCD and half-period jitter values. The half-period jitter was characterized using a PLL driving DDIO outputs.
JTAG Timing Specifications
Figure 5-10 shows the timing requirements for the JTAG signals.
Figure 5-10. Stratix II JTAG Waveforms
TMS
TDI t JCP t JCH TCK tJPZX TDO t JPCO t JPXZ t JCL t JPSU t JPH
5-96 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-102 shows the JTAG timing parameters and values for Stratix II devices.
Table 5-102. Stratix II JTAG Timing Parameters & Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ
(1)
Parameter
TCK clock period TCK clock high time TCK clock low time
JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance
Min
30 13 13 3 5
Max
Unit
ns ns ns ns ns
11 (1) 14 (1) 14 (1)
ns ns ns
Note to Table 5-102:
A 1 ns adder is required for each VC C I O voltage step down from 3.3 V. For example, tJPCO = 12 ns if VC C I O of the TDO I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
Document Revision History
Table 5-103 shows the revision history for this chapter.
Table 5-103. Document Revision History (Part 1 of 3) Date and Document Version
May 2007, v4.3

Changes Made
Updated RCONF in Table 5-4 Updated fIN (min) in Table 5-92 Updated fIN and fINPFD in Table 5-93
Summary of Changes
--
Moved the Document Revision History section to the end of the chapter. August, 2006, v4.2
-- --
Updated Table 5-73, Table 5-75, Table 5-77, Table 5-78, Table 5-79, Table 5-81, Table 5-85, and Table 5-87.
Altera Corporation May 2007
5-97 Stratix II Device Handbook, Volume 1
Document Revision History
Table 5-103. Document Revision History (Part 2 of 3) Date and Document Version
April 2006, v4.1

Changes Made
Updated Table 5-3. Updated Table 5-11. Updated Figures 5-8 and 5-9. Added parallel on-chip termination information to "On-Chip Termination Specifications" section. Updated Tables 5-28, 5-30,5-31, and 5-34. Updated Table 5-78, Tables 5-81 through 5-90, and Tables 5-92, 5-93, and 5-98. Updated "PLL Timing Specifications" section. Updated "External Memory Interface Specifications" section. Added Tables 5-95 and 5-101. Updated "JTAG Timing Specifications" section, including Figure 5-10 and Table 5-102.

Summary of Changes
Changed 0.2 MHz to 2 MHz in Table 5-93. Added new spec for half period jitter (Table 5-101). Added support for PLL clock switchover for industrial temperature range. Changed fI N P F D (min) spec from 4 MHz to 2 MHz in Table 5-92. Fixed typo in tO U T J I T T E R specification in Table 5-92. Updated VD I F AC & DC max specifications in Table 5-28. Updated minimum values for tJ C H , tJ C L , and tJ P S U in Table 5-102. Update maximum values for tJ P C O , tJ P Z X , and tJ P X Z in Table 5-102. --

December 2005, v4.0 July 2005, v3.1

Updated "External Memory Interface Specifications" section. Updated timing numbers throughout chapter. Updated HyperTransport technology information in Table 5-13. Updated "Timing Model" section. Updated "PLL Timing Specifications" section. Updated "External Memory Interface Specifications" section. Updated tables throughout chapter. Updated "Power Consumption" section. Added various tables. Replaced "Maximum Input & Output Clock Rate" section with "Maximum Input & Output Clock Toggle Rate" section. Added "Duty Cycle Distortion" section. Added "External Memory Interface Specifications" section.
--
May 2005, v3.0

--

March 2005, v2.2 January 2005, v2.1
Updated tables in "Internal Timing Parameters" section. Updated input rise and fall time.
-- --
5-98 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
DC & Switching Characteristics
Table 5-103. Document Revision History (Part 3 of 3) Date and Document Version
January 2005, v2.0

Changes Made
Updated the "Power Consumption" section. Added the "High-Speed I/O Specifications" and "On-Chip Termination Specifications" sections. Removed the ESD Protection Specifications section. Updated Tables 5-3 through 5-13, 5-16 through 5-18, 5-21, 5-35, 5-39, and 5-40. Updated tables in "Timing Model" section. Added Tables 5-30 and 5-31. Updated Table 5-3. Updated introduction text in the "PLL Timing Specifications" section. Re-organized chapter. Added typical values and CO U T F B to Table 5-32. Added undershoot specification to Note (4) for Tables 5-1 through 5-9. Added Note (1) to Tables 5-5 and 5-6. Added VI D and VI C M to Table 5-10. Added "I/O Timing Measurement Methodology" section. Added Table 5-72. Updated Tables 5-1 through 5-2 and Tables 5-24 through 5-29.
Summary of Changes
--
October 2004, v1.2 July 2004, v1.1

--

--
February 2004, v1.0
Added document to the Stratix II Device Handbook.
--
Altera Corporation May 2007
5-99 Stratix II Device Handbook, Volume 1
Document Revision History
5-100 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007
6. Reference & Ordering Information
SII51006-2.1
Software
Stratix(R) II devices are supported by the Altera(R) Quartus(R) II design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap(R) II logic analyzer, and device configuration. See the Quartus II Handbook for more information on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink(R) interface.
Device Pin-Outs Ordering Information
Device pin-outs for Stratix II devices are available on the Altera web site at (www.altera.com). Figure 6-1 describes the ordering codes for Stratix II devices. For more information on a specific package, refer to the Package Information for Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX Device Handbook.
Altera Corporation May 2007
6-1
Document Revision History
Figure 6-1. Stratix II Device Packaging Ordering Information
EP2S Family Signature EP2S: Stratix II 90 F 1508 C 7 ES Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample
Device Type 15 30 60 90 130 180 Speed Grade 3, 4, or 5, with 3 being the fastest
Operating Temperature C: Commercial temperature (tJ = 0 C to 85 C) I: Industrial temperature (tJ = -40 C to 100 C)
Package Type F: FineLine BGA H: Hybrid FineLine BGA
Pin Count Number of pins for a particular FineLine BGA package
Document Revision History
Table 6-1 shows the revision history for this chapter.
Table 6-1. Document Revision History Date and Document Version
May 2007, v2.1 January 2005, v2.0 October 2004, v1.1 February 2004, v1.0
Changes Made
Moved the Document Revision History section to the end of the chapter. Contact information was removed. Updated Figure 6-1. Added document to the Stratix II Device Handbook.
Summary of Changes
-- -- -- --
6-2 Stratix II Device Handbook, Volume 1
Altera Corporation May 2007

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