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STW81103
Multi-band RF frequency synthesizer with integrated VCOs
Features

Integer-N frequency synthesizer Dual differential integrated VCOs with automatic center frequency calibration: - 2500 - 3050 MHz (direct output) - 4350 - 5000 MHz (direct output) - 1250 - 1525 MHz (internal divider by 2) - 2175 - 2500 MHz (internal divider by 2) - 625 - 762.5 MHz (internal divider by 4) - 1087.5 - 1250 MHz (internal divider by 4) Excellent integrated phase noise Fast lock time: 150s Dual modulus programmable prescaler (16/17 or 19/20) 2 programmable counters to achieve a feedback division ratio from 256 to 65551 (prescaler 16/17) and from 361 to 77836 (prescaler 19/20). Programmable reference frequency divider (10 bits) Phase frequency comparator and charge pump Programmable charge pump current Digital lock detector Dual digital bus interface: SPI and I2C bus (fast mode) with 3 bit programmable address (1100A2A1A0)
Applications

2.5G and 3G Cellular infrastructure equipment CATV equipment Instrumentation and test equipment Other wireless communication systems
Description
The STMicroelectronics STW81103 is an integrated RF synthesizer with voltage controlled oscillators (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81103 is a low cost one chip alternative to discrete PLL and VCOs solutions. STW81103 includes an Integer-N frequency synthesizer and two fully integrated VCOs featuring low phase noise performance and a noise floor of -155dBc/Hz. The combination of wide frequency range VCOs (thanks to centerfrequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover the 625 MHz-762.5 MHz, the 1087.5 MHz-1525 MHz, the 2175 MHz-3050 MHz and the 4350 MHz-5000 MHz bands. The STW81103 is designed with STMicroelectronics advanced 0.35 m SiGe process.

3.3 V power supply Power down mode (hardware and software) Small size exposed pad VFQFPN28 package 5 mm x 5 mm x 1.0 mm Process: BICMOS 0.35 m SiGe
March 2008
Rev 3
1/53
www.st.com
1
Contents
STW81103
Contents
1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4 5
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.8.1 5.8.2 5.8.3 VCO selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VCO frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 VCO voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.9 5.10
Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.9.1 Output buffer control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External VCO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6
I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/53
STW81103 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7
Contents Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.2 6.3
Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.3.1 6.3.2 6.3.3 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4
VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 7.2 7.3 7.4 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Bit tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.3.1 Default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.4.1 VCO calibration auto-restart feature . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.1 8.2 8.3 8.4 Direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9 10 11 12
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3/53
List of tables
STW81103
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Current value vs. selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VCO A performances versus amplitude setting (Freq = 2.8 GHz) . . . . . . . . . . . . . . . . . . . 24 VCO B performances vs. amplitude setting (Freq = 4.7 GHz) . . . . . . . . . . . . . . . . . . . . . . 25 EXT_PD pin function setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Current byte address read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data and clock timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Start and stop timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Ack timing specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write-only registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Bits at 00h and ST1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Bits at 01h and ST2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4/53
STW81103
List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. VCO A (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. VCO B (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5. VCO A (direct output) closed loop phase noise at 2.775 GHz (FSTEP=200 kHz; FPFD=200 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. VCO B (direct output) closed loop phase noise at 4.675 GHz (FSTEP=200 kHz; FPFD=200 kHz; ICP=3 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz (FSTEP=200 kHz; FPFD=400 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz (FSTEP=200 kHz; FPFD=400 kHz; ICP=2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz (FSTEP=200 kHz; FPFD=800 kHz; ICP=1 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz (FSTEP=200 kHz; FPFD=800 kHz; ICP=1.5 mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 11. PFD frequency spurs (direct output; FPFD=200 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA) . . . . . . . . . . . . . . . 17 Figure 15. Reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. VCO divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 17. PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 18. Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 19. VCO sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 20. Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 21. START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 22. Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 23. Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 24. Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 25. Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 26. SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 27. SPI timing specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn) . . . . . . . . . 41 Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 42 Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn) . . . . . . . . . . . . . . . . 43 Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . 43 Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 44 Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn) . . . . . . . . . . . . . . . . 44 Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . . . . 45 Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn) . . . . . . . . . . . . . . . . 46 Figure 36. Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 37. Ping-pong architecture diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 38. Application diagram with external VCO (LO output from STW81103) . . . . . . . . . . . . . . . . 49 Figure 39. Application diagram with external VCO (LO output from VCO) . . . . . . . . . . . . . . . . . . . . . 49 Figure 40. VFQFPN28 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5/53
Block diagram and pin configuration
STW81103
1
1.1
Block diagram and pin configuration
Block diagram
Figure 1. Block diagram
6/53
STW81103
Block diagram and pin configuration
1.2
Pin configuration
Figure 2. Pin connection (top view)
ADD0/LOAD VDD_DBUS DBUS_SEL VDD_BUFVCO EXTVCO_INP EXTVCO_INN VDD_PLL REF_CLK TEST2 LOCK_DET VDD_ESD VDD_CP
SDA/DATA
SCL/CLK
VDD_VCOA
VDD_DIV2 VDD_OUTBUF
OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB
QFN 28
VCTRL
Table 1.
Pin No 1 2 3 4 5 6 7 8 9
Pin description
Name VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VDD_ESD VCTRL Description VCO A power supply Divider by 2 power supply Output buffer power supply LO buffer positive output LO buffer negative output Divider by 4 power supply VCO B power supply ESD positive rail power supply VCO control voltage Open collector Open collector Observation
TEST1
REXT
ICP
EXT_PD
ADD2
ADD1
7/53
Block diagram and pin configuration Table 1.
Pin No 10 11 12 13 ICP REXT VDD_CP TEST1
STW81103
Pin description (continued)
Name Description PLL charge pump output External resistance connection for PLL charge pump Power supply for charge pump Test input 1 For test purposes only; must be connected to GND CMOS output (IOUT=4mA) For test purposes only; must be connected to GND Observation
14
LOCK_DET
Lock detector
15 16 17 18
TEST2 REF_CLK VDD_PLL EXTVCO_INN
Test input 2 Reference clock input PLL digital power supply External VCO negative input
For test purposes only; must be connected to GND For test purposes only; must be connected to GND
19 20 21 22 23 24 25 26 27
EXTVCO_INP VDD_BUFVCO DBUS_SEL VDD_DBUS EXT_PD SDA/DATA SCL/CLK ADD0/LOAD ADD1
External VCO positive input VCO buffer power supply Digital Bus Interface select SPI and I2C bus power supply
CMOS input
Power down hardware `0' device ON; `1' device OFF I2CBUS/SPI data line I2CBUS/SPI clock line I2CBUS address select pin/ SPI load line I2CBUS address select pin
CMOS input CMOS Bidir Schmitt triggered (IOUT=4mA) CMOS input Schmitt triggered CMOS input CMOS input; must be connected to GND in SPI mode CMOS input; must be connected to GND in SPI mode
28
ADD2
I2CBUS address select pin
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STW81103
Electrical specifications
2
2.1
Table 2.
Symbol AVCC DVCC Tstg
Electrical specifications
Absolute maximum ratings
Absolute maximum ratings
Parameter Analog supply voltage Digital supply voltage Storage temperature Electrical static discharge - HBM(1) - CDM-JEDEC standard - MM Values 0 to 4.6 0 to 4.6 +150 4 1.5 0.2 Unit V V C
ESD
kV
1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 800 V.
2.2
Table 3.
Symbol AVCC DVCC IVDD1 IVDD2 Tamb Tj
Operating conditions
Operating conditions (1)
Parameter Analog supply voltage Digital supply voltage VDD1 current consumption VDD2 current consumption Operating ambient temperature Maximum junction temperature Junction to ambient package thermal resistance Junction to board package thermal resistance Junction to case package thermal resistance Multilayer JEDEC board 44 -40 Test conditions Min. 3.0 3.0 Typ. 3.3 3.3 90 12 85 125 Max. 3.6 3.6 Units V V mA mA C C
Rth j-a
C/W
Rth j-b
Multilayer JEDEC board
26.3
C/W
Rth j-c
Multilayer JEDEC board
6.3
C/W
1. Refer to Figure 36: Typical application diagram.
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Electrical specifications
STW81103
2.3
Table 4.
Symbol Vil Vih Vhyst Vol Voh
Digital logic levels
Digital logic levels
Parameter Low-level input voltage High-level input voltage Schmitt trigger hysteresis Low-level output voltage High-level output voltage 0.85*Vdd 0.8*Vdd 0.8 0.4 Test conditions Min. Typ. Max. 0.2*Vdd Units V V V V V
2.4
Table 5.
Symbol
Electrical specifications
All electrical specifications are intended for a 3.3 V supply voltage. Electrical specifications
Parameter Condition Min. Typ. Max. Unit
l
Output frequency range Direct output FOUTA Output frequency range with VCOA Divider by 2 Divider by 4 Direct output FOUTB Output frequency range with VCOB Divider by 2 Divider by 4 VCO dividers Prescaler 16/17 N VCO divider ratio Prescaler 19/20 Reference clock and phase frequency detector Fref Reference input frequency Reference input R FPFD sensitivity(1) 10 0.35 2 1 200 1.5 1023 16 Prescaler 16/17 FSTEP Frequency step(2) Prescaler 19/20 FOUT/ 65551 FOUT/ 77836 FOUT/ 256 FOUT/ 361 MHz Hz Hz MHz Vpeak 361 77836 256 65551 2500 1250 625 4350 2175 1087.5 3050 1525 762.5 5000 2500 1250 MHz MHz MHz MHz MHz MHz
Reference divider ratio PFD input frequency
10/53
STW81103 Table 5.
Symbol Charge pump ICP VOCP ICP sink/source(3) Output voltage compliance range Direct output (FPFD=200 kHz) Spurious
(4)
Electrical specifications Electrical specifications (continued)
Parameter Condition Min. Typ. Max. Unit
3-bit programmable 0.4 -76 -82 -88
5 Vdd-0.3
mA V dBc dBc dBc
Divider by 2 (FPFD=400 kHz) Divider by 4 (FPFD=800 kHz)
VCOs Lower frequency range KVCOA VCOA sensitivity(5) Intermediate frequency range Higher frequency range Lower frequency range KVCOB VCOB sensitivity(5) Intermediate frequency range Higher frequency range TLK Maximum temperature variation for continuous lock(5) (6) VCOA pushing(5) VCOB VCTRL pushing(5) 0.4 VCO A VCO B 45 60 85 45 60 85 125 95 4 15 7 21 3 -20 FVCO=2.8 GHz; amplitude[11] FVCO=2.8 GHz; amplitude[00] VCOB current consumption VCO buffer consumption Divider by 2 consumption Divider by 4 consumption FVCO=4.7 GHz; amplitude[11] FVCO=4.7 GHz; amplitude[00] 30 16 24 13 15 17 14 65 80 105 65 80 100 85 105 145 85 100 130 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V C C MHz/V MHz/V V dBc mA mA mA mA mA mA mA
VCO control voltage(5) LO harmonic spurious(5)
IVCOA
VCOA current consumption
IVCOB IVCOBUF IDIV2 IDIV4
LO output buffer PLO RL Output level Return loss Matched to 50 ohms DIV4 Buff IOUTBUF Current consumption DIV2 Buff Direct output 0 15 26 23 39 dBm dB mA mA mA
11/53
Electrical specifications Table 5.
Symbol External VCO Frequency range Input level Current consumption PLL miscellaneous IPLL tlock Current consumption Lockup time(5) (7) Input buffer, prescaler, digital dividers, misc. 25 kHz PLL bandwidth; within 1 ppm of frequency error 12 150 VCO internal buffer 0.625 -10 28 5.0 +6
STW81103
Electrical specifications (continued)
Parameter Condition Min. Typ. Max. Unit
GHz dBm mA
mA s
1. In order to achieve best phase noise performance 1 V peak level is suggested. 2. The frequency step is related to the PFD input frequency as follows: - Fstep = FPFD for direct output - Fstep = FPFD/2 for divided by 2 output - Fstep = FPFD/4 for divided by 4 output 3. See relationship between ICP and REXT in Section 5.7: Charge pump. 4. The level of the spurs may change depending on PFD frequency, charge pump current, selected channel and PLL loop BW. 5. Guaranteed by design and specification. 6. When setting a specified output frequency, the VCO calibration procedure must be run in order to select the best sub-range for the VCO covering the desired frequency. Once programmed at the initial temperature T0 inside the operating temperature range (-40 C to +85 C), the synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by TLK, provided that the final temperature T1 is still inside the nominal range. If higher T are required the "VCO calibration auto-restart" feature can be enabled, thus allowing to re-start the VCO calibration procedure automatically when the part loose the lock condition (trigger on lock detector signal). 7. Frequency jump from 2250 to 2400 MHz; it includes the time required by the VCO calibration procedure (7 FPFD cycles with FPFD=400 kHz).
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STW81103
Electrical specifications
2.5
Table 6.
Phase noise specification
Phase noise specification (1)
Parameter Test conditions Min. Typ. Max. Unit
In-band phase noise floor - closed loop(2) Normalized inband phase noise floor Inband phase noise floor direct output Inband phase noise floor divider by 2 Inband phase noise floor divider by 4 PLL integrated phase noise - direct output Integrated phase noise 100 Hz to 40 MHz FOUT=4.675 GHz, FPFD=200 kHz, FSTEP=200 kHz, PLL BW = 15 kHz, ICP=3 mA -34.6 1.5 dBc rms ICP=4 mA, PLL BW=50 kHz; including reference clock contribution -222 -222+20log(N)+10log(FPFD) -228+20log(N)+10log(FPFD) -234+20log(N)+10log(FPFD) dBc/Hz dBc/Hz dBc/Hz dBc/Hz
PLL integrated phase noise - divider by 2 Integrated phase noise 100 Hz to 40 MHz FOUT=2.3376 GHz, FPFD=400 kHz, FSTEP=200 kHz, PLL BW=25 kHz, ICP=2 mA -42.6 0.6 dBc rms
PLL integrated phase noise - divider by 4 Integrated phase noise 100 Hz to 40 MHz FOUT=1.1688 GHz, FPFD=800 kHz, FSTEP=200 kHz, PLL BW=35 kHz, ICP=1.5 mA -49.5 0.27 dBc rms
VCO A direct (2500 MHz-3050 MHz) - open loop(3) Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise @ 40 MHz VCO B direct (4350 MHz-5000 MHz) - open loop(3) Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise @ 40 MHz -54 -82 -105 -127 -147 -157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -59 -87 -109 -131 -151 -161 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
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Electrical specifications Table 6. Phase noise specification (1) (continued)
Parameter Test conditions Min. Typ.
STW81103
Max.
Unit
VCO A with divider by 2 (1250 MHz-1525 MHz) - open loop(3) Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz VCO B with divider by 2 (2175 MHz-2500 MHz) - open Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz VCO A with divider by 4 (625 MHz-762.5 MHz) - open Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz VCO B with divider by 4 (1087.5 MHz-1250 MHz) - open Phase noise @ 1 kHz Phase noise @ 10 kHz Phase noise @ 100 kHz Phase noise @ 1 MHz Phase noise @ 10 MHz Phase noise floor @ 40 MHz loop(3) -66 -94 -117 -138 -153 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz loop(3) -71 -99 -121 -142 -154 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz loop(3) -60 -88 -111 -132 -150 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -65 -93 -115 -137 -153 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
1. Phase Noise SSB. VCO amplitude setting to value [11]. All closed-loop performances are specified using a reference clock signal at 76.8 MHz with a phase noise of -135 dBc/Hz @1 kHz offset, -145dBc/Hz @10kHz offset and -149.5 dBc/Hz of noise floor. 2. Normalized PN = Measured PN - 20log(N) - 10log(FPFD), where N is the VCO divider ratio (N=B*P+A) and FPFD is the comparison frequency at the PFD input. 3. Typical phase noise at centre band frequency.
An evaluation kit is available upon request, including a powerful simulation tool (STWPLLSim) that allows a very accurate estimation of the device's phase noise according to the desired project parameters (VCO frequency, selected output stage, reference clock, frequency step, and so on); refer to Section 8: Application information for more details.
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STW81103
Typical performance characteristics
3
Typical performance characteristics
Phase noise is measured with the Agilent E5052A Signal Source Analyzer. All closed-loop measurements are done with FSTEP=200 kHz, with the FPFD and charge pump current properly set. The loop filter configuration is depicted in Figure 36: Typical application diagram, and the reference clock signal is at 76.8 MHz with a phase noise of -135 dBc/Hz @1 kHz offset, -145 dBc/Hz @10 kHz offset and -149.5 dBc/Hz of noise floor.
Figure 3.
VCO A (direct output) open loop phase noise
Figure 4.
VCO B (direct output) open loop phase noise
Figure 5.
VCO A (direct output) closed loop phase noise at 2.775 GHz (FSTEP=200 kHz; FPFD=200 kHz; ICP=2 mA)
Figure 6.
VCO B (direct output) closed loop phase noise at 4.675 GHz (FSTEP=200 kHz; FPFD=200 kHz; ICP=3 mA)
1.0 rms
1.5 rms
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Typical performance characteristics
STW81103
Figure 7.
VCO A (div. by 2 output) closed loop phase noise at 1.3876 GHz (FSTEP=200 kHz; FPFD=400 kHz; ICP=1.5 mA)
Figure 8.
VCO B (div. by 2 output) closed loop phase noise at 2.3376 GHz (FSTEP=200 kHz; FPFD=400 kHz; ICP=2 mA)
0.4 rms
0.6 rms
Figure 9.
VCO A (div. by 4 output) closed loop phase noise at 693.8 MHz (FSTEP=200 kHz; FPFD=800 kHz; ICP=1 mA)
Figure 10. VCO B (div. by 4 output) closed loop phase noise at 1168.8 MHz (FSTEP=200 kHz; FPFD=800 kHz; ICP=1.5 mA)
0.19 rms
0.27 rms
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STW81103
Typical performance characteristics
Figure 11. PFD frequency spurs (direct output; FPFD=200 kHz)
Figure 12. PFD frequency spurs (div. by 2 output; FPFD=400 kHz)
-76 dBc @200KHz
-84 dBc @400KHz
Figure 13. PFD frequency spurs (div. by 4 output; FPFD=800 kHz)
Figure 14. Settling time (final frequency=2.4 GHz; FPFD=400 kHz; ICP=2.5 mA)
< -90 dBc @800KHz
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General description
STW81103
4
General description
Figure 1: Block diagram shows the separate blocks that, when integrated, form an Integer-N PLL frequency synthesizer.
The STW81103 consists of two internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dualmodulus prescaler. The 5-bit A-counter and 12-bit B-counter, in conjunction with the dualmodulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P +A. The division ratio of both reference and VCO dividers is controlled through the selected digital interface (I2C bus or SPI). The digital interface type is selected through the proper hardware connection of pin DBUS_SEL (0 V for I2C bus, 3.3 V for SPI). All devices operate with a power supply of 3.3 V, and can be powered down when not in use.
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STW81103
Circuit description
5
5.1
Circuit description
Reference input stage
The reference input stage is shown in Figure 15. The resistor network feeds a DC bias at the Fref input, while the inverter used as the frequency reference buffer is AC coupled. Figure 15. Reference frequency input buffer
VDD
F
ref
INV
BUF
Power Down
5.2
Reference divider
The 10-bit programmable reference counter allows division of the input reference frequency to produce the input clock to the PFD. The division ratio is programmed through the digital interface.
5.3
Prescaler
The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus P is programmable and can be set to 16 or 19. The prescaler is based on a synchronous 4/5 core whose division ratio depends on the state of the modulus input.
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Circuit description
STW81103
5.4
A and B counters
The 5-bit A-counter and 12-bit B-counter, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler, allow the generation of output frequencies that are spaced only by the reference frequency divided by the reference division ratio. The division ratio and the VCO output frequency are given by the following formulas: N=BxP+A (B x P + A) F VCO = ----------------------------- x F ref R where FVCO: output frequency of VCO P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface) B: division ratio of the main counter A: division ratio of the swallow counter Fref: input reference frequency R: division ratio of the reference counter N: division ratio of the PLL For the VCO divider to work correctly, B absolutely must be greater than A, which can take any value ranging from 0 to 31. The value range of N is either from 256 to 65551 (if P=16) or from 361 to 77836 (P=19). Figure 16. VCO divider diagram
VCOBUFPrescaler 16/17 or 19/20 VCOBUF+ To PFD
modulus
5-bit A-counter
12-bit B-counter
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STW81103
Circuit description
5.5
Phase frequency detector (PFD)
The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function.
Figure 17 is a simplified schematic of the PFD.
Figure 17. PFD diagram
VDD D FF Up
F ref
R
Delay
R
F ref
VDD D FF Down ABL
5.6
Lock detect
This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). The Lock Detect signal is high when the PLL is locked and low when the PLL is unlocked. Lock Detect consumes current only during PLL transients.
5.7
Charge pump
This block drives two matched current sources, IUP and IDOWN, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (connected to the REXT input pin) and a 3-bit word that allows selection among 8 different values. The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V)
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Circuit description Table 7.
CPSEL2 0 0 0 0 1 1 1 1
STW81103 Current value vs. selection
CPSEL1 0 0 1 1 0 0 1 1 CPSEL0 0 1 0 1 0 1 0 1 Current IMIN 2*IMIN 3*IMIN 4*IMIN 5*IMIN 6*IMIN 7*IMIN 8*IMIN Value for REXT=4.7 K 0.5 mA 1.0 mA 1.5 mA 2.0 mA 2.5 mA 3.0 mA 3.5 mA 4.0 mA
Note:
The current is output on pin ICP. During VCO auto-calibration, the ICP and VCTRL pins are forced to VDD/2.
Figure 18. Loop filter connection
VDD
VCTRL
BUF
C3
R3
Charge Pump
ICP
R1 C2
C1
BUF Cal bit
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STW81103
Circuit description
5.8
5.8.1
Voltage controlled oscillators
VCO selection
The STW81103 integrates two low-noise VCOs to cover a wide band from:

2500 MHz to 3050 MHz and from 4350 MHz to 5000 MHz (direct output) 1250 MHz to 1525 MHz and from 2175 MHz to 2500 MHz (selecting divider by 2) 625 MHz to 762.5 MHz and from 1087.5 MHz to 1250 MHz (selecting divider by 4)
The frequency range is 2500 MHz-3050 MHz for VCO A, and 4350 MHz-5000 MHz for VCO B.
5.8.2
VCO frequency calibration
Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors from the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variation on the VCO center frequency. The range is automatically selected when the SERCAL bit is set to 1. The charge pump is inhibited, and the ICP and VCTRL pins are at VDD/2 volts. The ranges are then tested with this VCO input voltage to select the one nearest to the desired output frequency (FOUT = N*Fref/R). After this selection, the SERCAL bit is automatically reset to 0 and the charge pump is once again enabled. To enable a fast settle, the PLL needs only to perform fine adjustments around VDD/2 on the loop filter to reach FOUT.
Figure 19. VCO sub-bands frequency characteristics
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Circuit description
STW81103
The SERCAL bit should be set to "1" at each division ratio change. The VCO calibration procedure takes approximately 7 periods of the PFD frequency. The maximum allowed FPFD to perform the calibration process is 1 MHz. When using a higher FPFD, follow the steps below: 1. 2. Calibrate the VCO at the desired frequency with an FPFD less than 1 MHz. Set the ratio of the A, B and R dividers for the desired FPFD.
VCO calibration auto-restart feature
The VCO calibration auto-restart feature, once activated, allows to restart the calibration procedure when the lock detector reports that the PLL has moved to an unlock condition (trigger on `1' to `0' transition of lock detector signal). This situation could happen if the device experiences a significant temperature variation. Once programmed at the initial temperature T0 inside the operating temperature range (-40 C to +85 C), the synthesizer is able to maintain the lock status only if the temperature drift (in either direction) is within the limit specified by the TLK parameter, provided that the final temperature T1 is still inside the nominal range. Each VCO featured by STW81103 has its specific TLK parameter reported in Table 5, that is typically lower than the maximum allowable drift (TMAX=125; from -40 C to +85 C and vice versa). By enabling the VCO calibration auto-restart feature (through the CAL_AUTOSTART_EN bit), the part will be able to select again the proper VCO frequency sub-range if the temperature drift exceeds the TLK limit, without any external user command.
5.8.3
VCO voltage amplitude control
The voltage swing of the VCOs can be adjusted over four levels by means of two dedicated programming bits (PLL_A1 and PLL_A0). Higher amplitudes provide best phase noise, whereas lower amplitudes save power.
Table 8 gives the voltage swing level expected on the resonator nodes, the current consumption, and the phase noise at 1 MHz.
Table 8. VCO A performances versus amplitude setting (Freq = 2.8 GHz)
Differential voltage swing (Vp) 1.1 1.3 1.9 2.1 Current consumption (mA) 16 19 27 30 PN @1 MHz (dBc/Hz) -126 -127 -130 -131
PLL_A[1:0] 00 01 10 11
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STW81103 Table 9.
Circuit description VCO B performances vs. amplitude setting (Freq = 4.7 GHz)
Differential voltage swing (Vp) 1.1 1.3 1.9 2.1 Current consumption (mA) 13 15 22 24 PN at 1 MHz (dBc/Hz) -121 -122 -126 -127
PLL_A[1:0] 00 01 10 11
5.9
Output stage
The differential output signal of the synthesizer can be selected by software among three different signal paths (direct, divider by 2 and divider by 4) providing multi-band capability. The selection of the output stage is done by programming properly the PD[4:0] bits. The output stage is an open-collector structure which is able to meet different requirements over the desired output frequency range by proper connections on the PCB. Refer to Section 8: Application information for more details on PCB connections.
5.9.1
Output buffer control mode
This control mode allows to enable/disable the output stage by a hardware control pin (EXT_PD, pin#23) while the PLL stays locked at the desired frequency; in such a way a very fast switching time is achieved. This feature can be useful in designing a ping-pong architecture saving the cost of an external RF switch. The function of pin#23 (EXT_PD) is set with the OUTBUF_CTRL_EN bit as shown in Table 10. Table 10. EXT_PD pin function setting
Function of the EXT_PD pin Device hardware power down EXT_PD = 3.3 V EXT_PD = 0 V 1 Output Buffer control EXT_PD = 3.3 V Output Stage OFF Device OFF Output Stage ON EXT_PD pin settings EXT_PD = 0 V 0 Device ON
OUTBUF_CTRL_EN
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Circuit description
STW81103
5.10
External VCO buffer
Although the main benefits of the STW81103 are the two wideband and low-noise VCOs, the capability to use an external VCO is also provided. The external VCO buffer is able to manage a signal coming from an external VCO in order to build a synthesizer using the STW81103 only as PLL IC. The output signal of the synthesizer can also be taken from the output section of the STW81103 (direct, divided by 2 or divided by 4 by) by properly setting the PD[4:0] bits, thus providing additional flexibility. The external VCO signal can range from 625 MHz up to 5 GHz and its minimum power level must be -10 dBm.
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STW81103
I2C bus interface
6
I2C bus interface
The I2C bus interface is selected by hardware connection of pin #21 (DBUS_SEL) to 0 V. Data is transmitted from microprocessor to the STW81103 through the 2-wire (SDA and SCL) I2C bus interface. The STW81103 is always a slave device. The I2C bus protocol defines any device that sends data on the bus as a transmitter, and any device that reads the data as a receiver. The device controlling the data transfer is the master, and the others are slaves. The master always initiates the transfer and provides the serial clock for synchronization. The STW81103 I2C bus supports Fast Mode operation (clock frequency up to 1MHz).
6.1
6.1.1
General features
Data validity
Data changes on the SDA line must only occur when the SCL is low. SDA transitions while the clock is high are used to identify a START or STOP condition. Figure 20. Data validity
SDA
SCL Data line Stable data Valid Change data allowed
6.1.2
START and STOP conditions
START condition
A START condition is identified by a transition of the data bus SDA from high to low while the clock signal SCL is stable in the high state. A START condition must precede any data transfer command.
STOP condition
A STOP condition is identified by a transition of the data bus SDA from low to high while the clock signal SCL is stable in the high state. A STOP condition terminates communications between the STW81103 and the bus master.
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I2C bus interface Figure 21. START and STOP conditions
STW81103
SCL
SDA
START
STOP
6.1.3
Byte format and acknowledge
Every byte put on the SDA line must be 8 bits long, starting with the most significant bit (MSB), and be followed by an acknowledge bit to indicate a successful data transfer. The transmitter releases the SDA line after sending 8 bits of data. During the 9th clock pulse, the receiver pulls the SDA line low to acknowledge the receipt of 8 bits of data. Figure 22. Byte format and acknowledge
SCL
1
2
3
7
8
9
//
SDA START
MSB
//
Acknowledgement from receiver
6.1.4
Device addressing
The master must first initiate with a START condition to communicate with the STW81103, and then send 8 bits (MSB first) on the SDA line which correspond to the device select address and the read or write mode. The first seven MSBs are the device address identifier, which corresponds to the I2C bus definition. For the STW81103, the address is set at "1100A2A1A0", 3 bits programmable. The 8th bit (LSB) is the read or write (RW) operation bit, which is set to 1 in read mode and to 0 in write mode. Following a START condition, the STW81103 identifies the device address on the bus and, if matched, acknowledges the identification on the SDA bus during the 9th clock pulse.
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STW81103
I2C bus interface
6.1.5
Single-byte write mode
Following a START condition, the master sends a device select code with the RW bit set to 0. The STW81103 sends an acknowledge and waits for the 1-byte internal sub-address that provides access to the internal registers. After receiving the sub-address internal byte, the STW81103 again responds with an acknowledge. A single-byte write to sub-address 00H changes the FUNCTIONAL_MODE register, a single-byte write with sub-address 04H changes the CONTROL register, and so on. Table 11.
S
Single-byte write mode
0 ack sub-address byte ack DATA IN ack P
1100A2A1A0
6.1.6
Multi-byte write mode
The multi-byte write mode can start from any internal address. The master sends the data bytes, and each one is acknowledged. The master terminates the transfer by generating a STOP condition. The sub-address decides the starting byte. For example, a multi-byte with sub-address 01H and 2 DATA_IN bytes changes the B_COUNTER and A_COUNTER registers (01H,02H), and a multi-byte with sub-address 00H and 6 DATA_IN bytes changes all the STW81103 registers. Table 12.
S
Multi-byte write mode
sub-address byte ack DATA IN ack ....... DATA IN ack P
1100A2A1A0 0 ack
6.1.7
Current byte address read mode
In the current byte address read mode, following a START condition, the master sends the device address with the RW bit set to 1. Note that no sub-address is needed since there is only one read register. The STW81103 acknowledges this and outputs the data byte. The master does not acknowledge the received byte, and terminates the transfer with a STOP condition. Table 13.
S
Current byte address read mode
1 ack DATA OUT No ack P
1100A2A1A0
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I2C bus interface
STW81103
6.2
Timing specification
Figure 23. Data and clock
SDA
SCL
t
cwl
t
cs
t
ch
t
cwh
Table 14.
Symbol tcs tch tcwh tcwl
Data and clock timing specifications
Parameter Data to clock setup time Data to clock hold time Clock pulse width high Clock pulse width low Minimum time 2 2 10 5 Units ns ns ns ns
Figure 24. Start and stop
SDA
SCL
t
start
t
stop
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STW81103 Table 15. Start and stop timing specifications
Parameter Clock to data start time Data to clock down stop time
I2C bus interface
Symbol tstart tstop
Minimum time 2 2
Units ns ns
Figure 25. Ack
SDA
8 SCL
9
t d1
t d2
Table 16.
Ack timing specifications
Parameter Ack begin delay Ack end delay Minimum time 2 2 Units ns ns
Symbol td1 td2
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I2C bus interface
STW81103
6.3
I2C registers
The STW81103 has 6 write-only registers and 1 read-only register.
6.3.1
Write-only registers
Table 17 gives a short description of the write-only registers.
Table 17. Write-only registers
DEC code 0 1 2 3 4 5 Description FUNCTIONAL_MODE B_COUNTER A_COUNTER REF_DIVIDER CONTROL CALIBRATION
HEX code 0x00 0x01 0x02 0x03 0x04 0x05
FUNCTIONAL_MODE
MSB b7 OUTBUF_CTRL_EN b6 CAL_AUTOSTART_EN b5 PD4 b4 PD3 b3 PD2 b2 PD1 b1 PD0 LSB b0 B11
OUTBUF_CTRL_EN: CAL_AUTOSTART_EN:
Output buffer control mode enable (0 = Off; 1 = ON) VCO calibration auto-restart enable (0 = Off; 1 = ON)
The bits PD[4:0] allow to select different functional modes for the STW81103 synthesizer according to the Table 18. Table 18. Functional modes
Decimal value PD[6:0] Description 0 1 2 3 4 5 6 7 8 9 Power down mode Enable VCO A, output frequency divided by 2 Enable VCO B, output frequency divided by 2 Enable external VCO, output frequency divided by 2 Enable VCO A, output frequency divided by 4 Enable VCO B, output frequency divided by 4 Enable external VCO, output frequency divided by 4 Enable VCO A, direct output Enable VCO B, direct output Enable external VCO, direct output
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STW81103
I2C bus interface
B_COUNTER
MSB b7 B10 b6 B9 b5 B8 b4 B7 b3 B6 b2 B5 b1 B4 LSB b0 B3
B[10:3]. B counter value (bit B11 in the previous register, bits B[2:0] in the next register)
A_COUNTER
MSB b7 B2 b6 B1 b5 B0 b4 A4 b3 A3 b2 A2 b1 A1 LSB b0 A0
Bits B[2:0] for B_COUNTER, A_COUNTER values.
REF_DIVIDER
MSB b7 R9 b6 R8 b5 R7 b4 R6 b3 R5 b2 R4 b1 R3 LSB b0 R2
Reference clock divider ratio R[9:1] (bits R1, R0 in the next register).
CONTROL
MSB b7 R1 b6 R0 b5 PLL_A1 b4 PLL_A0 b3 CPSEL2 b2 CPSEL1 b1 CPSEL0 LSB b0 PSC_SEL
The CONTROL register is used to set the charge pump current, the VCO output voltage amplitude and the prescaler modulus:
PLL_A[1:0]: CPSEL[2:0]: PSC_SEL: VCO amplitude charge pump output current prescaler modulus select ('0' for P=16, '1' for P=19)
The LO output frequency is programmed by setting the proper values for A, B and R according to the following formula:
F OUT =D R FREF - CLK x ( B x P + A ) x ---------------------------------R
where DR equals
{
1 0.5
for direct output for output divided by 2
0.25 for output divided by 4
and P is the selected prescaler modulus.
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I2C bus interface
STW81103
CALIBRATION
MSB b7 INITCAL b6 SERCAL b5 SELEXTCAL b4 CAL4 b3 CAL3 b2 CAL2 b1 CAL1 LSB b0 CAL0
This register controls the VCO calibrator using the following values:
INITCAL: SERCAL: for test purposes only, must be set to 0 at 1 starts the VCO auto-calibration (automatically reset to 0 at the end of calibration)
SELEXTCAL: for test purposes only; must be set to 0 CAL[4:0]: for test purposes only; must be set to 0
6.3.2
Read-only register
MSB b7 DEV_ID1 b6 DEV_ID0 b5 LOCK_DET b4 INTCAL4 b3 INTCAL3 b2 INTCAL2 b1 INTCAL1 LSB b0 INTCAL0
This register is automatically addressed in the `current byte address read mode', using the following values:
DEV_ID[1:0]: LOCK_DET: INTCAL[4:0]: device identifier bits; returns `10' 1 when PLL is locked internal value of the VCO control word
6.3.3
Default configuration
At power on, all the bits are set to '0'. Consequently the part starts in power down mode.
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STW81103
I2C bus interface
6.4
VCO calibration procedure
Calibration of the VCO center frequency is activated when the SERCAL bit (CALIBRATION register bit[6]) is set to 1. To program the device properly while ensuring VCO calibration, perform the following steps before every channel change: 1. Program all the registers using a multi-byte write sequence with the desired settings (functional mode, B and A counters, R counter, VCO amplitude, charge pump, prescaler modulus), and all the bits of the CALIBRATION register (05H) set to 0. Program the CALIBRATION register using a single-byte write sequence (subaddress 05H) with the SERCAL bit set to 1.
2.
The maximum allowed PFD frequency (FPFD) during calibration is 1 MHz; if you want a FPFD higher than 1 MHz, perform the following additional steps:

Perform all the steps of the calibration procedure, making sure to program the desired VCO frequency with proper settings for the R, B and A counters so that FPFD is 1 MHz. Program the device with the desired VCO and PFD frequency settings according to step 1) above.
6.4.1
VCO calibration auto-restart feature
The VCO calibration auto-restart feature can be enabled in two steps: 1. 2. set the desired frequency ensuring VCO calibration as described above (section 6.4) program the FUNCTIONAL_MODE register (sub-address 00H) using a single-byte write sequence with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others.
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SPI digital interface
STW81103
7
7.1
SPI digital interface
General features
The SPI digital interface is selected by hardware connection of pin #21 (DBUS_SEL) to 3.3 V. The STW81103 IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wire bus can be clocked at a frequency as high as 100 MHz to allow fast programming of the registers containing the data for RF IC configuration. The chip is programmed through serial words with a full length of 26 bits. The first 2 MSBs represent the address of the registers, and the 24 LSBs represent the value of the registers. Each data bit is stored in the internal shift register on the rising edge of the CLOCK signal. The outputs of the selected register are sent to the device on the rising edge of the LOAD signal.
Figure 26. SPI input and output bit order
Last bit sent (LSB)0 DATA 2 1 23 25(MSB)
24
A1
LOAD Address decoder
D23 (MSB)
LOAD #4
D0 (LSB)
Reg.#0 Reg.#1 Reg.#4
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STW81103 Table 19.
MSB
Address A1 A0 Data for register (24 bits)
SPI digital interface SPI data structure (MSB is sent first)
LSB
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 20.
Address A1 0 0 1 1 A0 0 1 0 1
Address decoder and outputs
Outputs DATABITS D23-D0 24 24 24 24 No 0 1 2 3 Name ST1 ST2 ST3 ST4 Function Reference divider, VCO amplitude, VCO calibration, charge pump current, prescaler modulus Functional modes, VCO dividers Reserved Reserved
7.2
Timing specification
tsetup thold
Figure 27. SPI timing specification
Data Clock
MSB
MSB-1
LSB
tclk_loadf tdk
Load
t
clk_loadr
tload
Table 21.
Symbol tsetup thold tclk tload tclk_loadr tclk_loadf
SPI timing specification
Parameter DATA to CLOCK setup time DATA to CLOCK hold time CLOCK cycle period LOAD pulse width CLOCK to LOAD rising edge CLOCK to LOAD falling edge Min. 0.8 0.2 10 3 2 0.5 Typ. Max. Units ns ns ns ns ns ns
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SPI digital interface
STW81103
7.3
Bit tables
Table 22. Bits at 00h and ST1
Register name = ST1 Description Serial interface address = 00h Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Name R9 R8 R7 R6 R5 Reference clock divider ratio R4 R3 R2 R1 R0 PLL_A1 VCO amplitude control PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0 For test purposes only; must be set to `0' Prescaler modulus select (0 for P=16, 1 for P=19) For test purposes only; must be set to 0 Enable VCO calibration (see Section 7.4) For test purposes only; must be set to `0' Charge pump output current control
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STW81103 Table 23. Bits at 01h and ST2
Register name = ST2 Description
SPI digital interface
Serial interface address = 01h Bit [23] [22] [21] [20] [19] [18] Name OUTBUF_CTRL_EN CAL_AUTOSTART_EN PD4 PD3 PD2 PD1
Output buffer control mode enable (0 = Off, 1 = On) VCO calibration auto restart enable (0 = Off, 1 = On) Device functional modes: 0. Power down 1. Enable VCO A, output frequency divided by 2 2. Enable VCO B, output frequency divided by 2 3. Enable external VCO, output frequency divided by 2 4. Enable VCO A, output frequency divided by 4 5. Enable VCO B, output frequency divided by 4 6. Enable external VCO, output frequency divided by 4 7. Enable VCO A, direct output 8. Enable VCO B, direct output 9. Enable external VCO, direct output
[17]
PD0
[16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
B11 B10 B9 B8 B7 B6 B_COUNTER bits B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 A_COUNTER bits
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SPI digital interface
STW81103
The LO output frequency is programmed by setting the proper value for A, B and R according to the following formula:
F REF - CLK x ( B x P + A ) x ---------------------------------R R
F
OUT
=D
where DR equals
{
1 0.5
for direct output for output divided by 2
0.25 for output divided by 4
and P is the selected prescaler modulus.
7.3.1
Default configuration
At power on, all the bits are set to '0'. Consequently the part starts in power down mode.
7.4
VCO calibration procedure
Calibration of the VCO center frequency is activated when the SERCAL bit (ST1 register bit[6]) is set to 1. To program the device properly while ensuring VCO calibration, perform the following steps before every channel change: 1. 2. Program the ST2 register with the desired settings (functional mode, B and A counters). Program the ST1 register with the desired settings (R counter, VCO amplitude, charge pump, prescaler modulus) and with the SERCAL bit set to 1.
The maximum allowed PFD frequency (FPFD) during calibration is 1 MHz; if you want a FPFD higher than 1 MHz, perform the following additional steps:
Perform all the steps (step 1 and 2 above) of the calibration procedure, making sure to program the desired VCO frequency with proper settings of the R, B and A counters so that FPFD is 1 MHz. Program the device with the desired VCO and PFD frequency settings as per steps 1 and 2 above with SERCAL bit set to 0.
7.4.1
VCO calibration auto-restart feature
The VCO calibration auto-restart feature can be enabled in two steps: 1. 2. Set the desired frequency ensuring VCO calibration as described above (Section 7.4) Program the ST2 register with the CAL_AUTOSTART_EN bit set to '1' while keeping unchanged the others.
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STW81103
Application information
8
Application information
The STW81103 features three different alternately selectable bands: direct output (2.5 to 3.05 GHz and 4.35 to 5.0 GHz), divided by 2 (1.25 to 1.525 GHz and 2.175 to 2.5 GHz) and divided by 4 (625 to 762.5 MHz and 1087.5 to 1250 MHz). To achieve a suitable power level, a good matching network is necessary to adapt the output stage to a 50 load. Moreover, since most commercial RF components have single-ended input and output terminations, a differential to single-ended conversion may be required. The different matching configurations shown below for each of the three bands are suggested as a guideline when designing your own application board. Inside the evaluation kit is the ADS design for each matching configuration suggested in this chapter. The name of the corresponding ADS design is given in each figure. The ADS designs provide only a first indication of the output stage matching, and should be reworked according to the choices of layout, board substrate, components and so on. The ADS designs of the evaluation boards are provided with a complete electromagnetic modelling (board, components, and so on).
8.1
Direct output
If you do not need a differential to single conversion, you can match the output buffer of the STW81103 in the simple way shown in Figure 28. This illustrates the differential to singleended output network in the 2.5 - 5.0 GHz range (MATCH_LC_LUMP_4G_DIFF.dsn). Figure 28. Differential/single-ended output network (MATCH_LC_LUMP_4G_DIFF.dsn)
Vcc
100 ohm
5.5nH 10pF
50 ohm
RF
OUTP
10pF RF
OUTN
100 ohm
5.5nH
50 ohm
Vcc
Since most discrete components for microwave applications are single-ended, you can easily use one of the two outputs and terminate the other one to 50 with a 3 dB power loss.
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Application information
STW81103
Alternatively, you can combine the two outputs in other ways. A first topology for the direct output (2.5 to 5.0 GHz) is suggested in Figure 29. It basically consists of a simple LC balun and a matching network to adapt the output to a 50 load. The two LC networks shift output signal phase of -90 and +90, thus combining the two outputs. This topology, designed for a center frequency of 4 GHz, is intrinsically narrow-band since the LC balun is tuned at a single frequency. If the application requires a different sub-band, the LC combiner can be easily tuned to the frequency of interest. Figure 29. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn)
Vcc
50 ohm
1.9nH
0.8pF 1.9nH
RF
OUTP
0.8pF
2.5pF
1.9nH RF
50 ohm
OUTN
0.8pF 50 ohm 1.9nH 0.8pF
Vcc
The 1.9 nH shunt inductor works as a DC feed for one of the open collector terminals as well as a matching element along with the other components. The 1.9 nH series inductors are used to resonate the parasitic capacitance of the chip. For optimum output matching, it is recommended to use 0402 Murata or AVX capacitors and 0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths to minimize losses and undesired impedance shift. An alternative topology that permits a more broadband matching as well as balanced to unbalanced conversion, is shown in Figure 30.
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STW81103
Application information Figure 30. Evaluation board (EVB4G) matching network (MATCH_EVB4G.dsn)
Vcc
50 ohm
5.5nH 12pF 12pF 2:1 12pF 4.7pF
RF
OUTP
RF
1pF
1pF
1.2pF
1.2pF
50 ohm
OUTN
50 ohm
5.5nH
Vcc
For differential to single conversion, the 50 to 100 Johanson balun is recommended (3700BL15B100).
8.2
Divided by 2 output
If your application does not require a balanced to unbalanced conversion, the output matching reduces to the simple circuit shown below (Figure 31), which illustrates a differential to single-ended output network in the 1.25 - 2.5 GHz range (MATCH_LC_LUMP_2G_DIFF.dsn). You can easily use this solution to provide one singleended output that terminates the other output at 50 with a 3 dB power loss. Figure 31. Differential/single-ended output network (MATCH_LC_LUMP_2G_DIFF.dsn)
Vcc
50 ohm
22nH 10pF
50 ohm
RF
OUTP
10pF RF
OUTN
50 ohm
22nH
50 ohm
Vcc
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Application information
STW81103
A first solution to combine the differential outputs is the lumped LC type balun tuned in the 2 GHz band (Figure 32). Figure 32. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn)
Vcc
50 ohm
2.7nH
2pF 2.7nH
RF
OUTP
2pF
3pF
2.7nH 3nH RF
OUTN
50 ohm
2pF 50 ohm 2.7nH 2pF
Vcc
The same recommendation for the SMD components also applies to the divided by 2 output. Another topology suited to combining the two outputs for the divided by 2 frequencies is represented in Figure 33. Figure 33. Evaluation board (EVB2G) matching network (MATCH_EVB2G.dsn)
Vcc
50 ohm
5.5nH 22pF 22pF 2:1 22pF
RF
1.9nH
OUTP
RF
1.2pF
50 ohm
OUTN
50 ohm
5.5nH
Vcc
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STW81103
Application information For differential to single conversion, the 50 to 100 Johanson balun (1600BL15B100) is recommended.
8.3
Divided by 4 output
The topology, components, values and considerations of Figure 31 also apply to the divided by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn). As for the previous sections, a solution to combine the differential outputs is the lumped LC type balun tuned in the 1 GHz band (Figure 34). Figure 34. LC lumped balun for divided by 4 output (MATCH_LC_LUMP_1G.dsn)
Vcc
25 ohm
5.5nH
4pF
5.5nH
RF
OUTP
4pF
6pF
5.5nH RF
14nH
50 ohm
OUTN
4pF 25 ohm 5.5nH 4pF
Vcc
If you prefer to use an RF balun, you can adapt the topology depicted in Figure 33, and change the balun and the matching components (Figure 35). The suggested balun for the 0.625 - 1.25 GHz frequency range is the 1:1 Johanson 900BL15C050.
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Application information
STW81103
Figure 35. Evaluation board (EVB1G) matching network (MATCH_EVB1G.dsn)
Vcc
25 ohm
18nH 8.2pF 22pF 1:1 8.2pF
RF
2.1nH
OUTP
RF
0.5pF
50 ohm
OUTN
25 ohm
18nH
Vcc
8.4
Evaluation kit
An evaluation kit can be delivered upon request, including the following:

Evaluation board GUI (graphical user interface) to program the device Measured S parameters of the RF output ADS2005 schematics providing guidelines for application board design STWPLLSim software for PLL loop filter design and noise simulation Application programming interface (API)
Three different evaluation kits are available, each optimized for one of the following frequency ranges:

1 GHz 2 GHz 4 GHz
When ordering, please specify one of the following order codes: Table 24. Order code of the evaluation kit
Part number STW81103-EVB1G STW81103-EVB2G STW81103-EVB4G Description 1 GHz frequency range - divider by 4 output optimized 2 GHz frequency range - divider by 2 output optimized 4 GHz frequency range - direct output optimized
The three evaluation kits differ only for the output stage network and can be adapted from one frequency band variant to a different one replacing properly the matching components and the balun.
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STW81103
Application diagram
9
Application diagram
Figure 36. Typical application diagram
From/to microcontroller
100
100
100
15p
15p
15p
ADD0/LOAD
SCL/CLK
1n
22p
10
SDA/DATA
EXT_PD
ADD2
ADD1
VDD1
VDD_DBUS
I2C SPI VDD2
VDD_VCOA VDD_DIV2
DBUS_SEL
VDD_BUFVCO
VDD1 RF Out
VDD_OUTBUF
EXTVCO_INP
OUTBUFP
STW81103
1n EXTVCO_INN
22p
10
OUTBUFN
VDD_PLL
VDD_DIV4
REF_CLK
ref clk
1.8n 51
VDD _CP
VDD_ESD
VCTR L
VDD1
1n 22p 10
REXT
ICP
4.7K
VDD1
2.2K 8.2K 68p 2.7n 1n 22p 10 270p
loop filter
TEST1
VDD_VCOB
LOCK_DET
VDD1
TEST2
to microcontroller
Note:
1 2 3 4
See Section 8: Application information for further information on output matching topology. EXT_PD, ADD2, ADD1 (and ADD0 when the I2C bus is selected) can be hard wired directly on the board. Loop filter values are for FSTEP = 200 kHz. For best performance VDD1 must be a low noise supply (20 VRMS in 10 Hz-100 kHz BW).
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Application diagram Figure 37. Ping-pong architecture diagram
STW81103
Note:
1 2 3 4
See Section 8: Application information for further information on output matching topology. EXT_PD, ADD2, ADD1 (and ADD0 when the I2C bus is selected) can be hard wired directly on the board. Loop filter values are for FSTEP = 200 kHz. For best performance VDD1_1 and VDD1_2 must be low noise supplies (20 VRMS in 10 Hz-100 KHz BW).
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STW81103
Application diagram Figure 38. Application diagram with external VCO (LO output from STW81103)
Note:
See Section 8: Application information for further information on output matching topology.
Figure 39. Application diagram with external VCO (LO output from VCO)
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Package mechanical data
STW81103
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages, which have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 40. VFQFPN28 mechanical drawing
Note:
1 2
VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead. (Very thin: A=1.00 Max) Details of the terminal 1 identifier are optional, but if given, must be located on the top surface of the package by using either a mold or marked features.
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STW81103 Table 25.
Ref. A A1 A2 A3 b D D1 D2 E E1 E2 e L P K ddd 0.350 2.950 2.950 4.850 0.180 4.850
Package mechanical data Package dimensions
Min. 0.800 Typ. 0.900 0.020 0.650 0.200 0.250 5.000 4.750 3.100 5.000 4.750 3.100 0.500 0.550 0.750 0.600 14 0.080 3.250 3.250 5.150 0.300 5.150 Max. 1.000 0.050 1.000 Unit mm mm mm mm mm mm mm mm mm mm mm mm mm mm degrees mm
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Ordering information
STW81103
11
Ordering information
Table 26. Order codes
Temp range, C -40 to 85 -40 to 85 Package VFQFPN28 VFQFPN28 Tray Tape and reel Packing
Part number STW81103AT STW81103ATR
12
Revision history
Table 27.
Date 18-Jul-2007 14-Aug-2007
Document revision history
Revision 1 2 Initial release. Added Chapter 8: Application information. Modified Section 6.4: VCO calibration procedure, and pin #23 description in Table 1. Updated Table 1: Pin description. Updated Table 2: Absolute maximum ratings, Table 3: Operating conditions, Table 5: Electrical specifications and Table 6: Phase noise specification. Updated Section 5.8.2: VCO frequency calibration. Added VCO calibration auto-restart feature. Updated Section 5.8.3: VCO voltage amplitude control. Added Section 5.9: Output stage and Section 5.10: External VCO buffer. Updated FUNCTIONAL_MODE and CALIBRATION registers. Added Section 6.3.3: Default configuration. Updated Section 6.4: VCO calibration procedure and added Section 6.4.1: VCO calibration auto-restart feature. Updated Table 23: Bits at 01h and ST2. Added Section 7.3.1: Default configuration. Updated Section 7.4: VCO calibration procedure and added Section 7.4.1: VCO calibration auto-restart feature. Added `Application program interface API' item in Section 8.4. Modified notes after Figure 36. Added Figure 37, Figure 38 and Figure 39. Modified Figure 40. Changes
28-Mar-2008
3
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STW81103
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