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LTC4307-1 High Definition Multimedia Interface (HDMI) LevelShifting 2-Wire Bus Buffer FEATURES

DESCRIPTIO

Bidirectional Buffer for Display Data Channel (DDC) Compliant with HDMI Specification Version 1.3 DDC Capacitance Requirement Level Translation Between 3.3V and 5V 5kV Human Body Model ESD Protection 60mV Buffer Offset Independent of Load Compatible with Non-Compliant VOL I2C Devices Isolates Input SDA and SCL Line from Output Compatible with I2CTM, I2C Fast Mode and SMBus READY Open-Drain Output High Impedance SDA, SCL Pins for VCC = 0V Small 8-Lead (3mm x 3mm) DFN and 8-Lead MSOP Packages
The LTC4307-1 is a 2-wire bus buffer that provides capacitance buffering between input and output. The HDMI specification requires that devices have less than 50pF of input capacitance on their DDC bus lines. The LTC4307-1's capacitance buffering feature, in conjunction with its sub-10pF data and clock input capacitance, allows HDMI components to easily meet the 50pF requirement and tolerate high capacitance on the internal bus. The LTC4307-1 also provides level-shifting between 3.3V and 5V systems to allow lower voltage HDMI transmitters, receivers and EEPROM to interface to the 5V DDC bus. READY is an open-drain digital output flag that indicates whether or not the input and output busses are connected and can interface to the HDMI hot plug detect (HPD) signal. When driven high, the ENABLE digital input allows the LTC4307-1 to connect after a stop bit or bus idle. Driving ENABLE low breaks the connection between the input and output busses.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7032051, 6356140, 6650174
APPLICATIO S

HDMI 3.3V/5V Level Translation Capacitance Buffer/Bus Extender
TYPICAL APPLICATIO
DVD PLAYER (SOURCE)
TV (SINK) 3.3V
5V 1.8k HDMI TX IC 1.8k
EEPROM
0.1F 10k 10k 200mV/DIV
LTC4307-1 HDMI CABLE <50pF VCC SDAIN SDAOUT SCLIN SCLOUT DDC GROUND ENABLE GND
HDMI RX IC C
43071 TA01a
U
Rising Edge from Asserted Low
1000 800 600 LOW OFFSET SDAOUT SDAIN 200 400 0 0 100 200 300 400 100ns/DIV 500 600
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U
U
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LTC4307-1 ABSOLUTE AXI U RATI GS
VCC to GND ................................................. - 0.3V to 6V SDAIN, SCLIN, SDAOUT, SCLOUT, READY, ENABLE .......................................... -0.3V to 6V Maximum Sink Current (SDAIN, SCLIN, SDAOUT, SCLOUT, READY) .............................................. 50mA Operating Temperature Range LTC4307C ................................................ 0C to 70C LTC4307I .............................................- 40C to 85C
PIN CONFIGURATION
TOP VIEW ENABLE 1 SCLOUT 2 SCLIN 3 GND 4 9 8 7 6 5 VCC SDAOUT SDAIN READY ENABLE SCLOUT SCLIN GND 1 2 3 4 TOP VIEW 8 7 6 5 VCC SDAOUT SDAIN READY
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 43C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC4307CDD-1#PBF LTC4307IDD-1#PBF LTC4307CMS8-1#PBF LTC4307IMS8-1#PBF TAPE AND REEL LTC4307CDD-1#TRPBF LTC4307IDD-1#TRPBF LTC4307CMS8-1#TRPBF LTC4307IMS8-1#TRPBF PART MARKING* LDBP LDBP LTDBN LTDBN PACKAGE DESCRIPTION 8-Lead (3mm x 3mm) Plastic DFN 8-Lead (3mm x 3mm) Plastic DFN 8-Lead Plastic MSOP 8-Lead Plastic MSOP TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V, unless otherwise noted.
SYMBOL Power Supply VCC ICC ISD tIDLE Positive Supply Voltage Supply Current Shutdown Supply Current Bus Idle Time VCC = 5.5V, VSCLOUT = VSDAOUT = 0V (Note 5)

ELECTRICAL CHARACTERISTICS
PARAMETER
2
U
WW
W
(Notes 1, 6)
Storage Temperature Range DFN ....................................................- 65C to 125C MSOP ................................................- 65C to 150C Lead Temperature (Soldering, 10 sec) MSOP ............................................................... 300C
MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 125C, JA = 200C/W
CONDITIONS
MIN 2.3
TYP
MAX 5.5
UNITS V mA A s
8 900 55 95
11 1200 175
VCC = 5.5V, ENABLE = GND, SDA, SCL = 5.5V
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LTC4307-1 ELECTRICAL CHARACTERISTICS
SYMBOL VTHR_ENABLE IENABLE tPLH_EN tPHL_EN tPLH_READY tPHL_READY VOL_READY IOFF_READY tPHL tPLH tFALL PARAMETER ENABLE Threshold ENABLE Input Current ENABLE Delay Off-On ENABLE Delay On-Off READY Delay Off-On READY Delay On-Off READY Output Low Voltage READY Off Leakage Current SDA/SCL Propagation Delay High to Low SDA/SCL Propagation Delay Low to High SDA/SCL Transition Time High to Low ENABLE from 0V to VCC VCC = 3.3V (Figure 1) VCC = 3.3V (Note 3) (Figure 1) VCC = 3.3V (Note 3) (Figure 1) VCC = 3.3V (Note 3) (Figure 1) IPULLUP = 3mA, VCC = 2.3V VCC = READY = 5.5V CLOAD = 50pF, 2.7k to VCC on SDA, SCL, VCC = 3.3V (Notes 2, 3) (Figure 1) CLOAD = 50pF, 2.7k to VCC on SDA, SCL, VCC = 3.3V (Notes 2, 3) (Figure 1) CLOAD = 100pF, 10k to VCC on SDA, SCL, VCC = 3.3V (Notes 3, 4) (Figure 1) 2.7k to VCC on SDA, SCL, VCC = 3.3V, Driven SDA, SCL = 0.2V Rising Edge (Note 3) (Note 3) SDA, SCL, Pins SDA, SCL Pins, ISINK = 4mA, SDAIN/SCLIN = 0.2V, VCC = 2.7V 2.7k to VCC on SDA, SCL, VCC = 3.3V, Driven SDA, SCL = 0.1V VILMAX fI2C,MAX tBUF tHD,STA tSU,STA tSU,STO tHD,DATI tSU,DAT Buffer Input Logic Low Voltage I2C Maximum Operating Frequency Bus Free Time Between Stop and Start Condition Repeated Start Condition Set-Up Time Stop Condition Set-Up Time Data Hold Time Input Data Set-Up Time VCC = 3.3V (Note 3) (Note 3) Timing Characteristics 400 600 1.3 100 0 0 0 100 Note 3: Determined by design, not tested in production. Note 4: Measure points are 0.3 * VCC and 0.7 * VCC. Note 5: ICC test performed with connection circuitry active. Note 6: All currents into pins are positive; all voltages are referenced to GND unless otherwise specified. kHz s ns ns ns ns ns

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3.3V, unless otherwise noted.
CONDITIONS MIN 0.8 TYP 1.4 0.1 95 10 10 10 0.4 0.1 70 10 30 300 5 MAX 2 5 UNITS V A s ns ns ns V A ns ns ns
Propagation Delay
Input-Output Connection VOS VTHR VHYS CIN ILEAK VOL Input-Output Offset Voltage SDA, SCL Logic Input Threshold Voltage SDA, SCL Logic Input Threshold Voltage Hysteresis Digital Input Capacitance SDAIN, SDAOUT, SCLIN, SCLOUT Input Leakage Current Output Low Voltage 20 60 100 mV V mV 10 5 0 120 160 0.4 205 1.2 pF A V mV V
0.45VCC 0.55VCC 0.65VCC 50
Hold Time After (Repeated) Start Condition (Note 3) (Note 3) (Note 3) (Note 3) (Note 3)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: See "Propagation Delays" in the Operations section for a discussion of tPHL and tPLH as a function of pull-up resistance and bus capacitance.
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LTC4307-1 TIMING DIAGRAMS
ENABLE, CONNECT, READY Timing
tPLH_READY tPLH_EN ENABLE tPHL_READY tPHL_EN
CONNECT
READY
4307 F01a
Rising and Falling Propagation Delay and Rise and Fall Times for SDAIN, SDAOUT and SCLIN, SCLOUT
tRISE tPLH SDAIN/SCLIN tPHL tRISE tFALL tFALL
SDAOUT/SCLOUT
4307 F01b
Figure 1. Timing Diagrams
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LTC4307-1 TYPICAL PERFOR A CE CHARACTERISTICS
ICC vs Temperature
8.3 VCC = 5.5V 8.0 900 7.7 tPHL (ns) 7.4 ICC (mA) 7.1 6.8 VCC = 2.3V 6.5 6.2 5.9 -50 -25 50 25 TEMPERATURE (C) 0 75 100
4307 G01
ISD (A)
VCC = 3.3V
Input-Output High to Low Propagation Delay vs COUT
130 120 110 tPHL (ns) 100 90 80 70 60 0 200 400 600 COUT (pF) 800 1000
4307 G04
CIN = 50pF RPULLUPIN = RPULLUPOUT = 10k
VOUT - VIN (mV)
VCC = 5.5V
UW
TA = 25C, VCC = 3.3V, unless otherwise indicated. Input-Output High to Low Propagation Delay vs Temperature
100 VCC = 5.5V 80 VCC = 2.3V VCC = 3.3V 60
ISD vs Temperature
950 VCC = 5.5V
850
800
VCC = 3.3V
40
750
VCC = 2.3V
20 CIN = COUT = 50pF RPULLUPIN = RPULLUPOUT = 10k 75 100
4307 G02
700 -50
-25
25 50 0 TEMPERATURE (C)
0 -50
-25
0 25 50 TEMPERATURE (C)
75
100
4307 G03
Connection Circuitry VOUT - VIN (VOS)
85
75
65
VCC = 3.3V
55
45 1 2 3 4 6 7 5 RPULLUP (k) 8 9 10
4307 G05
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LTC4307-1 PI FU CTIO S
ENABLE (Pin 1): Connection Enable Input. This is a 1.4V digital threshold input pin. For normal operation pull or tie ENABLE high. Driving ENABLE below 0.8V isolates SDAIN from SDAOUT, SCLIN from SCLOUT and asserts READY low. A rising edge on ENABLE after a fault has occurred forces a connection between SDAIN, SDAOUT and SCLIN, SCLOUT. Connect to VCC if unused. SCLOUT (Pin 2): Serial Clock Output. Connect this pin to the clock line of a DDC bus. A pull-up resistor should be connected between this pin and a supply voltage greater than or equal to the VCC voltage. SCLIN (Pin 3): Serial Clock Input. Connect this pin to the clock line of a DDC bus. A pull-up resistor should be connected between this pin and a supply voltage greater than or equal to the VCC voltage. GND (Pin 4): Device Ground. Connect this pin to a ground plane for best results. READY (Pin 5): Connection READY Status Output. The READY pin is an open-drain N-channel MOSFET output that pulls low when ENABLE is low, or when the start-up and connection sequence described in the Operation section has not been completed. READY goes high when ENABLE is high and a connection is made. READY can be used to control the HDMI HPD signal. Connect a pull-up resistor, typically 10k, from this pin to VCC to provide the pull-up. This pin can be floated if unused. SDAIN (Pin 6): Serial Data Input. Connect this pin to the data line of a DDC bus. A pull-up resistor should be connected between this pin and a supply voltage greater than or equal to the VCC voltage. SDAOUT (Pin 7): Serial Data Output. Connect this pin to the data line of a DDC bus. A pull-up resistor should be connected between this pin and a supply voltage greater than or equal to the VCC voltage. VCC (Pin 8): Supply Voltage Input. Place a bypass capacitor of at least 0.01F close to VCC for best results. Exposed Pad (Pin 9, DFN Package Only): Exposed Pad may be left open or connected to device ground.
6
U
U
U
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LTC4307-1 BLOCK DIAGRA W
Low Offset Level-Shifting 2-Wire Bus Buffer
VCC 8 CONNECT 6 SDAIN SDAOUT 7 SLEW RATE DETECTOR CONNECT CONNECT 3 SCLIN SCLOUT 2 SLEW RATE DETECTOR CONNECT
SLEW RATE DETECTOR
SLEW RATE DETECTOR
+ -
0.55VCC
+
0.55VCC
- + +
LOGIC
-
0.55VCC READY
0.55VCC
-
CONNECT
5
1
ENABLE
+
1.4V
-
UVLO
95s DELAY
CONNECT
GND
4
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LTC4307-1 OPERATION
Start-Up When the LTC4307-1 first receives power on its VCC pin during power-up, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA or SCL pins until VCC rises above 2V (typ). This is to ensure that the LTC4307-1 does not try to function until it has enough voltage to do so. Once the LTC4307-1 comes out of UVLO, it monitors both 2-wire busses for either a stop bit or bus idle condition to indicate the completion of data transactions. When both sides are idle or one side has a stop bit condition while the other is idle, the input-to-output connection circuitry is activated, joining SDAIN to SDAOUT and SCLIN to SCLOUT. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. The LTC4307-1 is tolerant of I2C bus DC logic low voltages up to the 0.3VCC VIL I2C specification. When the LTC4307-1 senses a rising edge on the bus, it deactivates its pull-down devices for bus voltages as low as 0.48V. Care must be taken to ensure that devices participating in clock stretching or arbitration force logic low voltages below 0.48V at the LTC4307-1 inputs. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4307-1. Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the capacitances of the two 2-wire busses isolated from each other. Placing an LTC4307-1 close to an HDMI port inside an HDMI transmitter or receiver allows the HDMI device to pass the capacitance compliance specification. Because of this isolation, the waveforms on SDAIN and SCLIN look slightly different than the corresponding waveforms on SDAOUT and SCLOUT as described here. Input to Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4307-1's data or clock pins, the LTC4307-1 regulates the voltage on the opposite data or clock pins to a slightly higher voltage, typically 60mV above VLOW1. This offset is practically independent of pull-up current (see the Typical Performance curves). Propagation Delays During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent capacitance on the line. If the pull-up resistors are the same, a difference in rise time occurs which is directly proportional to the difference in capacitance between the two sides. Users must account for differences in the RC time constants between the two 2-wire busses and ensure that all system timing specifications are met on both busses. There is a finite propagation delay through the connection circuitry for falling waveforms. Figure 2 shows the falling edge waveforms for VCC = 5.5V, a 10k pull-up resistor on each side, 150pF parasitic capacitance on the input bus and 50pF on the output pins. An external N-channel MOSFET device pulls down the voltage on the side with 150pF capacitance; the LTC4307-1 pulls down the voltage on the opposite side with a delay of 80ns. This delay is always positive and is a function of supply voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical Performance Characteristics section shows propagation delay as a function of temperature and voltage for 10k pull-up resistors and 50pF equivalent capacitance on both sides of the part. Also, the tPHL vs COUT curve for VCC = 5.5V shows that increasing the
INPUT SIDE 150pF 1V/DIV
OUTPUT SIDE 50pF 1V/DIV
200ns/DIV
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Figure 2. Input-Output Falling Edge Waveforms
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LTC4307-1 OPERATION
capacitance from 50pF to 150pF results in a tPHL increase from 81ns to 91ns. Larger output capacitances translate to longer delays (up to 125ns). Users must quantify the difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold times accordingly. READY Digital Output This pin provides a digital flag which is low when either ENABLE is low or the start-up sequence described earlier in this section has not been completed. READY goes high when ENABLE is high and the input and output 2-wire busses are connected. The pin is driven by an open-drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor to VCC to provide the pull-up. READY can be used to control the HDMI hot plug detect (HPD) signal to prevent the possibility of erroneous attempts by the source to contact the sink before the sink is ready to communicate.
Table 1. Differences Between the LTC4307 and the LTC4307-1
SPECIFICATION Pre-charge Level Shifting Stuck Bus Disconnect and Recovery Rise Time Accelerators LTC4307 Yes No Yes Yes LTC4307-1 No Yes, 2.2V to 5.5V No No COMMENTS ON LTC4307-1 HDMI DDC Lines are Not Hot Swapped Provides Communication Between 3.3V and 5V DDC Busses, Protects 3.3V Devices from 5V Supply Stuck Busses, Not an Issue in HDMI Systems Complies with HDMI Specification Version 1.3 DDC Capacitance Requirement
ENABLE When the ENABLE pin is driven below 0.8V with respect to the LTC4307-1's ground, the input 2-wire bus is disconnected from the output 2-wire bus and the READY pin is internally pulled low. When the pin is driven above 2V, the part waits for data transactions on both 2-wire busses to be complete (as described in the Start-Up section) before connecting the two sides. At this time the internal pull-down on READY releases. LTC4307 and LTC4307-1 Feature Differences The LTC4307-1 HDMI level-shifting 2-wire bus buffer is specifically intended for HDMI applications. Features in the general purpose LTC4307 device that are not required in HDMI systems have been removed. In addition, levelshifting functionality has been added to the LTC4307-1 to allow 3.3V HDMI devices to interface safely to the 5V HDMI DDC bus. See Table 1 for a list of the differences between the LTC4307 and LTC4307 -1.
APPLICATIONS INFORMATION
Figure 3 shows the LTC4307-1 in a capacitance buffering application. Due to the LTC4307-1's capacitance buffering feature and sub-10pF input capacitance, this application circuit passes the HDMI 50pF maximum DDC capacitance specification easily when the LTC4307-1 is located right at the HDMI connector interface as shown. The capacitance of the internal bus connected to the SDAIN and SCLIN pins may be much larger than 50pF, but because of the LTC4307-1's capacitance buffering, the internal bus capacitance is isolated from the HDMI connector. In HDMI, the sink device pulls the hot plug detect HPD signal high to tell the source that it is ready to accept commands through the DDC. This signal can be controlled through the READY pin of the LTC4307-1 to prevent the possibility of erroneous attempts by the source to contact the sink before the sink is ready to return its extended display identification data (EDID). The READY pin only goes high after 5V is applied and the LTC4307-1 ENABLE pin is pulled high by the HDMI receiver IC, a controller in the sink, or the 5V line itself.
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LTC4307-1 APPLICATIONS INFORMATION
Figure 4 shows the LTC4307-1 being used for capacitance buffering and 5V to 3.3V level shifting. In this application, the EEPROM is powered by a backup 3.3V supply that is available when the component is turned off. The EDID in the EEPROM should be available for reading even when a component's power is off. Although the applications shown in this section are for HDMI receive channels, the LTC4307-1 can also be used in HDMI transmit channels with equal success as shown in the Typical Application on the last page of this data sheet.
5V R1 1.8k SDA TO SCL HDMI TX IC HPD R3 100k HDMI SOURCE (DVD PLAYER) HDMI CABLE R2 1.8k
5V C1 0.1F R4 47k R5 1k R6 100k R7 10k R8 10k
EEPROM VCC SCL SDA GND
3.3V R9 10k R10 10k HDMI RX IC
LTC4307-1 VCC READY SDAOUT SDAIN SCLOUT SCLIN ENABLE GND
DDC
DDC/CEC GROUND
HDMI SINK (DIGITAL TV)
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Figure 3. The LTC4307-1 in HDMI Capacitance Buffering Application
SWITCHED 3.3V
5V R1 1.8k TO SDA HDMI SCL TX IC DDC/CEC GROUND HDMI SOURCE (DVD PLAYER) HDMI REPEATER (DIGITAL RECEIVER)
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5V R2 1.8k R3 47k R4 47k C1 0.1F
BACKUP 3.3V
R5 100k R6 10k R7 10k
EEPROM VCC SCL SDA
LTC4307-1 READY VCC SDAIN SDAOUT SCLIN SCLOUT
HDMI RX IC
HDMI CABLE
DDC
ENABLE GND
C
Figure 4. The LTC4307-1 in a Level Shifting and Capacitance Buffering HDMI Application with Backup 3.3V
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LTC4307-1 PACKAGE DESCRIPTION
DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115 TYP 5 0.675 0.05 0.38 0.10 8
3.5 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE PIN 1 TOP MARK (NOTE 6)
3.00 0.10 (4 SIDES)
1.65 0.10 (2 SIDES)
(DD8) DFN 1203
0.200 REF
0.75 0.05
4 0.25 0.05 2.38 0.10 (2 SIDES)
1 0.50 BSC
0.00 - 0.05
BOTTOM VIEW--EXPOSED PAD
MS8 Package 8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 0.102 (.118 .004) (NOTE 3)
8
7 65
0.52 (.0205) REF
0.889 0.127 (.035 .005) GAUGE PLANE 5.23 (.206) MIN 3.20 - 3.45 (.126 - .136)
0.254 (.010)
DETAIL "A" 0 - 6 TYP
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE 4)
1 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.22 - 0.38 (.009 - .015) TYP 1.10 (.043) MAX
23
4 0.86 (.034) REF
0.42 0.038 (.0165 .0015) TYP
0.65 (.0256) BSC
RECOMMENDED SOLDER PAD LAYOUT
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.65 (.0256) BSC
0.1016 0.0508 (.004 .002)
MSOP (MS8) 0307 REV F
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4307-1 TYPICAL APPLICATION
HDMI Application with LTC4307-1's Providing Capacitance Buffering On Both the Transmit and Receive Channels
DVD PLAYER (SOURCE) TV (SINK)
5V C1 0.1F R1 10k R2 10k LTC4307-1 VCC READY SDAIN SDAOUT HDMI TX IC SCLIN SCLOUT ENABLE GND DDC GROUND R3 10k R4 1.8k R5 1.8k HDMI CABLE
EEPROM C2 0.1F LTC4307-1 VCC READY SDAIN SDAOUT SCLIN SCLOUT ENABLE GND
3.3V
R6 10k
R7 10k
<50pF
HDMI RX IC C
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ThinSOT is a trademark of Linear Technology Corporation
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12 Linear Technology Corporation
(408) 432-1900
LT 0208 REV A * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
FAX: (408) 434-0507 www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2007

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