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| CCLD-915 Model 9X14 mm SMD, 3.3V, LVDS Frequency Range: Frequency Stability: Temperature Range: (Option M) (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Load: 100 Ohms Logic: Output Voltage Levels Disable Time Enable Time 12KHz to 20MHz ree dF ea oHS nt L R plia m Co Differential LVDS Clock Oscillator Designed to meet today's requirements for 3.3V LVDS applications. The CCLD-915 is a very low noise, low jitter clock oscillator. Also available in 2.5V model. Available on tape and reel in quantities of 500ea. 162MHz to 250MHz 25ppm to 100ppm 0C to 70C -20C to 70C -40C to 85C -55C to 120C 3.3V 0.3V 35mA Typ, 47mA Max Differential LVDS 45/55% Max @ 50% Vdd 1ns Max @ 20% to 80% Vdd Connected between OUT and COUT "0" = 1.10V Typical, 0.90V Min "1" = 1.45V Typical, 1.65V Max 200ns Max 200ns Max 1ps RMS Max Jitter: Aging: <3ppm 1st/yr, 1ppm every year thereafter SUGGESTED PAD LAYOUT 0.560 (14.2) Bottom View 0.560 (14.2) 0.210 (5.3) 0.050 (1.27) 0.360 (9.14) CRYSTEK P/N Frequency Date Code 1 6 0.100 (2.54) 2 5 3 4 0.040 (1.01) 0.070 (1.77) 0.090 (2.28) 0.280 (7.11) 0.200 (5.08) Bypass Capacitor Recommended RECOMMENDED REFLOW SOLDERING PROFILE 235 185 150 100 Temperature (4C/sec Max) 1 to 2 minutes Time (seconds) Example: CCLD-915X-25-250.000 = 3.3V, 45/55, -40/85C, 25ppm, 250 MHz Reflow 5C Crystek Part Number Guide CCLD-915 X - 25 - 250.000 #1 #2 #3 #4 #5 Cooling 1-5C/Sec Stability Indicator: #1 Crystek 9X14 SMD LVDS Osc. #2 Model 915 = 162MHz ~ 250MHz #3 Temp. Range: Blank = 0/70C, M= -20/70C, X= -40/85C #4 Stability: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places Blank (std) 50 25 100ppm 50ppm 25ppm 10 sec Max Table 1 260C Reflow Profile NOT recommended for this product Pad 1 2 3 4 5 6 Connection E/D N/C GND OUT COUT Vdd Table 2 Tri-State Function E/D pin Open "1" level 0.7V Min "0" level 0.3V Max Table 3 Specifications subject to change without notice. Output pin Active Active High Z TD-031104 Rev.B |
Price & Availability of CCLD-915
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