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G = 0.2, Level Translation, 16-Bit ADC Driver AD8275
FEATURES
Translates 10 V to +4 V Drives 16-bit SAR ADCs Small MSOP package Input overvoltage: +40 V to -35 V (VS = 5 V) Fast settling time: 450 ns to 0.001% Rail-to-rail output Wide supply operation: +3.3 V to +15 V High CMRR: 80 dB Low gain drift: 1 ppm/C Low offset drift: 2.5 V/C
+10V
PIN CONFIGURATION
REF1 1 -IN 2 +IN 3 -VS 4
8
AD8275
TOP VIEW (Not to Scale)
REF2 +VS SENSE
07546-001
7 6 5
OUT
Figure 1.
TYPICAL APPLICATION
+5V 0.1F
7
0.1F
+4.048V +2.048V +0.048V
+VS
2
50k -IN
10k SENSE OUT
APPLICATIONS
Level translator ADC driver Instrumentation amplifier building block Automated test equipment
5
33
6
IN+ IN- REF
VDD AD7685 GND
2.7nF
-10V VIN
3
50k +IN
20k 20k -VS REF2 REF1
8 1
VREF 4.096V
10F
07546-002
AD8275
4
Figure 2. Translating 10 V to 4.096 V ADC Full Scale
GENERAL DESCRIPTION
The AD8275 is a G = 0.2 difference amplifier that can be used to translate 10 V signals to a +4 V level. It solves the problem typically encountered in industrial and instrumentation applications where 10 V signals must be interfaced to a single-supply 4 V or 5 V ADC. The AD8275 interfaces the two signal levels, simplifying design. The AD8275 has fast settling time of 450 ns and low distortion, making it suitable for driving medium speed successive approximation (SAR) ADCs. Its wide input voltage range and rail-torail outputs make it an easy to use building block. Single-supply operation reduces the power consumption of the amplifier and helps to protect the ADC from overdrive conditions. Internal, matched, precision laser-trimmed resistors ensure low gain error, low gain drift of 1 ppm/C (maximum), and high common-mode rejection of 80 dB. Low offset and low offset drift, combined with its fast settling time, make the AD8275 suitable for a variety of data acquisition applications where accurate and quick capture is required. The AD8275 can be used as an analog front end, or it can follow buffers to level translate high voltages to a voltage range accepted by the ADC. In addition, the AD8275 can be configured for differential outputs if used with a differential ADC. The AD8275 is available in a space-saving, 8-lead MSOP and is specified for performance over the -40C to +85C temperature range. Table 1. Difference Amplifiers by Category
Low Distortion AD8270 AD8273 AD8274 AD8275 AMP03 High Voltage AD628 AD629 Single-Supply Current Sense AD8202 AD8203 AD8205 AD8206 AD8216
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD8275 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Pin Configuration ............................................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Maximum Power Dissipation ..................................................... 4 ESD Caution .................................................................................. 4 Pin Configuration and Function Descriptions ............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 11 Basic Connection........................................................................ 11 Power Supplies ............................................................................ 12 Reference ..................................................................................... 12 Common-Mode Input Voltage Range ..................................... 12 Input Protection ......................................................................... 12 Configurations ............................................................................ 13 Applications Information .............................................................. 14 Driving a Single-Ended ADC ................................................... 14 Differential Outputs ................................................................... 14 Increasing Input Impedance ..................................................... 15 AC Coupling ............................................................................... 15 Using the AD8275 as a Level Translator in a Data Acquisition System .......................................................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8275 SPECIFICATIONS
VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 k connected to VS/2, TA = 25C, unless otherwise noted. Specifications referred to output unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE Small Signal Bandwidth Slew Rate Settling Time to 0.01% Settling Time to 0.001% Overload Recovery Time NOISE/DISTORTION 1 THD + N Voltage Noise Spectral Noise Density GAIN Gain Error Gain Drift Gain Nonlinearity OFFSET AND CMRR Offset 2 vs. Temperature vs. Power Supply Reference Divider Accuracy Common-Mode Rejection Ratio 3 INPUT CHARACTERISTICS Input Voltage Range 4 Impedance 5 Differential Common Mode OUTPUT CHARACTERISTICS Output Swing Capacitive Load 6 Short-Circuit Current Limit POWER SUPPLY Specified Voltage Range Operating Voltage Range Supply Current Over Temperature TEMPERATURE RANGE Specified Performance
1 2
Test Conditions/Comments -3 dB 4 V step 4 V step on output, CL = 100 pF 4 V step on output, CL = 100 pF 50% overdrive f = 1 kHz, VOUT = 4 V p-p, 22 kHz band pass filter f = 0.1 Hz to 10 Hz, referred to output f = 1 kHz, referred to output VREF2 = 4.096 V, REF1 and RL connected to GND, (VIN+) - (VIN-) = -10 V to +10 V -40C to +85C VOUT = 4 V p-p, RL = 600 , 2 k, 10 k Referred to output, VS = 2.5 V, reference and input pins grounded -40C to +85C VS = 3.3 V to 5 V VCM = 10 V, referred to output
Min 10 20
A Grade Typ 15 25 350 450 300 106 1 40 0.2
Max
Min 10 20
B Grade Typ 15 25 350 450 300 106
Max
Unit MHz V/s ns ns ns dB
450 550
4
1 40 0.2
4
V p-p nV/Hz V/V % ppm/C ppm V V/C dB % dB
1 2.5 300 2.5 90
0.024 3
0.3 2.5 150 2.5 100
0.024 1 3 500 7 0.024
700
0.024 80 96 86
-12.3 VCM = VS/2 108||2 27.5||2 -VS + 0.048 100 30 5 3.3 IO = 0 mA, VS = 2.5 V, reference and input pins grounded IO = 0 mA, VS = 2.5 V, reference and input pins grounded, -40C to +85C -40 1.9 2.1
+12
-12.3 108||2 27.5||2
+12
V k||pF k||pF
VREF2 = 4.096 V, REF1 and RL connected to GND, RL = 2 k
+VS - 0.1
-VS + 0.048 100 30 5
+VS - 0.1
V pF mA V V mA mA
15 2.3 2.7
3.3 1.9 2.1
15 2.3 2.7
+85
-40
+85
C
Includes amplifier voltage and current noise, as well as noise of internal resistors. Includes input bias and offset current errors. 3 See Figure 7 for CMRR vs. temperature. 4 The input voltage range is a function of the voltage supplies, reference voltage, and ESD diodes. When operating on other supply voltages, see the Absolute Maximum Ratings section, Figure 11, and Table 5 for more information. 5 Internal resistors are trimmed to be ratio matched but have 20% absolute accuracy. 6 See Figure 25 to Figure 28 in the Typical Performance Characteristics section for more information.
Rev. 0 | Page 3 of 16
AD8275 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Output Short-Circuit Current Voltage at +IN, -IN Pins Voltage at REFx, +VS, - VS, SENSE, and OUT Pins Current into REFx, +IN, -IN, SENSE, and OUT Pins Storage Temperature Range Specified Temperature Range Thermal Resistance (JA) Package Glass Transition Temperature (TG) ESD Human Body Model Rating 18 V See derating curve (Figure 3) -VS + 40 V, +VS - 40 V -VS - 0.5 V, +VS + 0.5 V 3 mA -65C to +130C -40C to +85C 135C/W 140C 2 kV
midsupply, the total drive power is VS/2 x IOUT, some of which is dissipated in the package and some of which is dissipated in the load (VOUT x IOUT). The difference between the total drive power and the load power is the drive power dissipated in the package. PD = Quiescent Power + (Total Drive Power - Load Power)
V V PD = (VS x I S ) + S x OUT 2 RL
VOUT 2 - RL
In single-supply operation with RL referenced to -VS, the worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces JA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature on a 4-layer JEDEC standard board.
2.00 1.75 1.50 1.25 1.00 0.75 0.50
07546-003
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8275 package is limited by the associated rise in junction temperature (TJ) on the die. The plastic encapsulating the die locally reaches the junction temperature. At approximately 140C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8275. Exceeding a junction temperature of 140C for an extended period can result in changes in silicon devices, potentially causing failure. The still air thermal properties of the package and PCB (JA), the ambient temperature (TA), and the total power dissipated in the package (PD) determine the junction temperature of the die. The junction temperature is calculated as follows: TJ = TA + (PD x JA) The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming the load (RL) is referenced to
MAXIMUM POWER DISSIPATION (W)
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
0.25 0 -40
-20
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (C)
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 4 of 16
AD8275 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REF1 1 -IN 2 +IN 3 -VS 4
8
AD8275
TOP VIEW (Not to Scale)
REF2 +VS SENSE
07546-001
7 6 5
OUT
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic REF1 -IN +IN -VS SENSE OUT +VS REF2 Description Reference Pin. Sets the output voltage level (see the Reference section). Negative Input Pin. Positive Input Pin. Negative Supply Pin. Sense Output Pin. Tie this pin to the OUT pin. Output Pin (Force Output). Positive Supply Pin. Reference Pin. Sets the output voltage level (see the Reference section).
Rev. 0 | Page 5 of 16
AD8275 TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, G = 0.2, REF1 connected to GND and REF2 connected to 5 V, RL = 2 k connected to VS/2, TA = 25C, unless otherwise noted.
300 14 12 10 250 200
OFFSET VOLTAGE (V)
150 100 50 0 -50 -100 -150 -200
07546-007
HITS
8 6 4
07546-004
2 0
-250
-600
-400
-200
0
200
400
600
NORMALIZED AT 25C, REPRESENTATIVE SAMPLES -300 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
120
OFFSET VOLTAGE (V)
Figure 5. Typical Distribution of System Offset Voltage, Referred to Output
Figure 8. Offset Voltage vs. Temperature, Normalized at 25C, Referred to Output
50 40
70 60
30
GAIN ERROR (V/V)
50 40
20 10 0 -10 -20 -30
HITS
30 20 10 0 -60
07546-005
-40 GAIN ERROR NORMALIZED AT 25C -50 -45 -30 -15 0 15 30 45 60 75 TEMPERATURE (C) 90 105 120
-40
-20
0 CMRR (V/V)
20
40
60
Figure 6. Typical Distribution of CMRR, Referred to Output
60
Figure 9. Gain Error vs. Temperature, Normalized at 25C
5
40
QUIESCENT CURRENT (mA)
4
20
CMRR (V/V)
0
3
5V
-20
2
3.3V
-40
07546-006
07546-009
-60 -40
-20
0
20
40
60
80
100
120
1 -50
-25
0
25
50
75
100
125
TEMPERATURE (C)
TEMPERATURE (C)
Figure 7. CMRR vs. Temperature, Normalized at 25C
Figure 10. Quiescent Current vs. Temperature
Rev. 0 | Page 6 of 16
07546-008
AD8275
35 30
120 100 80 60 40 20 0 -20 100
INPUT COMMON-MODE VOLTAGE (V)
20 15 10 5 0 -5 -10 -15 -20 -25 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
07546-010
POWER SUPPLY REJECTION (dB)
25
1k
10k FREQUENCY (Hz)
100k
1M
OUTPUT VOLTAGE (V)
Figure 11. Input Common-Mode Voltage vs. Output Voltage, No Load
0
Figure 14. Power Supply Rejection vs. Frequency, Referred to Output
6
MAXIMUM OUTPUT VOLTAGE (V p-p)
-5 -10 -15 -20 -25 -30
07546-011
5
4
GAIN (dB)
3
2
-40 100
1k
10k
100k
1M
10M
100M
0 100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12. Gain vs. Frequency
100
20 15
Figure 15. Maximum Output Voltage vs. Frequency
COMMON-MODE REJECTION (dB)
90
GAIN NONLINEARITY (ppm)
10 5 0 -5 -10
07546-015
80
70
60
50
07546-012
-15 -20
40 100
1k
10k
100k
1M
10M
0
1
2 OUTPUT VOLTAGE (V)
3
4
FREQUENCY (Hz)
Figure 13. Common-Mode Rejection vs. Frequency, Referred to Input
Figure 16. Gain Nonlinearity, RL = 600 , 2 k, 10 k
Rev. 0 | Page 7 of 16
07546-014
-35
1
07546-013
AD8275
60 50 +VS +VS - 0.4 5V SOURCE 3.3V SOURCE
-40C +125C +85C +25C
30 20
OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY RAILS)
40
+VS - 0.8 +VS - 1.2 +VS - 1.6 +VS - 2.0 -VS + 2.0 -VS + 1.6 -VS + 1.2 -VS + 0.8 -VS + 0.4 -VS 0 2 4
CURRENT (mA)
10 0 -10 -20 -30 -40 -50 -60 -70 -50 -25 0 25 50 75 100 125 3.3V SINK 5V SINK
07546-016
-40C
TEMPERATURE (C)
6 8 10 OUTPUT CURRENT (mA)
12
14
Figure 17. Short-Circuit Current vs. Temperature, VS = 3.3 V, 5 V
+VS +VS - 0.2
Figure 20. Output Voltage Swing vs. Output Current, VS = 5 V
1k
-40C +25C +85C +125C
OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY RAILS)
+VS - 0.4 +VS - 0.6 +VS - 0.8 +VS - 1.0 -VS + 1.0 -VS + 0.8 -VS + 0.6 -VS + 0.4 -VS + 0.2 -VS
VOLTAGE NOISE DENSITY (nV/Hz)
100
+125C +85C
07546-017
-40C
10 1 10 100 1k 10k FREQUENCY (Hz)
100
1k RLOAD ()
10k
100k
100k
Figure 18. Output Voltage Swing vs. RLOAD, VS = 5 V
+VS +VS - 0.4
Figure 21. Voltage Noise Density vs. Frequency, Referred to Output
-40C +25C +125C +85C
OUTPUT VOLTAGE SWING (V) (REFERRED TO SUPPLY RAILS)
+VS - 0.8 +VS - 1.2 +VS - 1.6 +VS - 2.0 -VS + 2.0 -VS + 1.6 -VS + 1.2 -VS + 0.8 -VS + 0.4 -VS 0 2 4
07546-018
-40C
6 8 10 OUTPUT CURRENT (mA)
12
14
TIME (1s/DIV)
Figure 19. Output Voltage Swing vs. Output Current, VS = 3.3 V
Figure 22. 0.1 Hz to 10 Hz Voltage Noise, Referred to Output
Rev. 0 | Page 8 of 16
07546-020
+25C
+85C
+125C
VOLTAGE NOISE (1V/DIV)
07546-019
+25C
07546-119
+25C
+85C +125C
AD8275
40 35 30
60
50
SLEW RATE (V/s)
25 20 15 10
07546-021
OVERSHOOT (%)
+SR -SR
40 3.3V 30 5V 20
0 -40
-20
0
20
40
60
80
100
120
0
0
20
40
60
80
100
120
140
160
TEMPERATURE (C)
CAPACITANCE (pF)
Figure 23. Slew Rate vs. Temperature
Figure 26. Small Signal Overshoot vs. Capacitive Load, No Resistive Load
60
CLOAD = 47pF
2k NO LOAD
50
600
OVERSHOOT (%)
40 3.3V 5V 20
20mV/DIV
30
10k
07546-022
10
07546-025
0
1s/DIV
0
20
40
60
80
100
120
140
160
CAPACITANCE (pF)
Figure 24. Small Signal Step Response for Various Resistive Loads (Step Responses Staggered for Clarity)
NO RESISTIVE LOAD 20pF 100pF
Figure 27. Small Signal Overshoot vs. Capacitive Load, 600 in Parallel with Capacitive Load
60
50
NO CAP
OVERSHOOT (%)
40 3.3V 30 5V 20
20mV/DIV
47pF
07546-023
10
07546-026
0
1s/DIV
0
20
40
60
80
100
120
140
160
CAPACITANCE (pF)
Figure 25. Small Signal Pulse Response for Various Capacitive Loads (Step Responses Staggered for Clarity)
Figure 28. Small Signal Overshoot vs. Capacitive Load, 2 k in Parallel with Capacitive Load
Rev. 0 | Page 9 of 16
07546-024
5
10
AD8275
1.0 VOUT = 4V p-p
0.1
10V/DIV
THD + N (%)
0.01 RL = 600 0.001
10mV/DIV
RL = 2k
07546-029
07546-027
2s/DIV
RL = 10k 0.0001 10 100 1k FREQUENCY (Hz) 10k
100k
Figure 29. Large Signal Pulse Response and Settling Time, RL = 2 k
Figure 30. THD + N vs. Frequency, VOUT = 4 V p-p
Rev. 0 | Page 10 of 16
AD8275 THEORY OF OPERATION
The AD8275 level translates 10 V signals at its inputs to 4 V at its output. It does this by attenuating the input signal by 5. A subtractor network performs the attenuation, the level shifting, and the differential-to-single-ended conversion. One benefit of the subtractor topology is that it can accept input signals beyond its supply voltage. The subtractor is composed of tightly matched resistors. By integrating the resistors and trimming the resistor ratios, the AD8275 achieves 80 dB CMRR and 0.024% gain error.
+VS -IN INPUT ESD 50k 10k +VS -VS 7k 7k 2.5V -VS -VS -VS -VS 20k -VS +VS 50k -VS
07546-030
The AD8275 employs a balanced, high gain, linear output stage that adaptively generates current as required, eliminating the dynamic errors found in other amplifiers. This is useful when driving SAR ADCs, which can deliver kickback current into the output of the amplifier. The result is a design that achieves low distortion, consistent bandwidth, and high slew rate.
BASIC CONNECTION
The basic configurations for the AD8275 are shown in Figure 33 and Figure 34. In Figure 33, REF1 and REF2 are tied together. A voltage, VREF, applied to the tied REF1 and REF2 pins, sets the output voltage level to VREF. For example, in Figure 33, if VREF = 2 V and the inputs are tied to ground, the output remains at 2 V.
+5V 0.1F
SENSE -VS +VS +VS OUT
+VS +VS REF2 50k -IN
7
+VS VINN 2 10k SENSE OUT
6 5
VOUT VREF
+IN
INPUT ESD
20k
REF1
VINP 3
50k +IN
20k 20k -VS
4
REF2 REF1
8 1
Figure 31. AD8275 Simplified Schematic
To achieve a wider input voltage range, the AD8275 uses an internal 2.5 V voltage bias tied to -VS and two 7 k resistors, as shown in Figure 31. The resistors help to set the common mode of the internal amplifier. The benefit of this circuit is that it extends the input range without causing crossover distortion typical of amplifiers that have rail-to-rail complementary transistor inputs. The input range of the internal op amp is +VS - 0.9 V to -VS + 1.35 V.
600
AD8275
VOUT =
(VINP) - (VINN) 5
+ VREF
Figure 33. Basic Configuration 1: Shared Reference
In contrast, Figure 34 shows REF1 tied to ground and REF2 tied to VREF. In this example, the two 20 k resistors serve as a resistor divider, and VREF is divided by 2. For example, if both inputs of the AD8275 are grounded and VREF = 5 V, the output is 2.5 V.
+5V 0.1F
400
200
OFFSET (V)
7
+VS
0
VINN 2
50k -IN
10k SENSE OUT
5
-200
6
VOUT VREF
-400
07546-132
VINP 3
50k +IN
20k 20k -VS
4
-600 -10
REF2 REF1
8 1
-8
-6
-4
-2
0
2
4
6
8
10
COMMON-MODE VOLTAGE (V)
Figure 32. AD8275 Does Not Have Crossover Distortion Typical of Rail-to-Rail Input Amplifiers
VOUT =
AD8275
(VINP) - (VINN) 5
+
VREF + 0V 2
Figure 34. Basic Configuration 2: Split Reference
Rev. 0 | Page 11 of 16
07546-032
07546-031
AD8275
POWER SUPPLIES
Use a stable dc voltage to power the AD8275. Noise on the supply pins can adversely affect performance. Place a bypass capacitor of 0.1 F between each supply pin and ground, as close to each pin as possible. A tantalum capacitor of 10 F should also be used between each supply and ground. It can be farther away from the AD8275 and typically can be shared by other precision integrated circuits.
COMMON-MODE INPUT VOLTAGE RANGE
The common-mode voltage range is a function of the input voltage range of the internal op amp, the supply voltage, and the reference voltage. Equation 1 expresses the maximum positive common-mode voltage range. VCM_POS 13.14(+VS) - 7.14(-VS) - 5((REF1 + REF2)/2) - 29.69 (1) Equation 2 expresses the minimum common-mode voltage range. VCM_NEG 6(-VS) - 5((REF1 + REF2)/2) - 0.11 (2) The voltage range of the internal op amp varies depending on temperature. The equations reflect a typical input voltage range of +VS - 0.9 V and -VS + 1.35 V over temperature. Table 5 lists expected common-mode ranges for typical configurations.
Table 5. Expected Common-Mode Voltage Range for Typical Configurations
+VS (V)1 5 5 5 3.3 3.3 5 5 5 5 5 5 5
1
REFERENCE
The reference terminals are used to provide a bias level for the output. For example, in a single-supply 5 V operation, the reference terminals can be set so that the output is biased at 2.5 V. This ensures that the output can swing positive or negative around a 2.5 V level. Figure 33 and Figure 34 illustrate two different ways to set the reference voltage. See the Basic Connection section for the differences between the two settings. The allowable reference voltage range is a function of the common-mode input and supply voltages. The REF1 and REF2 pins should not exceed either +VS or -VS by more than 0.5 V. The REFx terminals should be driven by low source impedance because parasitic resistance in series with REF1 and REF2 can adversely affect CMRR and gain accuracy.
CORRECT
+VS
7
INCORRECT
+VS
7
2
50k -IN
10k SENSE
5
2
50 50k -IN
NSE 10k SENSE
5
OUT
6
O OUT VREF
6
VREF
VREF1 (V) 5 2.5 4.096 3.3 2.5 5 4.096 3 2.5 2.048 1.25 0
VREF2 (V) 0 0 0 0 0 5 4.096 3 2.5 2.048 1.25 0
VCM+ (V) 23.5 29.8 25.8 5.4 7.4 11.0 15.5 21.0 23.5 25.8 29.8 36.0
VCM- (V) -12.6 -6.4 -10.4 -8.4 -6.4 -25.1 -20.6 -15.1 -12.6 -10.4 -6.4 -0.1
3
50k +IN
20k REF2 20k REF1 -VS
4
8 1
3
50k 0k +IN
20k REF2 0k R 20k REF1 -VS
4
-VS = 0 V.
8 1
INPUT PROTECTION
The inputs of the AD8275, +IN and -IN, are protected by ESD diodes that clamp 40 V above -VS and 40 V below +VS. When operating on a single +5 V supply, the ESD diode conducts at input voltages less than -35 V and greater than +40 V.
AD8275
AD8275
+VS
7
+VS
7
2
50k -IN
10k SENSE
5
2
50 50k -IN
NSE 10k SENSE
5
OUT
6
OUT VREF
6
VREF
3
50k +IN
20k REF2 20k REF1 -VS
4
8 1
3
50k 0k +IN
20k REF2 0k R 20k REF1 -VS
4
8 1
07546-033
If the input voltage is expected to exceed the maximum ratings of the AD8275, use external transorbs. Adding series resistors to the inputs of the AD8275 is not recommended because the internal resistor ratios are matched to provide optimal CMRR and gain accuracy. Adding external series resistors to the input degrades the performance of the AD8275. All other pins are protected by ESD diodes that clamp 0.5 V beyond either supply rail. For example, the voltage range of the REF1 and REF2 pins on a 5 V supply is -0.5 V to +5.5 V.
AD8275
AD8275
Figure 35. REF1 and REF2 Pin Guidelines
Rev. 0 | Page 12 of 16
AD8275
CONFIGURATIONS
Figure 36 and Figure 37, along with Table 6 and Table 7, provide examples of the possible input and output ranges for various supplies and reference voltages.
+5V 0.1F LINEAR VIN RANGE HI VINN 2 MID
7
Note that Table 6 and Table 7 list the typical voltage range of the AD8275; these values do not reflect variation over process or temperature.
+5V 0.1F LINEAR VIN RANGE HI VINN 2 MID
7
USEFUL VOUT HI +SWING -SWING +VS 50k -IN 10k
USEFUL VOUT HI +SWING -SWING
+VS 50k -IN 10k SENSE OUT
6 5
LO
5
LO
SENSE OUT
6
VOUT VREF
VOUT VREF
LO
VINP 3
50k +IN
20k 20k -VS REF2 REF1
8 1
LO
VINP 3
50k +IN
20k 20k -VS
4
REF2 REF1
8 1
07546-136
4
Figure 36. Split Reference
Figure 37. Shared Reference
Table 6. Input and Output Relationships for Split Reference Configuration in Figure 36
VOUT for VIN = 0 V 2.5 V Linear Differential VIN Range High: +12 V Mid: 0 V Low: -12.3 V High: +18.3 V Mid: 0 V Low: -6 V High: +14.3 V Mid: 0 V Low: -10 V High: +8 V Mid: 0 V Low: -8 V High: +10 V Mid: 0 V Low: -6 V Useful VOUT Ranges High: +4.95 V Swing: +2.45 V, -2.455 V Low: +0.045 V High: +4.95 V Swing: +3.7 V, -1.205 V Low: +0.045 V High: +4.95 V Swing: +2.902 V, -2.003 V Low: +0.045 V High: +3.24 V Swing: +1.59 V, -1.605 V Low: +0.045 V High: +3.24 V Swing: +1.99 V, -1.205 V Low: +0.045 V
Table 7. Input and Output Relationships for Shared Reference Configuration in Figure 37
VOUT for VIN = 0 V 5V Linear Differential VIN Range High: -0.1 V Mid: 0 V Low: -24.7 V High: +4.4 V Mid: 0 V Low: -20.2 V High: +9.5 V Mid: 0 V Low: -14.8 V High: +12 V Mid: 0 V Low: -12.3 V High: +14.3 V Mid: 0 V Low: -10 V +18.3 V to -6 V Useful VOUT Ranges High: +4.98 V Swing: -4.94 V Low: +0.06 V High: +4.98 V Swing: +0.884 V to -4.03 V Low: +0.06 V High: +4.95 V Swing: +1.9 V, -2.955 V Low: +0.045 V High: +4.95 V Swing: +2.45 V, -2.455 V Low: +0.045 V High: +4.95 V Swing: +2.902 V, -2.003 V Low: +0.045 V High: +4.95 V Swing: +3.7 V, -1.205 V Low: +0.045 V High: 4.95 V Swing: 4.95 V Low: 0.045 V
+VS1 5V
VREF 5V
+VS1 5V
VREF 5V
5V
4.096 V
4.096 V
5V
2.5 V
1.25 V
5V
3V
3V
5V
4.096 V
2.048 V
5V
2.5 V
2.5 V
3.3 V
3.3 V
1.65 V
5V
2.048 V
2.048 V
3.3 V
2.5 V
1.25 V
5V
1.25 V
1.25 V
1
-VS = 0 V.
0V
0V
0V
24.5 V to 0.2 V
1
-VS = 0 V.
Rev. 0 | Page 13 of 16
07546-137
AD8275
AD8275
AD8275 APPLICATIONS INFORMATION
DRIVING A SINGLE-ENDED ADC
The AD8275 provides the common-mode rejection that SAR ADCs often lack. In addition, it enables designers to use costeffective, precision, 16-bit ADCs such as the AD7685, yet still condition 10 V signals. One important factor in selecting an ADC driver is its ability to settle within the acquisition window of the ADC. The AD8275 is able to drive medium speed SAR ADCs. In Figure 38, the 2.7 nF capacitor serves to store and deliver necessary charge to the switched capacitor input of the ADC. The 33 series resistor reduces the burden of the 2.7 nF load from the amplifier and isolates it from the kickback current injected from the switched capacitor input of the AD7685. The output impedance of the amplifier can affect the THD of the ADC. In this case, the combined impedance of the 33 resistor and the output impedance of the AD8275 provides extremely low THD of -112 dB. Figure 39 shows the ac response of the AD8275 driving the AD7685.
+5V 0.1F
7
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170
ADC FULL SCALE (dB)
0
1
2
3
4 5 6 FREQUENCY (kHz)
7
8
9
10
Figure 39. FFT of AD8275 Directly Driving the AD7685 Using the 5 V Reference of the Evaluation Board (Input = 20 V p-p, 1 kHz, THD = -112 dB)
The AD8275 can condition signals for higher resolution ADCs such as 18-bit SAR converters, provided that a narrower bandwidth is sampled to limit noise.
0.1F
DIFFERENTIAL OUTPUTS
In certain applications, it is necessary to create a differential signal. For example, high resolution ADCs often require a differential input. In other cases, transmission over a long distance can require differential signals for better immunity to interference.
+VS
2
50k -IN
10k SENSE OUT
5
33
6
IN+ IN- REF
VDD AD7685 GND
2.7nF
VIN
3
50k +IN
20k 20k -VS
4
REF2 REF1
8 1
Figure 38. Driving a Single-Ended ADC
07546-034
AD8275
VREF (ADR444, ADR445)
10F
Figure 40 shows how to configure the AD8275 to output a differential signal. The AD8655 op amp is used in an inverting topology to create a differential voltage. VREF sets the output midpoint. Errors from the op amp are common to both outputs and are thus common mode. Likewise, errors from using mismatched resistors cause a common-mode dc offset error. Such errors are rejected in differential signal processing by differential input ADCs or by instrumentation amplifiers. When using this circuit to drive a differential ADC, VREF can be set using a resistor divider from the ADC reference to make the output ratiometric with the ADC.
+5V 0.1F
7
+VS
2
50k -IN
10k SENSE OUT
5
+VOUT
6
+4.5V +2.5V +0.5V
2k +10V -10V
3
AD8655 VREF = 2.5V
50k +IN
20k 20k -VS
4
REF2 REF1
8 1
8.2F 2k 0.1F
+5V +4.5V +2.5V -VOUT +0.5V
Figure 40. AD8275 Configured for Differential Output (for Driving a Differential ADC)
Rev. 0 | Page 14 of 16
07546-035
AD8275
07546-139
AD8275
INCREASING INPUT IMPEDANCE
In applications where a high input impedance is needed, low input bias current op amps can be used to buffer the AD8275. In Figure 41, an AD8620 is used to provide high input impedance. Input bias current is limited to 10 pA.
+5V +13V
8
USING THE AD8275 AS A LEVEL TRANSLATOR IN A DATA ACQUISITION SYSTEM
Signal size varies dramatically in some data acquisition applications. Instrumentation amplifiers, such as the AD8253, AD8228, or AD8221, are often used at the inputs to provide CMRR and high input impedance. However, the instrumentation amplifiers output 10 V signals and the ADC full scale is 5 V or 4.096 V. In Figure 43, the AD8275 serves as a level translator between the in-amp and the ADC. The AD8275, along with the AD8228 and the AD8253, have very low gain drift because all gain setting resistors are internal and laser-trimmed.
+5V 0.1F
7
0.1F
INVERTING INPUT
3 2
7
0.1F AD8620 1/2
1 2
+VS 50k -IN OUT 10k SENSE
5
6
VOUT VREF
0.1F
6 5
AD8620 2/2
4
7
3
50k +IN
20k 20k -VS
REF2 REF1
8 1
+VS
2
50k -IN
10k SENSE OUT
NONINVERTING INPUT
5
0.1F
AD8275
33
6
07546-036
-13V
4
+15V 0.1F
50k +IN 20k 20k -VS
+IN
VCC ADC
2.7nF
3 8 1
Figure 41. Adding Op Amp Buffers for High Input Impedance
IN-AMP
-IN REF GND
AC COUPLING
An integrator can be tied to the AD8275 in feedback to create a high-pass filter as shown in Figure 42. This circuit can be used to reject dc voltages and offsets. At low frequencies, the impedance of the capacitor, C, is high. Thus, the gain of the integrator is high. DC voltage at the output of the AD8275 is inverted and gained by the integrator. The inverted signal is injected back into the REFx pins, nulling the output. In contrast, at high frequencies, the integrator has low gain because the impedance of C is low. Voltage changes at high frequencies are inverted but at a low gain. The signal is injected into the REFx pins but it is not enough to null the output. High frequency signals are, therefore, allowed to pass. When a signal exceeds fHIGH-PASS, the AD8275 outputs the conditioned input signal.
+5V 0.1F
7
REF2 REF1
VREF 10F
07546-143
-15V
0.1F
AD8275
4
Figure 43. Level Translation in a Data Acquisition System
+VS
2
50k -IN
10k SENSE OUT
VOUT
5
fHIGH-PASS =
1 2RC VOUT R
6
3
50k +IN
20k 20k -VS
4
REF2 REF1
8 1
C
AD8275
OP AMP
VREF
07546-037
0.1F
+5V
Figure 42. AC-Coupled Level Translator
Rev. 0 | Page 15 of 16
AD8275 OUTLINE DIMENSIONS
3.20 3.00 2.80 5.15 4.90 4.65
3.20 3.00 2.80 PIN 1
8
5
1
4
0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40
0.23 0.08
COPLANARITY 0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 44. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8275ARMZ 1 AD8275ARMZ-R71 AD8275ARMZ-RL1 AD8275BRMZ1 AD8275BRMZ-R71 AD8275BRMZ-RL1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead MSOP 8-Lead MSOP, Tape and Reel 8-Lead MSOP, 13" Tape and Reel 8-Lead MSOP 8-Lead MSOP, Tape and Reel 8-Lead MSOP, 13" Tape and Reel
Package Option RM-8 RM-8 RM-8 RM-8 RM-8 RM-8
Branding Y13 Y13 Y13 Y1V Y1V Y1V
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07546-0-10/08(0)
Rev. 0 | Page 16 of 16

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