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STN3NF06L N-channel 60 V, 0.07 4 A, SOT-223 , STripFETTM II Power MOSFET Features Type STN3NF06L VDSS (@Tjmax) 60 V RDS(on) max < 0.1 ID 4A 2 Exceptional dv/dt capability Avalanche rugged technology 100% avalanche tested Low threshold drive 1 SOT-223 2 3 Application Switching applications Figure 1. Internal schematic diagram Description This Power MOSFET is the latest development of STMicroelectronics unique "single feature size" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. Table 1. Device summary Marking 3NF06L Package SOT-223 Packaging Tape and reel Order code STN3NF06L June 2008 Rev 8 1/12 www.st.com 12 Contents STN3NF06L Contents 1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 4 5 Test circuit ................................................ 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 STN3NF06L Electrical ratings 1 Electrical ratings Table 2. Symbol VDS VGS ID(1) ID IDM (2) Absolute maximum ratings Parameter Drain-source voltage (VGS = 0) Gate-source voltage Drain current (continuous) at TC = 25 C Drain current (continuous) at TC=100 C Drain current (pulsed) Total dissipation at TC = 25 C Derating factor Value 60 16 4 2.9 16 3.3 0.026 10 200 -55 to 150 Unit V V A A A W W/C V/ns mJ C PTOT dv/dt (3) EAS (4) Peak diode recovery voltage slope Single pulse avalanche energy Operating junction temperature Storage temperature TJ Tstg 1. Current limited by the package 2. Pulse width limited by safe operating area 3. 4. ISD 3 A, di/dt 150 A/s, VDD V(BR)DSS, TJ TJMAX Starting Tj = 25 C, ID = 4 A, VDD = 30 V Table 3. Symbol Rthj-pcb Rthj-pcb Tl(3) Thermal data Parameter Thermal resistance junction-PCB(1) max Thermal resistance junction-PCB(2) max Value 38 100 260 Unit C/W C/W C Maximum lead temperature for soldering purpose typ 1. When Mounted on FR-4 board with 1 inch2 pad, 2 oz. of Cu. and t <10 sec. 2. When mounted on minimum recommended footprint 3. for 10 sec. 1.6 mm from case 3/12 Electrical characteristics STN3NF06L 2 Electrical characteristics (TCASE = 25 C unless otherwise specified) Table 4. Symbol V(BR)DSS IDSS IGSS VGS(th) RDS(on) On/off states Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Static drain-source on resistance Test conditions ID = 250 A, VGS= 0 VDS = Max rating, VDS = Max rating @125 C VGS = 16 V VDS= VGS, ID = 250 A VGS= 10 V, ID= 1.5 A VGS= 5 V, ID= 1.5 A 1 0.07 0.085 Min. 60 1 10 100 Typ. Max. Unit V A A nA V 2.8 0.10 0.12 Table 5. Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd Dynamic Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS= 15 V, ID=1.5 A Min. Typ. 3 340 63 30 7 1.5 2.8 9 Max. Unit S pF pF pF nC nC nC VDS =25 V, f=1 MHz, VGS=0 VDD=48 V, ID = 3 A VGS =5 V (see Figure 15) 1. Pulsed: pulse duration=300s, duty cycle 1.5% Table 6. Symbol td(on) tr td(off) tf Switching times Parameter Turn-on delay time rise time Test conditions VDD=30 V, ID=1.5 A, RG=4.7 , VGS=5 V (see Figure 14) VDD=30 V, ID=1.5 A, RG=4.7 , VGS=5 V (see Figure 14) Min. Typ. 9 25 20 10 Max. Unit ns ns Turn-off delay time fall time ns ns 4/12 STN3NF06L Electrical characteristics Table 7. Symbol ISD ISDM (1) Source drain diode Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD= 4 A, VGS=0 ISD= 4 A, di/dt = 100 A/s, VDD=25 V, Tj=150 C (see Figure 16) 50 88 3.5 Test conditions Min. Typ. Max 4 16 1.5 Unit A A V ns nC A VSD(2) trr Qrr IRRM 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration=300s, duty cycle 1.5% 5/12 Electrical characteristics STN3NF06L 2.1 Figure 2. Electrical characteristics (curves) Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Transconductance Figure 7. Static drain-source on resistance 6/12 STN3NF06L Figure 8. Gate charge vs. gate-source voltage Figure 9. Electrical characteristics Capacitance variations Figure 10. Normalized gate threshold voltage vs. temperature Figure 11. Normalized on resistance vs. temperature Figure 12. Source-drain diode forward characteristics Figure 13. Normalized breakdown voltage vs. temperature 7/12 Test circuit STN3NF06L 3 Test circuit Figure 15. Gate charge test circuit Figure 14. Switching times test circuit for resistive load Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test switching and diode recovery times circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform 8/12 STN3NF06L Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STN3NF06L SOT-223 MECHANICAL DATA mm MIN. a b c d e1 e4 f g l1 l2 L 2.9 0.67 6.7 3.5 6.3 3 0.7 7 3.5 6.5 2.27 4.57 0.2 0.63 1.5 TYP. 2.3 4.6 0.4 0.65 1.6 MAX. 2.33 4.63 0.6 0.67 1.7 0.32 3.1 0.73 7.3 3.7 6.7 114.2 26.4 263.8 137.8 248 118.1 27.6 275.6 137.8 255.9 MIN. 89.4 179.9 7.9 24.8 59.1 mils TYP. 90.6 181.1 15.7 25.6 63 MAX. 91.7 182.3 23.6 26.4 66.9 12.6 122.1 28.7 287.4 145.7 263.8 DIM. L l2 e1 a b f d c e4 C l1 B C E g P008B 10/12 STN3NF06L Revision history 5 Revision history Table 8. Date 21-Jun-2004 04-Oct-2006 01-Feb-2007 12-Jun-2008 Document revision history Revision 5 6 7 8 Complete version. New template, no content change. Typo mistake on Table 2. Corrected marking on Table 1 Changes 11/12 STN3NF06L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. 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