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STA2062A
CartesioTM family infotainment application processor with embedded GPS
Data Brief
Features

High performance ARM926 MCU (up to 333 MHz) MCU memory organization - Cache: 16 Kbyte instruction, 16 Kbyte data - 8 Kbyte instruction TCM (tightly coupled memory) - 8 Kbyte data TCM - 32 Kbyte embedded ROM for boot - Two banks of 64 Kbyte embedded SRAM - 512 Byte embedded SRAM for back-up - 4 Gbyte total linear address space - Memory extension through: Flexible static memory controller-FSMC (NOR/NAND Flash, CF/CF+, ROM, SRAM support) Mobile DDR/SDRAM controller: 16 bit data @166 MHz, 2 Chip Select, 512 Kbit each Interrupt - 64-channel interrupt controller (VIC) - 16-vectorized interrupts with 16 programmable priority level DMA - Two 8-channel double port system DMA controllers - 32 DMA request for each controller - Two external DMA requests are supported 32-channel high performance GPS correlation embedded subsystem Eight 32-bit free running timers/counters Four 16-bit extended function timer (EFT) with input capture/output compare and PWM Real-time clock (RTC) Pulse width light modulator (PWL) 32-bit watchdog timer Four autobaud UART with 64X8 transmit and 64x12 receive FIFO with DMA and hardware flow control One IrDA(SIR/MIR/FIR) interface Three I2C multi-master/slave interfaces Two synchronous serial port (SSP) with 32x32 separate transmit and receive FIFO with
LFBGA361 (16x16x1.4mm)

Motorola-SPI, National-MICROWIRE and Texas- SSI support modes Four multichannel serial ports (MSP) with 32x8 separate transmit and receive FIFO Color LCD controller for STN,TFT or HR-TFT panels USB 2.0 OTG high speed dual role controller (ULPI interface) USB full speed dual role controller with integrated 1.1 physical layer transceiver Two secure-digital multimedia memory card interface (SD/SDIO/MMC) up to 8 bit data SPDIF input interface C3 hardware Reed-Solomon decoder Hardware sample rate converter (SaRaC) Two controller area network (CAN) Four 32-bit GPIO ports JTAG based in-circuit emulator (ICE) with embedded medium trace module Typical working condition: Vdd: 1.2 V 10%, VIO: 1.8 V Overdrive: Vdd: 1.4 V 5%, VIO: 1.8 V 10%, 2.5 V 10% Bus frequency: 166 MHz (overdrive) Bus/DDR frequency: 166 MHz HCMOS 0.90 m process Package: - LFBGA16x16x1.4 mm (19x19 balls) - 0.8 mm ball pitch, (0.4 mm ball) - Full array Ambient temperature range: -40 / +85 C Device summary
Package LFBGA361 Packing Tray
Table 1.
Order code STA2062A
April 2008
Rev 1
1/5
www.st.com 5
For further information contact your local STMicroelectronics sales office.
1
MCU APB
APB I/F
SPDIF
APB I/F
MCFBCLK
UART(0,3)
WDT
APB I/F
APB I/F
APB I/F
SD/SDIO/MMC(0,1)
uC2 APB
MXTAL
MSPSCKx MSPRXDx
SUPPLY
VDD12 VDD33 VDDPLL
GPSCLK
2/5
DACK0 DACK1
ETM TEST PORT (JTAG)
Description
Figure 1.
DREQ0 DREQ1
DMA 1 DMA 0 M1 S M0 LCDC Interface ULPI Interface
JTAG 16 KB I / 16KB DCACHE
USB PHY
M0 S M1
ADDRESS
CTRL
FSMC LCD CTRL VIC
(8K x 32)
8K ITCM / 8K DTCM ARM926EJ
S USB OTG HS USB FS S S eROM S
Description
PORT FSMC
DATA
IM
DM
S
S
M
ADDRESS
ARM AHB Instruction ARM AHB Data DMA 0 M0 S
(32K x 32)
CTRL
S LCD AHB DMA 0/1 M1 DMA1 M0 BACKUP S AHB / APB Audio & Automotive Bridge S
APB I/F
eSRAM
Block diagram
PORT SDMC
DATA
SDMC
PLL1
S AHB / APB Core Peripheral Bridge S
APB I/F
S PLL2 SRC
MXTAL
RAM
(128 x 32)
AHB / APB DMA Bridge PWL
APB I/F
SXTAL PWLOUT
GPIO(0,3)
AHB / APB GPS Bridge
BACKUP
APB I/F
FIRRXD
IrDA
CANTxx
RTT
APB I/F
CANRxx
ARM HPGPS
APB I/F
FIRTXD
(FIR/MIR/SIR)
APB I/F
CAN(0,1)
RTC
ECLK0-3
APB I/F
I2CSDAx
APB I/F
I2CSCLx APB I/F
I2C(0,1,2) PMU
OCMPxA/OCMPxB SPDIFIN ICAPxA/ICAPxB
ARM7TMIS
Memory
EFT(0,3)
MCCMD MCCMDDIR MCCLK
UTXDx URTSxn UDTR0n
WDT ,EFT EIC
X RAM
(8K x 16)
Y RAM
(12K x 16)
C3
Emerald DSP
P RAM
(8K x 32)
MCDIR0 MCDIR2 MCDIR31 MCDIR74 APB I/F
URXD0 UCTSxn UDCD0n UDSR0n URI0n
MTU(0,1)
APB I/F
MCDAT[7:0]
CHITF
APB I/F
SSPTXDx
UUID Support APB
APB I/F
BD
CLK2 CLK2
SSPTXDx
32-Channels GPS Correlator
APB I/F
APB I/F
SSP(0,1)
Acquisition Memory
SaRaC
CLK16
SSPCLKx SSPFRMx
MSPTXDx CORE IOs PLL
HPGPS Interface
MSPTFSx MSPTCKx MSPRCKx
APB I/F
MSP(0,1,2,3)
The STA2062A is an highly integrated SoC application processor combining host capability with embedded GPS.
Figure 1: Block diagram gives an overview of the complete processor, showing how the ARM926 microcontroller and its peripherals are interfaced.
STA2062A targets vehicles and personal mobile navigation (PND), telematics, advance audio and connectivity systems.
STA2062A
MSPRFSx
STA2062A
Package information
2
Package information
In order to meet environmental requirements, ST offers this device in ECOPACK(R) packages. This package has a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 2. LFBGA361 (16x16x1.4mm) mechanical data & package dimensions
mm DIM. MIN. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 0.350 0.400 0.210 0.985 0.200 0.800 TYP. MAX. 1.400 0.0082 0.0387 0.0079 0.0315 MIN. TYP. MAX. 0.0551 inch
OUTLINE AND MECHANICAL DATA
0.450 0.0138 0.0157 0.0177
15.850 16.000 16.150 0.6240 0.6299 0.6358 14.400 0.5669
15.850 16.000 16.150 0.6240 0.6299 0.6358 14.400 0.800 0.800 0.100 0.150 0.080 0.5669 0.0315 0.0315 0.0039 0.0059 0.0031
Body: 16 x 16 x 1.4mm
LFBGA361 Low profile Fine Pitch Ball Grid Array
8033008 B
3/5
Revision history
STA2062A
3
Revision history
Table 2.
Date 16-Apr-2008
Document revision history
Revision 1 Initial release. Changes
4/5
STA2062A
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5/5

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