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Datasheet File OCR Text:

SABRE-LL-I
Combo motor driver
Preliminary Data
Features

Configurable device 4 full bridges to generate - Up 2 DC motor drivers and 1 stepper motor driver or - 4 DC motor drivers
Bridges (1 & 2) additional configurations are - Super DC - 2 half bridges - 1 super half bridge - 2 switches - 1 super switch Bridges (3 & 4) additional configurations are: - Same as bridges 1&2, listed above - 2 buck regulators (bridge 3) - 1 super buck regulator - Battery charger (bridge 4) One variable voltage buck switching regulator One switching regulator controller One linear regulator Bidirectional serial interface Programmable watchdog function Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin Thermal shutdown protection with thermal warning capability Very low power dissipation in shut-down mode (~35 mW) Device summary
Part number SABRE-LL-I
TQFP64 exposed pad
Aux features - Operational amplifiers - Comparators - Pass switches - Multi-channels 9 bit ADC - GPIOs
Description
S.A.B.ReTM (structured architecture of bridges and regulators) is a new concept of IC in the motion & power supply field. ST aim is to follow the S.A.B.Re specification and to offer to the customer an IC with a wide number of features, that can be configured and customized: motor drivers, regulators, high precision A/D converter, operational amplifiers and voltage comparators. The start up configuration can be defined by the GPIOs and then through the serial interface; a customization can be done through a metal layer in order to set more complex functions.

Table 1.
Package TQFP64
Packing Tray
November 2007
Rev 1
1/141
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
SABRE-LL-I
Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2 3
S.A.B.Re's main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Global specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 Absolute maximum rating specifications . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 4.4 4.5 4.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSupplyInt regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VSupplyInt specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 V3v3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 5.2 5.3 5.4 5.5 5.6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 nRESET specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TSD specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 6.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 7.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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8
Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.1 8.2 8.3 8.4 8.5 8.6 8.7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Sub-configurations for slave, master or single device modes . . . . . . . . . 29
8.7.1 8.7.2 8.7.3 8.7.4 8.7.5 8.7.6 Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bridge+ VEXT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9
Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1 10.2 10.3 10.4 10.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11
Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12
Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.1 12.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13
Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.1 13.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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13.3 13.4 13.5
Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Switching regulator controller specifications . . . . . . . . . . . . . . . . . . . . . . 45 Switching regulator controller application considerations . . . . . . . . . . . . . 45
14
Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
14.1 14.2 14.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Synchronous buck regulator configuration . . . . . . . . . . . . . . . . . . . . . . . 64 Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
15
AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
15.1 15.2 15.3 15.4 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 A2D specification with A2dType=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A2D specification with A2dType=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
16
Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
17
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17.1 17.2 17.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Operational amplifiers specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Operational amplifiers used as comparators specifications . . . . . . . . . . . 85
18
Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
18.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
19
General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
19.1 19.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 88
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19.3
Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 88
20
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
20.1 20.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt controller monitored signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
21
Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
22
GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
22.10 GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 22.11 GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 22.12 GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 22.13 GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 22.14 GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.15 GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.16 GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
23
Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
23.1 23.2 Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
24 25
Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Schematic samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
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26
Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
26.1 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
27 28
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VSupplyInt specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VPump specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSupplyInt specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 nRESET circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TSD circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 nAWAKE function specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 System linear regulator operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Main switching regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Switching regulator controller application feedback reference . . . . . . . . . . . . . . . . . . . . . . 46 PWM selection truth for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PWM selection truth for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Bridge selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Full bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Half bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Switch truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Stepper specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Sequencer drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Stepper mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Blanking times specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Battery charger control loop FBRef specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Battery charger control loop CurrRef specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
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List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100.
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Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Battery charger operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADC truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Channel addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Current DAC truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Current DAC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Configurable 3.3V operational amplifier specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Configurable 3.3V operational amplifier used as comparator specification . . . . . . . . . . . . 85 3.3V low power switch specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Interrupt controller specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Comparison type truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 DataX selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 GPIO[0] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 GPIO[0] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 GPIO[1] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 GPIO[1] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 GPIO[2] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 GPIO[2] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 GPIO[3] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 GPIO[3] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 GPIO[4] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GPIO[4] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 GPIO[5] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[5] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 GPIO[6] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 GPIO[6] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 GPIO[7] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 GPIO[7] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 GPIO[8] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 GPIO[8] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO[9] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 GPIO[9] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO[10] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 GPIO[10] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 GPIO[11] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 GPIO[11] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 GPIO[12] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 GPIO[12] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 GPIO[13] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 GPIO[13] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 GPIO[14] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 GPIO[14] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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List of tables
Table 101. Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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List of figures
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List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSupplyInt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Linear main regulator external bipolar example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Switching regulator controller output driving equivalent circuit . . . . . . . . . . . . . . . . . . . . . . 44 H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Configurable 3.3V operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Digital Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 134 Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 135
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List of figures TQFP64 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
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General description
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1
1.1
General description
Overview
S.A.B.Re represents a new concept of IC in motion & power supply field. The aim that ST followed in defining S.A.B.Re specification was to offer to the customer an IC with a wide number of features: motor drivers, regulators, high precision A/D converter, operational amplifiers, voltage comparators and many other circuits can easily be configured and customized. The device configuration can be defined by programming the IC via the Serial Interface while a deeper customization can be done through metal layer in order to set more complex functions.
Figure 1.
Block diagram
OP.Amps
(2x) 3.3V Pass Switch
Digital auxiliary
Digital compar.
Current DAC
SPI
SA B R e
Thermal Manager Analog Mux
S/H
Power sequencing
Osc.
Start Up config.
Bridge 1
GPIOs
Bridge 3
Rsense
Supervisory & Reset Manager
Main Switching regulator
Switching Reg. controller
Charge Pump
Int. Ref. Volt
Main Linear regulator
Internal regulators
Batt. Charg. circuitry
Stepper circuitry
Bridge 2
ADC
Bridge 4
Rsense
Note:
See following "S.A.B.Re's Main features" for a detailed description of possible configurations.
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S.A.B.Re's main features
2
S.A.B.Re's main features
S.A.B.Re includes the following circuits:
Four widely configurable full bridges: - Bridges 1 and 2: - - - - - Diagonal RDSon: 0.6 typ. Max operative current = 2.5A. Diagonal RDSon: 0.85 typ. Max operative current = 1.5A.
Bridges 3 and 4:
Possible configurations for each bridge are the following: - Bridge 1: - - - - - - - - DC motor driver. Super DC (bridge 1 and 2 paralleled form superbridge1). 2 independent half bridges. 1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form superhalfbridge1). 2 independent switches (high or low side). 1 super switch (high or low side).
Bridge 2 has the same configurations of bridge 1. Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following: - - - 1/2 Stepper motor driver. 2 buck regulators (VAUX1_SW, VAUX2_SW). 1 Super buck regulator (VAUX1//2_SW). 1/2 stepper motor driver. 1 super buck regulator (VAUX3_SW). Battery charger.
-
Bridge 4 has the same configurations of bridge 1 plus the following: - - -
One buck type switching regulator (VMAIN_SW) with: - - - - - - - Output regulated voltage range: 1-5 Volts. Output load current: 3.0 A. Internal output power DMOS. Internal soft start sequence. Internal PWM generation. Switching frequency: ~250kHz. Pulse skipping strategy control. Output regulated voltage range: 1-30 Volts. Selectable current limitation. Internal PWM generation. Pulse skipping strategy control.
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One switching regulator controller (VEXT_SW) with: - - - -
S.A.B.Re's main features
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One linear regulator (VMAIN_LIN) that can be used to generate low current/low ripple voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages. One bidirectional serial interface with address detection so that different ICs can share the same data bus. Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin. Fourteen general purpose I/Os that can be used to drive/read internal/external analog/logic signals. One 8-bit/9-bit A/D converter (100KS/sec @ 9-bit, 200KS/sec @8-bit). It can be used to measure most of the internal signals, of the input pins and a voltage proportional to IC temperature. - - - - Current sink DAC: Three output current ranges: up to 0.64/6.4/64 mA. 64 (6-bit programmable) available current levels for each range. 5V output tolerant. 3.3V supply, rail to rail input compatibility, internally compensated. They can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip. Unity gain bandwidth > 1MHz. They can also be set as comparators with 3.3V input compatibility and low offset.

Two operational amplifiers: - - - -

Two 3.3V pass switches with 1 RDSon and short circuit protected. Programmable watchdog function. Thermal shutdown protection with thermal warning capability. Very low power dissipation in "Low Power mode" (~35mW) S.A.B.Re is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility S.A.B.Re includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET.
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Global specifications
3
3.1
Global specifications
Absolute maximum rating specifications
The following specifications define the maximum range of voltages or currents for S.A.B.Re. Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 2. Absolute maximum rating
Description VSupply voltage VGPIO_SPI voltage 3.3V pins input voltage Switching regulators output pin voltage range Switching regulators min pulsed voltage Charge pump pins voltage Junction temperature(2) For less than 500ns
(1)
Parameter VSupply_Abs VGPIO_SPI_Abs V3V3pin_Abs VSw_Abs VSw_pulse VPump_Abs Tj_Abs
Test condition
Min
Max 40 3.9 3.9
Unit V V V V V
-1 -3
VSupply
15 -40 0 190 TSD
V C C
Storage Operating
1. This value is useful to define the voltage rating for external capacitor to be connected from VPump to VSupply. VPump is internally generated and can never be supplied by external voltage source nor is intended to provide voltage to external loads. 2. TSD is the thermal shut down temperature of the device.
3.2
Operating ratings specifications
Table 3. IC operating ratings
Description VSupply voltage range VSupply operative current VSupply shut down state current VGPIO_SPI voltage range VGPIO_SPI operative current 3.3V input pins voltage range Junction temperature Operating
(2) (1)
Parameter VSupply_Op ISupply_Op IShut_down VGPIO_SPI_OP IVGPIO_SPI_OP V3v3pin_Op Tj_Abs
Test condition
Min 23
Max 38 15 1.5
Unit V mA mA V mA V C
2.4
3.6 TBD
-0.3 0
3.6 125.
1. Operating Supply current is measured with System regulators operating but not loaded. 2. Operating VGPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO's, operational amplifiers and pass switches) enabled but not loaded.
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Internal supplies
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4
4.1
Internal supplies
Overview
S.A.B.Re includes three internal regulators used to provide a regulated voltage to internal circuits. The internal regulators are the following: - VSupplyInt regulator. - Charge pump regulator. - V3v3 regulator.
4.2
VSupplyInt regulator
VSupplyInt is the output of an internal regulator used to supply some internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected to this pin (preferably towards VSupply pin). Figure 2. VSupplyInt pin
Vsupply VsupplyInt
IS_Int_TYP
SABRe internal circuits SABRe GND
The VSupplyInt pin may also be externally connected to VSupply pin by means of an external resistor REXT: this allows REXT, particularly when VSupply is at the max values of the operative supply range, to dissipate power that otherwise would be dissipated inside the chip. The choice of the optimal resistor depends on the application since it is strictly depending on both VSupply and the current used inside the chip (that is changing with the chosen configuration).
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Internal supplies
4.3
VSupplyInt specifications
Table 4. VSupplyInt specification
Description VSupplyInt output voltage VSupplyInt operative current External resistor value External capacitor Test condition
(1) (2)
Parameter VS_Int_RNG IS_Int_TYP RExt CExt
Min 18
Typ 19.5 11 1000
Max 21
Unit V mA
VSupply=32V IS_Int=12mA(3) 80
1.5 120
nF
100
1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt. 2. This typical value is only intended to give an extimation of the current consumption when S.A.B.Re is configured in simple regulators mode (see following Chapter 8.7.4) at the end of the start up sequence and with no load on regulators. This typical value allows a raw choose of the external resistor but the definitive choose must be done according to following Note 3). 3. REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max). IS_Int max is depending from the chosen configuration and represents the total current needed by the circuits connected to this pin.
4.4
Charge pump regulator
S.A.B.Re implements a charge pump regulator to generate a voltage over VSupply.This voltage is used to drive internal circuits and the external FET driver and cannot be used for any other purpose. This circuit is always under the supervisory circuit control, so no regulator can start before the VPump voltage reaches its undervoltage rising threshold. If VPump voltage falls down below its under voltage falling threshold, all the regulators will be switched off. The charge pump circuit is disabled when S.A.B.Re is in "Low Power mode". Table 5.
Parameter VPump FPump CFLY CBOOST
VPump specification
Description Regulated Voltage VPump clock frequency Flying capacitor Boost capacitor Test condition VSupply=32V Fosc = 16MHz typ Min VSupply +10.5 Typ VSupply +12.5 Fosc/64 100 1 Max VSupply +14.5 Unit V KHz nF F
4.5
V3v3 regulator
V3v3 is the output of an internal regulator used to supply some low voltage internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected from this pin to gnd.
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Internal supplies
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4.6
V3v3 specifications
Table 6.
Parameter V3V3 CExt
VSupplyInt specification
Description V3v3 output voltage External capacitor Test condition VSupply=32V Min 3.15 80 Typ 3.3 100 Max 3.45 120 Unit V nF
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Supervisory system
5
5.1
Supervisory system
Overview
The supervisory circuitry monitors the state of several functions inside S.A.B.Re and resets the device (and other ICs if connected to nRESET pin) when the monitored functions are outside their normal range. Supervisory circuitry can be divided into three main blocks: - - - Power on reset (POR) generation circuitry. nRESET (nRST_int) generation circuitry. Thermal shut down (TSD) generation circuitry.
POR circuitry monitors the voltages that S.A.B.Re needs to guarantee its own functionality; nRESET circuitry controls if S.A.B.Re's main voltages are inside their normal range; TSD is the thermal shut down of the chip in case of overheating.
5.2
Power on reset (POR) circuit
Power on reset circuit monitors VSupply, and V3v3 voltages. The purpose of this circuit is to set the device is in a stable and controlled status until the minimum supply voltages that guarantee the device functionality are reached. The output signal of this circuit (in the following indicated as "POR") becomes active when VSupply or V3v3 go under their falling threshold. When POR output signal is active, all functions and all flags inside S.A.B.Re are set in their reset state; once POR signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized Table 7.
.
Power on reset specifications
Description Test condition InRESET = 1mA VSupply falling Min 4 6 3 V3V3 falling V3V3 rising 1.9 2.2 2.7 0.5 1.5 9 Typ Max Unit V V s V V V s
Parameter
VSupply_POR_valid VSupply voltage for POR valid VSupply_POR_fall tSupply_POR_filt V3V3_POR_fall V3V3_POR_rise V3V3_POR_hys t3V3_POR_filt VSupply POR falling threshold VSupply POR filter Time V3v3 POR falling threshold V3v3 POR rising threshold V3v3 POR hysteresis V3v3 PORfilter time
5.3
nRESET generation circuit
The nRESET circuit monitors VSupply, VSupply_int, VPump, VGPIO_SPI and all system regulators (VSystem) voltages. The purpose of this circuit is to prevent the device functionality until the monitored voltages reach their operative value (please note that V3v3
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Supervisory system
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is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is not active). This circuit generates an internal reset signal (in the following indicated as "nRST_int") that will also be signaled to external circuits by pulling low the nRESET pin. The signal nRST_int becomes active in the following cases: 1. When one of the following voltages is lower than its own under voltage threshold: - - - - 2. 3. 4. VSupply and VSupply_int. VPump. VSystem (all switching or linear system regulators voltages). VGPIO_SPI.
When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only if watchdog function is enabled). When S.A.B.Re is in "Low Power mode". When EnExtSoftRst bit in SoftResReg register is at logic level = "1" and a "SoftRes" command is applied (see SoftResReg register description in Chapter 25).
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a "stretch" time that starts from the moment that nRST_int signal returns in the operative state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register according to following table: Table 8. Stretch time selection
Selected stretch time ID[1] 0 0 1 1 ID[0] Typ 0 1 0 1 16ms 32ms 48ms 64ms Default state Note
When nRST_int becomes active (logic level = "0") it sets in their reset state some of the functions inside S.A.B.Re. The main functions that will be reset by nRST_int signal are the following: - - - - - - - - - - Serial interface will be reset and will not accept any other command. The bridges 1 and 2 will place their outputs in high impedance and PWM and direction signals will be reset. Not system regulators will be powered off. AD converter will be powered off. GPIOs will be powered off. Current DAC will be powered off. Operational amplifiers will be powered off. Watchdog count will be reset (while Watchdog flags won't be reset). Interrupt controller will be powered off. Digital comparator will be powered off.
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Supervisory system Additionally the system regulators will be powered off but only if the voltage that caused the nRST_int event is checked before the system regulator in the power up sequence. This means that: - - - all system regulators will be powered off if nRST_int is caused by VSupply, VSupply_int, VPump (and also if V3v3 causes a POR); no one of the system regulators will be powered off if nRST_int is caused by VGPIO_SPI; only the system regulators that follows the system regulator that caused the nRST_int in power up sequence will be powered off.
5.4
nRESET specifications
Table 9. nRESET circuit specifications
Description nRESET Low level output voltage nRESET fall time nRESET delay time VSupply falling threshold VSupply rising threshold VSupply hysteresis VSupply UV filter time VSupplyInt falling threshold VSupplyInt rising threshold VSupplyInt hysteresis VSupplyInt UV filter time VPump falling threshold VPump rising threshold VPump hysteresis VPump UV filter time VGPIO_SPI falling threshold VGPIO_SPI rising threshold VGPIO_SPI hysteresis VGPIO_SPI UV filter time 250 3.5 1.8 2.4 1.5 3.5 VSupply +7 VSupply + 9.5 1.5 3.5 14.0 17.5 2 3.5 Test condition I=10mA I=1mA C=50pF(1)
(2)
Parameter nRST_VOL nRST_fall nRST_del VSupply_UV_f VSupply_UV_r VSupply_UV_hys tSupply_UV VS_Int_UV_f VS_Int_UV_r VS_Int_UV_hys tS_Int_UV VPump_UV_f VPump_UV_r VPump_UV_hys tPump_UV VGPIO_SPI_UV_f VGPIO_SPI_UVr VGPIO_SPI_hys tGPIO_SPI_UV
Min
Typ
Max 0.4 15 150
Unit V ns ns V
18.5 23
V V us V V V s V V V us V V mV us
1. Measured between 10% and 90% of output voltage transition. 2. Measured from a fault detection to 50% of output voltage transition.
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Supervisory system Figure 3. nReset generation circuit
nRST_in Filter
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UV comparator UV Filter
V SupplyUV
V SupplyInt
UV comparator UV Filter
V SupplyIntUV
Low Power Mode
V Supply
V Pump
UV comparator UV Filter
nRESET pin
V PumpUV
nGateCtrl
nRESET pin Driver
V SysX
UV comparator UV Filter SystemregulatorsUV
POR
WD_En_nRst
V SysY
UV comparator UV Filter
to SPI
Note:
All regulator voltages included in power up sequence (VSysX - VSysY in Figure 3) will be considered as nRESET circuit voltages.
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WatchDog Elapsed
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Supervisory system
5.5
Thermal shut down generation circuit
The third component of the supervisory circuit is the thermal shut down generation circuit. This circuit generates two different flags depending on the IC temperature: - - the "TSD" flag indicates that the IC temperature is greater than the maximum allowable temperature. the "Warm" flag, that can be read using serial interface, becomes active at a lower temperature respect to TSD signal, therefore it can be used to prevent the IC from reaching over temperature.
When a TSD event occurs, S.A.B.Re will enter in the reset state placing the bridges in high impedance and turning off all regulators and other circuits until the internal temperature decreases below the Warm temperature. At this point, S.A.B.Re will restart the power up sequence and TSD bit will be set and will be readable as soon as S.A.B.Re will come out from the reset state. This TSD bit can be reset in three ways: - - - by writing a logic level `1' in the ClearTSD bit in the ICTemp register (see Chapter 25); by a POR event; by entering in "Low Power Mode".
The Warm bit, set by S.A.B.Re when IC is working over the warming temperature, can be read using the SPI interface. Once this bit is set it can be reset in three ways: - - - by writing a logic level `1' in the ClearWarm bit; by a POR event; by entering in "Low Power Mode".
The thermal sensor voltage can be converted using the internal A/D: this way the microcontroller can directly measure the IC temperature. To avoid unwanted commutation especially when temperature is near the thresholds, the output signal is filtered for both TSD and Warm.
5.6
TSD specifications
Table 10. TSD circuit specifications
Description Thermal shut down temperature Warming temperature Thermal shut down to warming difference Thermal shut down filter time Warming filter time Test condition Min Typ 170 140 30 8 8 Max Unit C C C us us
Parameter TTSD TWARM TDIFF tTSD_FILT tWARM_FILT
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Watchdog circuit
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6
6.1
Watchdog circuit
Overview
The Watchdog timer can be used to reset S.A.B.Re if it is not serviced by the firmware that can periodically write at logic level "1' the ClrWDog bit in the WatchDogStatus register. This circuit is disabled by default; firmware can enable it by setting at logic level `1' the WDEnable bit in the WatchDogCfg register. When the Watchdog timeout event happens, S.A.B.Re sets to `1' a latched bit WDTimeOut in theWatchDogStatus register that can be read using SPI interface; once this bit is set it can be cleared in three ways: - - - by writing a `1' in the WDClear bit in the WatchDogStatus register. by writing a `1' in the SoftReset bit in the WatchDogStatus register. by a POR event.
The Watchdog function includes also a warning bit WDWarning to indicate, via serial interface or via the circuit called Interrupt Controller (see Chapter 21) that the watchdog is near to its timeout; this bit is asserted to logic level "1" exactly one watch dog clock period (WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut signal to cause an "nRst_int" event by setting to logic `1' the WDEnnRst bit. Figure 4. Watchdog circuit block diagram
WDdelay[3:0]
WDEnable
ClrWDog
To nRSTint generation circuit
WD_req_nRst WD_En_nRst
Fosc
Frequency divider
WD_clk Watchdog counter
WDTimeOut WDWarning
To SPI
The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective programmed WD time is changed in the register only when the watchdog circuit is serviced by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of the WD delay value is loaded. The watchdog timer can be programmed to generate different timeouts using the WDdelay[3:0] bits in the WatchDogCfg register according to following table:
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SABRE-LL-I Table 11. Watchdog timeout specifications
Watchdog circuit
WD timeout WDdelay[3:0] Typ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 8*WD_Tclk 9*WD_Tclk 10*WD_Tclk 11*WD_Tclk 12*WD_Tclk 13*WD_Tclk 14*WD_Tclk 15*WD_Tclk 16*WD_Tclk 17*WD_Tclk 18*WD_Tclk 19*WD_Tclk 20*WD_Tclk 21*WD_Tclk 22*WD_Tclk 23*WD_Tclk
6.2
Watchdog specifications
Table 12.
Parameter WD_Tclk
Watchdog specifications
Description Watchdog clock period Test condition Min Typ Tosc * 222 Max Unit s
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Internal clock oscillator
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7
7.1
Internal clock oscillator
Overview
S.A.B.Re includes a free running oscillator that does not require any external components. This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16MHz. The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in "Low Power mode".
7.2
Internal clock specifications
Table 13.
Parameter
Internal clock specifications
Description Oscillator frequency Oscillator period Test condition Min Typ Max Unit
Fosc Tosc
V3V3 =3.3V
14.4
16 1/Fosc
17.6
MHz
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Start-up configurations
8
8.1
Start-up configurations
Overview
S.A.B.Re start-up configuration is selected by setting in different states the GPIO[0], GPIO[3] and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish among the following situations: Table 14. Possible start-up pins state symbol
Pin condition Shorted to ground Shorted to V3v3 pin Floating
Note: "Shorted" means: R1KOhm; "Z" means: R10KOhm, C200pF
State symbol 0 1 Z
8.2
Operation modes
When VSupply voltage is applied to S.A.B.Re, the internal regulator V3v3, used to supply the logic circuits inside the device, starts its functionality. When it reaches its final value, S.A.B.Re enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will sample the GPIO[0] state. If it is found to be in high impedance, S.A.B.Re does not consider GPIO[3] and GPIO[4] pins state and starts its "Basic device" mode sequence. If GPIO[0] is found to be connected to ground or to V3v3, S.A.B.Re checks the state of GPIO[3] and GPIO[4] pins to select its start-up configuration. The possible configurations can be classified in four "Major" modes: 1. 2. 3. 4. Basic device. Slave device. Master device. Single device.
Hereafter is reported the correspondence table between GPIO[X] state and S.A.B.Re configurations.
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Start-up configurations Table 15. Start-up correspondence
Pin state(1) Major mode GPIO[0] Z 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 GPIO[3] X 0 0 0 Z Z Z 1 1 1 0 0 0 Z Z Z 1 1 1 GPIO[4] X 0 Z 1 Single 0 Z 1 0 Z 1 Master 0 Z 1 0 Z 1 Slave 0 Z 1 Simple regulator Bridge + VEXT Simple regulator Bridge + VEXT Simple regulator Bridge + VEXT Basic Bridge Minor mode(2)
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Primary regulator Regulators
Secondary Regulators Bridge Primary regulator Regulators
Secondary Regulators Bridge Primary regulator Regulators
Secondary Regulators.
1. "X" means "don't care". 2. The description of these modes is in the following paragraph 9.7.
8.3
Basic device mode
The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode S.A.B.Re doesn't use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses. When in this mode the regulators included in the start up sequence (except VMAIN_SW) are considered as system regulators and they start in the following sequence: 1. 2. 3. 4. Auxiliary switching regulator1 (VAUX1_SW). Auxiliary switching regulator2 (VAUX2_SW). Main linear regulator (VMAIN_LIN). Main switching regulator (VMAIN_SW) (Not system regulator).
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Start-up configurations
8.4
Slave device mode
In slave device mode, S.A.B.Re consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled. At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT seconds, S.A.B.Re enters directly in the "Low Power mode"; when nAWAKE pin is pulled high for a period higher than tAWAKEFILT seconds, S.A.B.Re begins its start up procedure.
8.5
Master device mode
In master device mode, S.A.B.Re begins its start up procedure without waiting for any external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices. During the whole start up time, it forces its GPIO[5] pin at logic level "0" in order to maintain all slave devices in "Low Power mode" as previously described. When start up operations are completed, S.A.B.Re forces the GPIO[5] output to logic level "1" to enable the slave devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its System regulators. If firmware writes in the PwrCtrl register to set Master S.A.B.Re in "Low Power mode" it immediately forces GPIO[5] output to logic level "0" to force the slave devices to enter in "Low Power mode", then it waits for TMASTWAIT time and it starts its "Low Power mode" sequence.
8.6
Single device mode
In single device mode, the device behaves similarly to master device mode but: 1. 2. It doesn't use the GPIO[5] pin to drive slave devices. It doesn't wait for TMASTWAIT before entering in "Low Power mode".
8.7
Sub-configurations for slave, master or single device modes
Each slave, master or single device modes can be divided in other minor modes depending on the start-up sequence needed for S.A.B.Re internal regulators. Unless otherwise specified, in all the following modes the regulators included in the start up sequence are considered system regulators and they start in the sequence indicated.
8.7.1
Bridge mode
In this configuration bridges 3 and 4 are not used as regulators and therefore can be configured by the firmware in any of their possible bridge modes. When in this mode the power-up sequence is: 1. 2. Main switching regulator (VMAIN_SW). Main linear regulator (VMAIN_LIN).
8.7.2
Primary regulator mode (KP)
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VAUX2_SW).is not considered a system regulator.
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Start-up configurations When in this mode the power-up sequence is: 1. 2. 3. Auxiliary switching regulator1 (VAUX1_SW).
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Main switching regulator (VMAIN_SW) together with main linear regulator (VMAIN_LIN). Auxiliary switching regulator2 (VAUX2_SW) (Not system regulator).
8.7.3
Regulators mode
In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators, but the start up sequence is different previous one. When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VMAIN_SW). Auxiliary switching regulator1 (VAUX1_SW) Auxiliary switching regulator2 (VAUX2_SW)
8.7.4
Simple regulator mode (KT)
Also in this configuration Bridge 4 can be configured by firmware while Bridge3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VMAIN_SW).is not considered a system regulator. When in this mode the power-up sequence is: 1. 2. 3. 4. Auxiliary switching regulator1 (VAUX1_SW). Auxiliary switching regulator2 (VAUX2_SW) Main linear regulator (VMAIN_LIN) Main switching regulator (VMAIN_SW) (not system regulator).
8.7.5
Bridge+ VEXT mode
In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained using the switching regulator controller (VEXT) is included in start-up. When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VMAIN_SW). Switching regulator controller regulator (VEXT). Main linear regulator (VMAIN_LIN).
8.7.6
Secondary regulators mode
In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (VAUX_(1//2)SW). When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VMAIN_SW). Auxiliary switching regulator (VAUX(1//2)_SW). Main linear regulator (VMAIN_LIN).
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Power sequencing
9
9.1
Power sequencing
Overview
As soon as VSupply and VSupplyInt are above their power on reset level, S.A.B.Re will start the charge pump circuit; once VPump voltage reaches its under voltage rising threshold, S.A.B.Re begins a sequence that starts the regulators considered system regulators. A regulator is considered a System regulator if: - - - It has to start in on state without any user action. It is included in the power-up sequence. Its under-voltage event is considered by S.A.B.Re as an error condition to be signaled through nRESET pin.
Once VSupply and VSupplyInt, VPump and all the system regulators are over their under voltage rising threshold, S.A.B.Re enters in the normal operating state, that will release nRESET pin and will wait for SPI commands. S.A.B.Re will reduce the noise introduced in the system by switching out of phase all its power circuits (switching regulators, bridges and charge pump). The S.A.B.Re's startup sequence of operation is the following: - - - - - - - start V3v3 internal linear regulator sample startup configuration wait enable if slave device start charge pump start system regulators (see order in Section 8.7) send enable to slave device, if master wait until VGPIO_SPI becomes ok
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Power saving modes
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10
10.1
Power saving modes
Overview
Saving power is very important for today platforms: S.A.B.Re implements different functions to achieve different levels of power saving. Sections here below describe these different power saving modes.
10.2
Standby mode
Almost all low voltage circuitry inside S.A.B.Re are powered by V3v3 internal regulator; this regulator is a linear regulator powered by VSupplyInt. This means that all the current provided by V3v3 regulator is directly coming from VSupplyInt and therefore the total power consumption is: Low voltage power = VSupply* IV3v3. because VSupplyInt is feeded by VSupply, directly or with a resistor in series. This power could be reduced by using a switching buck regulator to supply V3v3: in this case, assuming the buck regulator efficiency near to 100%, the dissipated power would become: Low voltage power 3.3V * IV3v3. To achieve this result there is the need to switch off the internal V3v3 linear regulator and to use an additional pin to provide a 3.3V supply to internal circuits. S.A.B.Re can do this by using the low voltage switch implemented on GPIO6 pin. This switch internally connects VGPIOSpi voltage to GPIO6 output so, by externally connecting GPIO6 to V3v3 pin, the VGPIOSpi voltage can be provided to low voltage circuitry inside S.A.B.Re. Figure 5. Standby mode function description
VSupplyInt VGPIOSpi
StdByMode
Power Switch 1
GPIO6 External connection 3.3V
3.3 V 1.9 V
0 + 1
V3v3 Regulator
-
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Power saving modes The StdByMode bit used to switch off V3v3 and switch on the power switch can be set to `1' by writing the standby command in the StdByMode register. S.A.B.Re exits standby mode if a reset event happens or "Low Power mode" is selected. Because all internal low voltage circuitry powered by V3v3 are designed to work with a 3.3V voltage rail, when the standby mode is used, VGPIOSpi is requested to be at 3.3V.
10.3
Hibernate mode
S.A.B.Re's hibernate mode allows the firmware to switch off some (or all) selected System Regulators leaving in on state only those necessary to resume S.A.B.Re to operative condition when waked-up by an external signal. Hibernate mode is selected when the firmware writes the command word in the HibernateCmd register. When in hibernate mode S.A.B.Re will force regulators in the state (on/off) selected by the firmware by writing in the HibernateCmd register and will force nRESET pin low. The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5 pin if S.A.B.Re is in Slave mode); S.A.B.Re will also exit from hibernate mode if an undervoltage event happens on VSupply, VSupplyInt, VPump or V3v3. When the exit from hibernate mode is due to an external command, S.A.B.Re sets to `1' the bit HibModeLth in the HibernateStatus register.
10.4
Low power mode
When in normal operating mode, the microcontroller can place S.A.B.Re in "Low Power mode". In this condition S.A.B.Re sets all bridges outputs in high impedance, powers down all regulators (including system regulators and charge pump) and disables almost all its circuits including internal clock reducing as much as possible power consumption. The only circuits that remain active are: - - - - V3V3 internal regulator. nAWAKE pin current pull-up. nRESET pin that will be pulled low. POR circuit.
The entering in low power mode is obtained in different ways depending if S.A.B.Re is configured as slave device or not. When S.A.B.Re is configured as slave device the low power mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for a time longer then tAWAKEFILT, Low Power mode is entered; if this pin is high S.A.B.Re exits from Low Power mode. In all other start-up configurations, Low Power mode is entered by writing a Low Power mode command in the PowerModeControl register; once S.A.B.Re is in Low Power mode it starts checking the nAWAKE pin status: if it is found low for a time longer than tAWAKEFILT, S.A.B.Re exits from Low Power mode and restarts its startup sequence. When the nAWAKE pin is externally pulled low, the "AWAKE" event is stored and it is readable through SPI. S.A.B.Re will also exit from Low Power mode if a POR event is found. Note: When in "Low power mode" VSupply is monitored only for its power on reset level.
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Power saving modes
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10.5
nAWAKE pin
At the start up, before S.A.B.Re has identified the required operation mode (see Chapter 8), a current sink IINP is always active to pull down nAWAKE pin. As soon as the operation mode (basic, slave, master or single device) is detected, the functionality of nAWAKE pin will be different. If S.A.B.Re is not configured as Slave device a current source IOUT will be active on this pin, while the current sink IINP will be disabled. If S.A.B.Re is configured as a Slave device, the current sink IINP will be active until nAWAKE pin is detected high for the first time; after that both current sources IINP and IOUT will be disabled and the nAWAKE pin can be considered as a digital input. Here below is reported the nAWAKE pin simplified schematic. Figure 6. nAWAKE function block diagram
V 3v3 SlaveMode I OUT
AWAKE_req
AWAKE nAWAKE seen high for the first time after start up.
I INP
Table 16.
Parameter VIL VIH VHYS IOUT IINP tAWAKEFILT
nAWAKE function specifications
Description nAWAKE logic low threshold nAWAKE logic high threshold nAWAKE input hysteresys nAWAKE pin output current nAWAKE pin input current Filter time nAWAKE=0V(1) nAWAKE=0.8V
) (1
Test condition
Min
Typ
Max 0.8
Unit V V
1.6 0.25 - 0.72 0.2 1.2 -2 0.4
V mA mA ns
1. Current is defined to be positive when flowing into the pin.
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Linear main regulator
11
11.1
Linear main regulator
Overview
The linear main regulator is directly powered by VSupply voltage and it is one of the regulators that S.A.B.Re could consider as a system regulator. This means that the voltage generated by this regulator is not used to power any internal circuit, but S.A.B.Re will check that the feedback voltage VLINmain_FB is in the good value range before enabling all its internal functions. When an under-voltage event (with a duration longer than period Tlinear_uv defined by the deglitch filter) is detected during normal operation, S.A.B.Re will enter in reset state and it will signal this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks. Here are summarized the primary features of the regulator: - - - - - Regulated output voltage from 0.8V to VSupply-2V with a maximum load of 10mA. Band gap generated internal reference voltage. Short circuit protected (output current is clamped to 22mA typ). Under voltage signal (both continuous and latched) accessible through serial interface. Low power dissipation mode.
The internal series element is a P-channel MOS device. The voltage regulator will regulate its output so that feedback pin equals VLINmain_FB, therefore the regulated voltage can be calculated using the formula: VLINmain_OUT = VLINmain_ref *(Ra+Rb)/Rb Figure 7. Linear main regulator
V supply
Body Diode
V LINmain_OUT
Driver
Cc
+ -
Ra
V LINmain_FB V LINmain_ref
Rb
To extend the output current capability this regulator can be used as a controller for an external active component able to provide higher current (i.e. a Darlington device); the external power element allows the handling of an higher current since it dissipates the
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power externally (the power dissipated by a linear driver supplied at VSupply and regulating a voltage VLINmain_OUT with an output current IOUT is about: Pd= (VSupply-VLINmain_OUT)*IOUT. Figure 8. Linear main regulator external bipolar example
V supply
Body Diode VLINmain_OUT Cc
Driver
Cload
+ VLINmain_FB VLINmain_Ref
Ra
Rb
Whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin towards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100nF to 1F depending on the regulated voltage. When this regulator is disabled, the whole circuit is switched off and the current consumption is reduced to a very low level both from V3v3 and from VSupply. When in this condition, the output pin is pulled low by an internal switch. Table 17. System linear regulator operating specifications
Description Output pin voltage range Drop out voltage Internal switch pull down current Feedback pin voltage range Feedback reference voltage Feedback pin input current Test condition
(1)
Parameter VLINmain_OUT Vdrop
Min 0 2
Typ
Max VSupply
Unit V V
Vdrop= Vsupply-VLINmain_OUT Linear Main Regulator disabled; VLINmain_OUT=1V
IPD
3
mA
VLINmain_FB VLINmain_Ref ILINmain_Ref
0 0.776 -2 0.8
3.6 0.824 2
V V A
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SABRE-LL-I Table 17.
Linear main regulator System linear regulator operating specifications (continued)
Description Maximum Output current Output short circuit current Load regulation Line regulation Loop voltage accuracy Under voltage falling threshold Under voltage rising threshold Under voltage hysteresis Under voltage deglitch filter VLINmain_OUT =0.8V 0.8V 5V
(3)
Parameter IoutLinMax Ishort Vout/Vo Vout/VSupply Vloop_acc VuvFall VuvRise Vuvhys tprim_uv
Test condition Regulated voltage = Vsupply-2V VLINmain_OUT =0V, VLINmain_FB =0V 0 Iload IoutLinMax(2) Iload =10mA
(2)
Min 10 12
Typ
Max
Unit mA
24 0.8 0.2 2.5
mA % % % 89.5 95.5 % % % us
84.5 90.5
87 93 6 5 1 0.68 0.33 0.1
(3)
(3)
CC
Compensation capacitance
F
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This is to avoid change on output voltage due to heating effect. 3. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_Ref).
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Main switching regulator
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12
12.1
Main switching regulator
Overview
Main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. It implements a soft start strategy and could be a system regulator so even if its output voltage VMAIN_SW is not used to power any internal circuit, S.A.B.Re will check that it is in the good value range before enabling all its internal functions. When S.A.B.Re detects a system regulator under-voltage event with a duration longer than the period defined by the deglitch filter (Tprim_uv), it will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal block (e.g. bridges, GPIOs, ...). The output voltage will be externally set by a divider network connected to feedback pin. To reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to choose between four feedback voltage references (and, as a consequence, four undervoltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef bits in the MainSwCfg register according to the table here below: Table 18. Switching regulator controller PWM specification
Reference voltage (VFBREF) Min 0.776 0.97 2.425 2.910 Typ 0.8 1 2.5 3 Max 0.824 1.03 2.575 3.09 V V V V Default state Unit Comments
MainSwCfg register SelFBref[1] 0 0 1 1 SelFBref[0] 0 1 0 1
Reference voltage range can be changed by using a metal layer change in order to adapt them to customer system. Here after are summarized the primary features of this regulator: - - - - - - - Internal power switch. Soft start circuitry to limit inrush current flow from primary supply. Internally generated PWM (250kHz switching frequency). Nonlinear pulse skipping control. Protected against load short circuit. Cycle by cycle current limiting using internal current sensor. Under voltage signal (both continuous and latched) accessible through SPI.
When S.A.B.Re is in "Low Power mode", this regulator will be disabled. In order to save external components and power when using two or more S.A.B.Re IC's on the same board, the primary switching regulator can be disabled by serial interface. Care must be paid using this function because an under-voltage on this regulator, as previously seen, will be read as a fault condition by S.A.B.Re.
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Main switching regulator
12.2
Pulse skipping operation
Pulse skipping is a well known, non linear, control strategy used in switching regulators. In this technique (see Figure 9) the feedback comparator output is sampled at the beginning of each switching cycle. At this time, if the sampled value shows that output voltage is lower than requested one, the complete PWM duty cycle is applied to power switch; otherwise no PWM is applied and the switching cycle is skipped. Once PWM is applied to power element only a current limit event can disable the power switch before the whole duty cycle is finished. Figure 9. Main switching regulator functional blocks
VSupply
Current Sense
Charge pump Voltage
High Side Driver VSWmain_SW La Ra C
Voltage From Central Logic
Control Logic
Regulator Freq
Loop Control
+
VSWmain_FB
Rb
Regulator Ref
Under voltage flag
Filter
+
Under voltage Threshold
To Central Logic
In pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty cycles that can be changed by writing the VmainSwSelPWM bits in the MainSwCfg register according to following table. Table 19. Main switching regulator PWM specification
Duty cycle value Comments VmainSwSelPWM[1:0] 00 01 10 11 Typical 12% 15% 26% 63.5% Default state
MainSwCfg register
Adjustable duty cycles can be changed by a metal layer change in order to adapt it to customer system. The only limitation is that all regulators share the same duty cycle bus, so any modification must consider all regulators duty cycles.
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The output current is limited to a value that can be set by means of selilimit bit in the MainSwCfg register according to following table: Table 20. Main switching regulator current limit
Current limit (min) 3.3A 2.3A Comments Default state
SelIlimit 0 1
Table 21.
Parameter
Main switching regulator specifications
Description Test condition
(1)
Min -1 -40 -15 -10 0.8 0.002
Typ
Max Vsupply +40 +5 +0 5 3 0.55
Unit V A A A V A O
VMAIN_SW Output pin voltage range IQ IQlp IQfb Vout Iload RonH Vloop VregR Output leakage current Output leakage current in "Low Power Mode" Feedback pin current Output voltage range Output load current Internal high side RDson Loop voltage accuracy Output voltage ripple (RMS) Under voltage falling threshold Under voltage rising threshold Under voltage hysteresys Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition. Switching output rise time Switching output fall time Operating frequency
Tjunction = 125C VSupply = 36V Tjunction = 125C Tjunction = 125C
(2)
VSupply = 36V Iload=1A Tjunction = 125C
3% L =150u, C=330F/ESR=0.54
(3) (4)
28
mVRMS
VuvFall VuvRise Vuvhys tprim_uv Ilimit tdeglitch tI_lim tI_limUV tr tf FregPwm
84.5 90.5
87 93 6 5
89.5 95.5
% % % us
(4)
SelIlimit ="0" SelIlimit ="1"
3.3 2.3 50
5 3.5
TBD TBD
A A ns
In normal operating mode (no UV)(5) When in Under Voltage(6) VSupply = 36V, Resistive load to gnd = 422 (7) VSupply = 36V, Resistive load to gnd = 10 (7) 5 5 Fosc/64
650 400 30 30
ns ns ns ns kHz
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Main switching regulator
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb. 3. The choice of proper values for L and C depends from the application. 4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 5. This condition is intended to simulate an extra current on output. 6. This condition is intended to simulate a short circuit on output. 7. Rise time is measured between 10% and 90% of supply voltage.
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Switching regulator controller
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13
13.1
Switching regulator controller
Overview
This circuit controls an external FET to implement a switching buck regulator using a non linear pulse skipping control with internally generated PWM signal. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under-voltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef bits in the SwCtrCfg register according to the following table. Table 22. Switching regulator controller PWM specification
Reference voltage (VFBREF) Min 0.776 0.970 2.425 2.910 Typ 0.8 1 2.5 3 Max 0.824 1.030 2.575 3.09 V V V V Default state Unit Comments
SwCtrCfg register SelFBref[1] 0 0 1 1 SelFBref[0] 0 1 0 1
Adjustable feedback voltages can be changed using a metal layer change in order to adapt it to customer system. This regulator is switched off when S.A.B.Re is powered up for the first time and can be enabled using S.A.B.Re's SPI interface. Here after are summarized the main features of the regulator: - - - - - - - Soft start circuitry to limit inrush current flow from primary supply. Changeable feedback reference voltage Internally generated PWM (250kHz switching frequency). Nonlinear pulse skipping control. Protected against load short circuit. Cycle by cycle current limiting using internal current sensor. Under voltage signal (both continuous and latched) accessible through SPI.
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SABRE-LL-I Figure 10. Switching regulator controller functional blocks
Switching regulator controller
V supply
Rsense
CurrentSense Charge pump Voltage
V SWDRW_sns N-CH Fet V SWDRV_gate V SWDRV
Voltage Loop Control
Driver La Ra C V SWDRV
FB
SW
V out
From Central Logic
Control Logic
Regulator Freq
+
SelFBRef1:0] [
Analog Mux
Vref = 3 V Vref = 3V Vref=0.8V Vref=0.8V
Rb
VFBRef
undervoltage flag
Filter
+
To Central Logic SelFBRef Uv Threshold 1
Analog Mux
Uv Threshold 2
Under voltage Threshold
13.2
Pulse skipping operation
Pulse skipping strategy has already been explained on main switching regulator section. This regulator has 4 possible PWM duty cycles that can be changed writing in the SelSwCtrPWM bits in the SwCtrCfg register using SPI. Table 23. Switching regulator controller PWM specification
Duty cycle value Comments SelSwCtrPWM[1:0] 00 01 10 11 Typical 9% 12% 22.5% 58% Default state
SwCtrCfg register
Adjustable duty cycles can be changed using a metal layer change in order to adapt it to customer system. The only limitation is that all regulators share the same duty cycle bus, so any modification must consider all regulators needed duty cycles.
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13.3
Output equivalent circuit
The switching regulator controller output driving stage can be represented with an equivalent circuit as in the figure below: Figure 11. Switching regulator controller output driving equivalent circuit
VPUMP
I SOURCE
Source command Tsink Sink pulse command RSUSTAIN Sink command I SINK V SWDRV_SW V SWDRV_gate
As can be seen from the above figure, the external switch gate is charged with a current generator ISOURCE and it is discharged towards ground with a current generator ISINK that is applied for a TSINK pulse while an equivalent resistor RSUSTAIN is connected between gate and source until the sink command is present. The table here below lists the values of the above mentioned parameters: Table 24.
Parameter ISOURCE ISINK tSINK RSUSTAIN
Switching regulator controller operating specification
Description Source current Sink current Sink discharge pulse time Gate-source sustain resistance (VSWCTR_GATE - VSWCTR_SRC) = 0.2V Test condition VPump=VSupply+12V VSWCTR_GATE=0V VSWCTR_GATE = VSupply Min Typ 25 20 600 650 Max 50 Unit mA mA ns
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Switching regulator controller
13.4
Switching regulator controller specifications
Table 25.
Parameter VSWDRV_SW VSWDRV_GAT
E
Switching regulator controller operating specification
Description VSWDRV_SW pin voltage range Gate drive pin voltage Test condition
(1)
Min -1 0 VSupply -3V
Typ
Max VSupply VPump VSupply
Uni t V V V V
VSWDRV_SNS Sense pin voltage Vvgs_ext IQ IQlp VSWDRV_FB Vloop VuvFall(1) Gate to source voltage for ext FET Output leakage current Output leakage current in "Low Power Mode" VSWDRV_FB pin current Loop voltage accuracy Under voltage falling threshold Under voltage rising threshold Under voltage hysteresys Under voltage deglitch filter Over current threshold voltage Current limit deglitch time Current limit response time Current Limit response time in UV condition. Operating frequency In normal operating mode (no UV)(2) When in Under Voltage(3) VSupply = 36V, Tjunction = 125C VSupply = 36V, Tjunction = 125C VSupply = 36V, Tjunction = 125C
VPump -15 -5 -10 3% 84.5 90.5 87 93 6 5 250 50 900 550 Fosc/6 4 300 350 89.5 95.5 +15 +5 +10
A A A
% % % us mV ns ns ns kHz
VuvRise(1) Vuvhys(1) tprim_uv Vovc tdeglitch tI_lim tI_limUV FregPwm
1. Under voltage rising and falling thresholds are referred to feedback pin voltage. 2. This condition is intended to simulate an extra current on output. 3. This condition is intended to simulate a short circuit on output.
13.5
Switching regulator controller application considerations
This controller can implement a step-down switching regulator used to provide a regulated voltage in the range 0.8V - 32V. Such kind of variation could be managed by considering
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some constraints in the application and particularly by choosing the correct feedback reference voltage as indicated in the following table: Table 26. Switching regulator controller application feedback reference
Feedback voltage reference 0.8V - 1V 2.5V - 3V
Output regulated voltage range 0.8V Vout < 5V 5V Vout 32V
Typical application can be considered the following, supposing the external mosfet type STD12NF06L: - - - - Max DC current load = 3A Typ Over current threshold = 3A * 1.5 = 4.5A L = 150 H C = 220-330 F
In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the VSupply range. Other application configurations could be evaluated before being implemented.
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Power bridges
14
14.1
Power bridges
Overview
S.A.B.Re includes four H bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations. Each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. When an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through SPI. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes (see Figure 12). Figure 12. H Bridge block diagram
High side Driver
High side Driver
Control Logic
Control Logic
Low side Driver
Low side Driver
During the start up procedure the bridges are in high impedance and after that they can be enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the bridges return in their start-up condition and they need to be re-enabled from the micro controller. The bridges can use PWM signals internally generated or externally provided (supplied through the GPIO pins). Internally generated PWM signals will run at approximately 31.25kHz with a duty cycle that, through serial interface, can be programmed and incremented in steps of 1/(512*Fosc). To reduce the peak current requested from supply voltage when all bridges are switching, the four internally generated PWM signals are outof-phase. Each half bridge will use the PWM signal selected by the respective MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if
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Power bridges
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two half bridges are configured as a full bridge, only the PWM signal chosen for side A will be used to drive the resulting H bridge. More in detail the PWM selection truth table will be as describe in the following tables: Table 27. PWM selection truth for bridge 1 or 2
Selected PWM(1) MotorXPWM (Configurable by means of MtrXCfg register). AuxXPWM (Configurable by means of AuxPwmXCtrl register). ExtPWM1 (from GPIO 9 input) ExtPWM2 (from GPIO 10 input)
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 1 1 0 1 0 1
1. In this table X stands for 1 or 2, Y stands for A or B.
Table 28.
PWM selection truth for bridge 3 or 4
Selected PWM(1) MotorXPWM (Configurable by means of MtrXCfg register). AuxXPWM (Configurable by means of AuxPwmXCtrl register). ExtPWM3 (from GPIO 2 input) ExtPWM4 (from GPIO 11 input)
MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 1 1 0 1 0 1
1. In this table X stands for 3 or 4, Y stands for A or B.
Here below is reported a block diagram representing the possible PWM choices for each S.A.B.Re half bridges. The figure is related only to bridges 1 and 2, but it could be assumed to be valid also for bridges 3 and 4, with few differences due to different possible configurations of these last drivers.
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SABRE-LL-I Figure 13. Bridge 1 and 2 PWM selection
Power bridges
Mtr1SelPWMSide [1:0] A 00 Motor1 PWM 01 Aux1PWM 10 ExtPWM1 11 ExtPWM2 Mtr1_2Parallel Mtr1SelPWMSideB [1:0] Mtr1Tablel[1:0] 00 Motor1 PWM 01Aux1PWM 10ExtPWM1 11ExtPWM2
Side B Power Section Side A Power Section Side B Power Section Side A Power Section
Motor 1 side A Logic Table
Motor 1 sideB Logic Table
Bridge 1
Mtr1_2Parallel
Mtr2SelPWMSide [1:0] A Mtr2Tablel[1:0] 00 Motor2 PWM 01Aux2Pwm 10ExtPwm1 11ExtPwm2 Mtr2SelPWMSide [1:0] A 00 Motor2 PWM 01 Aux2Pwm 10 ExtPwm1 11 ExtPwm2 Mtr1_2Parallel Mtr2Tablel[1:0]
Motor 2 side A Logic Table
Motor 2 sideB Logic Table
Bridge 2
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Power bridges
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14.2
Power bridges operating specifications
Table 29.
Parameter RON_1_2 RON_3_4 IMax IMax Idss IQlp
Power bridges operating specifications
Description Bridge 1 and 2 diagonal Ron Bridge 3 and 4 diagonal Ron Bridge 1 and 2 max operative current Bridge 3 and 4 max operative current Output leakage current. Output leakage current in "Low Power Mode" Tjunction = 125C VSupply = 36V, Tjunction = 125C MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 MtrXSideYILimSel[1:0]=10 MtrXSideYILimSel[1:0]=11(2) MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 MtrXSideYILimSel[1:0]=10 MtrXSideYILimSel[1:0]=11(2) -50 -10 0.6 1.4 2.4 2.4 0.7 1.5 2.5 2.5 Test condition I = 1.4A, VSupply = 36V, Tjunction = 125C I = 1A, VSupply = 36V, Tjunction = 125C Min Typ Max Unit 1.0 1.5 2.5 1.5 +50 +10 1.6 2.6 3.6 3.6 1.7 2.7 3.7 3.7 2.5 2.5 5 5 MtrXIlimitOffTimeY[1:0]=00 MtrXIlimitOffTimeY[1:0]=01 MtrXIlimitOffTimeY[1:0]=10 MtrXIlimitOffTimeY[1:0]=11(5) VSupply = 36V, Resistive load between outputs: R= 25 Ohm(6) VSupply = 36V, Resistive load between outputs: R= 36 Ohm(6) VSupply = 36V, Resistive load between outputs: R= 25 Ohm(6) 100 60 120 240 480 250

A A A A
IprotL_1&2
Low side current protection for bridges 1 & 2(1)
A
IprotH_1&2
High side current protection for bridges 1 & 2(1)
A
Iprot_3 Iprot_4 tfilter tdelay
Low side current protection for bridges 3 & 4(1) High side current protection for bridges 3 & 4(1) Current limit filter time Current limit delay time
MtrXSideYILimSel[1:0]=11(3)(4) 1.55 MtrXSideYILimSel[1:0]=11(3)(4) 1.6 2
A A us us ns ns ns ns ns
toc_off
Over current off time
tr1_2
Output rise time bridges 1 &2 Output rise time bridges 3 & 4 Output fall time bridges 1 & 2
tr3_4
50
200
ns
tf1_2
100
250
ns
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SABRE-LL-I Table 29.
Parameter
Power bridges Power bridges operating specifications (continued)
Description Output fall time bridges 3 & 4 Anti crossover rising dead time Anti crossover falling dead time Operating frequency Delay from PWM to output transition Test condition VSupply = 36V, Resistive load between outputs: R= 36 Ohm(6) Min Typ Max Unit
tf3_4
50
250
ns
tdeadRise tdeadFall Fpwm tresp
100 100 Fosc /512 500
450 450
ns ns kHz ns
1. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The protection is performed by switching off the output bridge when current reaches values higher than the Iprot max. No protection could be guaranteed for values in the middle range between Ioperative max and Iprot. 2. In this cell X stands for 1 or 2, Y stands for A or B 3. In this cell X stands for 3 or 4, Y stands for A or B 4. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value (MtrXSideYILimSel[1:0]= 11) is available. 5. Over Current Off time can be configured using SPI. 6. Rise and fall time are measured between 10% and 90% of supply voltage. With device in full bridge configuration (resistive load between outputs).
14.3
Possible configurations
The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0] bits in the MtrXCfg register. The table below shows the correspondence between MtrXTable[1:0] bits and the bridge configuration. Table 30. Bridge selection truth
MtrXTable[0] 0 1 0 1 Bridge truth Full bridge configuration High or low side switch configuration Half bridge configuration High or low side switch configuration
MtrXTable[1] 0 0 1 1
Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register: Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B paralleled form SuperHalfBridgeX or SuperSwitchX. Bridge 3 & 4 can be configured by means of Mtr3_4CfgTable[1:0] bits in the Mtr3_4Cfg register according to following table:
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Power bridges Table 31. Bridge 3 and 4 configuration
Mtr3_4CfgTable[0] 0 1 0 1
SABRE-LL-I
Mtr3_4CfgTable[1] 0 0 1 1
Bridge 3 and 4 configuration Two independent bridges Two bridges in parallel Stepper motor Stepper motor
The possible configurations for the bridges are described in the following:
14.3.1
Full bridge
When in full bridge configuration, the drivers will behave according to the following truth table: Table 32.
TSD 1 0 0 0 0 0 0 0 0 0 0
Full bridge truth
Low power mode X X 1 0 0 0 0 0 0 0 0 Enable X X X 0 1 1 1 1 1 1 1 Current MtrXCtrl MtrXCtrl limit SideA SideB X X X X 1 0 0 0 0 0 0 X X X X X 0 0 0 1 1 1 X X X X X 0 1 1 0 0 1 PWM X X X X X X 0 1 0 1 X OUT+ Z Z Z Z Z 0 1 0 1 1 1 OUTZ Z Z Z Z 0 1 1 1 0 1
nRESET X 0 1 1 1 1 1 1 1 1 1
Note: When "Low Power mode" is active, the bridges will enter in low power state and will reduce its biasing thus contributing to the power saving. When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the toff time.
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Power bridges
14.3.2
Parallel configuration (super bridge)
Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. In this configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase -. Figure 14. Super bridge configuration
Parallel Full Bridge
Super Bridge
Bridge 1 (3)
PH PH
Bridge 2 (4)
PH
PH
+
-
-
+
M
When this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and status bits (direction, PWM, ...): i.e. the used PWM signal will be chosen by Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI. If the bridges are not configured to be used in parallel, each side of the bridge will use the PWM selected by the respective MtrXPWMYSel[1:0] bits in the SPI, but if one of the two drivers is configured as a full bridge only one of the two selected PWM will be used to drive the motor and this is the PWM chosen for side A. In order to avoid any problem coming from different propagation times of PWM signals the anti-crossover dead times are slightly increased when the bridges are paralleled.
14.3.3
Half bridge configuration
Each bridge can be configured to be used as 2 independent half bridges or as 1 super half bridge (see Figure 15). It is also possible to parallel more than one bridge and use all of them as a single super half bridge.
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Power bridges Figure 15. Half bridge configuration
SABRE-LL-I
V Supply
V pump
High side Driver
Control Signals From SPI
DCX Phase output
Control Logic
In this case each half bridge will behave according to the following truth table. Table 33.
TSD 1 0 0 0 0 0 0 0 0
Half bridge truth
nReset X 0 1 1 1 1 1 1 1 Low power mode X X 1 0 0 0 0 0 0 Enable X X X 0 1 1 1 1 1 Current limit X X X X 0 0 0 0 1 MtrXCtrl SideA/B X X X X 0 0 1 1 X PWM X X X X 0 1 0 1 X OUT Z Z Z Z Z 0 Z 1 Z
Note: When "Low Power mode" bit is active the bridges will reduce its biasing thus contributing to the power saving. When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the toff time.
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Signals
Low side Driver
Fault
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Power bridges
14.3.4
Switch configuration
Each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground. It is also possible to parallel the two switches and use them as a single super switch. All resulting switches will behave according to the following truth table. Table 34.
TSD 1 0 0 0 0 0 0 0
Switch truth
nReset X 0 1 1 1 1 1 1 Low power mode X X 1 0 0 0 0 0 Enable X X X 0 1 1 1 1 Current limit X X X X 0 0 0 1 MtrXCtrl SideA/B X X X X 0 1 1 X PWM X X X X X 0 1 X OUT Z Z Z Z Z 1 0 Z
Note: When "Low Power mode" bit is active the bridge will reduce its biasing thus contributing to the whole power saving. When a current limit event occurs this event will be latched and the bridge will remain in high impedance state for the toff time.
14.3.5
Bipolar stepper configuration
The bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver for bipolar stepper motors. The primary features of the driver are the following: - - - Internal PWM current control. Micro stepping. Fast, mixed and slow current decay modes.
Each H-bridge is controlled with a fixed and selectable off-time PWM current-control circuit that limits the load current to a value set by choosing VSTEPREF voltage by means of the internal DAC and an the external RSENSE value. The max current level could be calculated using the formula: IMAX=VSTEPREF/RSENSE To obtain the best current profile, the user can choose three different current decay modes: slow, fast and mixed. Initially, during Ton, a diagonal pair of source and sink power MOS is enabled and current flows through the motor winding and the sense resistor. When the voltage across the sense resistor reaches the programmed DAC output voltage, the control logic will change the status of the bridge according to the selected decay mode (slow, fast or mixed). In slow decay mode the current is recirculated through the path including both high side power MOS for the whole toff time. In fast decay mode the current is recirculated through the high and low side power MOS opposite respect to those forcing current to
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Power bridges
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increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition. Additionally, by setting the SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the fast decay percentage in mixed mode always or only when the current is decreasing (i.e from 90 to 180 and from 270 to 360 of the sinusoidal wave). By using SPI interface the user can choose:

Control type (external firmware control, half step, normal drive, wave drive, micro-step). Up to 16 current levels (quasi-sinusoidal increments) for each bridge. Current direction. Decay mode. Blanking time. Off time (32 values from 2s to 64s). Percentage of fast decay respect to toff (when in mixed decay mode).
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SABRE-LL-I Figure 16. Bipolar stepper configuration
Power bridges
DC3_PHDC3SENSE
V supply
DC3_PH+
Stepper Motor
VRefA
Supply
DC4 PHSupply
PH-
PH+
PH-
PH+
DC4 PH+
Sense
Sense
Bridge Driver
- Control Logic - Toff generation - DAC reference selection
Bridge Driver
Ref1 V STEPREF Ref2 VRefA
VRefB
DC4SENSE
StepperDACPhA SelStepRef StepperDACPhB VRefB
The operating characteristics remain the same (when applicable) already seen in the power bridges operating specifications with the addition of the following: Table 35.
Parameter VSTEPREF Sense_off
Stepper specifications
Description Reference voltage Sense comparator offset Test condition SelStepRef =0 SelStepRef =1 Min Typ Max 0.520 0.780 12 Unit V mV
0.480 0.50 0.720 0.75 -12
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Using the StepCtrlMode[2:0] bits in StepCfg1 register, S.A.B.Re can be programmed to internally generate the stepping levels. In these cases and depending on the StepFromGpio bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd bit is set at logic level "1" or at each pulse transition longer than ~1s externally applied on GPIO12 (StepReq signal), according to following table: Table 36. Sequencer drive
StepFromGpio 0 1 Sequencer driven by StepCmd bit in StepCmd register. GPIO12 input pin.
The allowable control modes are as follows: 1. 2. Stepping sequence left to external microcontroller: in this mode the current level in each motor winding is set by the microcontroller via the serial interface. Full step: in this mode the electrical angle will change by 90 steps at each StepReq signal transition. There are two possibilities: - Normal step (two phases on): in normal step mode both windings are energized simultaneously and the current will be alternately reversed. The resulting electrical angles will be 45, 135, 225 and 315. Wave drive (one phase on): In wave drive mode each winding is alternately energized and reversed. The resulting electrical angles will be 90, 180 and 270 and 360.
-
3.
Half step: in this mode, one motor winding is energized and then two windings alternately so the electrical angles the motor will do when rotating in clockwise direction and using the same current limit in both the phases are: 45, 90, 135, 180, 225, 270, 315 and 360. Microstepping: in this mode the current in each motor winding has a quasi sinusoidal profile. The increment between each step is obtained at each transition of StepCmd bit in StepCmd register. The difference between each step could be chosen (4, 8 or 16 levels for each phase) according to following table: Stepper mode
Control mode No Control Half Step Normal Step Wave Drive 1/4 Step 1/8 Step 1/16 Step Description Stepping sequence control left to the external controller Half step Full step (two phases on) Full step (one phase on) Four micro steps Eight micro steps Sixteen micro steps
4.
Table 37.
StepCtrlMode[2:0] 000 or 111 001 010 011 100 101 110
Note: When in 1/16 step mode, the best phase approximation of sinusoidal wave, is obtained by repeating the "F" step as follows: 0, 1, 2, 3, ... , D, E, F, F, F, E, D, ... , 3, 2, 1, 0
When internal stepping sequence generation is used, the stepping direction is set by the StepDir bit according to the following table.
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SABRE-LL-I Table 38. Stepper sequencer direction
StepDir 0 1 Direction Counter Clockwise (CCW) Clockwise (CW)
Power bridges
Note: It is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase.
An internal DAC is used to digitally control the output regulated current. The available values are chosen to provide a quasi sinusoidal profile of the current. The current limit in each phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B. The table below describes the relation between the value programmed in the stepper DAC and the current level: Table 39. DAC
Phase Current ratio respect to IMAX PhXDAC [3:0] Min 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 7.8 17.5 27.0 36.3 45.1 53.6 61.4 68.7 75.3 81.1 86.2 90.4 93.7 96.5 Typ (Hi-Z) 9.8 19.5 29.0 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 IMAX 11.8 21.5 31.0 40.3 49.1 57.6 65.4 72.7 79.3 85.1 90.2 94.4 97.7 99.7 % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX Max Unit
Note: The Min and Max values are guaranteed by testing the percentage of VSTEPREF that allows the commuatation of the Rsense comparator. IMAX=VSTEPREF/ RSENSE. To obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the final (100%) value. So the full values sequence should be as follows: 0, 1, 2, 3 ... D, E, F, F, F, E, D ... 3, 2, 1, 0. Even if the total spread shows overlapping between current steps, the monotonicity is guaranteed by design.
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When the internal sequencer the minimum angle resolution is nominally 5.625, so depending on the control mode chosen, the selectable steps are the following: Table 40. Internal sequencer
Control mode Typical output current (% of IMAX ) 1/8 step 1/16 step Resulting electrical angle Electrical degrees 45 50.6 56.2 61.9 67.5 73.1 78.8 84.4 90 95.6 101.2 106.9 112.5 118.1 123.8 129.4 135 140.6 146.2 151.9 157.5 163.1 168.8 174.4 180 185.6 191.2 196.9
Half step 1
Full step (2 phases on) 1
Full step (1 phase on)
1/4 step
Phase A (sin)
Phase B (cos) 70.7 63.4 55.6 47.1 38.3 29.0 19.5 9.8 HiZ -9.8 -19.5 -29.0 -38.3 -47.1 -55.6 -63.4 -70.7 -77.3 -83.1 -88.2 -92.4 -95.7 -98.1 -100 -100 -100 -98.1 -95.7
1
1
1 2
70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 100 98.1 95.7 92.4 88.2 83.1 77.3 70.7 63.4 55.6 47.1 38.3 29.0 19.5 9.8 HiZ -9.8 -19.5 -29.0
2
3 4
2
3
5 6
4
7 8
2
1
3
5
9 10
6
11 12
4
7
13 14
8
15 16
3
2
5
9
17 18
10
19 20
6
11
21 22
12
23 24
4
2
7
13
25 26
14
27 28
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SABRE-LL-I Table 40. Internal sequencer (continued)
Control mode
Power bridges
Typical output current (% of IMAX ) 1/8 step 1/16 step
Resulting electrical angle Electrical degrees 202.5 208.1 213.8 219.4 225 230.6 236.2 241.9 247.5 253.1 258.8 264.4 270 275.6 281.2 286.9 292.5 298.1 303.8 309.4 315 320.6 326.2 331.9 337.5 343.1 348.8 354.4 360/0 5.6 11.2
Half step
Full step (2 phases on)
Full step (1 phase on)
1/4 step
Phase A (sin)
Phase B (cos) -92.4 -88.2 -83.1 -77.3 -70.7 -63.4 -55.6 -47.1 -38.3 -29.0 -19.5 -9.8 HiZ 9.8 19.5 29.0 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 100 98.1
8
15
29 30
-38.3 -47.1 -55.6 -63.4 -70.7 -77.3 -83.1 -88.2 -92.4 -95.7 -98.1 -100 -100 -100 -98.1 -95.7 -92.4 -88.2 -83.1 -77.3 -70.7 -63.4 -55.6 -47.1 -38.3 -29.0 -19.5 -9.8 HiZ 9.8 19.5
16 3 5 9 17
31 32 33 34
18
35 36
10
19
37 38
20
39 40
6
3
11
21
41 42
22
43 44
12
23
45 46
24
47 48
7
4
13
25
49 50
26
51 52
14
27
53 54
28
55 56
8
4
15
29
57 58
30
59
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Power bridges Table 40. Internal sequencer (continued)
Control mode Typical output current (% of IMAX ) 1/8 step 1/16 step
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Resulting electrical angle Electrical degrees 16.9 22.5 28.1 33.8 39.4
Half step
Full step (2 phases on)
Full step (1 phase on)
1/4 step
Phase A (sin)
Phase B (cos) 95.7 92.4 88.2 83.1 77.3
60 16 31 61 62 32 63 64
29.0 38.3 47.1 55.6 63.4
The voltage spikes on Rsense could be filtered by selecting an appropriate blanking time on the output of Current sense comparator. The Blanking time selection is made by using the StepBlkTime[1:0] bits in the StpCfg1 register, according to following table: Table 41. Blanking times specification
Blanking time StepBlkTime[1] 0 0 1 1 StepBlkTime[0] Min 0 1 0 1 0.6 0.95 1.5 3 Typ 0.95 1.4 2.25 4.25 Max 1.2 1.85 3 5.5 us us us us Default value Unit Comments
The stepper driver toff time could be programmed by means of the StepOffTime[4:0] bits in StpCfg1 register: Table 42. Stepper off time
Off time StepOffTime[4:0] Typ 00000 00001 00010 00011 00100 00101 00110 00111 01000 2 4 6 8 10 12 14 16 18 us us us us us us us us us Unit
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SABRE-LL-I Table 42. Stepper off time (continued)
Off time StepOffTime[4:0] Typ 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64
Power bridges
Unit us us us us us us us us us us us us us us us us us us us us us us us
By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of Toff time during which each phase will stay in fast decay mode could be programmed according to following table:
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Power bridges Table 43. Stepper fast decay
MixDecPhX[4:0] Fast decay percentage during toff Typ 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 1xxxx 0 6.25 12.5 18.75 25 31.25 37.6 43.75 50 56.25 62.5 68.75 75 81.25 87.5 93.75 100
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Unit
% % % % % % % % % % % % % % % % %
14.3.6
Synchronous buck regulator configuration
Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as a single high current synchronous buck regulator using GPIOs pins in order to close the voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control loop using an internally generated PWM signal. The voltage will be set externally with a divider network and PWM duty cycle that can be programmed in order to ensure a proper regulation. The regulator will be enabled/disabled using serial interface and will implement a soft start strategy similar to that used by primary switching regulator.
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SABRE-LL-I Here after are summarized the primary features of the regulator(s): - - - - - - - - Synchronous rectification
Power bridges
Automatic low side disabling when current in the inductance reaches 0 to optimize efficiency at low load Pulse skipping control Internally generated PWM Cycle by cycle current limiting using internal current sensor Protected against load short circuit Soft start circuitry Under voltage signal (both continuous and latched) accessible through serial interface.
Figure 17. Regulator block diagram
V supply
CurrentSense
Charge pump Voltage
High Side Driver
Half Bridge OUT
La Ra
V out
Low Side Driver
From Central Logic
C
Bridge Sense
Voltage Loop Control
Control Logic
Vref=3V N.C. N.C. Vref= 0.8V Regulator Freq
+
GPIO USED as FB
Rb
Regulator Ref
SelFBRef Obtained using spare analog /digital blocks
To Central Logic
Filter
+
Under voltage Threshold
Depending on the load current, there could be the necessity to add a Schottky diode on output to reduce internal thermal dissipation. This diode must be placed near to the pin and must be fast recovery and low series resistance type. For detail about pulse skipping please refer to main switching regulator paragraph. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error S.A.B.Re has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under-voltage thresholds) using serial interface. The feedback reference voltage is selected
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by writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers according to the following table: Table 44. Switching regulator controller PWM specification
Reference voltage (VFBREF) Comments SelFBref[1] 0 0 1 1 SelFBref[0] 0 1 0 1 Min 0.776 0.970 2.425 2.910 Typ 0.8 1 2.5 3 Max 0.824 1.030 2.575 3.09 Unit V V V V Default voltage for AUX1 Default voltage for AUX2
SelFBRef[1:0]
The switching regulators have four possible PWM duty cycles that can be changed using SPI according to following table: Table 45. Pwm specification
Typical duty cycle value 10% 13% 24% 61% Default state for AUX1 Default state for AUX2 Comments
AuxXPWMTable[1:0] 00 01 10 11
The operating characteristics remain the same (when applicable) already seen in the Section 15.2 with the addition of the following: Table 46.
Parameter VAUX_SW IQ IQlp IQfb Vout Iload RonH Vloop VregR VuvFall VuvRise
Operating specification
Description Output pin voltage range Output leakage current Output leakage current in "Low Power Mode" GPIO feedback pin current Output voltage range Output load current Internal high/low side RDSon Loop voltage accuracy Output voltage ripple (RMS) Under voltage falling threshold Under voltage rising threshold L = TBD, C = TBD/ESR=TBD m(3)
(4)
Test condition
(1)
Min -1 -50 -10 -10 0.8 0.002
Typ
Max VSupply +50 +10 +10 30 1.5 0.8
Unit V A A A V A
Tjunction = 125C VSupply = 36V Tjunction = 125C Tjunction = 125C 0VFeedback 3V VSupply = 36V(2) VSupply = 36V Tjunction = 125C Iload=1A
3% TBD 84.5 90.5 87 93 89.5 95.5 mVRMS % %
(4)
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SABRE-LL-I Table 46.
Parameter Vuvhys taux_uv Ilimit tdeglitch tI_lim tI_limUV tr tf tdead FregPwm
Power bridges Operating specification (continued)
Description Under voltage hysteresis Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition. Switching output rise time Switching output fall time Crossover dead time Operating frequency In normal operating mode (no UV)(5) When in Under Voltage(6) VSupply = 36V, Resistive load to gnd: R=422 (7) VSupply = 36V, Resistive load to gnd = 10 (7) 5 10 100 Fosc/64 1.6 50 700 500 30 50 Test condition Min Typ 6 5 2.5 Max Unit % s A ns ns ns ns ns ns kHz
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb. 3. The choice of proper values for L and C depends from the application. 4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 5. This condition is intended to simulate an extra current on output. 6. This condition is intended to simulate a short circuit on output. 7. Rise time is measured between 10% and 90% of supply voltage.
14.3.7
Regulation loop
As seen before S.A.B.Re contains 2 regulation loops for switching regulators that are used when bridge 3 is used as a regulator. These loops are assembled using internal comparators and filters similar to that used in main switching regulator. When bridge 3 is not used for this purpose or when only one regulation loop is needed, the control loop is available on a GPIO output thus enabling the customer to assembly a basic buck switching regulator using an external Power FET. The comparators used in the above mentioned regulation loops are general purpose low voltage (3.3 V) comparators; when the relative regulation loop is not used they can be accessed as shown in the diagram here below:
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Power bridges Figure 18. Internal comparator functional block diagram
SABRE-LL-I
GPIOx
GPIOy
GPIOx DECODE LOGIC
GPIOy DECODE LOGIC
GPIOyMode
GPIOxMode
+
GPIOz Value From SP GPIOzMod e
GPIOz DECODE LOGIC
The functionality of this circuit is obtained by using the bridge 4 output stage. This circuit is powered directly from VSupply and it is intended to be used as a battery charger or a switching regulator. The control loop block diagram is shown in the following figure: Figure 19. Battery charger control loop block diagram
-
V 3v3
GPIOz GPIOz Logic Driver
SABRE
IREF_FB
COMP_I VREF_FB
COMP_V
DIFF AMPLI
PULSE SKIPPING BURST CONTROL LOGIC PEAK CURRENT MODE CONTROL LOGIC
PWM BRIDGE 4 PARALLELED POWER STAGE
DC4_plus DC4_minus
TO LOAD
Ilimit
FBRef SelFBRef<1:0> CurrRef SelCurrRef<1:0>
The battery charger control loop implements an asynchronous switching regulator intended to be used as a constant voltage/constant current programmable source.
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SABRE-LL-I
Power bridges When used as a simple switching regulator, it could be a system regulator depending on startup configurations When a system regulator under-voltage event is detected S.A.B.Re will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks.
Battery charger regulator application (CC-CV).
When the control loop is intended to be used as a battery charger, the Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. This is because in this case the undervoltage event that will be sure present when charging a battery (see next battery charger profile) will not be considered during start up sequence.
Voltage regulation
The regulated output voltage will be externally set by a resistor divider network connected to VREF_FB pin. S.A.B.Re has the possibility to choose between four voltage references (and, as a consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef[1:0] bits in the Aux3SwCfg1 register according to the table here below: Table 47. Battery charger control loop FBRef specification
Reference voltage (FBRef) Comments SelFBref[1] 0 0 1 1 SelFBref[0] 0 1 0 1 Min 1.370 1.746 2.079 2.425 Typ 1.412 1.8 2.143 2.5 Max 1.455 1.854 2.207 2.575 Unit V V V V Default state
Aux3SwCfg1
Reference voltages values can be changed using a metal layer change in order to adapt them to customer system. The first, second and third reference voltage has been chosen to regulate 3.3V, 4.2V and 5V with the same resistor divider network, such that the commutation between different regulated voltages can be done on the fly in the application.
Current regulation
The regulation of the output current can be done externally, by using a sense resistor connected in series on the path that provides current to the load. By using an external differential amplifier the customer can set the desired V=f(I) characteristic, and therefore the regulated current: the voltage provided at the IREF_FB pin will be compared to the internal reference. S.A.B.Re has the possibility to choose between four voltage references using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register according to the following the table:
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Power bridges Table 48. Battery charger control loop CurrRef specification
Reference voltage (CurrRef)
SABRE-LL-I
Aux3SwCfg1 SelCurrRef[1] SelCurrRef[0] 0 0 1 1 0 1 0 1
Comments Min 0.873 1.394 1.746 2.182 Typ 0.900 1.437 1.8 2.25 Max 0.927 1.480 1.854 2.318 Unit V V V V Default state
Adjustable reference voltages values can be changed using a metal layer change in order to adapt them to customer system. Regardless of the CurrRef voltage, if the IREF_FB pin remains below the chosen threshold, the internal current limitation will work (see DC motor paragraph, Bridge4 Ilimit).
Battery charge profile
The battery charge profile can be chosen by fixing the desired CurrRef and FBRef internal reference voltages and by choosing the desired V=f(I) trans-characteristic of the external differential amplifier. The following is a typical Li-Ion battery charge profile: Figure 20. Li-ion battery charge profile
Voltage or Current
Veochrg Blue=Battery Voltage Vchrg Ichrg CurrRef depending Red=Battery Current FBRef depending
Iprechrg Ieochrg Time Precharge phase Rapid charge phase Constant V. phase End Of Charge
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SABRE-LL-I
Power bridges
Simple buck regulator application
The battery charge loop control can be used to implement a buck type switching regulator. The regulated output voltage will be externally set by a resistor divider network connected to VREF_FB pin, as already described in voltage regulation section, and the current protection will be the one implemented internally in the Bridge4 section. Figure 21. Simple buck regulator
SABRE
IREF_FB
COMP_I
VREF_FB
COMP_V
PULSE SKIPPING BURST CONTROL LOGIC PEAK CURRENT MODE CONTROL LOGIC
PWM BRIDGE 4 PARALLELED POWER STAGE
DC4_plus DC4_minus
TO LOAD
Ilimit
FBRef SelFBRef<1:0> CurrRef SelCurrRef<1:0>
When this control loop is intended to be used as a simple buck regulator, the proper Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. The regulator will also implement a soft start strategy. When S.A.B.Re "Low Power mode" is enabled this regulator will be disabled. Here after are summarized the primary features of the regulator: - - - - - - - - Internal power switch. Nonlinear pulse skipping control. Internally generated PWM (250 KHz switching frequency). Cycle by cycle current limiting using internal current sensor/ external current sense differential amplifier. Protected against load short circuit. Soft start circuitry to limit inrush current flow from primary supply. Under voltage signal (both continuous and latched) accessible through SPI. Over temperature protection.
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In pulse skipping control PWM the duty cycle must be decided by the user depending on supply voltage and regulated voltage. Therefore the switching regulator has 4 possible PWM duty cycles that can be changed writing in the Aux3PWMTable[1:0] bits in the Aux3SwCfg1 register according to the following table. Table 49. Battery charger regulator controller PWM specification
Typical duty cycle value 10% 13% 24% 61% Default state Comments
Aux3PWMTable [1:0] 00 01 10 11
Adjustable duty cycles can be changed using a metal layer change in order to adapt it to customer system. The only limitation is that ALL regulators share the same duty cycle bus, so any modification must consider ALL regulators needed duty cycles.
AUX3 Control loop parameters specifications
The following table assumes that DC4_PLUS and DC4_MINUS pins are externally shorted together. Table 50.
Parameter VAUX_SW IQ
Battery charger operating specification
Description Output pin voltage range Output leakage current Output leakage current in "Low Power Mode" GPIo feedback pin current Output voltage range Output load current Internal high/low side RDson Loop voltage accuracy Output voltage ripple (RMS) Under voltage falling threshold Under voltage rising threshold L = TBD, C = TBD,ESR=TBD m(3)
(4)
Test condition
(1)
Min -1 -100
Typ
Max VSupply +100
Unit V A
Tjunction = 125C VSupply = 36V Tjunction = 125C Tjunction = 125C 0V=Feedback=3V VSupply = 36V(2) VSupply = 36V Tjunction = 125C Iload=1.5A
IQlp
-20
+20
A
IQfb Vout Iload RonH Vloop VregR VuvFall VuvRise
-10 1.412 0.002
+10 30 3 0.4 3% TBD
A V A
mVRMS 89.5 95.5 % %
84.5 90.5
87 93
(4)
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SABRE-LL-I Table 50.
Parameter Vuvhys taux_uv Ilimit tdeglitch tI_lim tI_limUV tr tf tdead FregPwm
Power bridges Battery charger operating specification (continued)
Description Under voltage hysteresis Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition. Switching output rise time Switching output fall time Crossover dead time Operating frequency In normal operating mode (no UV)(5) When in Under Voltage(6) VSupply = 36V, Resistive load to gnd = 422 (7) VSupply = 36V, Resistive load to gnd = 10 (6) 5 10 100 Fosc/64 3.1 50 700 500 30 50 Test condition Min Typ 6 5 5.3 Max Unit % s A ns ns ns ns ns ns kHz
1. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. The regulated voltage can be calculated using the formula: VMAIN_SW = VFBREF *(Ra+Rb)/Rb. 3. The choice of proper values for L and C depends from the application. 4. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 5. This condition is intended to simulate an extra current on output. 6. This condition is intended to simulate a short circuit on output. 7. Rise time is measured between 10% and 90% of supply voltage.
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AD converter
SABRE-LL-I
15
15.1
AD converter
Overview
S.A.B.Re integrates and makes accessible via SPI a general purpose multi-input channel 3.3V analog to digital converter (ADC). The ADC can be configured to be used as: - - 8-bit resolution ADC. 9-bit resolution ADC.
The result of the conversion will always be a 9-bit word; the difference between the two configurations is that, to speed up the conversion, the resolution is reduced when the ADC is used in the 8-bit resolution mode. The ADC is seen at software level as a 2 channel ADC with different programmable sample times; a finite state machine will sample the requests done through the SPI interface on both the channel and will execute them in sequence. When used as 8-bit resolution the ADC can achieve a higher throughput and, if the minimum sample time is used, one conversion is completed in t = 5.5s. When used as 9-bit resolution ADC the circuit is slower and the minimum sample times are disabled. In that case the conversion will be completed in a time t= 10 s The use of ADC type must be decided at the start-up by writing in the one time programmable ADC configuration register; no A/D conversion will be enabled if this register is not set from last power-up sequence. This ADC can be used to measure some external pins as well as some S.A.B.Re's internal voltages. The converter is based on a cyclic architecture with an internal sample-and-hold circuit. Sample time can be changed using serial interface to enable good measure of higher impedance sources.
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SABRE-LL-I Figure 22. A2D block diagram
Analog Mux
AD converter
V supply V pump V 3v3 VLINmain VSWmain
SWDRV_FB
FB FB
GPio[13:0] V psw CurrDac
Temp Senso
Sample Tim e 1 SampleTime 0
S&H
A2D
A2DEnabl
Conversion Done 0 Conversion Done 1 Conversion Result
Conversion Address 1 Conversion Address 0
To SPI
The A2D system is enabled by setting the A2DEnable bit to `1' in the A2DControl register. The A2DType bit in the A2DConfigX registers selects the A2D active configuration (8-bit resolution or 9-bit) according to the following truth table: Table 51. ADC truth
A2DType0/1 X 0 1 A2D operation Disabled ADC working as a 8-bit ADC ADC working as a 9-bit ADC
A2DEnable 0 1 1
The multiplexer channel to be converted can be chosen by writing the A2DChannel1[4:0] or A2DChannel2[4:0] bits in the A2DConfigX register; the channel addresses table is reported in the following table.
A2DType0
A2DType1
Selected A2DType
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AD converter Table 52. Channel addresses
Converted channel VSupply scaled VSupplyInt scaled Vref_2_5V Temp Sensor1 Temp Sensor2 V3v3 scaled Not used Not used GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] clamp GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] MuxRefOpAmp1 MuxRefOpAmp2 OutStripStepperPhA OutStripStepperPhB Not used ST reserved ST reserved ST reserved Note
SABRE-LL-I
A2DChannelX[4:0] (bin.) 00000 00001 00010 00011 00100 00101 0011X 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
See voltage divider specification. See voltage divider specification.
Temperature sensor1 Temperature sensor2 See voltage divider specification.
See current DAC circuit
References AUX1 switching reg. 0.8V reference voltage 1.65V reference voltage
The sample time can be changed by modifying the A2DSampleX[2:0] bits in the A2DConfigX register; depending on which is the A2DType bit, the available sample times are reported in the following tables.
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SABRE-LL-I Table 53. ADC sample times when working as a 8-bit ADC
Sample time A2DSampleX[2:0] (binary) Typ 000 001 010 011 100 101 110 111 16*Tosc 32*Tosc 64*Tosc 128*Tosc 256*Tosc 512*Tosc 1024*Tosc 2048*Tosc
AD converter
Unit s s s s s s s s
Table 54.
ADC sample time when working as a 9-bit ADC
Sample time A2DSampleX[2:0] (binary) Typ 000 001 010 011 100 101 110 111 32*Tosc 64*Tosc 128*Tosc 256*Tosc 512*Tosc 1024*Tosc 2048*Tosc 4096*Tosc Unit s s s s s s s s
A conversion on channel 1 can be triggered by writing a logic `1' in the A2DTrig1 bit in the A2DConfigX register and a conversion on channel 2 can be triggered writing a logic `1' in the A2DTrig2 bit in the same register. While a request on a channel is pending but not yet completed S.A.B.Re will force to logic `0' the corresponding A2DdoneX bit in the A2DResultX registers and S.A.B.Re will not accept other conversion request on that channel. Continuous conversion on one channel can be accomplished by setting to logic `1' the A2DcontinuousX bit in the A2DConfigX register. When A2DcontinuousX bit is set, other conversions can be accomplished on the other channel; these conversions will be inserted between two conversions of the other channel and the end of the conversion will be signaled using A2DdoneX bit. Of course when a channel is in continuous mode its sample time and channel address cannot be changed. Continuous conversions on both 2 channels can be also accomplished by setting to logic `1' the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence.
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AD converter
SABRE-LL-I
15.2
A2D specification with A2dType=0
Table 55.
Parameter IMR INL DNL OE OEDrift GE GEDrift tconv
ADC specification
Description Measurement range Integral non-linearity Differential non-linearity Offset error Offset error drift Gain error Gain error drift Minimum conversion time Resolution
(7) (8)
Test condition A2dType = 0 A2dType = 0(2)(3) A2dType = 0(4)(3)
(5)
Min 0
Typ
Max Unit(1) V3v3 1 1 4 3 4 4 5.5 V LSB LSB LSB LSB LSB LSB s bits 4 pF
A2dType = 0
A2dType = 0 over time and temperature A2dType = 0(6) A2dType = 0 over time and temperature
8
Cin
Input capacitance
1. The definition of LSB for this table is LSB=IMRmax/(27.5-1). 2. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the "best straight line" approximating the ADC transfer curve. 3. The ADC ensures monotonic characteristic and no missing codes. 4. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1 LSB. 5. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB). 6. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 0.5 LSB), after adjusting for offset error. 7. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the ADC is used in the 8- bit resolution mode. 8. Actual input capacitance depends on the pin that must be converted.
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SABRE-LL-I
AD converter
15.3
A2D specification with A2dType=1
Table 56.
Parameter IMR INL DNL OE OEDrift GE GEDrift tconv
ADC specification
Description Measurement range Integral non-linearity Differential Non-Linearity Offset error Offset error drift Gain error Gain error drift Minimum conversion time Resolution 9
(7)
9
Test condition A2dType = 1 A2dType = 1(2)(3) A2dType = 1(4)(3)
(5)
Min 0
Typ
Max V3v3 1 1 4 3 4 4 10
Unit(1) V LSB LSB LSB LSB LSB LSB s bits
A2dType = 1
A2dType = 1 over time and temperature A2dType = 1(6) A2dType = 1 over time and temperature
Cin
Input capacitance
4
pF
1. The definition of LSB for this table is LSB=IMRmax/(2 -1). 2. Integral non linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the "best straight line" approximating the ADC transfer curve. 3. The ADC ensures monotonic characteristic and no missing codes. 4. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1 LSB. 5. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB). 6. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 0.5 LSB), after adjusting for offset error. 7. Actual input capacitance depends on the pin that must be converted.
15.4
Voltage divider specifications
As can be seen in the A2D block diagram, in order to report some voltages in the A2D working range, they are scaled with a resistor divider before the conversion. Here below are reported the resistor voltage divider specifications: Table 57.
Parameter RSupply_ratio RSupplyInt_rati
o
Voltage divider specification
Description VSupply divider ratio VSupply Int divider ratio V3v3 divider ratio Notes Min -10% -10% -10% Typ 1/15 1/15 1/2 Max +10% +10% -10% Unit
Rv3v3_ratio
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Current DAC circuit
SABRE-LL-I
16
16.1
Current DAC circuit
Overview
S.A.B.Re includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can be selected using the DacRange[1:0] bits in the CurrDacCtrl register. The output of this circuit is connected to GPIO[8] that is a 5V tolerant pin. The value of this pin can be converted using ADC. The pin value can be scaled before being converted by enabling the internal resistor divider connected to this pin. If the current sunk by resistor divider is not acceptable the pin voltage can be converted without scaling its value. When the conversion without scaling resistor is chosen a clamping connection is used to avoid voltage compatibility of the pin to the ADC system. The clamping circuit will sink a typical current of half microampere from the pin during the sampling time. Figure 23. Current DAC block diagram
Va3 Reference Current Generator
DacRange [1:0]
EnDac DacValue[5:0] DacRange [1:0]
Current Sink DAC
RCurrDac
Gpio[8]
Gpio8 Clamp (to ADC)
Clamp circuit
EnDac
A2DChannel1[4 :0] Combinatorial
Mask
Address Recognized Address Recognized EnDacScale Gpio[8] Digital Driver
A2DChannel2[4 Combinatorial :0]
Mask
The circuit is enabled by setting to logic `1' the EnDac bit in the CurrDacCtrl register then the desired sunk current value is chosen by changing the value of the DacValue[5:0] bits in the
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SABRE-LL-I
Current DAC circuit same register being DacValue[0] the least significant bit and DacValue[5] the most significant bit. The current DAC has three possible current ranges that can be selected using the DacRange[1:0] bits in the CurrDacCtrl register . The DAC range selection table is shown here below: Table 58. Current DAC truth
DacRange[0] 0 1 0 1 LSB typical current ILSB typ Disabled 10 A 100 A 1 mA Full scale typical current IFULL typ Disabled 0.63 mA 6.3 mA 63 mA
DacRange[1] 0 0 1 1
By changing LSB current value, all steps will change following this relation: Istep(N) = N * ILSB where N is the value of DacValue[5:0] bits. Table 59.
Parameter VR IOUT_OFF
Current DAC specification
Description Pin voltage operative range Output off leakage current Test condition
(1)
Min 0.7 -1 -10 -13 -12
Typ
Max 5.5 +1 10 13 12 2 2 1 1
Unit V A % of IFULL typ % of IFULL typ % of IFULL typ LSB LSB LSB LSB k
DacValue[5:0] = 000000 DacRange[1:0] =01 DacValue[5:0] = 111111 DacRange[1:0] =10 DacValue[5:0] = 111111 DacRange[1:0] =11 DacValue[5:0] = 111111
IFULL_ERR_01 Full scale current error IFULL_ERR_10 Full scale current error IFULL_ERR_11 Full scale current error INL10_11 DNL10_11 INL01 DNL01 RCurrDac_res Integral non-linearity for 10 and 11 ranges Differential non-linearity for 10 and 11 ranges Integral non-linearity for 01 range Differential non-linearity for 01 range Gpio[8] divider total resistance
-25%
45
+25%
RCurrDac_ratio Gpio[8] divider ratio tset Settling time
(2)
-2.5% 3/5 +2.5% 5 s
1. All parameters are guaranteed in the range between VOL and VR Max. 2. Measured from DacValue[5:0] change in SPI interface.
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Operational amplifiers
SABRE-LL-I
17
17.1
Operational amplifiers
Overview
S.A.B.Re contains two rail to rail output, high bandwidth internally compensated operational amplifiers supplied by VGPIO_SPI pin. The operative supply range is 3.3V4.5% Each operational amplifier can have all pin accessible or, to save pins, can be internally configured as a buffer. They can also be used as comparators; to do that the user must disable internal compensation by writing a logic level "1" in the OpXCompMode bit in the OpAmpXCtrl register. Here below are reported the block diagrams of the two operational amplifiers
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SABRE-LL-I Figure 24. Configurable 3.3V operational amplifiers
Operational amplifiers
GPIO[11]
Op1Ref[1:0]
Op1EnIntRef
Op1Plus Ref
V GPIO_SPI
Op1CompMode To A/D System
Op1EnPlusPin GPIO[9] GPIO[10] Op1BufConf Op1EnMinusPin
+ OpAmp 1 EnOp1
EnOp2 + + Op2CompMode
Op2BufConf
Op2EnMinusPin GPIO[13] GPIO[12] Op2EnPlusPin
V GPIO_SPI
Op2Plus Ref
Op2EnIntRef Op2Ref[1:0] GPIO[14]
Note:
Op1EnPlusRef and Op2EnPlusRef cannot be used to drive external pin so the user must be sure not to enable the path between one of these voltage references and the external pin. The operational amplifiers are capable to drive a capacitive load in buffer configuration up to a maximum of 100pF; for higher capacitance it is necessary to add resistive loads to increase the OP output current, and/or to add a low resistor (10 Ohm) in series to the load capacitance. The table here below describes the main operational amplifier parameters.
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Operational amplifiers
SABRE-LL-I
17.2
Operational amplifiers specifications
Table 60.
Parameter VGPIO_SPI VICM VOUT_MAX
Configurable 3.3V operational amplifier specification (Note: VGPIO_SPI=3.3V unless otherwise specified)
Description Supply voltage range Input common mode voltage range Output voltage Iload = 1mA Op1Ref[1:0]=00 Op1Ref[1:0]=01 Op1Ref[1:0]=10 Op1Ref[1:0]=11 Op2Ref[1:0]=00 Op2Ref[1:0]=01 Op2Ref[1:0]=10 Op2Ref[1:0]=11 VICM=1.65V Iload= 0mA Test condition Min 3.15 0 0.1 0.970 1 1.600 1.65 1.940 2 2.425 2.5 0.970 1 1.600 1.65 1.940 2 2.425 2.05 90 105 Iload= 6mA VICM=1.65V(1) 90 150 500 -5 Cload=100pF VICM=1.65V Rload=330 Ohm to VGPIO_SPI Vout=1.65V 12 Iload= 0 CLOAD=100pF 1.3 20 1.75 2 10 5 Typ Max 3.45 VGPIO_SP
I
Unit V V V
3.2 1.030 1.700 2.060 2.575 1.030 1.700 2.060 2.575
VOp1PlusRef
Operational amplifier 1 reference voltage
V
VOp1PlusRef
Operational amplifier 2 reference voltage
V
Open loop gain CMRR Common mode rejection ratio PSRR I in _offs I in _bias V in _offs GBWP Iout Ishort_max Slew Input offset current Input bias current Input offset voltage Gain bandwidth product Output current Short circuit current Slew rate
dB dB dB nA nA mV MHz mA mA V/s
1. VICM is the input common mode voltage.
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SABRE-LL-I
Operational amplifiers
17.3
Operational amplifiers used as comparators specifications
To use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register. Table 61.
Parameter VGPIO_SPI VICM VOUT_MAX Iin _offs Iin _bias Vin _offs Ishort_max tPHL
Configurable 3.3V operational amplifier used as comparator specification (Note: VGPIO_SPI=3.3V unless otherwise specified)
Description Supply voltage range Input Common Mode Voltage Range Output voltage Input offset current Input bias current Input offset voltage Short circuit current Output falling delay VCM = 1.65V Vi = -/+ 20mV CLOAD=100pF(1)(2) VCM = 1.65V Vi = -/+ 20mV CLOAD=100pF(1)(2) VCM = 1.65V Vi = -/+ 20mV CLOAD=100pF(1)(2) VCM = 1.65V Vi = -/+ 20mV CLOAD=100pF(1)(2) -5 12 20 1 Iload = 10mA Test condition Min 3.15 0 0.3 Typ Max 3.45 VGPIO_SPI 2.9 150 500 5 Unit V V V nA nA mV mA s
tFALL
Fall time
0.4
s
tPLH
Output rising delay
0.5
s
tRISE
Rise time
0.4
s
1. Vi is the differential voltage applied to input pins across the common voltage VCM. 2. Measured between 50% of input and output signal.
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Low voltage power switches
SABRE-LL-I
18
18.1
Low voltage power switches
Overview
Low voltage power switches are analog switches designed to operate from a single +2.4V to +3.6V VGPIO_SPI supply. They are intended to provide and remove power supply to low voltage devices. When switched on, they connect the VGPIO_SPI pin to their output pin (GPIO[6] for low voltage power switch 1 or GPIO[7] for low voltage power switch 2) thus powering the device connected to it. The turning on and off of each switch can be controlled through serial interface. S.A.B.Re provides a total of 2 low voltage power switches, each of them has current limitation to minimum 150mA to limit inrush current when charging a capacitive load. When the limit current has been reached, for more than a Tfilter time, then a flag is activated; this flag is latched in the central logic and can be cleared by the firmware. Please note that, in case of capacitive load, the current limit is reached the first time the low power switch is turned on: therefore the user will find a limit flag that must be cleared. The 2 low voltage power switches can be externally paralleled to obtain a single super low voltage power switch. Low voltage pass switches sink current IPASS needed for their functionality from pin VGPIO_SPI, they never inject current on this pin. Figure 25. Low power switch block diagram
V GPIO_SP
EnLowVSw[x]
Driving Circuit
GPIO[6] (LPS 1) or GPIO[7] (LPS 2)
Current Limit Sensor
LowVSwIlim[x] To SPI S LowVSwIlimLth[x] R
GPIO[6]/GPIO[7] Driver
ClrLowVrSwLth Reset Stat
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SABRE-LL-I Table 62.
Parameter VPSW VOUT_MAX RDSON ILIMIT tdeglitch tI_lim CLOAD tON
Low voltage power switches 3.3V low power switch specification
Description Input voltage range Output voltage On resistance Current limit Current limit deglitch time Current limit response time Max load capacitance On delay VGPIO_SPI=3.3V ILOAD=1mA CLOAD=100pF(1) VGPIO_SPI=3.3V ILOAD=1mA CLOAD=100pF(1) Iload=100mA 150 50 650 2.5 650 250 Test condition Min 2.4 Typ Max 3.6 VGPIO_SPI 1 350 Unit V V O mA ns ns F ns
tOFF
Off delay
450
ns
1. Time measured from change in SPI interface to 50% of external pin transition.
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General purpose PWM
SABRE-LL-I
19
19.1
General purpose PWM
Overview
S.A.B.Re includes three general purpose PWM generators that can be redirected on GPIO pins (see Chapter 23). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM) has a programmable base time clock and a programmable time for both high and low levels.
19.2
General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2)
The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits (where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty cycle will change according to the equation:
PWM_X_DUTY = AuxPwmXCtrl [ 9:0 ]/512
According to this equation a programmed "0" value will cause a 0% duty cycle (output always at logic level 0).
19.3
Programmable PWM generator (GpPwm)
GpPWM has a programmable base clock that can be changed by programming the GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the equation:
PWM_BASE_PERIOD = ( GpPwmBase [ 6:0 ] + 1 ) x Tosc
The high and low level duration (expressed in base clock periods), can be programmed writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will change according to following equations:
High_level_Time = GpPwmHigh [ 7:0 ] x PWM_BASE_PERIOD Low_level_Time = GpPwmLow [ 7:0 ] x PWM_BASE_PERIOD
The resulting period of the PWM will be:
Period = ( GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ] ) + PWM_BASE_PERIOD
and the positive duty cycle will result:
High_level_Time GpPwmHigh [ 7:0 ] DutyCycle = ---------------------------------------------------------------------------------------------- = -------------------------------------------------------------------------------------------------------High_level_Time + Low_level_Time GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ]
A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM generator output to be always at logic level "0".
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SABRE-LL-I
Interrupt controller
20
20.1
Interrupt controller
Overview
S.A.B.Re contains one programmable interrupt controller that can be used to advice the firmware, through the serial interface, when a certain event happens inside the IC. The output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can be signaled directly to the external circuits. Figure 26. Low power switch block diagram
IntCtrlAutoDisable EnIntCtrlPulse
DisableMonitor
Disable Pulse DisableSignals Generation logic
Decode logic
Monitored signals
Pulse Gen erator
To Gpio
Enable signal s
EnIntCtrl
IntCtrlPolarity
EnIntCtrlPulse
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Interrupt controller
SABRE-LL-I
20.2
Interrupt controller monitored signal
The table here below contains the events that can be monitored by the interrupt controller. Table 63. Interrupt controller event
Event description Bridge 1 fault (Ilimit event) Bridge 2 fault (Ilimit event) Bridge 3 fault (Ilimit event) Bridge 4 fault (Ilimit event) nAWAKE pin low Switching regulator controller Ilimit event. Main switching regulator Ilimit event. Low voltage power switch 1 Ilimit event. Low voltage power switch 2 Ilimit event Warming event Watch dog warning event Watch dog event Digital comparator ADC conversion done 1 ADC conversion done 2 AUX1 Ilimit event.
(1) (1)
Event Mtr1Fault Mtr2Fault Mtr3Fault Mtr4Fault nAWAKE SwRegCtrl Ilimit VMainSW Ilimit LowPowSw 1 LowPowSw 2 Warm WDWarn WD DigCmp ADCDone1 ADCDone2 Vloop1Ilim
Notes
1. This event is disabled if the related ADC channel is configured in continuous mode.
Any event detection can be enabled and disabled by setting at logic level 1 the relative enable bit in the interrupt controller configuration register (IntCrtlCfg). The interrupt controller can be programmed to give a pulse when a monitored event happens or to continuously maintaining the output active until the interrupt condition is finished. When programmed to signal the enabled events by giving pulses, the interrupt controller can be configured to disable the event that caused the interrupt request until the firmware re-enables it writing the relative bit in the control register (IntCrtlCtrl) or to continue to monitor the event. The GPIO output of this circuit can be programmed to be active high or active low. Table 64.
Parameter tPULSE tINTFILT
Interrupt controller specification
Description Pulse duration Filter time Test condition Min Typ 16*Tosc 200 Max Unit s ns
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SABRE-LL-I
Digital comparator
21
21.1
Digital comparator
Overview
S.A.B.Re includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other ADC channel. This circuit can be used to monitor the temperature of the IC advising the firmware when it reaches a certain value decided by the firmware by setting one ADC channel to do continuous conversions of the temperature sensor. The circuit operation can be enabled or disabled changing the EnDigCmp bit in the configuration register DigCmpCfg. By setting the DigCmpUpdate[1:0] bits in the configuration register, the comparator can be programmed to update its output in one of the following ways:

DigCmpUpdate[1:0]=00 - - - - Continuously (each clock). Each time a conversion is performed on ADC channel 0. Each time a conversion is performed on ADC channel 1. ADC state machine driven. DigCmpUpdate[1:0]=01 DigCmpUpdate[1:0]=10 DigCmpUpdate[1:0]=11
When the last option is selected, the digital comparator will update its output in two different ways depending on the configuration of the ADC converter. If ADC converter is configured to do continuous conversions on both channels, the output of the comparator will be updated when the double conversion is completed. If ADC converter is not configured to do continuous conversions on both channels, the output of the comparator will be updated each time a conversion is completed. The comparator output can be digitally filtered so that the programmed condition has to be found for three consecutive checks before to be signaled. The picture here below is a block representation of the comparator.
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Digital comparator Figure 27. Digital Comparator block diagram
SABRE-LL-I
A2DDone0
DigCmpValue [9:0]
A2DDone1
DigCmpSelCh0[1]
Logic `1'
ADC FSM Update Signal
A2DResult0[8:0]
DigCmpUpdate[1:0]
A2DResult1[8:0]
Three check s filter
DigCmpSelCh0[0]
Data0 [9:0]
DigCmpSelCh1[0]
CmpOut COMPARATOR
Data 1[9:0]
DigCmpSelCh1[1]
Here below is reported the comparison type truth table: Table 65. Comparison type truth
SelCmpType[1] X 0 0 1 1 SelCmpType[0] X 0 1 0 1 Comparison type Disabled Data0[9:0] 11/Data1[9:0] Data0[9:0] = Data1[9:0] Data0[9:0] > Data1[9:0] Data0[9:0] = Data1[9:0]
EnDigCmp 0 1 1 1 1
Here below is reported the Data0/Data1 selection truth table: Table 66. DataX selection truth
DigCmpSelChX[0] X 0 1 DataX[9:0] DigCmpValue[9:0] A2DResult1[8:0] A2DResult1[8:0]
DigCmpSelChX[1] 0 1 1
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SelCmpType[ 1:0]
EnDigCmp
SABRE-LL-I
GPIO pins
22
22.1
GPIO pins
Overview
Some of the pins of S.A.B.Re are indicated as GPIO (General Purpose I/O). These pins can be configured to be used in different ways depending on customer application. All GPIOs can be used as digital input/output pins with digital value settable/readable using serial interface or as analog input pins that can be converted using the A2D system. Some of the pins can be used for special purposes: i.e. two of them can be used to access to the pass switch function, other two are used as feedback pins for the auxiliary synchronous switching regulators. All input Schmitt triggers and output circuitry used for start-up purposes are powered by the internally generated V3v3, while the digital output buffers are powered by VGPIO_SPI pin. To ensure independency between V3v3 and VGPIO_SPI the GPIOs output drivers are open-drain driver or the high side MOS is in back-to-back configuration to avoid the presence of the body diode between output and supply (all back-to-back drivers can be customized to become open-drain drivers with a metal change). All digital output signals can be inverted before being provided on the relative GPIO pins. Here below is reported the table with GPIO functions:
Table 67.
Pin Name
GPIO functions description
Function(1) Input Analog Digital Analog Output Special Digital - SPI OUT - Interrupt ctrl. - AuxPwm1 - AuxPwm2 - SPI OUT - Interrupt ctrl. - AuxPwm1 - AuxPwm2 - SPI OUT - Interrupt ctrl. - AuxPwm2 - AuxPwm3 - SPI OUT - AuxPwm2 - AuxGpPwm3 - SPI OUT - Interrupt ctrl. - AuxPwm1 - AuxPwm3 Start-up Open drain configuration output pin Notes
GPIO[0]
- ADC input
- SPI IN
GPIO[1]
- ADC input - Comp1 In- Vaux1 F.B. - ADC input - Comp2 In- Vaux2 F.B.
- SPI IN
Open drain output
GPIO[2]
- SPI IN - IN PWM
Open drain output
GPIO[3]
- ADC input
- SPI IN
Start-up Open drain configuration output pin Start-up configuration Open drain output pin
GPIO[4]
- ADC input
- SPI IN
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GPIO pins Table 67.
Pin Name Analog
SABRE-LL-I GPIO functions description (continued)
Function(1) Input Digital Analog Output Special Digital - SPI OUT - Reg. loop 1 - Comp1 out - AuxPwm3 - SPI OUT - A2DGpo - AuxPwm2 - Comp2 out - SPI OUT - AuxPwm1 - AuxPwm3 - Comp1 out - SPI OUT - AuxPwm1 - AuxPwm3 - Comp2 out - SPI OUT - Interrupt contr. - AuxPwm1 - Reg. loop 3 - SPI OUT - Interrupt ctrl. - AuxPwm2 - AuxPwm3 - SPI OUT - A2DGpo - AuxPwm1 - AuxPwm2 - SPI OUT - Interrupt ctrl - Comp2 out - Reg. loop 2 Full driver BB powered by V3v3 Notes
GPIO[5]
- ADC input
- SPI IN
Slave Control
GPIO[6]
- ADC input
- SPI IN
- Low Pow Sw 1
Full driver connected to VGPIO_SPI
GPIO[7]
- ADC input
- SPI IN
- Low Pow Sw 2
Full driver connected to VGPIO_SPI
GPIO[8]
- ADC input
- SPI IN(2)
- CurrDAC
5 volt input tolerant
Open drain output
GPIO[9]
- SPI IN - ADC input - ID 1 - OpAmp1 in+ - IN PWM
Full driver connected to VGPIO_SPI
- SPI IN - ADC input GPIO[10] - ID 2 - OpAmp1 in- IN PWM
Full driver connected to VGPIO_SPI
GPIO[11] - ADC input
- SPI IN - IN PWM
- OpAmp1 Out
Full driver connected to VGPIO_SPI Full driver BB (can be powered by V3v3 with a metal change)
GPIO[12]
- ADC input - SPI IN - OpAmp2 in+ - STEP_REQ
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SABRE-LL-I Table 67.
Pin Name Analog
GPIO pins GPIO functions description (continued)
Function(1) Input Digital Analog Output Special Digital - SPI OUT - AuxPwm1 - Reg. loop 3 - AuxPwm3 - SPI OUT - Interrupt ctrl. - AuxPwm2 - AuxPwm3 Full driver connected to VGPIO_SPI Notes
- ADC input GPIO[13] - SPI IN - OpAmp2 in-
GPIO[14] - ADC input
- SPI IN
- OpAmp2 Out
Full driver connected to VGPIO_SPI
1. In the above table the following abbreviations were used. 2. Gpio[8] input Schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it needs to be enabled writing a logic `1' in the EnGpio8DigIn in CurrDacCtrl register.
Table 68.
Abbreviations
Meaning Input to the ADC system. Digital state of this pin is readable through SPI. Digital state of this pin can be set through SPI. Back to back high side driver. This pin can be used as minus input for comparator 1. This pin can be used as minus input for comparator 2. This pin can be used as feedback input for AUX1 regulator obtained by using bridge 3. This pin can be used to carry out the A2DGpo value related to the ADC conversion S.A.B.Re is doing. This pin can be used as output of the regulation loop used by AUX3 regulator obtained by using bridge 4. This pin can be used to request a stepper sequencer evolution step. This pin can be used to carry out the interrupt controller circuit output. This pin can be used as feedback pin by AUX2 regulator obtained by using bridge 3 This pin can be used to provide an external PWM to bridges. This pin can be used as output of the regulation loop used by AUX1 regulator. This pin can be used as output of the comparator 1. This pin can be used to carry out the PWM generated by AuxPwm1 circuit. This pin can be used as output of low voltage power switch 1.
Abbreviation ADC input SPI IN SPI OUT BB Comp1 IN Comp2 IN Vaux1 FB A2DGpo Reg. Loop 3 STEP_REQ Interrupt Ctrl Vaux2 FB IN PWM Reg. Loop 1 Comp1 OUT AuxPwm1 Low Volt. Pow. Sw. 1
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GPIO pins Table 68. Abbreviations (continued)
Meaning
SABRE-LL-I
Abbreviation Reg. Loop 2 Comp2 OUT AuxPwm2 Low Volt. Pow. Sw. 2 Reg. Loop 3 AuxPwm3 CurrDAC AuxPwm4 OpAmp1 in+ OpAmp1 inOpAmp1 Out OpAmp2 in+ OpAmp2 inOpAmp2 Out ID 1 ID 2 Slave Control
This pin can be used as output of the regulation loop used by AUX2 regulator. This pin can be used as output of the comparator 2. This pin can be used to carry out the PWM generated by AuxPwm2 circuit. This pin can be used as output of low voltage power switch 2. This pin can be used as output of the regulation loop used by AUX3 regulator. This pin can be used to carry out the PWM generated by AuxPwm3 circuit. This pin can be used to carry out the output of the current DAC circuit. This pin can be used to carry out the PWM generated by AuxPwm4 circuit. This pin can be used as operational amplifier 1 non-inverting input. This pin can be used as operational amplifier 1 inverting input. This pin can be used as operational amplifier 1 output. This pin can be used as operational amplifier 2 non-inverting input. This pin can be used as operational amplifier 2 inverting input. This pin can be used as operational amplifier 2 output. This pin is used to determine the SPI ID1 bit value. This pin is used to determine the SPI ID2 bit value. This pin is used as slave control when the IC is configured as master.
Hereafter are reported the detailed specifications for each GPIO. To enable the functionality of the GPIO as output pin, the relative GpioOutEnable[14:0] bit must be enabled in GpioOutEnable register. Each GPIO could be configured by setting the appropriate GpioXMode[2:0] in the GpioCtrlX register.
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GPIO pins
22.2
GPIO[0]
The GPIO[0] truth table is (for the abbreviation list please refer to Table 68): Table 69.
State at StartUp
GPIO[0] truth
GPIO[0] SPI BITS GpioOut Enable [0] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 Detection of StartUp config HiZ (SPI_IN) SPI OUT InterruptCtrl AuxPwm1 AuxPwm2 SPI OUT inverted InterruptCtrl inverted AuxPwm1 inverted AuxPwm2 inverted
(1) (1) (1) (1) (1) (1) (1) (1)
Note
1 0 0 0 0 0 0 0 0 0
See Chapter 8
1. In all configurations in which GPIO[0] is enabled as output: a) the GPIO[0] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[0] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[0] pin is an open drain output.
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GPIO pins Figure 28. GPIO[0] block diagram
SABRE-LL-I
V 3v3
To Serial Interface
To ADC
V 3v3
To Control Logic
Start up pin State Detect circuit V 3v3 V 3v3
GPIO[0]
From Serial Interface EnStartUpDtc From Power Up FSM
Logic Decode GPIO[0] Driver
Table 70.
Parameter VIH VIL VHYS VOL ILEAKAGE CLOAD tDELAY
GPIO[0] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Load capacitance Delay from serial write to pin Low CLOAD =50 pF(1) IOUT = 15mA 0 Vout V3v3 -1 0.22 0.4 1 200 500 Test condition Min 1.6 0.8 Typ Max Unit V V V V A pF ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.3
GPIO[1]
The GPIO[1] truth table is (for the abbreviation list please refer to Table 68): Table 71. GPIO[1] truth
GPIO[1] SPI BITS GpioOut Enable [1] X 0 0 1 1 1 1 1 1 1 1 Function Mode[2] X 0 1 0 0 0 0 1 1 1 1 Mode[1] X X X 0 0 1 1 0 0 1 1 Mode[0] X X X 0 1 0 1 0 1 0 1 AUX1 FB HiZ (SPI_IN) Comp1 IN SPI OUT AuxPwm1 AuxPwm2 InterruptCtrl SPI OUT inverted AuxPwm1 inverted AuxPwm2inverted IntCtrlinverted
(2) (2) (2) (2) (2) (2) (2) (2) (2) (1)
AUX1Enable or AUX1System 1 0 0 0 0 0 0 0 0 0 0
Note
1. AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a System or Not System regulator. 2. In all configurations in which GPIO[1] is enabled as output: a) the GPIO[1] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[1] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[1] pin is an open drain output.
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GPIO pins Figure 29. GPIO[1] block diagram
SABRE-LL-I
V 3v3
To Serial Interface
To ADC
To AUX1 Feedback comparator GPIO[1]
V 3v3
From Serial Interface Logic Decode
V 3v3
Gpio[1] Driver
Table 72.
Parameter VIH VIL VHYS VOL ILEAKAGE tDELAY
GPIO[1] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA 0 Vout V3v3 CLOAD =50 pF(1) -1 0.22 0.4 1 500 Test condition Min 1.6 0.8 Typ Max Unit V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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GPIO pins
22.4
GPIO[2]
The GPIO[2] truth table is (for the abbreviation list please refer to Table 68): Table 73. GPIO[2] truth
GPIO[1] SPI BITS GpioOut Enable [1] X 0 0 1 1 1 1 1 1 1 1 Function Mode[2] X 0 1 0 0 0 0 1 1 1 1 Mode[1] X X X 0 0 1 1 0 0 1 1 Mode[0] X X X 0 1 0 1 0 1 0 1 AUX2 FB HiZ (SPI_IN) Comp1 IN SPI OUT AuxPwm2 AuxPwm3 InterruptCtrl SPI OUT inverted AuxPwm2 inverted AuxPwm3 inverted IntCtrlinverted
(2) (2) (2) (2) (2) (2) (2) (2) (2) (1)
AUX2Enable or AUX2System 1 0 0 0 0 0 0 0 0 0 0
Note
1. AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System regulator. 2. In all configurations in which GPIO[2] is enabled as output: a) the GPIO[2] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[2] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[2] output is directly connected to ExtPWM3 input for Bridge 3 or 4 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM3 is selected for bridge 3 or 4; d) the GPIO[2] pin is an open drain output.
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GPIO pins Figure 30. GPIO[2] block diagram
SABRE-LL-I
To ExtPWM3 To Serial Interface
V 3v3
To ADC To AUX2 Feedback comparator
GPIO[2]
V 3v3
From Serial Interface Logic Decode
V 3v3
Gpio[2] Driver
Table 74.
Parameter VIH VIL VHYS VOL ILEAKAGE tDELAY
GPIO[2] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA 0 Vout V3v3 CLOAD =50 pF(1) -1 0.22 0.4 1 500 Test condition Min 1.6 0.8 Typ Max Unit V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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GPIO pins
22.5
GPIO[3]
The GPIO[3] truth table is (for the abbreviation list please refer to Table 68): Table 75.
State at StartUp
GPIO[3] truth
GPIO[3] SPI BITS GpioOut Enable [3] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] Mode[0] X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 Detection of StartUp config HiZ (SPI_IN) SPI OUT AuxPwm1 AuxPwm2 AuxPwm2 SPI OUT inverted AuxPwm1 inverted AuxPwm2 inverted AuxPwm3 inverted
(1) (1) (1) (1) (1) (1) (1) (1)
Note
1 0 0 0 0 0 0 0 0 0
See Chapter 8
1. In all configurations in which GPIO[3] is enabled as output: a) the GPIO[3] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[3] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[3] pin is an open drain output.
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GPIO pins Figure 31. GPIO[3] block diagram
SABRE-LL-I
V 3v3
To Serial Interface
To ADC
V 3v3
To Control Logic
Start up pin State Detect circ uit
GPIO[3]
V 3v3
From Serial Interface EnStartUpDtc From Power Up FSM Logic Decode
V 3v3
Gpio[3] Driver
Table 76.
Parameter VIH VIL VHYS VOL ILEAKAGE CLOAD tDELAY
GPIO[3] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Load capacitance Delay from serial write to pin low CLOAD =50 pF(1) IOUT = 15mA 0 Vout V3v3 -1 0.22 0.4 1 200 500 Test condition Min 1.6 0.8 Typ Max Unit V V V V A pF ns
1. Measured between nSS rising edge and 50% of Vout.
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GPIO pins
22.6
GPIO[4]
The GPIO[4] truth table is (for the abbreviation list please refer to Table 68): Table 77.
State at StartUp
GPIO[4] truth
GPIO[4] SPI BITS GpioOut Enable [4] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 Detection of StartUp config HiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm1 AuxPwm3 SPI OUT inverted Interrupt Ctrl AuxPwm1 inverted AuxPwm3 inverted
(1) (1) (1) (1) (1) (1) (1) (1)
Note
1 0 0 0 0 0 0 0 0 0
See Chapter 8
1. In all configurations in which GPIO[4] is enabled as output: a) the GPIO[4] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[4] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[4] pin is an open drain output.
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GPIO pins Figure 32. GPIO[4] block diagram
SABRE-LL-I
V 3v3
To Serial Interface
To ADC
V 3v3
To Control Logic
Start up pin State Detect circuit V 3v3
GPIO[4]
V 3v3
From Serial Interface EnStartUpDtc From PowerUp FSM Logic Decode
Gpio[4] Driver
Table 78.
Parameter VIH VIL VHYS VOL ILEAKAGE CLOAD tDELAY
GPIO[4] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Load capacitance Delay from serial write to pin low CLOAD =50 pF(1) IOUT = 15mA 0 Vout V3v3 -1 0.22 0.4 1 200 500 Test condition Min 1.6 0.8 Typ Max Unit V V V V A pF ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.7
GPIO[5]
The GPIO[5] truth table is (for the abbreviation list please refer to Table 68): Figure 33. GPIO[5] block diagram
To internal Logic & SPI
V 3v3
To ADC
V 3V3 V 3v3
GPIO[5]
Logic Decode
From Control logic
Back to Back Driver
Table 79.
GPIO[5] truth
GPIO[5] SPI BITS GpioOut enable[5] X X 0 1 1 1 1 1 1 1 1 Function Mode[2] Mode[1] Mode[0] X X X 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 Slave control Reg Loop1 OUT HiZ (SPI_IN) SPI OUT Comp1OUT Reg Loop1 OUT AuxPwm3 SPI OUT inverted Comp1OUT inverted Reg Loop1 OUT inverted AuxPwm3 inverted
(3) (3) (3) (3) (3) (3) (3) (3) (3)
AUX1 system Master(1) and Vloop1 external(2) 1 0 0 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 0
Note
1. Master bit is at logic level "1" when S.A.B.Re is used as a master device (seeChapter 8)
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GPIO pins
SABRE-LL-I
2. This bit is at logic level "1" if AUX1 regulator is a system regulator but its power stage is externally realized (and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic level "1", while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level "0" in CoreConfigReg register. 3. In all configurations in which GPIO[5] is enabled as output: a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3.
Table 80.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[5] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA IOUT = 5mA 0 Vout V3v3 CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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GPIO pins
22.8
GPIO[6]
The GPIO[6] truth table is (for the abbreviation list please refer to Table 68): Table 81.
StdByMode
GPIO[6] truth
GPIO[6] SPI BITS AEnLow VSw[1] X 1 0 0 0 0 0 0 0 0 GpioOut Mode[2] Mode[1] Mode[0] enable[6] X X 0 1 1 1 1 1 1 1 X X X 0 0 0 0 1 1 1 X X X 0 0 1 1 0 0 1 X X X 0 1 0 1 0 1 1 Function Note
1 0 0 0 0 0 0 0 0 0
Low Volt. Pow. Sw. 1 Low Volt. Pow. Sw. 1 HiZ (SPI_IN) SPI OUT A2DGpo AuxPwm2 Comp2OUT A2DGpo inverted AuxGpPwm2 inverted Comp2OUT inverted
(2) (2) (2) (2) (2) (2) (2) (1)
1. When EnLowVSw[1]= `1' the GpioOutEnable[6] bit is forced to 0. 2. In all configurations in which GPIO[6] is enabled as output: a) the GPIO[6] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[6] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[6] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 34. GPIO[6] block diagram
V GPIO_SPI
SABRE-LL-I
Power Switch 1
To internal Logic & SPI
V 3v3
To ADC
EnPass1
V 3v3
From Serial Interface Stand By mode
V 3v3
GPIO[6]
Logic Decode
Gpio[6] Driver
Table 82.
Parameter VIH VIL VHYS VOL ILEAKAGE tDELAY
GPIO[6] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA 0 Vout V3v3 CLOAD =50 pF(1) -1 0.22 0.4 1 500 Test condition Min 1.6 0.8 Typ Max Unit V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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GPIO pins
22.9
GPIO[7]
The GPIO[7] truth table is (for the abbreviation list please refer to Table 68): Table 83. GPIO[7] truth
GPIO[7] SPI BITS EnLowVSw[2] GpioOut enable[7] X 0 1 1 1 1 1 1 1 Function Mode[2] Mode[1] Mode[0] X X 0 0 0 0 1 1 1 X X 0 0 1 1 0 0 1 X X 0 1 0 1 0 1 1 Low Volt. Pow. Sw. 2 HiZ (SPI_IN) SPI OUT AuxPwm1 AuxPwm3 Comp1OUT AuxPwm1 inverted AuxPwm3 inverted Comp1OUT inverted
(2) (2) (2) (2) (2) (2) (2) (1)
Note
1 0 0 0 0 0 0 0 0
1. When EnLowVSw[2] = `1' the GpioOutEnable[7] bit is forced to 0. 2. In all configurations in which GPIO[7] is enabled as output: a) the GPIO[7] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[7] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[7] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 35. GPIO[7] block diagram
SABRE-LL-I
V GPIO_SPI
Power Switch 2
To internal Logic & SPI
V 3v3
To ADC
EnPass2
V GPIO_SPI
V 3v3
From Serial Interface
GPIO[7]
Logic Decode
Table 84.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[7] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = 15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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GPIO pins
22.10
GPIO[8]
The GPIO[8] truth table is (for the abbreviation list please refer to Table 68): Table 85.
EnDac
GPIO[8] truth
GPIO[8] SPI BITS
(1)
GpioOut enable[8] X 0 1 1 1 1 1 1 1
Function (2) Mode[2] X X 0 0 0 0 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 Mode[0] X X 0 1 0 1 0 1 1 CurrDAC HiZ (SPI_IN) SPI OUT AuxPwm1 AuxPwm3 Comp2OUT AuxPwm1 inverted AuxPwm3 inverted Comp2OUT inverted
Note
1 0 0 0 0 0 0 0 0
(3) (4) (4) (4) (4) (4) (4)
(4) (4)
1. The EnDAC bit in the CurrDacCtrl register enables the Current DAC (seeChapter 17) 2. This pin is 5 volt input tolerant. 3. When EnDAC = `1' the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to GPIO[8] pin so as soon as it is enabled it will sink current from pin. 4. The GPIO[8] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function). To avoid affecting the precision of CurrDAC when this is used to sink very low currents, it is necessary to enable the digital input functionality of GPIO[8]. Therefore to read their values through SPI interface (SPI_IN function), it is necessary to enable the EnGpio8DigIn bit in the CurrDacCtrl register.
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GPIO pins Figure 36. GPIO[8] block diagram
SABRE-LL-I
V 3v3
To internal Logic & SPI
EnGpio8 DigIn
To ADC
V 3v3
From Serial Interface
Logic Decode
V 3v3
GPIO[8] Gpio[8] Driver
From Serial Interface
Current Sink Circuit
Table 86.
Parameter VIH VIL VHYS VOL ILEAK_0 ILEAK_1
GPIO[8] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Leakage current IOUT = 15mA, EnGpio8DigIn=0, 0 Vout 5V EnGpio8DigIn=1, 0 Vout 5V ADChannelX[4:0] =10001 and bit EnDacScale=0 CLOAD =50 pF(1) -1 -1 0.22 0.4 1 5 Test condition Min 1.6 0.8 Typ Max Unit V V V V A A
IAD tDELAY
A/D path absorbed current Delay from serial write to pin low
-1
1 500
A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.11
GPIO[9]
The GPIO[9] truth table is (for the abbreviation list please refer to Table 68): Table 87. GPIO[9] truth
GPIO[9] SPI BITS Op1EnPlusPin
(1)
GpioOut enable[9] X 0 1 1 1 1 1 1 1
Function (2) Mode[2] X X 0 0 0 0 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 Mode[0] X X 0 1 0 1 0 1 1 OpAmp1 in+ HiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm2 Reg Loop 3 Interrupt Ctrl inverted AuxPwm2 inverted Reg Loop 3 inverted
Note
1 0 0 0 0 0 0 0 0
(3)
(4) (4) (4) (4) (4) (4) (4)
1. The Op1EnPlusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to GPIO[9] pin. 2. The GPIO[9] pin is used by the system when firmware requires the ID read action (Chapter 25) 3. When Op1EnPlusPin = `1' the GpioOutEnable[9] bit is forced to 0. 4. In all configurations in which GPIO[9] is enabled as output: a) the GPIO[9] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[9] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[9] output is directly connected to ExtPWM1 input for Bridge 1 or 2 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM1 is selected for bridge 1 or 2; d) the GPIO[9] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 37. GPIO[9] block diagram
SABRE-LL-I
To internal Logic & SPI ID1 SampleID
Pin State Sample Circuit
V 3v3
To ADC V GPIO_SPI GPIO[9]
V 3v3
From SPI
Logic Decode
Gpio[9] Driver To OpAmp1 In+
Table 88.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[9] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = 15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.12
GPIO[10]
The GPIO[10] truth table is (for the abbreviation list please refer to Table 68): Table 89. GPIO[10] truth
GPIO[10] SPI BITS Op1EnPlusPin
(1)
GpioOut enable[10] X 0 1 1 1 1 1 1 1
Function (2) Mode[2] X X 0 0 0 0 1 1 0 Mode[1] X X 0 0 1 1 0 0 0 Mode[0] X X 0 1 0 1 0 1 0 OpAmp1 inHiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm2 AuxPwm3 Interrupt Ctrl inverted AuxPwm2 inverted AuxPwm3 inverted
Note
1 0 0 0 0 0 0 0 0
(3)
(4) (4) (4) (4) (4) (4) (4)
1. The Op1EnMinusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to GPIO[10] pin. 2. The GPIO[10] pin is used by the system when firmware requires the ID read action (Chapter 25) 3. When Op1EnPlusPin = `1' the GpioOutEnable[10] bit is forced to 0. 4. In all configurations in which GPIO[10] is enabled as output: a) the GPIO[10] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[10] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[10] output is directly connected to ExtPWM2 input for bridge 1 or 2 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM2 is selected for bridge 1 or 2; d) the GPIO[10] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 38. GPIO[10] block diagram
SABRE-LL-I
To internal Logic & SPI ID2 SampleID
Pin State Sample Circuit
V 3v3
To ADC V GPIO_SPI GPIO[10]
V 3v3
From SPI
Logic Decode
Gpio[10] Driver To OpAmp1 In -
Table 90.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[10] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = 15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.13
GPIO[11]
The GPIO[11] truth table is (for the abbreviation list please refer to Table 68): Table 91.
EnOpl
GPIO[11] truth
GPIO[11] SPI BITS
(1)
GpioOut enable[11] X 0 1 1 1 1 1 1 1 1
Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 OpAmp1 Out HiZ (SPI_IN) SPI OUT A2DGpo AuxPwm1 AuxPwm2 SPI OUT inverted A2DGpo inverted AuxPwm1 inverted AuxPwm2 inverted
Note
1 0 0 0 0 0 0 0 0 0
(2)
(3) (3) (3) (3) (3) (3) (3) (3)
1. The EnOp1 bit in the OpAmp1Ctrl register enables the operational amplifier 1. 2. When EnOp1 = `1' the GpioOutEnable[11] bit is forced to 0. 3. In all configurations in which GPIO[11] is enabled as output: a) the GPIO[11] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[11] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[11] output is directly connected to ExtPWM4 input for bridge 3 or 4 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM4 is selected for bridge 3 or 4; d) the GPIO[11] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 39. GPIO[11] block diagram
SABRE-LL-I
To internal Logic & SPI
V 3v3
To ADC
V GPIO_SPI V 3v3
GPIO[11] From Central Logic
Logic Decode
OpAmp 1
Table 92.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[11] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level Output voltage Leakage current Delay from serial write to pin low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = -15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.14
GPIO[12]
The GPIO[12] truth table is (for the abbreviation list please refer to Table 68): Table 93.
AUX2enable or AUX2syste m (1) 1 0 0 0 0 0 0 0 0 0 Op2En PlusPin GpioOut Mode[2] Mode[1] Mode[0] enable[12] X X 0 1 1 1 1 1 1 1 X X X 0 0 0 0 1 1 1 X X X 0 0 1 1 0 0 1 X X X 0 1 0 1 0 1 1
GPIO[12] truth
GPIO[12] SPI BITS Function Note
X 1 0 0 0 0 0 0 0 0
RegLoop2 OpAmp2 in+ HiZ (SPI_IN) SPI OUT Interrupt Ctrl Comp2OUT RegLoop2 Interrupt Ctrl inverted Comp2OUT inverted RegLoop2 inverted
(3) (3) (3) (3) (3) (3) (3) (2)
1. AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or not system). 2. When Op2EnPlusPin = `1' the GpioOutEnable[11] bit is forced to 0. 3. In all configurations in which GPIO[12] is enabled as output: a) the GPIO[12] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[12] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[12] output is directly connected to StepCmd input for stepper driver and therefore particular care must be taken in order to avoid wrong PWM signals when StepCmd is selected for stepper driver (STEP_REQUEST function) d) the GPIO[12] pin is a rail to rail, back to back output supplied by VGPIO_SPI.
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GPIO pins Figure 40. GPIO[12] block diagram
SABRE-LL-I
To internal Logic & SPI
V 3v3
To ADC
V 3v3
From SPI
Logic Decode
V GPIO_SPI
GPIO[12]
To OpAmp2 In+
Back to Back Driver
Table 94.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[12] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from Serial Write to pin Low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = 15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF (1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.15
GPIO[13]
The GPIO[13] truth table is (for the abbreviation list please refer to Table 68): Table 95. GPIO[13] truth
GPIO[13] SPI BITS Op2En mimusPin(1) 1 0 0 0 0 0 0 0 0 GpioOut enable[13] X 0 1 1 1 1 1 1 1 Mode[2] X X 0 0 0 0 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 Mode[0] X X 0 1 0 1 0 1 1 OpAmp2 inHiZ (SPI_IN) SPI OUT AuxPwm1 Reg Loop 3 AuxPwm3 AuxPwm1 inverted Reg Loop 3 inverted AuxPwm3 inverted
(3) (3) (3) (3) (3) (3) (3) (2)
Function
Note
1. The Op2EnMinusPin bit in the OpAmp2Ctrl register enables the connection of the positive input of Op1 to GPIO[13] pin. 2. When Op2EnMinusPin = `1' the GpioOutEnable[13] bit is forced to 0. 3. In all configurations in which GPIO[9] is enabled as output: a) the GPIO[13] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[13] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[13] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 41. GPIO[13] block diagram
SABRE-LL-I
To internal Logic &SPI
V 3v3
To ADC GPIO[13]
V 3v3
From SPI
Logic Decode
V GPIO_SP
Gpio[13] Driver To OpAmp2 In -
Table 96.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[13] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = 15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
GPIO pins
22.16
GPIO[14]
The GPIO[14] truth table is (for the abbreviation list please refer to Table 68): Table 97.
EnOp2
(1)
GPIO[14] truth
GPIO[14] SPI BITS GpioOut enable[14] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 OpAmp2 Out HiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm2 AuxPwm3 SPI OUT inverted Interrupt Ctrl inverted AuxPwm2 inverted AuxPwm3 inverted
(3) (3) (3) (3) (3) (3) (3) (3) (2)
Note
1 0 0 0 0 0 0 0 0 0
1. The EnOp2 bit in the OpAmp2Ctrl register enables the operational amplifier 2. 2. When EnOp2 = `1' the GpioOutEnable[14] bit is forced to 0. 3. In all configurations in which GPIO[14] is enabled as output: a) the GPIO[14] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[14] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[14] pin is a rail to rail output supplied by VGPIO_SPI.
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GPIO pins Figure 42. GPIO[14] block diagram
SABRE-LL-I
To internal Logic & SPI
V 3v3
To ADC
V GPIO_SP V 3v3
GPIO[14] From Central Logic
Logic Decode
Gpio[14] Driver
OpAmp 2
Table 98.
Parameter VIH VIL VHYS VOL VOH ILEAKAGE tDELAY
GPIO[14] specification
Description High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA, VGPIO_SPI = 3.15V IOUT = 15mA, VGPIO_SPI = 3.15V 0 Vout VGPIO_SPI, VGPIO_SPI = 3.15V CLOAD =50 pF(1) 2.75 -1 1 500 0.22 0.4 Test condition Min 1.6 0.8 Typ Max Unit V V V V V A ns
1. Measured between nSS rising edge and 50% of Vout.
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SABRE-LL-I
Serial interface
23
Serial interface
S.A.B.Re can communicate with an external microprocessor by using an integrated slave SPI (Serial Protocol Interface). Through this interface almost all S.A.B.Re functionalities can be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit each. The SPI is a simple industry standard communications interface commonly used in embedded systems and it has the following four I/O pins: - - - - Miso (master input slave output) Mosi (Master Output Slave Input) sclk (serial clock [controlled by the master]) nSS (slave select active low [controlled by the master])
The "Miso" (master in, slave out) signal carries synchronous data from the slave to the master device. The mosi (master out, slave in) signal carries synchronous data from the master to the slave device. The sclk signal is driven by the master, synchronizing all data transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master output pin. Slave devices do not respond to transactions unless their nSS input signal is driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for each slave device. S.A.B.Re will maintain its miso pin in high impedance until it does not recognize its address in serial frame.
23.1
Read transaction
A read transaction (see Figure 43) is always started by the master device that lowers the nSS pin. The other bits are then sent on the mosi pin with this order: 1. 2. 3. 4. 7-bit representing the address of the register that must be read (MSB first [A6...A0]); 2-bit that must be "10" for a read transaction; 2-bit representing S.A.B.Re IC address; 1-bit reserved for future use that must be set at "0".
At this point the data stored in the register at the selected address will be shifted out on the miso pin. The read operation is terminated by raising the signal on nSS pin.
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Serial interface Figure 43. SPI read transaction
SABRE-LL-I
nSS sclk Registe r Address field mosi miso
A6 A0
Control IC Field address
Data Field
High Impedance
D15
D0
23.2
Write transaction
A write transaction (see Figure 44) is always started by the master lowering the signal on nSS pin. The other bits are then sent on the mosi pin with this order: 1. 2. 3. 4. 7-bit representing the address of the register that must be written (MSB first [A6...A0]); 2-bit that must be "01" for a read transaction; 2-bit representing S.A.B.Re IC address; 1-bit reserved for future use that must be set at "0".
The data to be written (MSB first D15...D0) are then read from mosi pin. The length of data field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched on rising edge of the nSS line. Figure 44. SPI write transaction
nSS sclk Register Address field mosi miso
A6 A0
Control IC Field addres
D15
Data Field
D0
High Impedance
The SPI input and output timing definitions are shown in the following tables:
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SABRE-LL-I Figure 45. SPI input timing diagram
Serial interface
T nss nSS
setup
T sclk
period
T nss
hold
T nss
min
V IH V IL T sclk
hig
T sclk
low
sclk
V IH V IL V IH V IL T mosi T mosi T sclk
rise
mosi T sclk
setup
hold
fall
Figure 46. SPI output timing diagram
T sclk
T nss nSS
setup
period
T nss
hold
T nss
min
V IH V IL T sclk
high
T sclk
low
sclk
V IH V IL
mosi T sclk miso
rise
T sclk
fall
V OH V OL T miso
valid
T miso
disable
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Serial interface Table 99.
Parameter VIH VIL VHYS VOH VOL tsclk_period tsclk_rise tsclk_fall tsclk_high tsclk_low tnss_setup tnss_hold tnss_min tmosi_setup tmosi_hold tmiso_rise tmiso_fall tmiso_valid tmiso_disable CLOAD
SABRE-LL-I SPI interface specifications (Note: VGPIO_SPI=3.3V unless otherwise specified)
Description High level input voltage Low level input voltage Input voltage hysteresis High level output voltage Low level output voltage SCLK period SCLK rise time SCLK fall time SCLK high time SCLK low time nSS setup time nSS hold time nSS high minimum time Mosi setup time Mosi hold time Miso rise time Miso fall time Miso valid from clock low Miso disable time Miso maximum load CLOAD =50pF(3)
(3) (1) (1)
Test condition
Min 1.6
Typ
Max
Unit V
0.8 0.22
(2)
V V V
IOUT = -10mA, IOUT = 10mA,
2.75 0.4 62.5 2 2 20 20 10 10 30 10 10 9 9 0 0 15 15 200
(2)
V ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF
CLOAD=50pF
1. Specification applies to nSS, sclk and mosi pins. 2. Current is considered to be positive when flowing towards the IC 3. These times are measured at the pin output between specified VOH and VOL.
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SABRE-LL-I
Registers list
24
Registers list
Many of the S.A.B.Re functionalities are controlled or can be supervised by accessing to the relative register through serial interface. All these registers can be seen from the user (microcontroller) point of view as a register table. Each register is one word wide (16-bit) and can be read using a 7-bit address Table 100. Register address map
Address[6:0] (binary) 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 StdByMode SwCtrCfg MainlinCfg Mtr1_2PwrCtrl MainVSwCfg HibernateStatus HibernateCmd Name DevName CoreConfigReg ICTemp ICStatus EnTestRegs SampleID WatchDogCfg WatchDogStatus SoftResReg Comment Read only Address[6:0] (binary) 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 100_1010 100_1011 100_1100 100_1101 100_1110 100_1111 101_0000 101_0001 101_0010 101_0011 101_0100 101_0101 101_0110 101_0111 101_1000 101_1001 101_1010 101_1011 GpioOutEnable GpioCtrl1 GpioCtrl2 GpioCtrl3 A2DControl A2DConfig1 A2DResult1 A2DConfig2 A2DResult2 IntCtrlCfg IntCtrlCtrl DigCmpCfg DigCmpValue Name AuxPwm1Ctrl AuxPwm2Ctrl GpPwm3Base GpPwm3Ctrl Comment
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Registers list Table 100. Register address map (continued)
Address[6:0] (binary) 001_1100 001_1101 001_1110 001_1111 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 CurrDacCtrl StpCfg1 StpCfg2 StpCtrl StpCmd StpTest Aux1SwCfg Aux2SwCfg Aux3SwCfg1 Aux3SwCfg2 Power Mode Control Mtrs3_4Cfg Mtr3Cfg Mtr3Ctrl Mtr3ILimit Mtr4Cfg Mtr4Ctrl Mtr4ILimit Mtrs1_2Cfg Mtr1Cfg Mtr1Ctrl Mtr1Limit Mtr2Cfg Mtr2Ctrl Mtr2Limit Name Comment Address[6:0] (binary) 101_1100 101_1101 101_1110 101_1111 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 111_1100 REV_MFCT RESERVED OpAmpCtrl1 OpAmpCtrl2 LowVSwitchCtrl Name GpioPadVal GpioOutVal
SABRE-LL-I
Comment Read only
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SABRE-LL-I Table 100. Register address map (continued)
Address[6:0] (binary) 011_1101 011_1110 011_1111 Name Comment Address[6:0] (binary) 111_1101 111_1110 111_1111 Name RESERVED RESERVED RESERVED
Registers list
Comment
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25
nSS Gpio0 Gpio1 Gpio2
J1
nAWAKE
nSS
73 72 71 70
33uH 3A Coilcraf t DO5010H-333MLD +3_3VS L1 C12 100pF C13 100nF + C25 470uF 16V D3 STPS3L60U D6
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3 2 U1 SABRe L2 C2 1uF D7 6CWQ06 Vsupply C7 C3 1uF 1210 +3_3VS Gpio6 +3_3VS Gpio7 C11 C9 100nF nRESET C8 100nF C10 100nF R14 1K V3v 3 100nF C26 330uF 25V R18 1K
1
Gpio5
Gpio3 Gpio4
12 34 56 78 9 10
TAB TAB TAB TAB
3
C1 1uF Vsupply MISO MOSI
Q3 BC846B Gpio8 C5 680nF SCLK
LED 1
330
DC2_plus nSS Gpio0 Gpio1 Gpio2 DC2_minus DC2_minus GND2 GND1 DC1_minus DC1_minus Gpio3 Gpio4 VSWDRV_FB VSWDRV_sns DC1_plus
2
100nF
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DC2_plus Vsupply MISO MOSI VLINmain_FB VLINmain_OUT Gpio8 VSWmain_SW Vsupply VSWmain_FB VREF_FB IREF_FB SCLK Vsupply DC4_plus DC4_plus
TAB TAB TAB TAB TAB DC1_plus Vsupply CPL CPH Vpump VSWDRV_gate VSWDRV_SW Gpio6 VGPIO_SPI Gpio7 Vsupply Int V3v 3 nRESET Vsupply DC3_plus DC3_plus
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
3
J10
Gpio12 Gpio13 Gpio14
Gpio11 Gpio10 Gpio9 Gpio5
V3v 3 +3_3VS nAWAKE R7 4.7K
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
DC4_sense nAWAKE Gpio12 Gpio13 Gpio14 DC4_minus DC4_minus DC4_sense DC3_sense DC3_minus DC3_minus Gpio11 Gpio10 Gpio9 Gpio5 DC3_sense
R41 1K C16 680uF 50V
C4 1uF
2
3
2
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Start up configuration JP2 JP3 JP4 R17 CON3 100nF J4 R12 Vsupply Gpio8 330 1nF JP8 R37 1nF R42 0.047 1W LED C18 C17 D4 1 2 DC2_plus DC2_minus Gpio13 Gpio14 1K 1 2 DC1_plus DC1_minus 1 C31 R16 1K 1nF Gpio6 Gpio7 Gpio11 Gpio12 1nF J3 1 2 3 1 +3_3VS R15 GND 1K C19 C20 Gpio1 Gpio2 1 2 3 4 5 6 7 8 9 10 CON10 1 V3v 3 J11 3 2 3 2 3 2 R36 2.2K Q5 STD12NF06L LED 2.2K J9 1 2 VSWDRV GND 12V 3A 33uH 4.5A Coilcraf t DO5040H-333MLD
Schematic samples
J2
R1
R2
D1
Vsupply GND
1 2
Vsupply
4.7K
4.7K
LED
J7
VSWMAIN GND 3.3V 2.5A
1 2
Slave
Master
R38 Open
Schematic samples
nRESET MISO MOSI SCLK
JP1
+
C14 100nF
C15 100pF
R43 22K
R44 39K
CON5X2
D5
R13
+3_3VS
R21 1K
J8
R10 4.7K
Q4 BSP51
VLINMAIN GND 1.2V 0.5A + C27 10uF 10V
1 2
C29
R39 Open
R40 560
C28 330nF
+
Q1 BC846B 100nF
1 R5 4.7K R8 4.7K
RESET
D2
+3_3VS R19 R20 1K 1K
Device ID 3 2 3 2 1 JP5 1 JP6 ID2 1nF 1nF J5 1 2 J6 1 2 C22 1nF C21 1nF Phase B Phase A ID1 C23 C24 Stepper
nRESET JP7
R11
330
nSS
nSS
SCLK Close on Master AWAKE C6 100nF JP9 R9 4.7K 4.7K R6 Q2 BC846B 1
LED
R3
4.7K
MISO MOSI
AWAKE
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 JP11 JP12 JP13 JP14
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
RESET
CON17X2 JP15 JP16
R22 1
R23 2.2
R24 3.9
R25 3.9
R26 2.2
R27 1
Figure 47. Application with 2 DC motors, 1 stepper motor and 3 power supplies
SABRE-LL-I
SABRE-LL-I
To PractiSpin J1 J2 Vsupply JP1 10K 1W JP3 R3 CON3 J4 R35 Vsupply R4 0.047 1W D11 R36 C3 1nF 1nF C4 D10 1 2 D20 LED RED DC2_plus DC2_minus 1K 1 2 DC1_plus DC1_minus 1 R2 1nF 1K 1nF J3 D18 LED GREEN D19 LED RED 1 2 3 JP2 1 R1 JP8 1K C1 C2 LED GREEN R46 10K 1W Vsupply GND 1 2 +3_3VS 4.7K 330 1 V3v 3 R32 D8
Start up configuration J12
D9
R33
nRESET JP4
nSS
nSS
3 2 3 2 3 2
SCLK
LED GREEN
R34
Gpio6 Gpio7 Gpio8 Gpio11 Gpio12 +3_3VS
MISO MOSI 330 J5 1 2
1 2 3 4 5 6 7 8 CON8
AWAKE
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 D21 LED GREEN 10K 1W R47 Q1 STD12NF06L U1 SABRe R5 2.2K 2.2K
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
RESET
CON34A
VSWMAIN GND 3.3V 3A
nSS Gpio0 Gpio1 Gpio2
J7
nAWAKE
nSS
73 72 71 70
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3 2 R7 1K
1
Gpio5
Gpio3 Gpio4
Slave
Master
LED GREEN
J6 33uH 4.5A Coilcraf t DO5040H-333MLD L2 C9 330uF 25V + C10 100pF C11 100pF R8 15K 1 2 VSWDRV GND 12.8V 3A
12 34 56 78 9 10 R37 +3_3VS Vsupply MISO MOSI C13 1uF +3_3VS Gpio6 +3_3VS Gpio7 C16 C17 V3v 3 100nF R10 1K 100nF nRESET C12 100nF Vsupply
CON10A
3
Q6 BC846B Q2 BSP51 C15 680nF SCLK Gpio8
LED 1
GREEN330
DC2_plus nSS Gpio0 Gpio1 Gpio2 DC2_minus DC2_minus GND2 GND1 DC1_minus DC1_minus Gpio3 Gpio4 VSWDRV_FB VSWDRV_sns DC1_plus
D12
TAB TAB TAB TAB
nRESET MISO MOSI SCLK
JP5
LED GREEN 33uH 3A Coilcraf t DO5010H-333MLD +3_3VS L1 C6 C7 100pF 100nF + C8 470uF 16V D1 STPS3L60U
D2 6CWQ06 R9 1K
2
J8
R38 4.7K
VLINMAIN GND 1.2V 0.5A C18 330nF + C19 10uF 10V
1 2
D13
R39 680
3
Vsupply
R11 560
R14 4.7K 1W + C21 1uF C20 470uF 63V
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DC2_plus Vsupply MISO MOSI VLINmain_FB VLINmain_OUT Gpio8 VSWmain_SW Vsupply VSWmain_FB VREF_FB IREF_FB SCLK Vsupply DC4_plus DC4_plus
TAB TAB TAB TAB TAB DC1_plus Vsupply CPL CPH Vpump VSWDRV_gate VSWDRV_SW Gpio6 VGPIO_SPI Gpio7 Vsupply Int V3v 3 nRESET Vsupply DC3_plus DC3_plus Q3 BC846B
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ResetOn RED LED 1 4.7K
RESET
R40 +3_3VS
270
D14
4 2
2
R15 1K
R12 R13 4.7K
LED GREEN 1 R41 L3 33uH 2A Coilcraf t DO3316P-333MLD 1K J9 1 2 D4 STPS1L60U C24 470uF 16V + C25 100nF C26 100pF R16 820
3
Device ID 1K 1 Gpio1 3 2 ID1 JP6 1K 3 2 1 ID2 R21 1K JP7 L5 33uH 2A Coilcraf t DO3316P-333MLD J11 1 2 +Vop D7 STPS1L60U C29 470uF 16V + C30 100nF C31 100pF R27 1K R42 680
Q7 BC846B
DC4_sense nAWAKE Gpio12 Gpio13 Gpio14 DC4_minus DC4_minus DC4_sense DC3_sense DC3_minus DC3_minus Gpio11 Gpio10 Gpio9 Gpio5 DC3_sense
1
+
3
D3 BZX284C15
C22 22uF 16V
+Vop
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Q4 BSP51
Gpio12 Gpio13 Gpio14
D5 L4 R20 10K 0.1% + D6 STPS3L60U U2A LM358 R23 10K 0.1% V3v 3 R26 4.7K nAWAKE + 2 R25 150K 0.1% R28 150K 0.1% D16 Y ELLOW LED Charge in progress 3 C27 470uF 16V R43 1K C28 100nF
ES3B
R17
0.1 1W
33uH 2A Coilcraf t DO3316P-333MLD
Gpio11 Gpio10 Gpio9 Gpio5
J10
C23 100nF
+3_3VS R18 R22
BATTERY + GND 12V 1.5A max
1 2
2
R19 10K
1
C32 100pF
3
Q9 R44 2.2K BC857B
R45 1K
R24 10K
1
8
C5 10pF
8
R48 330
4
U2B 5 + 6 R49 C14 100nF 7 LM358
Close on Master AWAKE JP9 R31 4.7K 4.7K
R29
Q5 BC846B 1
3
D17 RED LED Disconnect the battery
Gpio2 R30 1K D15 LED GREEN
2
4
1K
R6 4.7K
2
VDC3+ GND 1.8V 1A VSWDC3GND 5V 1A
Figure 48. Application with 2 DC motors, a battery charger and 5 power supplies
Schematic samples
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Pin list
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26
26.1
Pin list
Pin list
Table 101. Pins configuration
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pin name DC1_PLUS Description Bridge 1 phase "plus" output Type Output Analog input Analog input Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Output Output Power/digital Power/digital Output Output Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog Input - CMOS input CMOS input Output Output Power input CMOS output CMOS input Analog input Power output Analog In/Out - CMOS bi-dir Power output Power Input Analog input Analog input Analog input CMOS input Power input Output
VSWDRV_SNS Switching regulator controller sense VSWDRV_FB GPIO4 GPIO3 Switching regulator controller feedback General purpose I/O General purpose I/O
DC1_MINUS Bridge 1 phase "minus" output DC1_MINUS Bridge 1 phase "minus" output GND1 GND2 Ground pin for bridge1 Ground pin for
(1)(2)(3)
bridge2(1)(2)(3)
DC2_MINUS Bridge 2 phase "minus" output DC2_MINUS Bridge 2 phase "minus" output GPIO2 GPIO1 GPIO0 nSS DC2_PLUS DC2_PLUS VSupply MISO MOSI VLINmain_FB General purpose I/O General purpose I/O General purpose I/O SPI chip select pin Bridge 2 phase "plus" output Bridge 2 phase "plus" output Main voltage supply SPI serial data output SPI serial data input Linear main regulator feedback
VLINmain_OUT Linear main regulator output GPIO 8 VSWmain_SW VSupply VSWmain_FB VREF_FB IREF_FB SCLK VSupply DC4_PLUS General purpose I/O Main switching regulator switching output Main voltage supply Main switching regulator feedback pin Regulator voltage feedback Regulator current feedback SPI input clock pin Main voltage supply Bridge 4 phase "plus" output
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SABRE-LL-I Table 101. Pins configuration (continued)
Pin # 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 E_Pad Pin name N.C. Not connected Output CMOS input Description Type
Pin list
DC4_SENSE Bridge 4 sense output(4) nAWAKE GPIO12 GPIO13 GPIO14 N.C. Device wake up General purpose I/O General purpose I/O General purpose I/O Not connected
Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir
DC4_MINUS Bridge 4 phase "minus" output DC4_SENSE Bridge 4 sense output
(4)
Output Output Output Output
DC3_SENSE Bridge 3 sense output(4) DC3_MINUS Bridge 3 phase "minus" output N.C. GPIO11 GPIO10 GPIO9 GPIO5 Not connected General purpose I/O General purpose I/O General purpose I/O General purpose I/O
(4)
Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Output
DC3_SENSE Bridge 3 sense output N.C. DC3_PLUS VSupply nRESET V3v3 VSupplyInt GPIO7 VGPIO_SPI GPIO6 VSWDRV_SW VSWDRV_GAT
E
Not connected Bridge 3 phase "plus" output Main voltage supply Open drain system reset pin Internal 3.3 volt regulator Internal voltage supply General purpose I/O Low voltage pins power supply General purpose I/O Switching regulator controller source input Switching driver gate drive pin Charge pump voltage Charge pump high switch pin Charge pump low switch pin Main voltage supply Bridge 1 phase "plus" output
(1)(2)(3)
Output Power input CMOS Input/output Power Input/output Power Input Analog In/Out - CMOS bi-dir Power input Analog In/Out - CMOS bi-dir Power input Analog output Power Input/output Power Input/output Power Input/output Power input Output
VPump CPH CPL VSupply DC1_plus GND_PAD
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Pin list
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1. These pins must be connected all together to a unique PCB ground. 2. Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together). 3. The analog ground is connected to exposed pad E-Pad. 4. The pin must be tied to ground if bridge is not used as a stepper motor.
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SABRE-LL-I
Package information
27
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 49. TQFP64 mechanical data & package dimensions
mm DIM. MIN. A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L L1 k ccc 0 0.45 11.80 9.80 2.00 7.50 0.50 0.60 1.00 3.5 7 0.080 0 0.75 0.05 0.95 0.17 0.09 11.80 9.80 2.00 7.50 12.00 10.00 12.20 10.20 0.464 0.386 0.787 0.295 0.0197 0.0177 0.0236 0.0295 0.0393 3.5 7 0.0031 12.00 10.00 1.00 0.22 TYP. MAX. 1.20 0.15 1.05 0.27 0.20 12.20 10.20 0.002 MIN. TYP. MAX. 0.0472 0.006 inch
OUTLINE AND MECHANICAL DATA
0.0374 0.0393 0.0413 0.0066 0.0086 0.0086 0.0035 0.464 0.386 0.787 0.295 0.472 0.394 0.480 0.401 0.472 0.394 0.0078 0.480 0.401
TQFP64 (10x10x1.0mm) Exposed Pad Down
7278840 B
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Revision history
SABRE-LL-I
28
Revision history
Table 102. Document revision history
Date 14-Nov-2007 Revision 1 Initial release. Changes
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SABRE-LL-I
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