View IDT82V2051EPPG_4240514.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FEATURES
* * * * Single channel E1 short haul line interfaces Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays Single 3.3 V power supply with 5 V tolerance on digital interfaces Meets or exceeds specifications in - ANSI T1.102 - ITU I.431, G.703, G.736, G.775 and G.823 - ETSI 300-166, 300-233 and TBR12/13 Software programmable or hardware selectable on: - Wave-shaping templates - Line terminating impedance (75 /120 ) - Adjustment of arbitrary pulse shape - JA (Jitter Attenuator) position (receive path or transmit path) - Single rail/dual rail system interfaces - HDB3/AMI line encoding/decoding - Active edge of transmit clock (TCLK) and receive clock (RCLK) - Active level of transmit data (TDATA) and receive data (RDATA) - Receiver or transmitter power down
IDT82V2051E
* * * * *
*
- High impedance setting for line drivers - PRBS (Pseudo Random Bit Sequence) generation and detection with 215-1 PRBS polynomials - 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS error counter - Analog loopback, Digital loopback, Remote loopback Short circuit protection and internal protection diode for line drivers AIS (Alarm Indication Signal) detection Supports serial control interface, Motorola and Intel Multiplexed interfaces and hardware control mode Pin compatibe to 82V2081 T1/E1/J1 Long Haul/Short Haul LIU and 82V2041E T1/E1/J1 Short Haul LIU Package: Available in 44-pin TQFP packages Green package options available
DESCRIPTION
The IDT82V2051E is a single channel E1 Line Interface Unit. The IDT82V2051E performs clock/data recovery, AMI/HDB3 line decoding and detects and reports the LOS conditions. An integrated Adaptive Equalizer is available to increase the receive sensitivity and enable programming of LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform Shaper. There is one Jitter Attenuator, which can be placed in either the receive path or the transmit path. The Jitter Attenuator can also be disabled. The IDT82V2051E supports both Single Rail and Dual Rail system interfaces. To facilitate the network maintenance, a PRBS generation/detection circuit is integrated in the chip, and different types of loopbacks can be set according to the applications. Two different kinds of line terminating impedance, 75 and 120 are selectable. The chip also provides driver shortcircuit protection and internal protection diode. The chip can be controlled by either software or hardware. The IDT82V2051E can be used in LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2005 Integrated Device Technology, Inc.
December 9, 2005
DSC-6528/2
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
LOS RCLK RD/RDP CV/RDN
LOS/AIS Detector Data and Clock Recovery Data Slicer Adaptive Equalizer Receiver Internal Termination Analog Loopback Transmitter Internal Termination TTIP TRING RTIP RRING
HDB3/AMI Decoder PRBS Detector
Jitter Attenuator
Remote Loopback
Digital Loopback Waveform Shaper Line Driver
TCLK TD/TDP TDN
HDB3/AMI Decoder PRBS Generator TAOS
Jitter Attenuator
Clock Generator
Software Control Interface
Register Files
Pin Control
SDO / ACK / RDY
RD / DS / SCLKE
SDI/ WR /R/W
SCLK/ALE/AS
Figure-1 Block Diagram
Functional Block Diagram
2
MODE[1:0] TERM RXTXM[1:0] PULS PATT[1:0] JA[1:0] MONT LP[1:0] THZ RCLKE RPD RST
VDDIO VDDD VDDA VDDT
MCLK
CS
AD[7:0]
INT
December 9, 2005
Table of Contents
1 2 3 IDT82V2051E Pin Configurations ............................................................................................... 8 Pin Description ............................................................................................................................ 9 Functional Description .............................................................................................................. 15 3.1 Control Mode Selection .................................................................................................... 15 3.2 Transmit Path ................................................................................................................... 15 3.2.1 Transmit Path System Interface.............................................................................. 15 3.2.2 Encoder.................................................................................................................. 15 3.2.3 Pulse Shaper .......................................................................................................... 15 3.2.3.1 Preset Pulse Templates .......................................................................... 15 3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 16 3.2.4 Transmit Path Line Interface................................................................................... 17 3.2.5 Transmit Path Power Down .................................................................................... 17 3.3 Receive Path .................................................................................................................... 18 3.3.1 Receive Internal Termination .................................................................................. 18 3.3.2 Line Monitor ............................................................................................................ 19 3.3.3 Adaptive Equalizer .................................................................................................. 20 3.3.4 Receive Sensitivity.................................................................................................. 20 3.3.5 Data Slicer .............................................................................................................. 20 3.3.6 CDR (Clock & Data Recovery)................................................................................ 20 3.3.7 Decoder .................................................................................................................. 20 3.3.8 Receive Path System Interface............................................................................... 21 3.3.9 Receive Path Power Down ..................................................................................... 21 3.4 Jitter Attenuator ................................................................................................................ 21 3.4.1 Jitter Attenuation Function Descripton .................................................................... 21 3.4.2 Jitter Attenuator Performance ................................................................................. 22 3.5 Los And AIS Detection ...................................................................................................... 22 3.5.1 LOS Detection......................................................................................................... 22 3.5.2 AIS Detection .......................................................................................................... 23 3.6 Transmit And Detect Internal Patterns .............................................................................. 24 3.6.1 Transmit All Ones ................................................................................................... 24 3.6.2 Transmit All Zeros................................................................................................... 24 3.6.3 PRBS Generation And Detection............................................................................ 24 3.7 Loopback .......................................................................................................................... 24 3.7.1 Analog Loopback .................................................................................................... 24 3.7.2 Digital Loopback ..................................................................................................... 24 3.7.3 Remote Loopback................................................................................................... 24 3.8 Error Detection/Counting And Insertion ............................................................................ 27
Table of Contents
3
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.9 3.10
3.11
3.12 3.13 3.14 3.15 4
3.8.1 Definition Of Line Coding Error ............................................................................... 27 3.8.2 Error Detection And Counting ................................................................................. 27 3.8.3 Bipolar Violation And PRBS Error Insertion ............................................................ 28 Line Driver Failure Monitoring ........................................................................................... 28 MCLK And TCLK .............................................................................................................. 29 3.10.1 Master Clock (MCLK).............................................................................................. 29 3.10.2 Transmit Clock (TCLK) ........................................................................................... 29 Microcontroller Interfaces ................................................................................................. 30 3.11.1 Parallel Microcontroller Interface ............................................................................ 30 3.11.2 Serial Microcontroller Interface ............................................................................... 30 Interrupt Handling ............................................................................................................. 30 5V Tolerant I/O Pins ......................................................................................................... 31 Reset Operation ................................................................................................................ 31 Power Supply .................................................................................................................... 31
Programming Information ........................................................................................................ 32 4.1 Register List And Map ...................................................................................................... 32 4.2 Reserved Registers .......................................................................................................... 32 4.3 Register Description ......................................................................................................... 33 4.3.1 Control Registers .................................................................................................... 33 4.3.2 Transmit Path Control Registers............................................................................. 35 4.3.3 Receive Path Control Registers.............................................................................. 37 4.3.4 Network Diagnostics Control Registers .................................................................. 39 4.3.5 Interrupt Control Registers...................................................................................... 41 4.3.6 Line Status Registers.............................................................................................. 43 4.3.7 Interrupt Status Registers ....................................................................................... 45 4.3.8 Counter Registers ................................................................................................... 46 Hardware Control Pin Summary .............................................................................................. 47 Test Specifications .................................................................................................................... 49 Microcontroller Interface Timing Characteristics ................................................................... 56 7.1 Serial Interface Timing ...................................................................................................... 56 7.2 Parallel Interface Timing ................................................................................................... 57
5 6 7
Table of Contents
4
December 9, 2005
List of Tables
Table-1 Table-2 Table-3 Table-4 Table-5 Table-6 Table-7 Table-8 Table-9 Table-10 Table-11 Table-12 Table-13 Table-14 Table-15 Table-16 Table-17 Table-18 Table-19 Table-20 Table-21 Table-22 Table-23 Table-24 Table-25 Table-26 Table-27 Table-28 Table-29 Table-30 Table-31 Table-32 Table-33 Table-34 Table-35 Table-36 Table-37 Table-38 Table-39 Table-40 Table-41
List of Tables
Pin Description ................................................................................................................ 9 Transmit Waveform Value For E1 75 ohm.................................................................... 16 Transmit Waveform Value For E1 120 ohm.................................................................. 16 Impedance Matching for Transmitter ............................................................................ 17 Impedance Matching for Receiver ................................................................................ 18 Criteria of Starting Speed Adjustment........................................................................... 22 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 22 LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 23 AIS Condition ................................................................................................................ 23 Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 24 EXZ Definition ............................................................................................................... 27 Interrupt Event............................................................................................................... 31 Register List and Map ................................................................................................... 32 ID: Device Revision Register ........................................................................................ 33 RST: Reset Register ..................................................................................................... 33 GCF: Global Configuration Register ............................................................................. 33 TERM: Transmit and Receive Termination Configuration Register .............................. 33 JACF: Jitter Attenuation Configuration Register ........................................................... 34 TCF0: Transmitter Configuration Register 0 ................................................................. 35 TCF1: Transmitter Configuration Register 1 ................................................................. 35 TCF2: Transmitter Configuration Register 2 ................................................................. 35 TCF3: Transmitter Configuration Register 3 ................................................................. 36 TCF4: Transmitter Configuration Register 4 ................................................................. 36 RCF0: Receiver Configuration Register 0..................................................................... 37 RCF1: Receiver Configuration Register 1..................................................................... 37 RCF2: Receiver Configuration Register 2..................................................................... 38 MAINT0: Maintenance Function Control Register 0...................................................... 39 MAINT1: Maintenance Function Control Register 1...................................................... 39 MAINT6: Maintenance Function Control Register 6...................................................... 39 INTM0: Interrupt Mask Register 0 ................................................................................. 41 INTM1: Interrupt Masked Register 1 ............................................................................. 41 INTES: Interrupt Trigger Edge Select Register ............................................................. 42 STAT0: Line Status Register 0 (real time status monitor)............................................. 43 STAT1: Line Status Register 1 (real time status monitor)............................................. 44 INTS0: Interrupt Status Register 0 ................................................................................ 45 INTS1: Interrupt Status Register 1 ................................................................................ 45 CNT0: Error Counter L-byte Register 0......................................................................... 46 CNT1: Error Counter H-byte Register 1 ........................................................................ 46 Hardware Control Pin Summary ................................................................................... 47 Absolute Maximum Rating ............................................................................................ 49 Recommended Operation Conditions ........................................................................... 49
5 December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-42 Table-43 Table-44 Table-45 Table-46 Table-47 Table-48 Table-49 Table-50 Table-51 Table-52 Table-53
Power Consumption...................................................................................................... DC Characteristics ........................................................................................................ Receiver Electrical Characteristics................................................................................ Transmitter Electrical Characteristics............................................................................ Transmitter and Receiver Timing Characteristics ......................................................... Jitter Tolerance ............................................................................................................. Jitter Attenuator Characteristics .................................................................................... Serial Interface Timing Characteristics ......................................................................... Multiplexed Motorola Read Timing Characteristics....................................................... Multiplexed Motorola Write Timing Characteristics ....................................................... Multiplexed Intel Read Timing Characteristics .............................................................. Multiplexed Intel Write Timing Characteristics ..............................................................
50 50 50 51 52 53 54 56 57 58 59 60
List of Tables
6
December 9, 2005
List of Figures
Figure-1 Figure-2 Figure-3 Figure-4 Figure-5 Figure-6 Figure-7 Figure-8 Figure-9 Figure-10 Figure-11 Figure-12 Figure-13 Figure-14 Figure-15 Figure-16 Figure-17 Figure-18 Figure-19 Figure-20 Figure-21 Figure-22 Figure-23 Figure-24 Figure-25 Figure-26 Figure-27 Figure-28 Block Diagram ................................................................................................................. 2 IDT82V2051E TQFP44 Package Pin Assignment .......................................................... 8 E1 Waveform Template Diagram .................................................................................. 15 E1 Pulse Template Test Circuit ..................................................................................... 15 Receive Monitor Gain Adaptive Equalizer ..................................................................... 18 Transmit/Receive Line Circuit ....................................................................................... 18 Monitoring Receive Line in Another Chip ...................................................................... 19 Monitor Transmit Line in Another Chip .......................................................................... 19 Jitter Attenuator ............................................................................................................. 21 LOS Declare and Clear ................................................................................................. 22 Analog Loopback .......................................................................................................... 25 Digital Loopback ............................................................................................................ 25 Remote Loopback ......................................................................................................... 26 Auto Report Mode ......................................................................................................... 27 Manual Report Mode ..................................................................................................... 28 TCLK Operation Flowchart ............................................................................................ 29 Serial Microcontroller Interface Function Timing ........................................................... 30 Transmit System Interface Timing ................................................................................ 52 Receive System Interface Timing ................................................................................. 53 E1 Jitter Tolerance Performance .................................................................................. 54 E1 Jitter Transfer Performance ..................................................................................... 55 Serial Interface Write Timing ......................................................................................... 56 Serial Interface Read Timing with SCLKE=1 ................................................................ 56 Serial Interface Read Timing with SCLKE=0 ................................................................ 56 Multiplexed Motorola Read Timing ................................................................................ 57 Multiplexed Motorola Write Timing ................................................................................ 58 Multiplexed Intel Read Timing ....................................................................................... 59 Multiplexed Intel Write Timing ....................................................................................... 60
List of Figures
7
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
1
IDT82V2051E PIN CONFIGURATIONS
RDY / ACK / SDO / TERM
23
ALE / AS / SCLK/ LP1
25
33
32
31
30
29
28
27
26
24
WR / R/W / SDI / LP0
AD1 / PATT1
AD0 / PATT0
AD4 / PULS
AD2 / RPD
AD7
AD6
AD5
AD3
IC VDDT TRING TTIP GNDT GNDA RRING RTIP VDDA REF IC
34 35 36 37 38 39 40 41 42 43 44
22 21 20 19
RD / DS / SCLKE / MONT CS / RXTXM1 INT / RXTXM0 VDDIO GNDIO MODE1 MODE0 JA1 JA0 THZ RST
IDT82V2051E
18 17 16 15 14 13 12
10
MCLK
RDN / CV
RDP / RD
GNDD
RCLK
VDDD
TDP / TD
Figure-2 IDT82V2051E TQFP44 Package Pin Assignment
IDT82V2051E Pin Configurations
8
RCLKE
TCLK
TDN
LOS
11
1
2
3
4
5
6
7
8
9
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
2
PIN DESCRIPTION
Name Type Analog output Pin No. 37 36 Description TTIP/TRING: Transmit Bipolar Tip/Ring These pins are the differential line driver outputs. They will be in high impedance state under the following conditions: * THZ pin is high; * THZ bit is set to 1; * Loss of MCLK; * Loss of TCLK (exceptions: Remote Loopback; transmit internal pattern by MCLK); * Transmit path power down; * After software reset; pin reset and power on. RTIP/RRING: Receive Bipolar Tip/Ring These signals are the differential receiver inputs. TD: Transmit Data When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TD pin is sampled into the device on the active edge of TCLK and is encoded by AMI or HDB3 line code rules before being transmitted. In this mode, TDN should be connected to ground. TDP/TDN: Positive/Negative Transmit Data When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data on TDP/TDN pin is sampled into the device on the active edge of TCLK. The line code in dual rail mode is as follows: TDP 0 0 1 1 TCLK I 1 TDN 0 1 0 1 Output Pulse Space Positive Pulse Negative Pulse Space
Table-1 Pin Description
TTIP TRING
RTIP RRING TD/TDP TDN
Analog input I
41 40 2 3
TCLK: Transmit Clock input This pin inputs a 2.048 MHz transmit clock. The transmit data at TD/TDP or TDN is sampled into the device on the active edge of TCLK. If TCLK is missing1 and the TCLK missing interrupt is not masked, an interrupt will be generated. RD: Receive Data output In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI or HDB3 line code rules. CV: Code Violation indication In single rail mode, the BPV/CV code violation will be reported by driving the CV pin to high level for a full clock cycle. HDB3 line code violation can be indicated if the HDB3 decoder is enabled. When AMI decoder is selected, bipolar violation will be indicated. In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CV pin if single rail mode is chosen. RDP/RDN: Positive/Negative Receive Data output In dual rail mode, this pin outputs the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data if CDR is bypassed. Active edge and level select: Data on RDP/RDN or RD is clocked with either the rising or the falling edge of RCLK. The active polarity is also selectable.
RD/RDP CV/RDN
O
5 6
RCLK
O
4
RCLK: Receive Clock output This pin outputs a 2.048 MHz receive clock. Under LOS condition with AIS enabled (bit AISE=1), RCLK is derived from MCLK. In clock recovery mode, this signal provides the clock recovered from the RTIP/RRING signal. The receive data (RD in single rail mode or RDP and RDN in dual rail mode) is clocked out of the device on the active edge of RCLK. If clock recovery is bypassed, RCLK is the exclusive OR (XOR) output of the dual rail slicer data RDP and RDN. This signal can be used in applications with external clock recovery circuitry.
Notes: 1. TCLK missing: the state of TCLK continues to be high level or low level over 70 MCLK cycles.
Pin Description
9
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name MCLK Type I Pin No. 9 Description MCLK: Master Clock input A built-in clock system that accepts a 2.048MHz reference clock. This reference clock is used to generate several internal reference signals: * Timing reference for the integrated clock recovery unit. * Timing reference for the integrated digital jitter attenuator. * Timing reference for microcontroller interface. * Generation of RCLK signal during a loss of signal condition. * Reference clock to transmit All Ones, all zeros and PRBS pattern. Note that for ATAO and AIS, MCLK is always used as the reference clock. * Reference clock during the Transmit All Ones (TAO) condition or sending PRBS in hardware control mode. The loss of MCLK will turn TTIP/TRING into high impedance status. LOS: Loss of Signal Output This is an active high signal used to indicate the loss of received signal. When LOS pin becomes high, it indicates the loss of received signal. The LOS pin will become low automatically when valid received signal is detected again. The criteria of loss of signal are described in 3.5 Los And AIS Detection. REF: reference resister An external resistor (3 K, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. MODE[1:0]: operation mode of Control interface select The level on this pin determines which control mode is used to control the device as follows: MODE[1:0] 00 01 10 11 * * * RCLKE I 11 Control Interface mode Hardware interface Serial Microcontroller Interface Parallel -Multiplexed -Motorola Interface Parallel -Multiplexed -Intel Interface
LOS
O
7
REF MODE1 MODE0
I I
43 17 16
The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the selection of the active edge of SCLK. The parallel multiplexed microcontroller interface consists of CS, AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and INT pins. (refer to 3.11 Microcontroller Interfaces for details) Hardware interface consists of PULS, THZ, RCLKE, LP[1:0], PATT[1:0], JA[1:0], MONT, TERM, RPD, MODE[1:0] and RXTXM[1:0]
RCLKE: the active edge of RCLK select In hardware control mode, this pin selects the active edge of RCLK * L= select the rising edge as the active edge of RCLK * H= select the falling edge as the active edge of RCLK In software control mode, this pin should be connected to GNDIO. CS: Chip Select In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial or parallel microcontroller interface. RXTXM[1:0]: Receive and transmit path operation mode select In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3 line coding: * 00= single rail with HDB3 coding * 01= single rail with AMI coding * 10= dual rail interface with CDR enabled * 11= slicer mode (dual rail interface with CDR disabled)
CS
I
21
RXTXM1
Pin Description
10
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name INT Type O Pin No. 20 Description INT: Interrupt Request In software control mode, this pin outputs the general interrupt request for all interrupt sources. These interrupt sources can be masked individually via registers (INTM0, 14H) and (INTM1, 15H). The interrupt status is reported via the registers (INTS0, 19H) and (INTS1, 1AH). Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting INT_PIN[1:0] (GCF, 02H). RXTXM0 See RXTXM1 above. 25 SCLK: Shift Clock In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is sampled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the falling edge of SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin is low. ALE: Address Latch Enable In parallel microcontroller interface mode with multiplexed Intel interface, the address on AD[7:0] is sampled into the device on the falling edge of ALE. AS: Address Strobe In parallel microcontroller interface mode with multiplexed Motorola interface, the address on AD[7:0] is latched into the device on the falling edge of AS. LP[1:0]: Loopback mode select When the chip is configured by hardware, this pin is used to select loopback operation modes: * 00= no loopback * 01= analog loopback * 10= digital loopback * 11= remote loopback I 24 SDI: Serial Data Input In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sampled by the device on the rising edge of SCLK. WR: Write Strobe In Intel parallel multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data on AD[7:0] is sampled into the device in a write operation. R/W: Read/Write Select In Motorola parallel multiplexed interface mode, this pin is low for write operation and high for read operation. LP0 See LP1 above.
RXTXM0 SCLK
I I
ALE
AS
LP1
SDI
WR
R/W
LP0
Pin Description
11
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name SDO Type O Pin No. 23 Description SDO: Serial Data Output In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at SDO pin is clocked out of the device on the falling edge of SCLK if SCLKE pin is high, or on the rising edge of SCLK if SCLKE pin is low. ACK: Acknowledge Output In Motorola parallel mode interface, the low level on this pin means: * The valid information is on the data bus during a read operation. * The write data has been accepted during a write cycle. RDY: Ready signal output In Intel parallel mode interface, the low level on this pin means a read or write operation is in progress; a high acknowledges a read or write operation has been completed. I TERM: Internal or external termination select in hardware mode This pin selects internal or external impedance matching for both receiver and transmitter. * 0 = ternary interface with external impedance matching network * 1 = ternary interface with internal impedance matching network 22 SCLKE: Serial Clock Edge Select In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is valid after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge which clocks the data out of the device is selected as shown below: SCLKE Low High SCLK Rising edge is the active edge. Falling edge is the active edge.
ACK
RDY
TERM
SCLKE
I
RD
RD: Read Strobe In Intel parallel multiplexed interface mode, the data is driven to AD[7:0] by the device during low level of RD in a read operation. DS: Data Strobe In Motorola parallel multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation (R/ W = 0), the data on AD[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to AD[7:0] by the device. MONT: Receive Monitor gain select In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver: 0= 0 dB 1= 26 dB I/O 33 AD7: Address/Data Bus bit7 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. In Hardware mode, this pin has to be tied to GND.
DS
MONT
AD7
AD6
I/O
32
AD6: Address/Data Bus bit6 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. In Hardware mode, this pin has to be tied to GND.
Pin Description
12
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name AD5 Type I/O Pin No. 31 Description AD5: Address/Data Bus bit5 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. In Hardware mode, this pin has to be tied to GND. AD4 I/O 30 AD4: Address/Data Bus bit4 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. PULS: this pin is used to select the following functions in hardware control mode: * Transmit pulse template * Internal termination impedance (75 / 120 ) Refer to 5 Hardware Control Pin Summary for details. AD3 I/O 29 AD3: Address/Data Bus bit3 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor.
AD2
I/O
28
AD2: Address/Data Bus bit2 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. RPD: Receiver power down control in hardware control mode * 0= normal operation * 1= receiver power down
RPD
I
AD1
I/O
27
AD1: Address/Data Bus bit1 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. PATT[1:0]: Transmit pattern select In hardware control mode, this pin selects the transmit pattern * 00 = normal * 01= All Ones * 10= PRBS * 11= transmitter power down
PATT1
I
AD0
I/O
26
AD0: Address/Data Bus bit0 In Intel/Motorola multiplexed interface mode, this signal is the multiplexed bi-directional address/data bus of the microcontroller interface. In serial microcontroller interface mode, this pin should be connected to ground through a 10 k resistor. See above.
PATT0 JA1
I I 15
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (only used for hardware control mode) * 00 = JA is disabled * 01 = JA in receiver, broad bandwidth, FIFO=64 bits * 10 = JA in receiver, narrow bandwidth, FIFO=128 bits * 11 = JA in transmitter, narrow bandwidth, FIFO=128 bits In software control mode, this pin should be connected to ground. See above.
JA0
I
14
Pin Description
13
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name RST THZ Type I I Pin No. 12 13 Description RST: Hardware reset The chip is forced to reset state if a low signal is input on this pin for more than 100 ns. MCLK must be active during reset. THZ: Transmitter Driver High Impedance Enable This signal enables or disables transmitter driver. A low level on this pin enables the driver while a high level on this pin places driver in high impedance state. Note that the functionality of the internal circuits is not affected by this signal. Power Supplies and Grounds VDDIO GNDIO VDDT GNDT VDDA GNDA VDDD GNDD IC IC 19 18 35 38 42 39 8 10 34 44 3.3 V I/O power supply I/O ground 3.3 V power supply for transmitter driver Analog ground for transmitter driver 3.3 V analog core power supply Analog core ground Digital core power supply Digital core ground Others IC: Internal connection Internal Use. This pin should be left open when in normal operation. IC: Internal connection Internal Use. This pin should be connected to ground when in normal operation.
Pin Description
14
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3
3.1
FUNCTIONAL DESCRIPTION
CONTROL MODE SELECTION
in a positive pulse on the TTIP/TRING. If both TDP and TDN are high or low, the TTIP/TRING outputs a space (Refer to TD/TDP, TDN Pin Description). In hardware control mode, the operation mode of receive and transmit path can be selected by setting RXTXM1 and RXTXM0 pins. Refer to 5 Hardware Control Pin Summary for details. 3.2.3 PULSE SHAPER The IDT82V2051E provides two ways of manipulating the pulse shape before sending it. One is to use preset pulse templates, the other is to use user-programmable arbitrary waveform template. In software control mode, the pulse shape can be selected by setting the related registers. In hardware control mode, the pulse shape can be selected by setting PULS pin. Refer to 5 Hardware Control Pin Summary for details. 3.2.3.1 PRESET PULSE TEMPLATES The pulse shape is shown in Figure-3 according to the G.703 and the measuring diagram is shown in Figure-4. In internal impedance matching mode, if the cable impedance is 75 , the PULS[3:0] bits (TCF1, 06H) should be set to `0000'; if the cable impedance is 120 , the PULS[3:0] bits (TCF1, 06H) should be set to `0001'. In external impedance matching mode, for both E1/75 and E1/120 cable impedance, PULS[3:0] should be set to `0001'.
The IDT82V2051E can be configured by software or by hardware. The software control mode supports Serial Control Interface, Motorola Multiplexed Control Interface and Intel Multiplexed Control Interface. The Control mode is selected by MODE1 and MODE0 pins as follows:
Control Interface mode 00 01 10 11 Hardware interface Serial Microcontroller Interface. Parallel -Multiplexed -Motorola Interface Parallel -Multiplexed -Intel Interface
* * *
The serial microcontroller Interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the selection of active edge of SCLK. The parallel Multiplexed microcontroller Interface consists of CS, AD[7:0], DS/RD, R/W/WR, ALE/AS, ACK/RDY and INT pins. Hardware interface consists of PULS, THZ, RCLKE, LP[1:0], PATT[1:0], JA[1:0], MONT, TERM, RPD, MODE[1:0] and RXTXM[1:0]. Refer to 5 Hardware Control Pin Summary for details about hardware control.
3.2
TRANSMIT PATH
1 .2 0 1 .0 0
The transmit path of IDT82V2051E consists of an Encoder, an optional Jitter Attenuator, a Waveform Shaper, a Line Driver and a Programmable Transmit Termination.
Normalized Amplitude
0 .8 0
3.2.1
TRANSMIT PATH SYSTEM INTERFACE
0 .6 0
The transmit path system interface consists of TCLK pin, TD/TDP pin and TDN pin. TCLK is a 2.048 MHz clock. If TCLK is missing for more than 70 MCLK cycles, an interrupt will be generated if it is not masked. Transmit data is sampled on the TD/TDP and TDN pins by the active edge of TCLK. The active edge of TCLK can be selected by the TCLK_SEL bit (TCF0, 05H). And the active level of the data on TD/TDP and TDN can be selected by the TD_INV bit (TCF0, 05H). In hardware control mode, the falling edge of TCLK and the active high of transmit data are always used. The transmit data from the system side can be provided in two different ways: Single Rail and Dual Rail. In Single Rail mode, only TD pin is used for transmitting data and the T_MD[1] bit (TCF0, 05H) should be set to `0'. In Dual Rail Mode, both TDP pin and TDN pin are used for transmitting data, the T_MD[1] bit (TCF0, 05H) should be set to `1'. 3.2.2 ENCODER In Single Rail mode, the Encoder can be configured to be a HDB3 encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 05H). In Dual Rail mode, the Encoder is by-passed. In Dual Rail mode, a logic `1' on the TDP pin and a logic `0' on the TDN pin results in a negative pulse on the TTIP/TRING; a logic `0' on TDP pin and a logic `1' on TDN pin results
0 .4 0
0 .2 0
0 .0 0
-0 .2 0
- 0 .6
-0 .4
-0 .2
0 T im e in U n it In te rv a ls
0 .2
0 .4
0 .6
Figure-3 E1 Waveform Template Diagram
TTIP
IDT82V2051E
TRING
RLOAD
VOUT
Note: 1. For RLOAD = 75 (nom), Vout (Peak) = 2.37 V (nom) 2. For RLOAD = 120 (nom), Vout (Peak) = 3.00 V (nom)
Figure-4 E1 Pulse Template Test Circuit
Functional Description
15
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.2.3.2 USER-PROGRAMMABLE ARBITRARY WAVEFORM When the PULS[3:0] bits are set to `11xx', user-programmable arbitrary waveform generator mode can be used. This allows the transmitter performance to be tuned for a wide variety of line condition or special application. Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by UI[1:0] bits (TCF3, 08H) and each UI is divided into 16 sub-phases, addressed by the SAMP[3:0] bits (TCF3, 08H). The pulse amplitude of each phase is represented by a binary byte, within the range from +63 to -63, stored in WDAT[6:0] bits (TCF4, 09H) in signed magnitude form. The most positive number +63 (D) represents the positive maximum amplitude of the transmit pulse while the most negative number -63 (D) represents the maximum negative amplitude of the transmit pulse. Therefore, up to 64 bytes are used. There are two standard templates which are stored in an on-chip ROM. User can select one of them as reference and make some changes to get the desired waveform. User can change the wave shape and the amplitude to get the desired pulse shape. In order to do this, firstly, users can choose a set of waveform value from the following two tables, which is the most similar to the desired pulse shape. Table-2 and Table-3 list the sample data and scaling data of each of the two templates. Then modify the corresponding sample data to get the desired transmit pulse shape. Secondly, through the value of SCAL[5:0] bits increased or decreased by 1, the pulse amplitude can be scaled up or down at the percentage ratio against the standard pulse amplitude if needed. For different pulse shapes, the value of SCAL[5:0] bits and the scaling percentage ratio are different. The following two tables list these values. Do the followings step by step, the desired waveform can be programmed, based on the selected waveform template: (1).Select the UI by UI[1:0] bits (TCF3, 08H) (2).Specify the sample address in the selected UI by SAMP [3:0] bits (TCF3, 08H) (3).Write sample data to WDAT[6:0] bits (TCF4, 09H). It contains the data to be stored in the RAM, addressed by the selected UI and the corresponding sample address. (4).Set the RW bit (TCF3, 08H) to `0' to implement writing data to RAM, or to `1' to implement read data from RAM (5).Implement the Read from RAM/Write to RAM by setting the DONE bit (TCF3, 08H) Repeat the above steps until all the sample data are written to or read from the internal RAM. (6).Write the scaling data to SCAL[5:0] bits (TCF2, 07H) to scale the amplitude of the waveform based on the selected standard pulse amplitude When more than one UI is used to compose the pulse template, the overlap of two consecutive pulses could make the pulse amplitude overflow (exceed the maximum limitation) if the pulse amplitude is not set properly. This overflow is captured by DAC_OV_IS bit (INTS1, 1AH), and, if enabled by the DAC_OV_IM bit (INTM1, 15H), an interrupt will be generated.
The following tables give all the sample data based on the preset pulse templates in detail for reference. For preset pulse templates, scaling up/ down against the pulse amplitude is not supported. 1.Table-2 Transmit Waveform Value For E1 75 2.Table-3 Transmit Waveform Value For E1 120
Table-2 Transmit Waveform Value For E1 75 ohm
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0000000 0000000 0000000 0001100 0110000 0110000 0110000 0110000 0110000 0110000 0110000 0110000 0000000 0000000 0000000 0000000 UI 2 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0] results in 3% scaling up/down against the pulse amplitude.
Table-3 Transmit Waveform Value For E1 120 ohm
Sample 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 UI 1 0000000 0000000 0000000 0001111 0111100 0111100 0111100 0111100 0111100 0111100 0111100 0111100 0000000 0000000 0000000 0000000 UI 2 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 3 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 UI 4 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000 0000000
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0] results in 3% scaling up/down against the pulse amplitude.
Functional Description
16
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.2.4
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIP pin and TRING pin. The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If T_TERM[2] is set to `0', the internal impedance matching circuit will be selected. In this case, the T_TERM[1:0] bits (TERM, 03H) can be set to choose 75 or 120 internal impedance of TTIP/TRING. If T_TERM[2] is set to `1', the internal impedance matching circuit will be disabled. In this case, the external impedance matching circuit will be used to realize the impedance matching. Figure-6 shows the appropriate external components to connect with the cable. Table-4 is the list of the recommended impedance matching for transmitter. In hardware control mode, TERM pin can be used to select impedance matching for both receiver and transmitter. If TERM pin is low, external impedance network will be used for impedance matching. If TERM pin is high, internal impedance will be used for impedance matching and PULS
pin will be set to select the specific internal impedance. Refer to 5 Hardware Control Pin Summary for details. The TTIP/TRING pins can also be turned into high impedance by setting the THZ bit (TCF1, 06H) to `1'. In this state, the internal transmit circuits are still active. In hardware control mode, TTIP/TRING can be turned into high impedance by pulling THZ pin to high. Refer to 5 Hardware Control Pin Summary for details. Besides, in the following cases, both TTIP/TRING pins will also become high impedance: * Loss of MCLK; * Loss of TCLK (exceptions: Remote Loopback; Transmit internal pattern by MCLK); * Transmit path power down; * After software reset; pin reset and power on.
Table-4 Impedance Matching for Transmitter
Cable Configuration E1 / 75 E1 / 120 000 001 Internal Termination T_TERM[2:0] PULS[3:0] 0000 0001 RT 0 T_TERM[2:0] 1XX External Termination PULS[3:0] 0001 RT 9.4
Note: The precision of the resistors should be better than 1%
3.2.5
TRANSMIT PATH POWER DOWN
The transmit path can be powered down by setting the T_OFF bit (TCF0, 05H) to `1'. In this case, the TTIP/TRING pins are turned into high impedance.
In hardware control mode, the transmit path can be powered down by pulling both PATT1 and PATT0 pins to high. Refer to 5 Hardware Control Pin Summary for details.
Functional Description
17
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.3
RECEIVE PATH
The receive path consists of Receive Internal Termination, Monitor Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive Equalizer, Data Slicer, CDR (Clock & Data Recovery), Optional Jitter Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-5. 3.3.1 RECEIVE INTERNAL TERMINATION The impedance matching can be realized by the internal impedance matching circuit or the external impedance matching circuit. If R_TERM[2]
is set to `0', the internal impedance matching circuit will be selected. In this case, the R_TERM[1:0] bits (TERM, 03H) can be set to choose 75 or 120 internal impedance of RTIP/RRING. If R_TERM[2] is set to `1', the internal impedance matching circuit will be disabled. In this case, the external impedance matching circuit will be used to realize the impedance matching. Figure-6 shows the appropriate external components to connect with the cable. Table-5 is the list of the recommended impedance matching for receiver.
LOS/AIS Detector
LOS
RTIP RRING
Receive Internal termination
Adaptive Equalizer/ Monitor Gain
Data Slicer
Clock and Data Recovery
RCLK Jitter Attenuator Decoder RDP RDN
Figure-5 Receive Monitor Gain Adaptive Equalizer
Table-5 Impedance Matching for Receiver
Cable Configuration E1/75 E1/120 Internal Termination R_TERM[2:0] 000 001 RR 120 1XX External Termination R_TERM[2:0] RR 75 120
A
RX Line
1:1 ** RR
4
VDDA D8 * VDDA D7 D6 D5
* *
RTIP
VDDA 0.1F
3.3 V 68F 1 * 3.3 V 0.1F 68F 1
*
B
2:1 ** TX Line Cp
*
* *
IDT82V2051E
RT4
VDDT D4 D3 VDDT D2
RRING * * TTIP
GNDA
VDDT
RT
4
D1
* *
TRING
GNDT
Note: 1. Common decoupling capacitor, one per chip 2. Cp 0-560 (pF) 3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060 4. RT/ RR: refer toTable-4 and Table-5 respecivley for RT and RR values
Figure-6 Transmit/Receive Line Circuit
Functional Description
18
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
In hardware control mode, TERM and PULS pins can be used to select impedance matching for both receiver and transmitter. If TERM pin is low, external impedance network will be used for impedance matching. If TERM pin is high, internal impedance will be used for impedance matching and PULS pins can be set to select the specific internal impedance. Refer to 5 Hardware Control Pin Summary for details. 3.3.2 LINE MONITOR The non-intrusive monitoring on channels located in other chips can be performed by tapping the monitored channel through a high impedance bridging circuit. Refer to Figure-7 and Figure-9. After a high resistance bridging circuit, the signal arriving at the RTIP/ RRING is dramatically attenuated. To compensate this attenuation, the Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB, selected by MG[1:0] bits (RCF2, 0CH). For normal operation, the Monitor Gain should be set to 0 dB. In hardware control mode, MONT pin can be used to set the Monitor Gain. When MONT pin is low, the Monitor Gain is 0 dB. When MONT pin is high, the Monitor Gain is 26 dB. Refer to 5 Hardware Control Pin Summary for details. Note that LOS indication is not supported if the device is operated in Line Monitor Mode
DSX cross connect point
RTIP
monitor gain=0dB
RRING
R
normal receive mode
RTIP
monitor gain =22/26/32dB
RRING
monitor mode
Figure-7 Monitoring Receive Line in Another Chip
DSX cross connect point
TTIP
TRING
R
normal transmit mode
RTIP
monitor gain monitor gain =22/26/32dB
RRING
monitor mode
Figure-8 Monitor Transmit Line in Another Chip
Functional Description
19
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.3.3
ADAPTIVE EQUALIZER
3.3.4
RECEIVE SENSITIVITY
The Adaptive Equalizer can be enabled to increase the receive sensitivity and to allow programming of the LOS level up to -24 dB. See3.5 Los And AIS Detection. It can be enabled or disabled by setting EQ_ON bit to `1' or `0' (RCF1, 0BH).
The Receive Sensitivity is -10 dB. With the Adaptive Equalizer enabled, the receive sensitivity will be -20 dB. In Hardware mode, the Adaptive Equalizer can not be enabled and the receive sensitivity is fixed at -10 dB. Refer to 5 Hardware Control Pin Summary for details. 3.3.5 DATA SLICER The Data Slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. The threshold can be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2, 0CH). The output of the Data Slicer is forwarded to the CDR (Clock & Data Recovery) unit or to the RDP/RDN pins directly if the CDR is disabled. 3.3.6 CDR (CLOCK & DATA RECOVERY) The CDR is used to recover the clock and data from the received signal. The recovered clock tracks the jitter in the data output from the Data Slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. The CDR can also be by-passed in the Dual Rail mode. When CDR is by-passed, the data from the Data Slicer is output to the RDP/RDN pins directly. 3.3.7 DECODER The R_MD[1:0] bits (RCF0, 0AH) are used to select the AMI decoder or HDB3 decoder. When the chip is configured by hardware, the operation mode of receive and transmit path can be selected by setting RXTXM1 and RXTXM0 pins. Refer to 5 Hardware Control Pin Summary for details.
Functional Description
20
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.3.8
RECEIVE PATH SYSTEM INTERFACE
3.4
JITTER ATTENUATOR
The receive path system interface consists of RCLK pin, RD/RDP pin and RDN pin. The RCLK outputs a recovered 2.048 MHz clock. The received data is updated on the RD/RDP and RDN pins on the active edge of RCLK. The active edge of RCLK can be selected by the RCLK_SEL bit (RCF0, 0AH). And the active level of the data on RD/RDP and RDN can be selected by the RD_INV bit (RCF0, 0AH). In hardware control mode, only the active edge of RCLK can be selected. If RCLKE is set to high, the falling edge will be chosen as the active edge of RCLK. If RCLKE is set to low, the rising edge will be chosen as the active edge of RCLK. The active level of the data on RD/RDP and RDN is the same as that in software control mode. The received data can be output to the system side in two different ways: Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 0AH). In Single Rail mode, only RD pin is used to output data and the RDN/CV pin is used to report the received errors. In Dual Rail Mode, both RDP pin and RDN pin are used for outputting data. In the receive Dual Rail mode, the CDR unit can be by-passed by setting R_MD[1:0] to `11' (binary). In this situation, the output data from the Data Slicer will be output to the RDP/RDN pins directly, and the RCLK outputs the exclusive OR (XOR) of the RDP and RDN. This is called receiver slicer mode. In this case, the transmit path is still operating in Dual Rail mode. 3.3.9 RECEIVE PATH POWER DOWN The receive path can be powered down by setting R_OFF bit (RCF0, 0AH) to `1'. In this case, the RCLK, RD/RDP, RDN and LOS will be logic low. In hardware control mode, receiver power down can be selected by pulling RPD pin to high. Refer to 5 Hardware Control Pin Summary for more details.
There is one Jitter Attenuator in the IDT82V2051E. The Jitter Attenuator can be deployed in the transmit path or the receive path, and can also be disabled. This is selected by the JACF[1:0] bits (JACF, 04H). In hardware control mode, Jitter Attenuator position, bandwidth and the depth of FIFO can be selected by JA[1:0] pins. Refer to 5 Hardware Control Pin Summary for details. 3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTON The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in Figure-9. The FIFO is used as a pool to buffer the jittered input data, then the data is clocked out of the FIFO by a de-jittered clock. The depth of the FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits (JACF, 04H). In hardware control mode, the depth of FIFO can be selected by JA[1:0] pins. Refer to 5 Hardware Control Pin Summary for details. Consequently, the constant delay of the Jitter Attenuator will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but at the cost of increasing data latency time.
Jittered Data
FIFO 32/64/128
W R
RD/RDP De-jittered Data RDN
Jittered Clock
DPLL
De-jittered Clock RCLK
MCLK
Figure-9 Jitter Attenuator The Corner Frequency of the DPLL can be 0.9 Hz or 6.8 Hz, as selected by the JABW bit (JACF, 04H). The lower the Corner Frequency is, the longer time is needed to achieve synchronization. When the incoming data moves faster than the outgoing data, the FIFO will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 1AH). If the incoming data moves slower than the outgoing data, the FIFO will underflow. This underflow is captured by the JAUD_IS bit (INTS1, 1AH). For some applications that are sensitive to data corruption, the JA limit mode can be enabled by setting JA_LIMIT bit (JACF, 04H) to `1'. In the JA limit mode, the speed of the outgoing data will be adjusted automatically when the FIFO is close to its full or emptiness. The criteria of starting speed adjustment are shown in Table-6. The JA limit mode can reduce the possibility of FIFO overflow and underflow, but the quality of jitter attenuation is deteriorated.
Functional Description
21
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-6 Criteria of Starting Speed Adjustment
FIFO Depth 32 Bits 64 Bits 128 Bits Criteria for Adjusting Data Outgoing Speed 2 bits close to its full or emptiness 3 bits close to its full or emptiness 4 bits close to its full or emptiness
signal level>P density=OK (observing windows= M) signal levelLOS=1
3.4.2
JITTER ATTENUATOR PERFORMANCE
The performance of the Jitter Attenuator in the IDT82V2051E meets the ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011 and ETSI TBR12/13 specifications. Details of the Jitter Attenuator performance is shown in Table-47 Jitter Tolerance and Table-48 Jitter Attenuator Characteristics.
LOS=0
3.5
3.5.1
LOS AND AIS DETECTION
LOS DETECTION
Figure-10 LOS Declare and Clear * LOS detect level threshold With the Adaptive Equalizer off, the amplitude threshold Q is fixed on 800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hysteresis). With the Adaptive Equalizer on, the value of Q can be selected by LOS[4:0] bit (RCF1, 0BH), while P=Q+4 dB (4 dB is the LOS level detect hysteresis). Refer to Table-20 TCF1: Transmitter Configuration Register 1 for LOS[4:0] bit values available. When the chip is configured by hardware, the Adaptive Equalizer can not be enabled and Programmable LOS levels are not available (pin 29 has to be set to `0'). * Criteria for declare and clear of a LOS detect The detection supports G.775 and ETSI 300233/I.431. The criteria can be selected by LAC bit (MAINT0, 0DH). Table-7 and Table-8 summarize LOS declare and clear criteria for both with and without the Adaptive Equalizer enabled. * All Ones output during LOS On the system side, the RDP/RDN will reflect the input pulse "transition" at the RTIP/RRING side and output recovered clock (but the quality of the output clock can not be guaranteed when the input level is lower than the maximum receive sensitivity) when AISE bit (MAINT0, 0DH) is 0; or output All Ones as AIS when AISE bit (MAINT0, 0DH) is 1. In this case, RCLK output is replaced by MCLK. On the line side, the TTIP/TRING will output All Ones as AIS when ATAO bit (MAINT0, 0DH) is 1. The All Ones pattern uses MCLK as the reference clock. LOS indicator is always active for all kinds of loopback modes.
The Loss of Signal Detector monitors the amplitude of the incoming signal level and pulse density of the received signal on RTIP and RRING. * LOS declare (LOS=1) A LOS is detected when the incoming signal has "no transitions", i.e., when the signal level is less than Q dB below nominal for N consecutive pulse intervals. Here N is defined by LAC bit (MAINT0, 0DH). LOS will be declared by pulling LOS pin to high (LOS=1) and LOS interrupt will be generated if it is not masked. Note that LOS indication is not supported if the device is operated in Line Monitor Mode. Refer to 3.3.2 Line Monitor. * LOS clear (LOS=0) The LOS is cleared when the incoming signal has "transitions", i.e., when the signal level is greater than P dB below nominal and has an average pulse density of at least 12.5% for M consecutive pulse intervals, starting with the receipt of a pulse. Here M is defined by LAC bit (MAINT0, 0DH). LOS status is cleared by pulling LOS pin to low.
Table-7 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled
Control bit (LAC) 0 = G.775 1 = I.431/ETSI LOS declare threshold Level < 800 mVpp; N=32 bits Level < 800 mVpp; N=2048 bits LOS clear threshold Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
Functional Description
22
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-8 LOS Declare and Clear Criteria, Adaptive Equalizer Enabled
Control bit LAC 0 G.775 1 I.431/ETSI 00000 ... 00010 00011 ... 01010 01011 - 11111 00000 00001 ... 01010 01011 - 11111 LOS[4:0] -4 ... -8 -10 ... -24 Reserved -4 -6 ... -24 Reserved Level < Q N=2048 bits Q (dB) Level > Q+ 4 dB M=32 bits 12.5% mark density <16 consecutive zeroes LOS declare threshold LOS clear threshold Note
Level < Q N=32 bits
G.775 Level detect range is -9 to -35 dB.
Level > Q+ 4 dB M=32 bits 12.5% mark density <16 consecutive zeroes
I.431 Level detect range is -6 to -20 dB.
3.5.2
AIS DETECTION
The Alarm Indication Signal can be detected by the IDT82V2051E when the Clock & Data Recovery unit is enabled. The status of AIS detection is reflected in the AIS_S bit (STAT0, 17H). The criteria for declaring/clearing
AIS detection comply with the ITU G.775 or the ETSI 300233, as selected by the LAC bit (MAINT0, 0DH). Table-9 summarizes different criteria for AIS detection Declaring/Clearing.
Table-9 AIS Condition
ITU G.775 (LAC bit is set to `0' by default) AIS cleared 3 or more zeros contained in each of two consecutive 512-bit streams are received ETSI 300233 (LAC bit is set to `1')
3 or more zeros contained in a 512-bit stream are received
AIS detected Less than 3 zeros contained in each of two consecutive 512-bit streams are received Less than 3 zeros contained in a 512-bit stream are received
Functional Description
23
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.6
TRANSMIT AND DETECT INTERNAL PATTERNS
The internal patterns (All Ones, All Zeros and PRBS pattern) will be generated and detected by IDT82V2051E. TCLK is used as the reference clock by default. MCLK can also be used as the reference clock by setting the PATT_CLK bit (MAINT0, 0DH) to `1'. If the PATT_CLK bit (MAINT0, 0DH) is set to `0' and the PATT[1:0] bits (MAINT0, 0DH) are set to `00', the transmit path will operate in normal mode. When the chip is configured by hardware, the transmit path will operate in normal mode by setting PATT[1:0] pins to `00'. Refer to 5 Hardware Control Pin Summary for details. 3.6.1 TRANSMIT ALL ONES In transmit direction, the All Ones data can be inserted into the data stream when the PATT[1:0] bits (MAINT0, 0DH) are set to `01'. The transmit data stream is output from TTIP/TRING. In this case, either TCLK or MCLK can be used as the transmit clock, as selected by the PATT_CLK bit (MAINT0, 0DH). In hardware control mode, the All Ones data can be inserted into the data stream in transmit direction by setting PATT[1:0] pins to `01'. Refer to 5 Hardware Control Pin Summary for details. 3.6.2 TRANSMIT ALL ZEROS If the PATT_CLK bit (MAINT0, 0DH) is set to `1', the All Zeros will be inserted into the transmit data stream when the PATT[1:0] bits (MAINT0, 0DH) are set to `00'. 3.6.3 PRBS GENERATION AND DETECTION A PRBS will be generated in the transmit direction and detected in the receive direction by IDT82V2051E. The PRBS is 215-1, with maximum zero restrictions according to ITU-T O.151. When the PATT[1:0] bits (MAINT0, 0DH) are set to `10', the PRBS pattern will be inserted into the transmit data stream with the MSB first. The PRBS pattern will be transmitted directly or invertedly. In hardware control mode, the PRBS data will be generated in the transmit direction and inserted into the transmit data stream by setting PATT[1:0] pins to `10'. Refer to 5 Hardware Control Pin Summary for details. The PRBS in the received data stream will be monitored. If the PRBS has reached synchronization status, the PRBS_S bit (STAT0, 17H) will be set to `1', even in the presence of a logic error rate less than or equal to 101. The criteria for setting/clearing the PRBS_S bit are shown in Table-10.
PRBS data can be inverted through setting the PRBS_INV bit (MAINT0, 0DH). Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0, 19H). The PRBS_IES bit (INTES, 16H) can be used to determine whether the `0' to `1' change of PRBS_S bit will be captured by the PRBS_IS bit or any changes of PRBS_S bit will be captured by the PRBS_IS bit. When the PRBS_IS bit is `1', an interrupt will be generated if the PRBS_IM bit (INTM0, 14H) is set to `1'. The received PRBS logic errors can be counted in a 16-bit counter if the ERR_SEL [1:0] bits (MAINT6, 13H) are set to `00'. Refer to 3.8 Error Detection/Counting And Insertion for the operation of the error counter.
3.7
LOOPBACK
To facilitate testing and diagnosis, the IDT82V2051E provides three different loopback configurations: Analog Loopback, Digital Loopback and Remote Loopback. 3.7.1 ANALOG LOOPBACK When the ALP bit (MAINT1, 0EH) is set to `1', the chip is configured in Analog Loopback mode. In this mode, the transmit signals are looped back to the Receiver Internal Termination in the receive path then output from RCLK, RD, RDP/RDN. At the same time, the transmit signals are still output to TTIP/TRING in transmit direction. The all-ones pattern can be generated during analog loopback. Figure-11 shows the process. 3.7.2 DIGITAL LOOPBACK When the DLP bit (MAINT1, 0EH) is set to `1', the chip is configured in Digital Loopback mode. In this mode, the transmit signals are looped back to the jitter attenuator (if enabled) and decoder in receive path, then output from RCLK, RD, RDP/RDN. At the same time, the transmit signals are still output to TTIP/TRING in transmit direction. Figure-12 shows the process. Both Analog Loopback mode and Digital Loopback mode allow the sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will overwrite the transmit signals. In this case, either TCLK or MCLK can be used as the reference clock for internal patterns transmission. In hardware control mode, Digital Loopback can be selected by setting LP[1:0] pins to `10'. 3.7.3 REMOTE LOOPBACK When the RLP bit (MAINT1, 0EH) is set to `1', the chip is configured in Remote Loopback mode. In this mode, the recovered clock and data output from Clock and Data Recovery on the receive path is looped back to the jitter attenuator (if enabled) and Waveform Shaper in transmit path. Figure13 shows the process. In hardware control mode, Remote Loopback can be selected by setting LP[1:0] pins to `11'.
Table-10 Criteria for Setting/Clearing the PRBS_S Bit
PRBS Detection 6 or less than 6 bit errors detected in a 64 bits hopping window.
PRBS Missing
More than 6 bit errors detected in a 64 bits hopping window.
Functional Description
24
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
LOS
LOS/AIS Detection Clock and Data Recovery Receiver Internal Termination RTIP RRING
RCLK RD/RDP CV/RDN
HDB3/AMI Decoder
Jitter Attenuator
Data Slicer
Adaptive Equalizer
Analog Loopback
TCLK TD/TDP TDN HDB3/AMI Encoder Jitter Attenuator Waveform Shaper Line Driver Transmitter Internal Termination TTIP TRING
Figure-11 Analog Loopback
LOS
LOS/AIS Detection Clock and Data Recovery Receiver Internal Termination RTIP RRING
RCLK RD/RDP CV/RDN
HDB3/AMI Decoder
Jitter Attenuator
Data Slicer
Adaptive Equalizer
Digital Loopback
TCLK TD/TDP TDN HDB3/AMI Encoder Jitter Attenuator Waveform Shaper Line Driver Transmitter Internal Termination TTIP TRING
Figure-12 Digital Loopback
Functional Description
25
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
LOS
LOS/AIS Detection Clock and Data Recovery Receiver Internal Termination RTIP RRING
RCLK RD/RDP CV/RDN
HDB3/AMI Decoder
Jitter Attenuator
Data Slicer
Adaptive Equalizer
Remote Loopback
TCLK TD/TDP TDN HDB3/AMI Encoder Jitter Attenuator Waveform Shaper Line Driver Transmitter Internal Termination TTIP TRING
Figure-13 Remote Loopback
Functional Description
26
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.8
3.8.1
ERROR DETECTION/COUNTING AND INSERTION
DEFINITION OF LINE CODING ERROR
*
The following line encoding errors can be detected and counted by the IDT82V2051E: * Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the same polarity are received, a BPV error is declared.
*
HDB3 Code Violation (CV) Error: In HDB3 coding, a CV error is declared when two consecutive BPV errors are detected, and the pulses that have the same polarity as the previous pulse are not the HDB3 zero substitution pulses. Excess Zero (EXZ) Error: There are two standards defining the EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 13H) chooses which standard will be adopted by the chip to judge the EXZ error. Table-11 shows definition of EXZ. In hardware control mode, only ANSI standard is adopted.
Table-11 EXZ Definition
EXZ Definition ANSI AMI HDB3 More than 15 consecutive 0s are detected More than 3 consecutive 0s are detected FCC More than 80 consecutive 0s are detected More than 3 consecutive 0s are detected
3.8.2
ERROR DETECTION AND COUNTING
Auto Report Mode (CNT_MD=1)
Which type of the receiving errors (Received CV/BPV errors, excess zero errors and PRBS logic errors) will be counted is determined by ERR_SEL[1:0] bits (MAINT6, 13H). Only one type of receiving error can be counted at a time except that when the ERR_SEL[1:0] bits are set to `11', both CV/BPV and EXZ errors will be detected and counted. The selected type of receiving errors is counted in an internal 16-bit Error Counter. Once an error is detected, an error interrupt which is indicated by corresponding bit in (INTS1, 1AH) will be generated if it is not masked. This Error Counter can be operated in two modes: Auto Report Mode and Manual Report Mode, as selected by the CNT_MD bit (MAINT6, 13H). In Single Rail mode, once BPV or CV errors are detected, the CV pin will be driven to high for one RCLK period. * Auto Report Mode In Auto Report Mode, the internal counter starts to count the received errors when the CNT_MD bit (MAINT6, 13H) is set to `1'. A one-second timer is used to set the counting period. The received errors are counted within one second. If the one-second timer expires, the value in the internal counter will be transferred to (CNT0, 1BH) and (CNT1, 1CH), then the internal counter will be reset and start to count received errors for the next second. The errors occurred during the transfer will be accumulated to the next round. The expiration of the one-second timer will set TMOV_IS bit (INTS1, 1AH) to `1', and will generate an interrupt if the TIMER_IM bit (INTM1, 15H) is set to `0'. The TMOV_IS bit (INTS1, 1AH) will be cleared after the interrupt register is read. The content in the (CNT0, 1BH) and (CNT1, 1CH) should be read within the next second. If the counter overflows, a counter overflow interrupt which is indicated by CNT_OV_IS bit (INTS1, 1AH) will be generated if it is not masked by CNT_IM bit (INTM1, 15H).
N
counting next second repeats the same process
One-Second Timer expired? Y data in counter
CNT0, CNT1 counter 0
Bit TMOV_IS is set to '1'
read the data in CNT0, CNT1 within the next second Bit TMOV_IS is cleared after the interrupt register is read
Figure-14 Auto Report Mode
Functional Description
27
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
* Manual Report Mode In Manual Report Mode, the internal Error Counter starts to count the received errors when the CNT_MD bit (MAINT6, 13H) is set to `0'. When there is a `0' to `1' transition on the CNT_TRF bit (MAINT6, 13H), the data in the counter will be transferred to (CNT0, 1BH) and (CNT1, 1CH), then the counter will be reset. The errors occurred during the transfer will be accumulated to the next round. If the counter overflows, a counter overflow interrupt indicated by CNT_OV_IS bit (INTS1, 1AH) will be generated if it is not masked by CNT_IM bit (INTM1, 15H).
Manual Report mode (CNT_MD=0)
3.8.3
BIPOLAR VIOLATION AND PRBS ERROR INSERTION
Only when three consecutive `1's are detected in the transmit data stream, will a `0' to `1' transition on the BPV_INS bit (MAINT6, 13H) generate a bipolar violation pulse, and the polarity of the second `1' in the series will be inverted. A `0' to `1' transition on the EER_INS bit (MAINT6, 13H) will generate a logic error during the PRBS transmission.
3.9
LINE DRIVER FAILURE MONITORING
counting N A '0' to '1' transition on CNT_TRF? Y CNT0, CNT1 counter counter 0 data in next round repeat the same process
The transmit driver failure monitor can be enabled or disabled by setting DFM_OFF bit (TCF1, 06H). If the transmit driver failure monitor is enabled, the transmit driver failure will be captured by DF_S bit (STAT0, 17H). The transition of the DF_S bit is reflected by DF_IS bit (INTS0, 19H), and, if enabled by DF_IM bit (INTM0, 14H), will generate an interrupt. When there is a short circuit on the TTIP/TRING port, the output current will be limited to 100 mA (typical), and an interrupt will be generated. In hardware control mode, the transmit driver failure monitor is always enabled.
Read the data in CNT0, CNT1 within next round1 Reset CNT_TRF for the next '0' to '1' transition
Figure-15 Manual Report Mode
Note: It is recommended that users should do the followings within next round of error counting: Read the data in CNT0 and CNT1; Reset CNT_TRF bit for the next `0' to `1' transition on this bit.
Functional Description
28
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.10 MCLK AND TCLK
3.10.1 MASTER CLOCK (MCLK) MCLK is an independent, free-running reference clock. MCLK is 2.048 MHz. This reference clock is used to generate several internal reference signals: * Timing reference for the integrated clock recovery unit. * Timing reference for the integrated digital jitter attenuator. * Timing reference for microcontroller interface. * Generation of RCLK signal during a loss of signal condition if AIS is enabled. * Reference clock during Transmit All Ones, All Zeros and PRBS pattern if it is selected as the reference clock. For ATAO and AIS, MCLK is always used as the reference clock. * Reference clock during Transmit All Ones (TAO) condition or sending PRBS in hardware control mode. Figure-16 shows the chip operation status in different conditions of MCLK and TCLK. The missing of MCLK will set the TTIP/TRING to high impedance state.
3.10.2 TRANSMIT CLOCK (TCLK) TCLK is used to sample the transmit data on TD/TDP and TDN. The active edge of TCLK can be selected by the TCLK_SEL bit (TCF0, 05H). During Transmit All Ones or PRBS patterns, either TCLK or MCLK can be used as the reference clock. This is selected by the PATT_CLK bit (MAINT0, 0DH). But for Automatic Transmit All Ones and AIS, only MCLK is used as the reference clock and the PATT_CLK bit is ignored. In Automatic Transmit All Ones condition, the ATAO bit (MAINT0, 0DH) is set to `1'. In AIS condition, the AISE bit (MAINT0, 0DH) is set to `1'. If TCLK has been missing for more than 70 MCLK cycles, TCLK_LOS bit (STAT0, 17H) will be set, and the TTIP/TRING will become high impedance if the chip is not used for remote loopback or is not using MCLK to transmit internal patterns (TAOS, All Zeros and PRBS). When TCLK is detected again, TCLK_LOS bit (STAT0, 17H) will be cleared. The reference frequency to detect a TCLK loss is derived from MCLK.
MCLK=H/L?
Clocked
yes
L/H
TCLK status?
clocked
transmitter high impedance
generate transmit clock loss interrupt if not masked in software control mode; transmitter high impedance
normal operation
Figure-16 TCLK Operation Flowchart
Functional Description
29
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.11 MICROCONTROLLER INTERFACES
The microcontroller interface provides access to read and write the registers in the device. The chip supports serial microcontroller interface and two kinds of parallel microcontroller interface: Motorola multiplexed mode and Intel multiplexed mode. Different microcontroller interfaces can be selected by setting MODE[1:0] pins to different values. Refer to MODE1 and MODE0 in pin description and Microcontroller Interface Timing Characteristics for details.
3.11.1 PARALLEL MICROCONTROLLER INTERFACE The interface is compatible with Motorola or Intel microcontroller. When MODE[1:0] pins are set to `10', Parallel-Multiplexed-Motorola interface is selected. When MODE[1:0] pins are set to `11', Parallel-Multiplexed-Intel Interface is selected. 3.11.2 SERIAL MICROCONTROLLER INTERFACE When MODE[1:0] pins are set to `01', Serial Interface is selected. In this mode, the registers are programmed through a 16-bit word which contains an 8-bit address/command byte (5 address bits A0~A4 and bit R/W) and an 8-bit data byte (D0~D7). When bit R/W is `1', data is read out from pin SDO. When bit R/W is `0', data is written into SDI pin. Refer to Figure-17.
CS
SCLK SDI A0 A1 A2 A3 A4 R/W D0 D1 D2 D3 D4 D5 D6 D7
address/command byte
SDO D0
input data byte (R/W=0)
D1 D2 D3 D4 D5 D6 D7
remains high impedance
output data byte (R/W=1)
Figure-17 Serial Microcontroller Interface Function Timing
3.12 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2051E are indicated by the INT pin. When the INT_PIN[0] bit (GCF, 02H) is `0', the INT pin is open drain active low, with a 10 K external pull-up resistor. When the INT_PIN[1:0] bits (GCF, 02H) are `01', the INT pin is push-pull active low; when the INT_PIN[1:0] bits are `10', the INT pin is push-pull active high. An active level on the INT pin represents an interrupt of the IDT82V2051E. The interrupt event is captured by the corresponding bit in the Interrupt Status Register (INTS0, 19H) or (INTS1, 1AH). Every kind of interrupt can be enabled/disabled individually by the corresponding bit in the register (INTM0, 14H) or (INTM1, 15H). Some event is reflected by the corresponding bit in the Status Register (STAT0, 17H) or (STAT1, 18H), and the Interrupt Trigger Edge Selection Register can be used to determine how the Status Register sets the Interrupt Status Register. After the Interrupt Status Register (INTS0, 19H) or (INTS1, 1AH) is read, the INT pin become inactive.
There are totally twelve kinds of events that could be the interrupt source: (1).LOS Detected (2).AIS Detected (3).Driver Failure Detected (4).TCLK Loss (5).Synchronization Status of PRBS (6).PRBS Error Detected (7).Code Violation Received (8).Excessive Zeros Received (9).JA FIFO Overflow/Underflow (10).One-Second Timer Expired (11).Error Counter Overflow (12).Arbitrary Waveform Generator Overflow Table-12 is a summary of all kinds of interrupt and the associated Status bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt Mask bit.
Functional Description
30
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-12 Interrupt Event
Interrupt Event LOS Detected AIS Detected Driver Failure Detected TCLK Loss Synchronization Status of PRBS PRBS Error Code Violation Received Excessive Zeros Received JA FIFO Overflow JA FIFO Underflow One-Second Timer Expired Error Counter Overflow Status bit (STAT0, STAT1) LOS_S AIS_S DF_S TCLK_LOS PRBS_S Interrupt Status bit (INTS0, INTS1) LOS_IS AIS_IS DF_IS TCLK_LOS_IS PRBS_IS ERR_IS CV_IS EXZ_IS JAOV_IS JAUD_IS TMOV_IS CNT_OV_IS DAC_OV_IS Interrupt Edge Selection bit (INTES) LOS_IES AIS_IES DF_IES TCLK_IES PRBS_IES Interrupt Mask bit (INTM0, INTM1) LOS_IM AIS_IM DF_IM TCLK_IM PRBS_IM ERR_IM CV_IM EXZ_IM JAOV_IM JAUD_IM TIMER_IM CNT_IM DAC_OV_IM
Arbitrary Waveform Generator Overflow
3.13 5V TOLERANT I/O PINS
All digital input pins will tolerate 5.0 10% volts and are compatible with TTL logic.
*
Hardware Reset: Asserting the RST pin low for a minimum of 100 ns will reset the chip. During Hardware Reset, the device requires an active clock on MCLK.
3.14 RESET OPERATION
* The chip can be reset in two ways: Software Reset: Writing to the RST register (01H) will reset the chip in 1 us.
After reset, all drivers output are in high impedance state, all the internal flip-flops are reset, and all the registers are initialized to default values.
3.15 POWER SUPPLY
This chip uses a single 3.3 V power supply.
Functional Description
31
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4
4.1
PROGRAMMING INFORMATION
REGISTER LIST AND MAP 4.2 RESERVED REGISTERS
When writing to registers with reserved bit locations, the default state must be written to the reserved bits to ensure proper device operation.
Map b7 b6 ID6 RW WDAT6 EQ_ON PATT1 BPV_INS JAOV_IM JAOV_IS Bit6 Bit14 b5 ID5 T_TERM2 JA_LIMIT DFM_OFF SCAL5 UI1 WDAT5 SLICE1 PATT0 ERR_INS JAUD_IM RLP_S JAUD_IS Bit5 Bit13 b4 ID4 T_TERM1 JACF1 T_OFF THZ SCAL4 UI0 WDAT4 R_OFF LOS4 SLICE0 PATT_CLK EXZ_DEF PRBS_IM ERR_IM PRBS_IES PRBS_S PRBS_IS ERR_IS Bit4 Bit12 b3 ID3 T_TERM0 JACF0 TD_INV PULS3 SCAL3 SAMP3 WDAT3 RD_INV LOS3 PRBS_INV ERR_SEL1 TCLK_IM EXZ_IM TCLK_IES TCLK_LOS TCLK_LOS_IS EXZ_IS Bit3 Bit11 b2 ID2 R_TERM2 JADP1 TCLK_SEL PULS2 SCAL2 SAMP2 WDAT2 RCLK_SEL LOS2 LAC RLP ERR_SEL0 DF_IM CV_IM DF_IES DF_S DF_IS CV_IS Bit2 Bit10 b1 ID1 INT_PIN1 R_TERM1 JADP0 T_MD1 PULS1 SCAL1 SAMP1 WDAT1 R_MD1 LOS1 MG1 AISE ALP CNT_MD AIS_IM TIMER_IM AIS_IES AIS_S AIS_IS TMOV_IS Bit1 Bit9 b0 ID0 INT_PIN0 R_TERM0 JABW T_MD0 PULS0 SCAL0 SAMP0 WDAT0 R_MD0 LOS0 MG0 ATAO DLP CNT_TRF LOS_IM CNT_IM LOS_IES LOS_S LOS_IS CNT_OV_IS Bit0 Bit8
The registers banks include control registers, status registers and counter registers.
Table-13 Register List and Map
Address (hex) Control Registers 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 1F-12 13 14 15 16 Line Status Register 17 18 19 1A Counter Registers 1B 1C CNT0 CNT1 R R Bit7 Bit15 STAT0 STAT1 INTS0 INTS1 R R R R DAC_OV_IS ID RST GCF TERM JACF TCF0 TCF1 TCF2 TCF3 TCF4 RCF0 RCF1 RCF2 MAINT0 MAINT1 MAINT2MAINT5 MAINT6 INTM0 INTM1 INTES R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DONE DAC_OV_IM ID7 Register R/W
Transmit Path Control Registers
Receive Path Control Registers
Network Diagnostics Control Registers
Interrupt Control Registers
Interrupt Status Register
Programming Information
32
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3
4.3.1
REGISTER DESCRIPTION
CONTROL REGISTERS (R, Address = 00H)
Symbol ID[7:0] Bit 7-0 Default 00H Current silicon chip ID. Description
Table-14 ID: Device Revision Register
Table-15 RST: Reset Register
(W, Address = 01H)
Symbol RST[7:0] Bit 7-0 Default 00H Description Software reset. A write operation on this register will reset all internal registers to their default values, and the status of all ports are set to the default status. The content in this register can not be changed. After reset, all drivers output are in high impedance state.
Table-16 GCF: Global Configuration Register
(R/W, Address = 02H)
Symbol INT_PIN[1:0] Bit 7-2 1-0 Default 000000 00 Reserved. Interrupt pin control = x0: Open drain, active low (with an external pull-up resistor) = 01: Push-pull, active low = 11: Push-pull, active high Description
Table-17 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 03H)
Symbol T_TERM[2:0] Bit 7-6 5-3 Default 00 000 Reserved. These bits select the internal termination for transmit line impedance matching. = 000: Internal 75 impedance matching = 001: Internal 120 impedance matching = 1xx: Selects external impedance matching resistors (see Table-4). These bits select the internal termination for receive line impedance matching. = 000: Internal 75 impedance matching = 001: Internal 120 impedance matching = 1xx: Selects external impedance matching resistors (see Table-5). Description
R_TERM[2:0]
2-0
000
Programming Information
33
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-18 JACF: Jitter Attenuation Configuration Register
(R/W, Address = 04H)
Symbol JA_LIMIT JACF[1:0] Bit 7-6 5 4-3 Default 00 1 00 Reserved. = 0: Normal mode = 1: JA limit mode Jitter attenuation configuration = 00/10: JA not used = 01: JA in transmit path = 11: JA in receive path Jitter attenuation depth select = 00: 128 bits = 01: 64 bits = 1x: 32 bits Jitter transfer function bandwidth select = 0: 6.8 Hz = 1: 0.9 Hz Description
JADP[1:0]
2-1
00
JABW
0
0
Programming Information
34
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.2
TRANSMIT PATH CONTROL REGISTERS (R/W, Address = 05H)
Symbol T_OFF Bit 7-5 4 Default 000 0 Reserved. Transmitter power down enable = 0: Transmitter power up = 1: Transmitter power down (line driver high impedance) Transmit data invert = 0: Data on TD or TDP/TDN is active high = 1: Data on TD or TDP/TDN is active low Transmit clock edge select = 0: Data on TDP/TDN is sampled on the falling edge of TCLK = 1: Data on TDP/TDN is sampled on the rising edge of TCLK Transmitter operation mode control T_MD[1:0] select different stages of the transmit data path = 00: Enable HDB3 encoder and waveform shaper blocks. Input on pin TD is single rail NRZ data = 01: Enable AMI encoder and waveform shaper blocks. Input on pin TD is single rail NRZ data = 1x: Encoder is bypassed, dual rail NRZ transmit data input on pin TDP/TDN Description
Table-19 TCF0: Transmitter Configuration Register 0
TD_INV
3
0
TCLK_SEL
2
0
T_MD[1:0]
0-1
00
Table-20 TCF1: Transmitter Configuration Register 1
(R/W, Address = 06H)
Symbol DFM_OFF Bit 7-6 5 Default 00 0 Reserved. This bit should be `0' for normal operation. Transmit driver failure monitor disable = 0: DFM is enabled = 1: DFM is disabled Transmit line driver high impedance enable = 0: Normal state = 1: Transmit line driver high impedance enable (other transmit path still work normally) These bits select the transmit template: TCLK 00001 0001 0010 - 1011 11XX 2.048 MHz 2.048 MHz Cable impedance 75 120 Reserved User programmable waveform setting Allowable Cable loss 0-24 dB 0-24 dB Description
THZ
4
1
PULS[3:0]
3-0
0000
1. In internal impedance matching mode, for E1/75 cable impedance, the PULS[3:0] bits (TCF1, 06H) should be set to `0000'. In external impedance matching mode, for E1/75 cable impedance, the PULS[3:0] bits should be set to `0001'.
Table-21 TCF2: Transmitter Configuration Register 2
(R/W, Address = 07H)
Symbol SCAL[5:0] Bit 7-6 5-0 Default 00 100001 Reserved. SCAL specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses which is to be transmitted if needed. The default value of SCAL[5:0] is `100001'. Refer to 3.2.3.2 User-Programmable Arbitrary Waveform. = 100001: Default value for 75 and 120 . One step change of this value results in 3% scaling up/down against the pulse amplitude. Description
Programming Information
35
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-22 TCF3: Transmitter Configuration Register 3
(R/W, Address = 08H)
Symbol DONE RW Bit 7 6 Default 0 0 This bit selects read or write operation = 0: Write to RAM = 1: Read from RAM These bits specify the unit interval address. There are totally 4 unit intervals. = 00: UI address is 0 (The most left UI) = 01: UI address is 1 = 10: UI address is 2 = 11: UI address is 3 These bits specify the sample address. Each UI has totally 16 samples. = 0000: Sample address is 0 (The most left sample) = 0001: Sample address is 1 = 0010: Sample address is 2 ...... = 1110: Sample address is 14 = 1111: Sample address is 15 Description After `1' is written to this bit, a read or write operation is implemented.
UI[1:0]
5-4
00
SAMP[3:0]
3-0
0000
Table-23 TCF4: Transmitter Configuration Register 4
(R/W, Address = 09H)
Symbol WDAT[6:0] Bit 7 6-0 Default 0 0000000 Reserved In Indirect Write operation, the WDAT[6:0] will be loaded to the pulse template RAM, specifying the amplitude of the Sample. After an Indirect Read operation, the amplitude data of the Sample in the pulse template RAM will be output to the WDAT[6:0]. Description
Programming Information
36
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.3
RECEIVE PATH CONTROL REGISTERS (R/W, Address = 0AH)
Symbol R_OFF Bit 7-5 4 Default 000 0 Reserved Receiver power down enable = 0: Receiver power up = 1: Receiver power down Receive data invert = 0: Data on RD or RDP/RDN is active high = 1: Data on RD or RDP/RDN is active low Receive clock edge select (this bit is ignored in slicer mode) = 0: Data on RD or RDP/RDN is updated on the rising edge of RCLK = 1: Data on RD or RDP/RDN is updated on the falling edge of RCLK Receive path decoding selection = 00: Receive data is HDB3 decoded and output on RD pin with single rail NRZ format = 01: Receive data is AMI decoded and output on RD pin with single rail NRZ format = 10: Decoder is bypassed, re-timed dual rail data with NRZ format output on RDP/RDN (dual rail mode with clock recovery) = 11: CDR and decoder are bypassed, slicer data with RZ format output on RDP/RDN (slicer mode) Description
Table-24 RCF0: Receiver Configuration Register 0
RD_INV
3
0
RCLK_SEL
2
0
R_MD[1:0]
1-0
00
Table-25 RCF1: Receiver Configuration Register 1
(R/W, Address= 0BH)
Symbol EQ_ON LOS[4:0] Bit 7 6 5 4:0 Default 0 0 0 10101 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 - 11111 Reserved = 0: Receive equalizer off = 1: Receive equalizer on (LOS programming enabled) Reserved. LOS Clear Level (dB) 0 >-2 >-4 >-6 >-8 >-10 >-12 >-14 >-16 >-18 >-20 Reserved LOS Declare Level (dB) <-4 <-6 <-8 <-10 <-12 <-14 <-16 <-18 <-20 <-22 <-24 Description
Programming Information
37
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-26 RCF2: Receiver Configuration Register 2
(R/W, Address = 0CH)
Symbol SLICE[1:0] Bit 7-6 5-4 Default 00 01 Reserved. Receive slicer threshold = 00: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 40% of the peak amplitude. = 01: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 50% of the peak amplitude. = 10: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 60% of the peak amplitude. = 11: The receive slicer generates a mark if the voltage on RTIP/RRING exceeds 70% of the peak amplitude. Reserved Monitor gain setting: these bits select the internal linear gain boost = 00: 0 dB = 01: 22 dB = 10: 26 dB = 11: 32 dB Description
MG[1:0]
3-2 1-0
10 00
Programming Information
38
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.4
NETWORK DIAGNOSTICS CONTROL REGISTERS (R/W, Address = 0DH)
Symbol PATT[1:0] Bit 7 6-5 Default 00 00 Reserved. These bits select the internal pattern and insert it into transmit data stream. = 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1) = 01: Insert All Ones = 10: Insert PRBS (E1: 215-1) = 11: Reserved Selects reference clock for transmitting internal pattern = 0: Uses TCLK as the reference clock = 1: Uses MCLK as the reference clock Inverts PRBS = 0: The PRBS data is not inverted = 1: The PRBS data is inverted before transmission and detection LOS/AIS criterion is selected as below: = 0: G.775 = 1: ETSI 300233& I.431 AIS enable during LOS = 0: AIS insertion on RDP/RDN/RCLK is disabled during LOS = 1: AIS insertion on RDP/RDN/RCLK is enabled during LOS Automatically Transmit All Ones (enabled only when PATT[1:0] = 00) = 0: Disabled = 1: Automatically Transmit All Ones pattern at TTIP/TRING during LOS Description
Table-27 MAINT0: Maintenance Function Control Register 0
PATT_CLK
4
0
PRBS_INV
3
0
LAC
2
0
AISE
1
0
ATAO
0
0
Table-28 MAINT1: Maintenance Function Control Register 1
(R/W, Address= 0EH)
Symbol RLP Bit 7-3 2 Default 00000 0 Reserved Remote loopback enable = 0: Disables remote loopback (normal transmit and receive operation) = 1: Enables remote loopback Analog loopback enable = 0: Disables analog loopback (normal transmit and receive operation) = 1: Enables analog loopback Digital loopback enable = 0: Disables digital loopback (normal transmit and receive operation) = 1: Enables digital loopback Description
ALP
1
0
DLP
0
0
Table-29 MAINT6: Maintenance Function Control Register 6
(R/W, Address = 13H)
Symbol BPV_INS Bit 7 6 Default 0 0 Reserved. BPV error insertion A `0' to `1' transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream. This bit must be cleared and set again for a subsequent error to be inserted. PRBS logic error insertion A `0' to `1' transition on this bit will cause a single PRBS logic error to be inserted into the transmit PRBS data stream. This bit must be cleared and set again for a subsequent error to be inserted. Description
ERR_INS
5
0
Programming Information
39
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-29 MAINT6: Maintenance Function Control Register 6 (Continued)
(R/W, Address = 13H)
Symbol EXZ_DEF Bit 5 Default 0 EXZ definition select = 0: ANSI = 1: FCC These bits choose which type of error will be counted = 00: The PRBS logic error is counted by a 16-bit error counter. = 01: The EXZ error is counted by a 16-bit error counter. = 10: The Received CV (BPV) error is counted by a 16-bit error counter. = 11: Both CV (BPV) and EXZ errors are counted by a 16-bit error counter. Counter operation mode select = 0: Manual Report mode = 1: Auto Report mode = 0: Clear this bit for the next `0' to `1' transition on this bit. = 1: Error counting result is transferred to CNT0 and CNT1 and the error counter is reset. Description
ERR_SEL
3-2
00
CNT_MD
1
0
CNT_TRF
0
0
Programming Information
40
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.5
INTERRUPT CONTROL REGISTERS (R/W, Address = 14H)
Symbol PRBS_IM Bit 7-5 4 Default 111 1 Reserved PRBS synchronic signal detect interrupt mask = 0: PRBS synchronic signal detect interrupt enabled = 1: PRBS synchronic signal detect interrupt masked TCLK loss detect interrupt mask = 0: TCLK loss detect interrupt enabled = 1: TCLK loss detect interrupt masked Driver Failure interrupt mask = 0: Driver Failure interrupt enabled = 1: Driver Failure interrupt masked Alarm Indication Signal interrupt mask = 0: Alarm Indication Signal interrupt enabled = 1: Alarm Indication Signal interrupt masked Loss Of Signal interrupt mask = 0: Loss Of Signal interrupt enabled = 1: Loss Of Signal interrupt masked Description
Table-30 INTM0: Interrupt Mask Register 0
TCLK_IM
3
1
DF_IM
2
1
AIS_IM
1
1
LOS_IM
0
1
Table-31 INTM1: Interrupt Masked Register 1
(R/W, Address = 15H)
Symbol DAC_OV_IM Bit 7 Default 1 DAC arithmetic overflow interrupt mask = 0: DAC arithmetic overflow interrupt enabled = 1: DAC arithmetic overflow interrupt masked JA overflow interrupt mask = 0: JA overflow interrupt enabled = 1: JA overflow interrupt masked JA underflow interrupt mask = 0: JA underflow interrupt enabled = 1: JA underflow interrupt masked PRBS logic error detect interrupt mask = 0: PRBS logic error detect interrupt enabled = 1: PRBS logic error detect interrupt masked Receive excess zeros interrupt mask = 0: Receive excess zeros interrupt enabled = 1: Receive excess zeros interrupt masked Receive error interrupt mask = 0: Receive error interrupt enabled = 1: Receive error interrupt masked One-Second Timer expiration interrupt mask = 0: One-Second Timer expiration interrupt enabled = 1: One-Second Timer expiration interrupt masked Counter overflow interrupt mask = 0: Counter overflow interrupt enabled = 1: Counter overflow interrupt masked Description
JAOV_IM
6
1
JAUD_IM
5
1
ERR_IM
4
1
EXZ_IM
3
1
CV_IM
2
1
TIMER_IM
1
1
CNT_IM
0
1
Programming Information
41
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-32 INTES: Interrupt Trigger Edge Select Register
(R/W, Address = 16H)
Symbol PRBS_IES Bit 7-5 4 Default 000 0 Reserved This bit determines the PRBS synchronization status interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the PRBS_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the PRBS_S bit in STAT0 status register This bit determines the TCLK Loss interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the TCLK_LOS bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the TCLK_LOS bit in STAT0 status register This bit determines the Driver Failure interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the DF_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the DF_S bit in STAT0 status register This bit determines the AIS interrupt event. = 0: Interrupt event is generated as a `0' to `1' transition of the AIS_S bit in STAT0 status register = 1: Interrupt event is generated as either a `0' to `1' transition or a `1' to `0' transition of the AIS_S bit in STAT0 status register This bit determines the LOS interrupt event. = 0: Interrupt is generated as a `0' to `1' transition of the LOS_S bit in STAT0 status register = 1: Interrupt is generated as either a `0' to `1' transition or a `1' to `0' transition of the LOS_S bit in STAT0 status register Description
TCLK_IES
3
0
DF_IES
2
0
AIS_IES
1
0
LOS_IES
0
0
Programming Information
42
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.6
LINE STATUS REGISTERS (R, Address = 17H)
Symbol PRBS_S Bit 7-5 4 Default 000 0 Reserved Synchronous status indication of PRBS (real time) = 0: 215-1 PRBS is not detected = 1: 215-1 PRBS is detected Note: If PRBS_IM=0: A `0' to `1' transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is `0'. Any changes of this bit causes an interrupt if PRBS_IES bit is set to `1'. Description
Table-33 STAT0: Line Status Register 0 (real time status monitor)
TCLK_LOS
3
0
TCLK loss indication = 0: Normal = 1: TCLK pin has not toggled for more than 70 MCLK cycles. Note: If TCLK_IM=0: A `0' to `1' transition on this bit causes an interrupt if TCLK _IES bit is `0'. Any changes of this bit causes an interrupt if TCLK_IES bit is set to `1'.
DF_S
2
0
Line driver status indication = 0: Normal operation = 1: Line driver short circuit is detected. Note: If DF_IM=0 A `0' to `1' transition on this bit causes an interrupt if DF _IES bit is `0'. Any changes of this bit causes an interrupt if DF_IES bit is set to `1'.
AIS_S
1
0
Alarm Indication Signal status detection = 0: No AIS signal is detected in the receive path = 1: AIS signal is detected in the receive path Note: If AIS_IM=0 A `0' to `1' transition on this bit causes an interrupt if AIS _IES bit is `0'. Any changes of this bit causes an interrupt if AIS_IES bit is set to `1'.
LOS_S
0
0
Loss Of Signal status detection = 0: Loss of signal on RTIP/RRING is not detected. = 1: Loss of signal on RTIP/RRING is detected. Note: If LOS_IM=0 A `0' to `1' transition on this bit causes an interrupt if LOS _IES bit is `0'. Any changes of this bit causes an interrupt if LOS_IES bit is set to `1'.
Programming Information
43
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-34 STAT1: Line Status Register 1 (real time status monitor)
(R, Address = 18H)
Symbol RLP_S Bit 7-6 5 Default 00 0 Reserved. Indicating the status of Remote Loopback = 0: The remote loopback is inactive. = 1: The remote loopback is active (closed). Reserved Description
-
4-0
00000
Programming Information
44
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.7
INTERRUPT STATUS REGISTERS (R, Address = 19H) (this register is reset and relevant interrupt request is cleared after a read)
Symbol PRBS_IS Bit 7-5 4 Default 000 0 Reserved This bit indicates the occurrence of the interrupt event generated by the PRBS synchronization status. = 0: No PRBS synchronization status interrupt event occurred = 1: PRBS synchronization status interrupt event occurred This bit indicates the occurrence of the interrupt event generated by the TCLK loss detection. = 0: No TCLK loss interrupt event. = 1: TCLK loss interrupt event occurred. This bit indicates the occurrence of the interrupt event generated by the Driver Failure. = 0: No Driver Failure interrupt event occurred = 1: Driver Failure interrupt event occurred This bit indicates the occurrence of the AIS (Alarm Indication Signal) interrupt event. = 0: No AIS interrupt event occurred = 1: AIS interrupt event occurred This bit indicates the occurrence of the LOS (Loss of signal) interrupt event. = 0: No LOS interrupt event occurred = 1: LOS interrupt event occurred Description
Table-35 INTS0: Interrupt Status Register 0
TCLK_LOS_IS
3
0
DF_IS
2
0
AIS_IS
1
0
LOS_IS
0
0
Table-36 INTS1: Interrupt Status Register 1
(R, Address = 1AH) (this register is reset and the relevant interrupt request is cleared after a read)
Symbol DAC_OV_IS Bit 7 Default 0 Description This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event. = 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred = 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event. = 0: No JA Overflow interrupt event occurred = 1: JA Overflow interrupt event occurred This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event. = 0: No JA Underflow interrupt event occurred = 1: JA Underflow interrupt event occurred This bit indicates the occurrence of the interrupt event generated by the detected PRBS logic error. = 0: No PRBS logic error interrupt event occurred = 1: PRBS logic error interrupt event occurred This bit indicates the occurrence of the Excessive Zeros interrupt event. = 0: No Excessive Zeros interrupt event occurred = 1: EXZ interrupt event occurred This bit indicates the occurrence of the Code Violation interrupt event. = 0: No Code Violation interrupt event occurred = 1: Code Violation interrupt event occurred This bit indicates the occurrence of the One-Second Timer Expiration interrupt event. = 0: No One-Second Timer Expiration interrupt event occurred = 1: One-Second Timer Expiration interrupt event occurred This bit indicates the occurrence of the Counter Overflow interrupt event. = 0: No Counter Overflow interrupt event occurred = 1: Counter Overflow interrupt event occurred
JAOV_IS
6
0
JAUD_IS
5
0
ERR_IS
4
0
EXZ_IS
3
0
CV_IS
2
0
TMOV_IS
1
0
CNT_OV_IS
0
0
Programming Information
45
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.8
COUNTER REGISTERS (R, Address = 1BH)
Symbol Bit 7-0 Default 00H Description This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
Table-37 CNT0: Error Counter L-byte Register 0
CNT_L[7:0]
Table-38 CNT1: Error Counter H-byte Register 1
(R, Address = 1CH)
Symbol CNT_H[7:0] Bit 7-0 Default 00H Description This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
Programming Information
46
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
5
HARDWARE CONTROL PIN SUMMARY
Pin No. TQFP 17 16 Symbol MODE1 MODE0 Description MODE[1:0]: Operation mode of control interface select 00= Hardware interface 01= Serial interface 10= Parallel - multiplexed - Motorola Interface 11= Parallel - multiplexed - Intel Interface TERM: Termination interface select This pin selects internal or external impedance matching for both receiver and transmitter 0= ternary interface with external impedance matching network. 1= ternary interface with internal impedance matching network RXTXM[1:0]: Receive and transmit path operation mode select 00= single rail with HDB3 coding 01= single rail with AMI coding 10= dual rail interface with CDR enable 11= slicer mode PULS: This pin is used to select the following functions: * Transmit pulse template * Internal termination impedance (75 / 120) PULS 0 1 28 RPD TCLK 2.048 MHz 2.048 MHz Cable impedance (internal matching impedance) 75 120 Cable loss 0-24 dB 0-24 dB
Table-39 Hardware Control Pin Summary
23
TERM
21 20
RXTXM1 RXTXM0
30
PULS
RPD: Receiver power down control 0= Normal operation 1= receiver power down PATT[1:0]: Transmit test pattern select In hardware control mode, these pins select the transmit pattern 00 = normal 01= All Ones 10= PRBS 11= transmitter power down JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select 00= JA is disabled 01= JA in receiver, broad bandwidth, FIFO=64 bits 10= JA in receiver, narrow bandwidth, FIFO=128 bits 11= JA in transmitter, narrow bandwidth, FIFO=128 bits MONT: Receive monitor n gain select 0= 0 dB 1= up to 26 dB LP[1:0]: Loopback mode select 00= no loopback 01= analog loopback 10= digital loopback 11= remote loopback THZ: Transmitter Driver High Impedance Enable This signal enables or disables transmitter driver. A low level on this pin enables the driver while a high level on this pin places the driver in high impedance state. RCLKE: the active edge of RCLK select when hardware control mode is used 0= select the rising edge as active edge of RCLK 1= select the falling edge as active edge of RCLK
27 26
PATT1 PATT0
15 14
JA1 JA0
22
MONT
25 24
LP1 LP0
13
THZ
11
RCLKE
Hardware Control Pin Summary
47
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-39 Hardware Control Pin Summary (Continued)
Pin No. TQFP 29 31 32 33 Symbol In Hardware mode, this pin has to be tied to GND. Description
Hardware Control Pin Summary
48
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
6
TEST SPECIFICATIONS
Table-40 Absolute Maximum Rating
Symbol VDDA, VDDD VDDIO VDDT Vin Core Power Supply I/O Power Supply Transmit Power Supply Input Voltage, Any Digital Pin Input Voltage, Any RTIP and RRING pin1 ESD Voltage, any pin Transient latch-up current, any pin Iin Input current, any digital pin
4 4
Parameter
Min -0.5 -0.5 -0.5 GND-0.5 GND-0.5 2000 2 500 3
Max 4.6 4.6 4.6 5.5 VDDA+0.5
Unit V V V V V V V
100 -10 10 100 1.41 120 -65 +150
mA mA mA W C C
DC Input current, any analog pin Pd Tc Ts Case Temperature Storage Temperature
Maximum power dissipation in package
CAUTION: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1.Reference to ground 2.Human body model 3.Charge device model 4.Constant input current
Table-41 Recommended Operation Conditions
Symbol VDDA, VDDD VDDIO VDDT TA Core Power Supply I/O Power Supply Transmitter Power Supply Ambient operating temperature 75 load Total current dissipation1,2,3 120 Load 50% ones density data 100% ones density data 58 70 64 76 mA 50% ones density data 100% ones density data 52 64 58 70 mA Parameter Min 3.13 3.13 3.13 -40 Typ 3.3 3.3 3.3 25 Max 3.47 3.47 3.47 85 Unit V V V C
1.Power consumption includes power consumption on device and load. Digital levels are 10% of the supply rails and digital outputs driving a 50 pF capacitive load. 2.Maximum power consumption over the full operating temperature and power supply voltage range. 3.In short haul mode, if internal impedance matching is chosen, 75 power dissipation values are measured with template PULS[3:0] = 0000; 120 power dissipation values are measured with template PULS[3:0] = 0001.
Test Specifications
49
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-42 Power Consumption
Symbol 3.3 V, 75 Load 50% ones density data: 100% ones density data: 3.3 V, 120 Load 50% ones density data: 100% ones density data: 192 243 264 mW 172 212 243 mW Parameter Min Typ Max1,2 Unit
1.Maximum power and current consumption over the full operating temperature and power supply voltage range. 2.Power consumption includes power absorbed by line load and external transmitter components.
Table-43 DC Characteristics
Symbol VIL VIH VOL VOH VMA IZL Ci Co Co Input High Voltage Output Low level Voltage (Iout=1.6mA) Output High level Voltage (Iout=400A) Analog Input Quiescent Voltage (RTIP, RRING pin while floating) High Impedance Leakage Current Input capacitance Output load capacitance Output load capacitance (bus pins) -10 Parameter Input Low Level Voltage Min 2.0 2.4 Typ 1.5 10 15 50 100 Max 0.8 0.4 VDDIO Unit V V V V V A pF pF pF
Table-44 Receiver Electrical Characteristics
Symbol Parameter Receiver sensitivity Adaptive Equalizer Disabled: Adaptive Equalizer Enabled: Analog LOS level Adaptive Equalizer Disabled: Adaptive Equalizer Enabled: 800 -4 -24 Min Typ Max -10 -20 Unit dB A LOS level is programmable with Adaptive Equalizer enabled. Not available in Hardware mode. Test conditions
mVp-p dB
Test Specifications
50
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-44 Receiver Electrical Characteristics (Continued)
Symbol Parameter Allowable consecutive zeros before LOS G.775: I.431/ETSI300233: LOS reset Receive Intrinsic Jitter 20 Hz - 100 kHz Input Jitter Tolerance 1 Hz - 20 Hz 20 Hz - 2.4 KHz 18 KHz - 100 KHz ZDM Receiver Differential Input Impedance Input termination resistor tolerance RRX Receive Return Loss 51 KHz - 102 KHz 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz Receive path delay Single rail Dual rail 20 20 20 7 2 37 5 2 20 1% dB dB dB U.I. U.I. G.703 Internal termination 12.5 0.05 Min Typ 32 2048 % ones U.I. U.I. U.I. U.I. K G.775, ETSI 300 233 JA enabled G.823, with 6 dB cable attenuation Max Unit Test conditions
Internal mode
RPD
JA disabled
Table-45 Transmitter Electrical Characteristics
Symbol Vo-p Output pulse amplitudes 75 load 120 load Zero (space) level 75 load 120 load Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses (T1.102) Tpw Output Pulse Width at 50% of nominal amplitude Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval (G.703) Ratio of the width of Positive and Negative Pulses at the center of the pulse interval (G.703) RTX Transmit Return Loss (G.703) 51 KHz - 102 KHz 102 KHz - 2.048 MHz 2.048 MHz - 3.072 MHz JTXp-p Td Intrinsic Transmit Jitter (TCLK is jitter free) 20 Hz - 100 KHz Transmit path delay (JA is disabled) Single rail Dual rail Isc Line short circuit current (measured on the TTIP/TRING pins) 8.5 4.5 100 U.I. U.I. mAp 0.050 U.I. 20 15 12 dB dB dB 232 0.95 0.95 244 Parameter Min 2.14 2.7 -0.237 -0.3 -1 Typ 2.37 3.0 Max 2.60 3.3 0.237 0.3 +1 200 256 1.05 1.05 Unit V V V V % mV ns
Vo-s
Test Specifications
51
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-46 Transmitter and Receiver Timing Characteristics
Symbol MCLK frequency MCLK tolerance MCLK duty cycle Transmit path TCLK frequency TCLK tolerance TCLK Duty Cycle t1 t2 Transmit Data Setup Time Transmit Data Hold Time Delay time of THZ low to driver high impedance Delay time of TCLK low to driver high impedance Receive path Clock recovery capture range 1 RCLK duty cycle 2 t4 t5 t6 t7 t8 RCLK pulse width 2 RCLK pulse width low time RCLK pulse width high time Rise/fall time 3 Receive Data Setup Time Receive Data Hold Time 200 200 244 244 40 457 203 203 80 50 488 244 244 60 519 285 285 20 ppm % ns ns ns ns ns ns 75 -50 10 40 40 10 2.048 +50 90 MHz ppm % ns ns us U.I. -100 30 Parameter Min Typ 2.048 100 70 Max Unit MHz ppm %
1.Relative to nominal frequency, MCLK= 100 ppm 2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2 UI displacement for E1 per ITU G.823). 3.For all digital outputs. C load = 15 pF
TCLK
t1
t2
TD/TDP TDN
Figure-18 Transmit System Interface Timing
Test Specifications
52
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
t4 RCLK t6 t5
t7 RDP/RD (RCLK_SEL = 0 software mode) (RCLKE = 0 hardware mode) RDN/CV
t8
t7 RDP/RD (RCLK_SEL = 1 software mode) (RCLKE = 1 hardware mode) RDN/CV
t8
Figure-19 Receive System Interface Timing
Table-47 Jitter Tolerance
Jitter Tolerance 1 Hz 20 Hz - 2.4 KHz 18 KHz - 100 KHz Min 37 1.5 0.2 Typ Max Unit U.I. U.I. U.I. Standard G.823 Cable attenuation is 6 dB
Test Specifications
53
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Figure-20 E1 Jitter Tolerance Performance
Table-48 Jitter Attenuator Characteristics
Parameter Jitter Transfer Function Corner (-3 dB) Frequency 32/64/128 bits FIFO JABW = 0: JABW = 1: Jitter Attenuator 6.8 0.9 Hz Hz Min Typ Max Unit
(G.736)
@ 3 Hz @ 40 Hz @ 400 Hz @ 100 kHz Jitter Attenuator Latency Delay 32 bits FIFO: 64 bits FIFO: 128 bits FIFO: Input jitter tolerance before FIFO overflow or underflow 32 bits FIFO: 64 bits FIFO: 128 bits FIFO:
-0.5 -0.5 +19.5 +19.5 16 32 64 28 58 120
dB
U.I. U.I. U.I. U.I. U.I. U.I.
Test Specifications
54
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Figure-21 E1 Jitter Transfer Performance
Test Specifications
55
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
7
7.1
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS
SERIAL INTERFACE TIMING
Table-49 Serial Interface Timing Characteristics
Symbol t1 t2 t3 t4 t5 t6 t7 t10 t11 SCLK High Time SCLK Low Time Active CS to SCLK Setup Time Last SCLK Hold Time to Inactive CS Time CS Idle Time SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK to SDO Valid Delay Time Inactive CS to SDO High Impedance Hold Time Parameter Min 100 100 5 41 41 0 82 95 90 Typ Max Unit ns ns ns ns ns ns ns ns ns Comments
CS t3 SCLK t6 SDI LSB t7 LSB t7 MSB t1 t2 t4 t5
Figure-22 Serial Interface Write Timing
1 SCLK CS SDO t10 0 1 2 3 4 5 6 t4 t11 7 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Figure-23 Serial Interface Read Timing with SCLKE=1
1 SCLK CS SDO
2
3
4
5
6
7
8
9 t10 0
10
11
12
13
14
15
16 t4 t11 7
1
2
3
4
5
6
Figure-24 Serial Interface Read Timing with SCLKE=0
Microcontroller Interface Timing Characteristics
56
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
7.2
PARALLEL INTERFACE TIMING
Table-50 Multiplexed Motorola Read Timing Characteristics
Symbol tRC tDW tRWV tRWH tASW tADD tADS tADH tPRD tDAZ tAKD tAKH tAKZ tRecovery Read Cycle Time Valid DS Width Delay from DS to Valid Read R/W to DS Hold Time Valid AS Width Delay from AS active to DS active Address to AS Setup Time Address to AS Hold Time DS to Valid Read Data Propagation Delay Delay from DS inactive to data bus High Impedance Acknowledgement Delay Acknowledgement Hold Time Acknowledgement Release Time Recovery Time from Read Cycle 5 5 5 65 10 0 5 5 175 20 190 15 5 Parameter Min 190 180 15 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tRC DS+CS tDW tRWH tRWV R/W tASW AS tPRD READ AD[7:0] Valid address tADS tADH tAKD ACK tADD
tRecovery
tDAZ Valid Data
tAKH
tAKZ
Figure-25 Multiplexed Motorola Read Timing
Microcontroller Interface Timing Characteristics
57
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-51 Multiplexed Motorola Write Timing Characteristics
Symbol tWC tDW tRWV tRWH tASW tADD tADS tADH tDV tDHW tAKD tAKH tAKZ tRecovery Write Cycle Time Valid DS Width Delay from DS to Valid Write R/W to DS Hold Time Valid AS Width Delay from AS active to DS active Address to AS Setup Time Address to AS Hold Time Delay from DS to Valid Write Data Write Data to DS Hold Time Acknowledgement Delay Acknowledgement Hold Time Acknowledgement Release Time Recovery Time from Write Cycle 5 5 65 150 15 5 65 10 0 5 5 15 Parameter Min 120 100 15 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tWC DS+CS tDW tRWH tRWV R/W tASW AS tDHW tDV Write AD[7:0] Valid address tADS tADH tAKD ACK tADD
tRecovery
Valid Data
tAKH
tAKZ
Figure-26 Multiplexed Motorola Write Timing
Microcontroller Interface Timing Characteristics
58
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-52 Multiplexed Intel Read Timing Characteristics
Symbol tRC tRDW tARD tALEW tADS tADH tPRD tDAZ tAKD tAKH tAKZ tRecovery Read Cycle Time Valid RD Width Delay from ALE to Valid Read Valid ALE Width Address to ALE Setup Time Address to ALE Hold Time RD to Valid Read Data Propagation Delay Delay from RD inactive to data bus High Impedance Acknowledgement Delay Acknowledgement Hold Time Acknowledgement Release Time Recovery Time from Read Cycle 5 5 5 Parameter Min 190 180 0 10 5 5 175 20 190 15 5 Max Unit ns ns ns ns ns ns ns ns ns ns ns
tRC RD+CS tALEW ALE tPRD READ AD[7:0] Valid address tADS tADH tAKD RDY tARD tRDW
tRecovery
tDAZ Valid Data
tAKH
tAKZ
Figure-27 Multiplexed Intel Read Timing
Microcontroller Interface Timing Characteristics
59
December 9, 2005
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-53 Multiplexed Intel Write Timing Characteristics
Symbol tWC tWRW tALEW tAWD tADS tADH tDV tDHW tAKD tAKH tAKZ tRecovery Write Cycle Time Valid WR Width Valid ALE Width Delay from ALE to Valid Write Address to ALE Setup Time Address to ALE Hold Time Delay from WR to Valid Write Data Write Data to WR Hold Time Acknowledgement Delay Acknowledgement Hold Time Acknowledgement Release Time Recovery Time from Write Cycle 5 5 65 150 15 5 Parameter Min 120 100 10 0 5 5 15 Max Unit ns ns ns ns ns ns ns ns ns ns ns
tWC WR+CS tALEW ALE tDHW tDV Write AD[7:0] Valid address tADS tADH tAKD RDY tAWD tWRW
tRecovery
Valid Data
tAKH
tAKZ
Figure-28 Multiplexed Intel Write Timing
Microcontroller Interface Timing Characteristics
60
December 9, 2005
IDT82V2051E IDT82P2816
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT HIGH-DENSITY T1/E1/J1
ORDERING INFORMATION
IDT XXXXXXX Device Type XX X Process/ Temperature Range
Blank
Industrial (-40 C to +85 C)
PP PPG
Thin Quad Flatpack (TQFP, PP44) Green Thin Quad Flatpack (TQFP, PPG44) Short Haul LIU
82V2051E
DATASHEET DOCUMENT HISTORY
12/09/2005 pgs. 1, 14, 18, 24, 31, 32, 39, 51, 52, 61
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
for Tech Support:
408-360-1552
email:TELECOMhelp@idt.com
61

▲Up To Search▲

Price & Availability of IDT82V2051EPPG

	To Download IDT82V2051EPPG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .