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| STA8058 TeseoTM high performance GPS multi chip module (MCM) Data Brief Features GPS Multi Chip Module: - STA2058 Teseo Baseband - STA5620 RF Front-end Complete Embedded Memory System: - Flash 256K+16K bytes - RAM 64K bytes. 66-MHz ARM7TDMI 32 bit processor High performance GPS engine (HPGPS) SBAS (WAAS and EGNOS) supported Sensitivity (-146dBm acquisition, -159dBm tracking) Time to first fix (1s reacquisition, 2.5s hot start, 34s warm start, 39s cold start) Accuracy (2m autonomous) Extensive GPS receiver interfaces: 32 GPIOs, 4 UARTs, 2 SPIs, 2 I2Cs, 1CANs 2.0, 1 USB 1.1, 1 HDLC and 4 channels ADC Compatible with L1 Signal (C/A code) ST Proprietary Technology - CMOS Flash Embebbed technology for STA2058 - BiCMOS Sige technology for STA5620 LFBGA104 lead-free package -40C to 85C operating temperature range LFBGA104 (7x11x1.4mm) Description STA8058 Teseo MCM is a fully embedded GPS engine integrating STA2058 Teseo baseband. and STA5620 RF front-end. The embedded flash memory enables the equipment manufacturer to load the entire GPS software (including tracking, acquisition, navigation and data output) after customising its interfaces to his needs. A standard GPS library is available from ST. By combining the ARM7TDMI microcontroller core with on-chip FLASH/RAM, 16-channel GPS correlator DSP, RF Front-end and an extensive range of interfaces on single package solution, the STA8058 provides a highly-flexible and costeffective solution for GPS applications. Evaluation kits STA8058 module reference designs (17x19mm and 25x25mm) Evaluation board hosting STA8058 module Device summary Order code STA8058 Table 1. Package LFBGA104 (7x11x1.4mm) Packing Tray October 2007 Rev 1 1/14 www.st.com 14 For further information contact your local STMicroelectronics sales office. Contents STA8058 Contents 1 2 Features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 LFBGA104 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/14 STA8058 Features summary 1 Features summary ARM7TDMI 16/32 bit RISC CPU based host microcontroller running at a frequency up to 66 MHz. Complete Embedded Memory System: - - FLASH 256K bytes + 16K bytes (100K erasing/programming cycles) RAM 64K bytes. 16 channel High performance GPS correlation DSP. ST Propietary Technology: - - CMOS Flash Embedded Technology for Baseband BiCMOS Sige for Radio Front-end SBAS (WAAS and EGNOS) supported. -40C to 85C operating temperature range. 104-pin LFBGA104 package. Power Supply: - - - - 3.0V to 3.6V operating supply range for Input/Output periphery 3.0V to 3.6V operating supply range for A/D Converter reference 1.8V operating supply range for core supply provided by internal Voltage Regulator with external stabilization capacitor or by external supply voltage 2.4V to 3V operating supply range for RF Front-end section Reset and Clock Control Unit able to provide low power modes (WAIT, SLOW, STOP, STANDBY) and to generate the internal clock from the external reference through integrated PLL. 32 programmable General Purpose I/O, each pin programmable independently as digital input or digital output; 30 are multiplexed with peripheral functions; 16 can generate an interrupt on input level/transition. Real time clock module with 32KHz low power oscillator and separate power supply to continue running during stand-by mode. 16-bit Watchdog Timer with 8 bits prescaler for system reliability and integrity. One CAN module compliant with the CAN specification V2.0 part B (active) and bit rate can be programmed up to 1 MBaud. Four 16-bit programmable Timers with 7 bit prescaler, up to two input capture/output compare, one pulse counter function, one PWM channel with selectable frequency each. 4 channels 12-bit sigma-delta Analog to Digital Converter, single channel or multi channel conversion modes, single-shot or continuous conversion modes, sample rate 1 KHz, conversion range 0-2.5V. Three Serial Communication Interfaces (UART) allow full duplex, asynchronous, communications with external devices, independently programmable TX and RX baud rates up to 625K baud. One UART adapted to suit Smart Card interface needs, for asynchronous SC as defined by ISO 7816-3. It includes SC clock generation. Two Serial Peripheral Interfaces (SPI) allow full duplex, synchronous communications with external devices, master or slave operation, max baud rate of 5.5Mb/s. One SPI may be used as Multimedia Card interface. 3/14 Features summary STA8058 Two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C mode (400 KHz), 7/10 bit addressing modes. One I2C Interface is multiplexed with one SPI, so either 2 x SPI + 1 x I2C or 1 x SPI + 2 x I2C may be used at a time. Enhanced Interrupt Controller supports 32 interrupt vectors, independently maskable, with interrupt vector table for faster response and 16 priority levels, software programmable for each source. Up to 2 maskable interrupts may be mapped on FIQ. Wake-up unit allows exiting from powerdown modes by detection of an event on two external pins (one is active high and other is active low) or on internal Real Time Clock alarm. USB unit V1.1 compliant, software configurable endpoint setting, USB Suspend/Resume support High Level Data Link Controller (HDLC) unit supports full duplex operating mode, NRZ, NRZI, FM0 and MANCHESTER modes, and internal 8-bit Baud Rate Generator. RF Front-end Features: - - - - - LOW IF (4MHz) architecture Compatible with GPS L1 signal VGA Gain internally regulated On chip programmable PLL SPI Interface 4/14 STA8058 Pin description 2 2.1 Pin description Logic symbol Figure 1. STA8058 Teseo MCM symbol V18 [2] V33 [7] Power Pads V27 [8] VSS [10] VSSRF [11] AVSS AVDD V18BKP TESEO MCM Xtal (IN,Out,Clk) SPI (DI,DO,CS, CLK) Enable (Chip,RF) Mode GPS_CLK Sign RF_IN AGC_CNTR IF_TEST RF Pads GPSCLK Clock & Reset CK RSTINn P0.[15:0] P1.[15:0] GeneraI Purpose I/O JTAG Port JTDI JTCK JTMS JTRSTn JTDO BOOTEN GPSDAT nSTDBY_I RTCXTO RTCXTI WAKEUP RTC & WKUP Pads USBDP USBDN USB Pads 5/14 Pin description STA8058 2.2 System block diagram Figure 2. STA8058 Teseo Baseband block diagram ARM7TD 1 DP MI 256K ARM7 Native BUS Flash 64KRAM 5 DP STC (JTAG) 3 DP 5 DP VREG RCCU PLL INTERRUPT CONTR. APB BRIDGE3 HPGPS 16-ch. correlator + Emerald DSP 3 DP APB BRIDGE1 APB BRIDGE2 I2C0 I2C1 APB BUS APB BUS SPI0 SPI1 UART0 UART1 UART2 UART3 [USB] [CAN] 2 AF 2 AF 4 AF 4 AF 2 AF 2 AF 2 AF 2 AF 3 DP 2 AF 4 AF 12-bit ADC TIMER0 4 AF 2 AF 4 AF TIMER1 TIMER2 TIMER3 RTC 2 DP 16 AF OSCILL Wakeup WATCH 2 AF DOG Fully Prog. 32 IO I/O PORTS HDLC 3 AF 6/14 STA8058 Figure 3. enabled by rfe & speci fic enables IR Mixer IF filter if_out_en AGC_CTRL IF_TEST SIGN RF_IN AGC ADC Combiner Polyphase Filter mag mag sign CP PFD gce & rfe CMOS Drivers 0 90 Buffer 2 bits MAG RFA STA5620 RF Front-end GPS_CLK /N lo48_clk / 48 test_clk /2 /R gps_clk LO96 TEST_EN1 TEST_EN2 TEST_CLK SPI_CS/ SPI_CLK SPI_DI SPI_DO MODE RF_EN SPI Interface hce Test Logic gps_clk sign mag gce sample_mode (1:0) Variable Xtal XTAL_CLK Pin description 7/14 8/14 Pin description Figure 4. The two dice must be interconnected eachother at board leve l STA8058 Teseo MCM SAW Filter LNA SPI_DI SPI_DO SPI_CLK S1_SCLK S1_MISO S1_MOSI RF_IN SPI_CS S1_SSN 3 Timers [9], ADC[4] SPI[4], I2C[3], 3 UARTS [6] USB[3], CAN[2], HDLC[3] P1.8/PPS P1.9/PRN Sign IF_TEST MODE CHIP_EN AGC_CNTR RF_EN GPIO GPIO GPS_Dat STA5620 RF Front-End STA2058 Baseband Wake_Up NRSTIN NSTDBY_IN STA8058 Teseo MCM block diagram BOOT0, BOOT1, BOOTEN JTDI,JTCK,JTMS,JTRSTn,JTDO XTAL_IN TCXO XTAL_CLK CK GPS_CLK GPSCLK RTCXTI RTCXTO V27_RF [5] V27_PLL[4] V33 VSSRF [10] VSSRF_A [2] VSSRF_IO V33 [4] AVDD V33IO_PLL V33_REG_BKP V18[2] V18BKP VSS [4] AVSS VSSIO_PLL VSS_REG VSS_BKP STA8058 VSS18[2] STA8058 Pin description 2.3 Table 2. 1 A VSS P1.2/T3_ OCMPA/ AIN.2 P1.1/T3_ ICAPA/AI N.1 V33IO_P LL LFBGA104 ball out Ball out for LFBGA104 package 2 AVSS 3 AVDD 4 V18BKP 5 RTCXTO NSTDBY _IN 6 RTCXTI 7 V33RE G_BKP VSSRE G 8 GPSDA T GPSCL K P0.5/S1 _MOSI P0.6/S1 _SCLK 9 nJTRST 10 RF_EN 11 XTAL_O UT V27PLL 12 XTAL_IN 13 VSSRF B VSS18 P1.0/T3_ OCMPB/ AIN.0 P1.3/T3_ ICAPB/AI N.3 V18 VSSBKP V33 GPS_CLK CHIP_EN V27PLL V27PLL C P1.4/T1 _ICAPA P1.7/T1 _OCMP A P1.9/PR N.11 P1.10/U SBCLK P0.1/SO _MOSI/ U3.RX P1.14/H RXD/IO. SDA P1.5/T1_ ICAPB NRSTIN PO.15/W AKEUP CK SPI_DI XTAL_CLK VSSRF V27PLL V27RF D VSS VSS JTCK P0.13/U2 _RX/T2. OCMPA P0.14/U2 _TX/T2.I CAPA P0.9/UO _TX/BO OT.0 JTDO SPI_CLK MODE VSSRF VSSRF VSSRF_A E VSSIO_P P1.8/PP LL S P1.11/ CANRX P1.12/ CANTX P1.6/T1_ OCMPB P0.3/SO _SSN/I1. SDA P0.0/SO _MISO/U 3.TX P1.15/HT XD VSS18 JTMS JTDI SPI_CS IF_TEST VSSRF VSSRF RF_IN F USBDP V18 V33 P0.11/U 1_TX/B OOT.1 PO.8/U O_RX/U 0.TX P0.4/S1 _MISO BOOTE N P0.10/U 1_RX/U 1.TX SPI_DO AGC_CNT R VSSRF VSSRF VSSRF_A G USBDN P0.7/S1_ SSN SIGN V27RF V27RF V27RF VSSRF H VSS P1.13/H CLK/IO.S CL P0.2/SO PO.12/S _SCLK/I1 CCLK .SCL V33 VSSRF:IO V33 V27RF VSSRF 2.4 Table 3. Symbol V33 VSS V33IO-PLL VSSIO-PLL V33REG_BKP VSSREG Power supply pins Power supply pins I/O Function Digital supply voltage for I/O circuitry (3.3 Volt) Digital ground for I/O circuitry Digital supply voltage for I/O circuitry and for PLL reference (3.3V) Digital ground for I/O circuitry and for PLL reference Digital supply voltage for backup block I/O circuitry and for Ballast I/O (3.3V) Digital ground for Ballast I/O Digital supply voltage for core circuitry (1.8 Volt): When using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 10F (Tantalum, low series resistance) + 33nF (ceramic) shall be connected between these pins and VSS18 to guarantee on-chip voltage stability. Digital ground for core circuitry Digital supply voltage for backup block (RTC, oscillator, Wake-up controller - 1.8 Volt): when using the internal voltage regulator, this pin shall not be driven by an external voltage supply, but a capacitance of at least 1F shall be connected between this pin and VSSBKP to guarantee on-chip voltage stability. LFBGA104 B6,F7,G10,H9,H11 A1,D4,D5,H1 D1 E1 A7 B7 V18 - B3,F5 VSS18 - B2,E5 V18BKP - A4 9/14 Pin description Table 3. Symbol VSSBKP AVDD AVSS V27RF V27PLL VSSRF VSSRF_A VSSRF_IO STA8058 Power supply pins (continued) I/O Function Digital ground for backup logic Analog supply voltage for the A/D converter Analog supply ground for the A/D converter Analog supply voltage for RF chain (2.7V) Analog supply voltage for PLL embedded into RF part (2.7V) Analog supply ground for RF core Analog supply ground for RF amplifier Analog supply ground for RF IO circuirty LFBGA104 B4 A3 A2 C13,G10,G11,G12,H 12 B11,B12,B13,C12 A13,C11,D11,D13, E11,E12,F11,F12, G13,H13 D13, F13 H10 Note: V33 and V33IO-PLL are all internally connected. Same for VSS and VSSIO-PLL. All VSS, VSS18, VSSBKP, AVSS,VSSRF,VSSRF_A and VSSRF_IO pins must be tied together to the common ground plane, taking care of noise filtering, especially on AVSS ,VSSRF , VSSRF_A and VSSRF_IO 10/14 STA8058 Electrical characteristics 3 Electrical characteristics See STA2058 (Teseo Baseband) and STA5620 (RF Front-end) datasheet for related data. 11/14 Package information STA8058 4 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 5. LFBGA104 (11x7x1.4mm) mechanical data and package dimensions mm DIM. MIN. A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff 6.900 0.350 0.400 0.210 0.990 0.200 0.800 TYP. MAX. 1.400 0.0083 0.0390 0.0079 0.0315 MIN. TYP. MAX. 0.0551 inch OUTLINE AND MECHANICAL DATA 0.450 0.0138 0.0157 0.0177 10.900 11.000 11.100 0.4291 0.4331 0.4370 9.600 7.000 5.600 0.800 0.700 0.100 0.150 0.080 0.3780 7.100 0.2717 0.2756 0.2795 0.2205 0.0315 0.0276 0.0039 0.0059 0.0031 Body: 11 x 7 x 1.4mm LFBGA104 Low profile Fine Pitch Ball Grid Array 8054244 B 12/14 STA8058 Revision history 5 Revision history Table 4. Date 25-Oct-2007 Document revision history Revision 1 Initial release. Changes 13/14 STA8058 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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