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| HV9982 Three-Channel, Closed-Loop, Switch Mode LED Driver IC Features Switch mode controller for single-switch converters Closed loop control of output current Buck Boost SEPIC High PWM dimming ratio Internal 40V linear regulator Constant frequency operation Programmable slope compensation Linear and PWM dimming +0.2A/-0.4A gate drives for the switching FETs Output short circuit protection Output over voltage protection Hiccup mode protection Analog control of PWM dimming General Description The HV9982 is a three-channel, closed loop, peak current mode PWM controller for driving a constant output current. It can be used for driving either RGB LEDs or multiple channels of white LEDs. The HV9982 includes a 40V linear regulator which provides an 8.0V supply to power the IC. The switching frequencies of the three converters are controlled by an external clock signal. The channels operate at a switching frequency of 1/12th of the external clock frequency to minimize the input current ripple. Each converter is driven by a peak current mode controller with output current feedback. The three output currents can be individually dimmed using either linear or PWM dimming. The IC also includes three disconnect FET drivers which enable high PWM dimming ratios and also help to disconnect the input in case of an output short circuit condition. HV9982 includes a hiccup mode protection for both open LED and short circuit condition with automatic recovery when the fault clears. Applications RGB backlight applications Multiple string white LED driver applications Typical Boost Application Circuit VIN VDD VDD1 VDD2 GATE1 CS1 GND1 OVP1 FLT1 VDD3 FDBK1 PWMD1 PWMD2 PWMD3 REF1 REF2 REF3 EN CLK GND COMP1 COMP2 COMP3 SKIP S1 S2 GATE3 CS3 GND3 OVP3 FLT3 FDBK3 RAMP GATE2 CS2 HV9982 GND2 OVP2 FLT2 FDBK2 HV9982 Ordering Information 40-Lead QFN Device HV9982 6x6mm body, 1.0mm height (max), 0.50mm pitch Pin Configuration GATE1 GATE2 FDBK2 VDD2 GATE3 31 30 VDD3 FLT3 CS3 COMP3 FBDK3 GND REF3 OVP3 CLK NC 10 11 COMP2 RAMP REF2 SKIP PWMD2 PWMD1 PWMD3 GND 20 OVP2 S1 21 S2 GND2 GND1 CS2 GND3 FLT2 HV9982K6-G 40 VDD1 FLTI CS1 COMP1 1 -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Parameter VIN to GND VDD to GND, VDD 1-3 to GND All other pins to GND Junction temperature Storage ambient temperature range Value -0.5V to +45V -0.3V to +10V -0.3V to (VDD + 0.3V) FBDK1 REF1 OVP1 VIN VDD EN +125C -65C to +150C 5000mW Continuous Power dissipation (TA = +25C) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 40-Lead QFN (K6) (top view) Product Marking HV9982 LLLLLL YYWW AAACCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = "Green" Packaging Thermal Resistance Package 40-Lead QFN ja 18.1OC/W 40-Lead QFN (K6) Electrical Characteristics (The * denotes the specifications which apply over the full operating ambient temperature range of 0C < TA < +85C, otherwise the specifications are at TA = 25C. VDD = 8.0V unless otherwise noted) Sym Input VINDC IINSD IIN REN Parameter Min Typ Max Units Conditions Input DC supply voltage Shut-down mode supply current Supply current Pull-down resistor * * - 10 100 130 40 500 4.5 160 V A mA k DC input voltage EN 0.8V EN 2.0V; PWMD1 = PWMD2 = PWMD3 = GND VEN = 5.0V VIN = 12-40V; EN = HIGH; PWMD1-3 = VDD; GATE1-3 = 1nF; CLK = 6MHz VDD falling VDD rising Internal Regulator VDD UVLORISE UVLOHYST Internally regulated voltage VDD under voltage lockout threshold VDD under voltage hysteresis * 7.25 6.0 7.75 500 8.25 6.5 V V mV # Denotes specifications guaranteed by design * The specifications which apply over the full operating temperature range at 0OC < TA < +85OC are guaranteed by design and characterization. 2 HV9982 Electrical Characteristics (cont.) Sym Parameter Min Typ Max Units Conditions PWM Dimming (PWMD1, PWMD2 and PWMD3) VPWMD(lo) VPWMD(hi) RPWMD PWMD input low voltage PWMD input high voltage PWMD pull down resistor * * 2.0 100 130 0.8 160 V V k ----VPWMD = 5V Gate (GATE1, GATE2 and GATE3) ISOURCE ISINK TRISE TFALL DMAX VOVP,rising VOVP,HYST Gate short circuit current, sourcing Gate sinking current Gate output rise time Gate output fall time Maximum duty cycle # # # 0.2 0.4 91.7 85 45 A A ns ns % VGATE = 0V VGATE = VDD CGATE = 1.0nF CGATE = 1.0nF --- Over Voltage Protection (OVP1, OVP2 and OVP3) Over voltage rising trip point Over voltage hysteresis * 4.5 5.0 0.5 5.5 V V OVP rising OVP falling Current Sense (CS1, CS2 and CS3) TBLANK TDELAY RDIS Leading edge blanking Delay to output of gate Discharge resistance for slope compensation * * * 100 250 200 650 ns ns --100mV overdrive to the current sense Gate = Low Internal Transconductance Opamp (Gm1, Gm2 and Gm3) GB AV VCM VO Gm VOFFSET IBIAS fOSC1 KSW TOFF TON VCLOCK,HI VCLOCK,LO Gain bandwidth product Open loop DC gain Input common-mode range Output voltage range Transconductance Input offset voltage Input bias current # # # # 65 -0.3 0.7 500 -5.0 1.0 600 0.5 3.0 VDD 700 5.0 1.0 MHz dB V V A/V mV nA 75pF capacitance at COMP pin Output open ----------- Oscillator (CLOCK) Oscillator frequency Oscillator divider ratio CLOCK low time CLOCK high time CLOCK input high CLOCK input low # # # * * 50 50 2.0 500 6.0 0.8 kHz ns ns V V FCLOCK = 6.0MHz ----------- # Denotes specifications guaranteed by design. * The specifications which apply over the full operating temperature range at 0OC < TA < +85OC are guaranteed by design and characterization. 3 HV9982 Electrical Characteristics (cont.) Sym Parameter Min Typ Max Units Conditions Disconnect Driver (FAULT1, FAULT2 and FAULT3) TRISE,FAULT TFALL,FAULT TBLANK,SC GSC Vomin TOFF Fault output rise time Fault output fall time 450 200 ns ns 330pF capacitor at FAULT pin 330pF capacitor at FAULT pin Short Circuit Protection (all three channels) Blanking time Gain for short circuit comparator Minimum current limit threshold Propagation time for short circuit detection * # 400 1.85 0.15 2.0 700 2.15 0.25 250 ns V ns ----REF = GND FDBK = 2 * REF + 0.1V HICCUP timer Current source at SKIP pin used for IHC,SOURCE hiccup mode protection VTH(H) VTH(L) FRAMP,min FRAMP,max VRAMP High threshold at SKIP pin Low threshold at SKIP pin # # - 10 5.0 0.1 - A V V ------- CRAMP for Analog Control of PWM Dimming Minimum frequency Maximum frequency Voltage of ramp 0.1 110 1250 1.9 Hz Hz V CRAMP = 10nF CRAMP = 1.0nF --- # Denotes specifications guaranteed by design. * The specifications which apply over the full operating temperature range at 0OC < TA < +85OC are guaranteed by design and characterization. 4 HV9982 Internal Block Diagram VIN EN VDD BANDGAP REF Linear Regulator CLK A CLK B CLK C UVLO POR CLK 1/12 Shared circuitry Replicated for each channel PWMD A CLK A S R Q FC GATE1 Q + BLANKING RAMP RAMP Generator RAMP RAMP S1 S2 + + PWMD A CS1 CLK A PWMD A PWMD1 FLT1 OVP1 REF + PWMD A FC OVD A RAMP - + SCD A FD A PWMD A REF1 FDBK1 + - 2 BLANKING COMP1 DIS Shared circuitry S1 S2 POR FDA FDB FDC 0.1V S1 S2 S Q Fault + - R 5V + - SKIP Fault DIS FC HV9982 5 HV9982 Functional Description Power Topology The HV9982 is a three-channel, switch-mode converter LED driver designed to control a continuous conduction mode buck, boost or SEPIC converter in a constant frequency mode. The IC includes an internal linear regulator, which operates from input voltages 10V to 40V. The IC can also be powered directly using the VDD pins and bypassing the internal linear regulator. The IC includes features typically required in LED drivers like open LED protection, output short circuit protection, linear and PWM dimming, programmable input current limiting and accurate control of the LED current. A high current gate drive output enables the controller to be used in high power converters. The IC is ideally suited for backlight application using either RGB or multi-channel white LED configurations. The EN pin is a TTL compatible input used to disable the IC. Pulling the EN pin to GND will shut down the IC and reduce the quiescent current drawn by the IC to be less than 500A. If the enable function is not required, the EN pin can be connected to VDD. Clock Input (CLK) The switching frequency of the converters is set by using a TTL compatible square wave input at the CLK pin. The switching frequencies of the three converters will be 1/12TH the frequency of the external clock. Current Sense (CS1-3) The current sense input is used to sense the source current of the switching FET. Each CS input of the HV9982 includes a built in 100ns (minimum) blanking time to prevent spurious turn off due to the initial current spike when the FET turns on. The IC includes an internal resistor divider network, which steps down the voltage at the COMP pins by a factor of 15. This voltage is used as the reference for the current sense comparators. Since the maximum voltage of the COMP pin is (VDD - 1.0V), this voltage determines the maximum reference current for the current sense comparator and thus the maximum inductor current. The current sense resistor RCS should be chosen so that the input inductor current is limited to below the saturation current level of the input inductor. For discontinuous conduction mode of operation, no slope compensation is necessary. In this case, the current sense resistor is chosen as: RCS = VDD - 1.0V 13 * IIN,pk where IIN,pk is the maximum desired peak input current. For continuous conduction mode converters operating in the constant frequency mode, slope compensation becomes necessary to ensure stability of the peak current mode controller, if the operating duty cycle is greater than 0.5. This factor must also be accounted for when determining RCS (see Slope Compensation section). Power Supply to the IC (VIN, VDD, VDD1-3) The HV9982 can be powered directly from its VIN pin that withstands a voltage up to 40V. When a voltage is applied at the VIN pin, the HV9982 tries to maintain a constant 7.75V (typ) at the VDD pin. The regulator also has a built in under-voltage lockout which shuts off the IC if the voltage at the VDD pin falls below the UVLO threshold. By connecting this VDD pin to the VDD1-3 pins of the three channels, the internal regulator can be used to power all three channels in the IC. In case the internal regulator is not utilized, an external power supply (7.0V-9.0V) can be used to power the IC. In this case, the power supply is directly connected to the VDD1-3 pins and the VIN pin is left unconnected. All four VDD pins must by bypassed by a low ESR capacitor (0.1F) to provide a low impedance path for the high frequency current of the output gate driver. These capacitors must be referenced to the individual grounds for proper noise rejection (see Layout Guidelines section for more information). Also, in all cases, the four VDD pins must be connected together externally. The input current drawn from the external power supply (or VIN pin) is a sum of the 4.5mA (max) current drawn by all the internal circuitry and the current drawn by the gate drivers (which in turn depends on the switching frequency and the gate charge of the external FET). IIN = 4.5mA + (Qg1 + Qg2 + Qg3) * fS In the above equation, fS is the switching frequency of the converters and Qg1-3 are the gate charges of the external FETs (which can be obtained from the FET datasheets). Slope Compensation Choosing a slope compensation which is one half of the down slope of the inductor current ensures that the converter will be stable for all duty cycles. Slope compensation in the HV9982 can be programmed by two external components (see Fig. 1). A resistor for VDD sets 6 HV9982 a current (which is almost constant since the VDD voltage is much larger than the voltage at the CS pin). This current flows into the capacitor and produces a ramp voltage across the capacitor. The voltage at the CS pin is then the sum of the voltage across the capacitor and the voltage across the current sense resistor, with the voltage across the capacitor providing the required slope compensation. When the GATE turns off, an internal pull down FET discharges the capacitor. The 300 resistance of the internal FET will prevent the voltage at the CS pin from going all the way to zero. Fig.1 Slope Compensation VDD transconductance amplifiers with tri-state output, which are used to close the feedback loops and provide accurate current control. The compensation networks are connected at the COMP pins (COMP1-3). The output of the op-amps are buffered and connected to the current sense comparators using 12:1 resistor dividers. The outputs of the op-amps are controlled by the signal applied to the PWMD pins (PWMD1-3). When PWMD is high, the output of the opamp is connected to the COMP pin. When PWMD is low, the output is left open. This enables the integrating capacitor to hold the charge when the PWMD signal has turned off the gate drive. When the IC is enabled, the voltage on the integrating capacitor will force the converter into steady state almost instantaneously. CS Rsc + Csc GATE Rcs Linear Dimming Linear Dimming can be accomplished in the HV9982 by varying the voltages at the REF pins. Note that since the HV9982 is a peak current mode controller, it has a minimum on-time for the GATE outputs. This minimum on-time will prevent the converters from completely turning off even when the REF pins are pulled to GND. Thus, linear dimming cannot accomplish true zero LED current. To get zero LED current PWM dimming has to be used. Note that different signals can be connected to the three REF pins if desired and they need not be connected together. Due to the offset voltage of the short circuit comparator as well as the non-linearity of the X2 gain stage, pulling the REF pin very close to GND would cause the internal short circuit comparator to trigger and shut down the IC. To overcome this, the output of the gain stage is limited to 125mV (minimum), allowing the REF pin to be pulled all the way to 0V without triggering the short circuit comparator. The minimum value of the voltage will instead be: VCS,MIN = VDD * 650 RSC The slope compensation capacitor is chosen so that it can be completely discharged by the internal 300 FET at the CS pin during the time the FET is off. Assuming the worst case switch duty cycle of 92%, CSC = 0.08 3 * 650 * fS Assuming a down slope of DS (A/ms) for the inductor current, the current sense resistor and the slope compensation resistor can be computed as: RCS = VDD - 1 * 13 1 DS * 106 * 0.92 + IIN,pk 2 * fS PWM Dimming PWM dimming in the HV9982 can be accomplished in one of two ways - true PWM dimming using TTL compatible square wave sources at the PWMD pins (PWMD1-3) or an analog control of PWM dimming by applying a 0 - 2.0V linear signal to the PWMD pins. The analog control of PWM dimming helps the HV9982 to be backward compatible with CCFL controllers. All three channels can be individually PWM dimmed as desired. The mode of PWM dimming is set using control pins S1 and S2. The truth table for S1 and S2 control is given in Table 1. It is recommended that the pins be connected to either VDD or GND and not left unconnected. RSC = 2 * VDD DS * 106 * CSC * RCS Control of the LED Current The LED currents in the HV9982 are controlled in a closedloop manner. The current references which set the three LED currents are provided at the REF pins (REF1-3). This reference voltage is compared to the voltage at the FDBK13 pins which sense the LED currents in the three channels using current sense resistors. HV9982 includes three 1MHz 7 HV9982 Table 1: S1 and S2 control logic S1 0 0 1 1 S2 0 1 0 1 PWMD output The output will follow PWMD input signal Input DC zero volt corresponds to 100% duty cycle output Input DC two volt corresponds to 100% duty cycle output The HV9982 is a robust controller which can protect the LEDs and the LED driver in case of fault conditions. The HV9982 includes both open LED protection and output short circuit protection. In both cases, the HV9982 shuts down and attempts a restart. The hiccup time can be programmed by a single external capacitor at the SKIP pin. During start-up or when a fault condition is detected, both GATE and FLT outputs are disabled, the COMP pins and SKIP pins are pulled to GND. Once the voltage at the SKIP pin falls below 0.1V and the fault condition(s) have disappeared, the capacitor at the SKIP pin is released and is charged slowly by a 10A current source. Once the capacitor is charged to 5.0V, the COMP pins are released and GATE and FLT pins are allowed to turn on. If the hiccup time is long enough, it will ensure that the compensation networks are all completely discharged and that the converters start at minimum duty cycle. The hiccup timing capacitor can be programmed as: CRAMP = 10A * tHICCUP 4.9V Fault Conditions When S1 is high and the HV9982 is operating in the analog control of PWM dimming mode, the PWM dimming frequency is set by a capacitor connected at the RAMP pin. The RAMP frequency range is 100Hz - 1.0kHz and the capacitor can be selected as: f(Hz) = 1.0S CRAMP (Note: In the following description of the PWM dimming performance the PWMD signals refer to the internal PWM dimming signal and not to the signal applied at the PWMD pins). When the PWM signal is high, the GATE and FLT pins are enabled and the output of the transconductance opamp is connected to the external compensation network. Thus, the internal amplifier controls the output current. When the PWMD signal goes low, the output of the transconductance amplifier is disconnected from the compensation network. Thus, the integrating capacitor maintains the voltage across it. The GATE is disabled, so the converter stops switching and the FLT pin goes low, turning off the disconnect switch. The output capacitor of the converter determines the PWM dimming response of the converter, since it has to get charged and discharged whenever the PWMD signal goes high or low. In the case of a buck converter, since the inductor current is continuous, a very small capacitor is used across the LEDs. This minimizes the effect of the capacitor on the PWM dimming response of the converter. However, in the case of a boost converter, the output current is discontinuous and a very large output capacitor is required to reduce the ripple in the LED current. Thus, this capacitor will have a significant impact on the PWM dimming response. By turning off the disconnect switch when PWMD goes low, the output capacitor is prevented from being discharged and thus the PWM dimming response of the boost converter Improves dramatically. Note that disconnecting the LED load during PWM dimming causes the energy stored in the inductor to be dumped into the output capacitor. The filter capacitor should be chosen large enough so that it can absorb the inductor energy without significant change to the voltage across it. Short Circuit Protection When a short circuit condition is detected (output current becomes higher than twice the steady state current), the GATE and FLT outputs are pulled low. As soon as the disconnect FET is turned off, the output current goes to zero and the short circuit condition disappears. At this time, the hiccup timer is started (Fig. 3). Once the timing is complete, the converter attempts to restart. If the fault condition still persists, the converter shuts down and goes through the cycle again. If the fault condition is cleared (due to a momentary output short) the converter will start regulating the output current normally. This allows the LED driver to recover from accidental shorts without having to reset the IC. During short circuit conditions, there are two conditions that determine the hiccup time. The first is the time required to discharge the compensation capacitors. Assuming a pole-zero R-C network at the COMP pin (series combination of RZ and CZ in parallel with CC), tCOMP,n = 3 * RZn * CZn where n refers to the channel number. In case the compensation networks are only type 1 (single capacitor), then: tCOMP,n = 3 * 300 * CZn 8 HV9982 Thus, the maximum COMP discharge time required can be computed as: tCOMP,max = max (tCOMP1, tCOMP2, tCOMP3) The second is the time required for the inductors to completely discharge following a short circuit. This time can be computed as: tind,n = 4 Ln * Con Over Voltage Protection The HV9982 provides hysteretic over voltage protection allowing the IC to recover in case the LED load is momentarily disconnected. When the load is disconnected in a boost converter, the output voltage rises as the output capacitor starts charging. When the output voltage reaches the OVP rising threshold, the HV9982 detects an over voltage condition and turns off the converter. The converter is turned back on only when the output voltage falls below the falling OVP threshold (which is 10% lower than the rising threshold). This time is mostly dictated by the R-C time constant of the output capacitor CO and the resistor network used to sense over voltage (ROVP1+ ROVP2). In case of a persistent open circuit condition, this cycle keeps repeating maintaining the output voltage within a 10% band. In most designs, the lower threshold voltage of the over voltage protection (VOVP - 10%) at which point the HV9982 attempts to restart will be more than the LED string voltage. Thus, when the LED load is reconnected to the output of the converter, the voltage differential between the actual output voltage and the LED string voltage will cause a spike in the output current. This causes a short circuit to be detected and the HV9982 will trigger short circuit protection. This behavior continues till the output voltage becomes lower than the LED string voltage at which point, no fault will be detected and normal operation of the circuit will commence. where L and CO are the input inductor and output capacitor of each power stage. Thus, the maximum time required to discharge the inductors can be computed as: tind,max = max (tind1, tind2, tind3) The hiccup time is then chosen as: thiccup > max (tCOMP,max, tind,max) False Triggering of the Short Circuit Comparator During PWM Dimming During PWM dimming, the parasitic capacitance of the LED string causes a spike in the output current when the disconnect FET is turned on. If this spike is detected by the short circuit comparator, it will cause the IC to falsely detect an over current condition and shut down. In the HV9982, to prevent these false triggerings, there is a built in 500ns blanking network for the short circuit comparator. This blanking network is activated when the PWMD input goes high. Thus, the short circuit comparator will not see the spike in the LED current during the PWM Dimming turn-on transition. Once the blanking timer is completed, the short circuit comparator will start monitoring the output current. Thus, the total delay time for detecting a short circuit will depend on the condition of the PWMD input. If the output short circuit exists before the PWM dimming signal goes high, the total detection time will be: tdetect1 = tBLANK + tDELAY 950ns(max) If the short circuit occurs when the PWM dimming signal is already high, the time to detect will be: tdetect1 = tDELAY 250ns(max) Layout Considerations For multi-channel peak current mode controller IC to work properly with minimum interference between the channels, it is important to have a good PCB layout which minimizes noise. Following the layout rules stated below will help to ensure proper performance of all three channels. 1. GND connection The IC has four separate ground connections - one for each of the three channels and one analog ground for the common circuitry. It is recommended that four separate ground planes be used in the PCB and all the GND planes be connected together at the return terminal of the input power lines. 2. VDD Connection Each VDD pin should be by passed with a low ESR capacitor to its OWN ground (i.e. VDD1 is bypassed to GND1 and so on). The common VDD pin can be bypassed to the common GND. 9 HV9982 3. REF Connection In case all the references are going to be driven from a single voltage source, it is recommended to have a small R-C low pass filter (1.0k, 1.0nF) at each REF pin with the filter being referenced to the appropriate channel's ground (as in the case of the VDD pins). If the REF pins are driven with three individual voltage sources, then just a small capacitor (1.0nF) at each pin would suffice. 4. GATE and CS connection The connection from GATE output to the gate of the external FET as well as the connection from the CS pin to the external sense resistor made as short as possible to avoid false triggering. 5. OVP protection Typically, the OVP resistor dividers would be located away from the IC. To prevent false triggering of the IC due to noise at the OVP pin, a small bypass capacitor (1.0nF) right at the OVP pin is recommended. Layout Guidelines VDD Connection Input Return Terminal GND1 VDD1 GND2 VDD2 GND3 VDD3 Star Connection of GND HV9982 Reference REF1 REF3 VDD GND REF2 REF Connection GND Tab Connection 10 HV9982 Pin Description Pin # Name Description Power supply pin for channel 1. It can either be connected to the VDD pin or supplied with an external power supply. It must be bypassed with a low ESR capacitor to GND1 (at least 0.1F). All VDD pins (VDD, VDD1-3) must be connected together externally. An external supply (7V - 9V) can be connected to these pins to power the IC if the internal regulator is not used. Used to drive an external disconnect switch. The disconnect switch is used to protect the LEDs in case of fault conditions and also help to provide excellent PWM dimming response by disconnecting and reconnecting the LEDs from the output capacitor during PWM dimming. Used to sense the source current of the external power FET used with channel 1. It includes a built-in 100ns (min) blanking timer. An R-C network at this pin programs the slope compensation. Refer to the Slope Compensation section for additional information. Stable closed loop control for channel 1 can be accomplished by connecting a compensation network between each COMP1 pin and GND1. Output current feedback input for channel 1. It receives a voltage signal from an external sense resistor. The voltage at this pin sets the output current level for channel 1. Recommended voltage range for this pin is 0V - 1.25V. Provides the over voltage protection for the channel 1. When the voltage at this pin exceeds 5.0V, the HV9982 is turned off and the fault timer starts. Upon completion of the fault timer the IC attempts to restart. Input of the internal 40V linear regulator. Output of the linear regulator. It maintains a regulated 7.75V as long as the voltage of the VIN pin is between 10V and 40V. It must be bypassed with a low ESR capacitor to GND (at least 0.1F). Can be used as a power supply for the three channels. When pin is pulled below 0.8V, the IC goes into a standby mode and draws minimal current. Ground connection for the common circuitry in the HV9982. Stable closed loop control for channel 2 can be accomplished by connecting a compensation network between each COMP2 pin and GND2. The voltage at this pin sets the output current level for channel 2. Recommended voltage range for this pin is 0V - 1.25V. Provides the over voltage protection for the channel 2. When the voltage at this pin exceeds 5.0V, the HV9982 is turned off and the fault timer starts. Upon completion of the fault timer the IC attempts to restart. Programs the hiccup timer for fault conditions. A capacitor to GND programs the hiccup time. Provides a ramp signal which is used while dimming the channels with pulse-width modulation with an analog input. A capacitor to GND programs the PWM dimming frequency. 1 VDD1 2 FLT1 3 CS1 4 5 6 COMP1 FDBK1 REF1 7 8 9 10 11 12 13 OVP1 VIN VDD EN GND COMP2 REF2 14 15 16 17 18 19 20 21 OVP2 SKIP RAMP PWMD1 PWM dimming of the three channels is accomplished by using the PWMD pins. If S1 is LOW, then the three pins directly control the PWM dimming of the three channels and a square wave input should be PWMD2 applied at these pins. If S1 is high, then a 0V - 2.0V analog signal should be applied at these pins. The PWM dimming is then done by comparing the analog voltage to the voltage at the RAMP pin. PWMD3 S1 S2 Digital input pins which select the operating mode of the PWMD inputs. Refer to the PWM dimming section for additional information. 11 HV9982 Pin Description (cont.) Pin # 22 23 Name NC CLK Description No connect. Clock input for the HV9982. The input to the CLK pin should be a TTL compatible square wave signal. The three channels will switch at 1/12th the switching frequency of the signal applied at the CLK pin. Provides the over voltage protection for the channel 3. When the voltage at this pin exceeds 5.0V, the HV9982 is turned off and the fault timer starts. Upon completion of the fault timer the IC attempts to restart. The voltage at this pin sets the output current level for channel 3. Recommended voltage range for this pin is 0V - 1.25V. Output current feedback input for channel 3. It receives a voltage signal from an external sense resistor. Stable closed loop control for channel 3 can be accomplished by connecting a compensation network between each COMP3 pin and GND3. Used to sense the source current of the external power FET used with channel 3. It includes a built-in 100ns (min) blanking timer. An R-C network at this pin programs the slope compensation. Refer to the Slope Compensation section for additional information. Used to drive an external disconnect switch. The disconnect switch is used to protect the LEDs in case of fault conditions and also help to provide excellent PWM dimming response by disconnecting and reconnecting the LEDs from the output capacitor during PWM dimming. Power supply pin for channel 3. It can either be connected to the VDD pin or supplied with an external power supply. It must be bypassed with a low ESR capacitor to GND3 (at least 0.1F). All VDD pins (VDD, VDD1-3) must be connected together externally. An external supply (7V - 9V) can be connected to these pins to power the IC if the internal regulator is not used. Output gate drive for an external N-channel power MOSFET. Ground return for channel 3. It is recommended that all the GNDs of the IC be connected together in a STAR connection at the input GND terminal to ensure best performance. Power supply pin for channel 2. It can either be connected to the VDD pin or supplied with an external power supply. It must be bypassed with a low ESR capacitor to GND2 (at least 0.1F). All VDD pins (VDD, VDD1-3) must be connected together externally. An external supply (7V - 9V) can be connected to these pins to power the IC if the internal regulator is not used. Ground return for channel 2. It is recommended that all the GNDs of the IC be connected together in a STAR connection at the input GND terminal to ensure best performance. Output gate drive for an external N-channel power MOSFET. Used to drive an external disconnect switch. The disconnect switch is used to protect the LEDs in case of fault conditions and also help to provide excellent PWM dimming response by disconnecting and reconnecting the LEDs from the output capacitor during PWM dimming. Used to sense the source current of the external power FET used with channel 2. It includes a built-in 100ns (min) blanking timer. An R-C network at this pin programs the slope compensation. Refer to the Slope Compensation section for additional information. Output current feedback input for channel 2. It receives a voltage signal from an external sense resistor. Ground return for channel 1. It is recommended that all the GNDs of the IC be connected together in a STAR connection at the input GND terminal to ensure best performance. Output gate drive for an external N-channel power MOSFET. 24 OVP3 25 26 27 REF3 FDBK3 COMP3 28 CS3 29 FLT3 30 VDD3 31 32 GATE3 GND3 33 VDD2 34 35 36 GND2 GATE2 FLT2 37 CS2 38 39 40 FDBK2 GND1 GATE1 12 HV9982 40-Lead QFN Package Outline (K6) 6x6mm body, 1.00mm height (max), 0.50mm pitch 40 D D2 40 Note 1 (Index Area D/2 x E/2) 1 Note 1 (Index Area D/2 x E/2) E b e 1 E2 View B Top View Bottom View Note 3 A A1 A3 Seating Plane L1 Note 2 L Side View View B Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol MIN Dimension (mm) NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 REF b 0.18 0.25 0.30 D 5.85 6.00 6.15 D2 1.75 3.70 4.25 E 5.85 6.00 6.15 E2 1.75 3.70 4.25 e 0.50 BSC L 0.30 0.40 0.50 L1 0.00 0.15 O 0 14 JEDEC Registration MO-220, Variation VJJD-2, Issue K, June 2006. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-HV9982 NR032608 13 |
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