|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
0 R XC9536XV High-performance CPLD 0 1 DS053 (v2.6) April 15, 2005 Product Specification For a general estimate of ICC, the following equation may be used: PTOTAL = PINT + PIO = ICCINT x VCCINT + PIO Separating internal and I/O power here is convenient because XC9500XV CPLDs also separate the corresponding power pins. PIO is a strong function of the load capacitance driven, so it is handled by I = CVf. ICCINT is another situation that reflects the actual design considered and the internal switching speeds. An estimation expression for ICCINT (taken from simulation) is: ICCINT(mA) = MCHS(0.122 X PTHS + 0.238) + MCLP(0.042 x PTLP + 0.171) + 0.04(MCHS + MCLP) x fMAX x MCTOG where: MCHS = # macrocells used in high speed mode MCLP = #macrocells used in low power mode PTHS = average p-terms used per high speed macrocell PTLP = average p-terms used over low power macrocell fMAX = max clocking frequency in the device MCTOG = % macrocells toggling on each clock (12% is frequently a good estimate This calculation was derived from laboratory measurements of an XC9500XV part filled with 16-bit counters and allowing a single output (the LSB) to be enabled. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. For a more detailed discussion of power consumption in this device, see Xilinx application note XAPP361, "Planning for High Speed XC9500XV Designs." 60 50 Typical ICC (mA) 200 MHz Features * * 36 macrocells with 800 usable gates Available in small footprint packages - 44-pin PLCC (34 user I/O pins) - 44-pin VQFP (34 user I/O pins) - 48-pin CSP (36 user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Superior pin-locking and routability with Fast CONNECTTM II switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold circuitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 3.3V-core XC9536XL device in the 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages * * * * * * * Description The XC9536XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of two 54V18 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview. 40 H ig h fo P er rma n ce 120 MHz er 30 20 Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. Low Pow 10 0 50 100 150 Clock Frequency (MHz) 200 DS053_01_121501 Figure 1: Typical ICC vs. Frequency for XC9536XV (c) 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS053 (v2.6) April 15, 2005 Product Specification www.xilinx.com 1 XC9536XV High-performance CPLD R 3 JTAG Port 1 JTAG Controller In-System Programming Controller 54 I/O I/O I/O Fast CONNECT II Switch Matrix I/O 54 18 18 Function Block 1 Macrocells 1 to 18 Function Block 2 Macrocells 1 to 18 I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 2 DS053_02_041200 Figure 2: XC9536XV Architecture Function block outputs (indicated by the bold line) drive the I/O Blocks directly. Supported I/O Standards Table 1: IOSTANDARD Options IOSTANDARD LVTTL LVCMOS2 X25TO18 VCCIO 3.3V 2.5V 1.8V The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS2 standard is used in 2.5V applications. XC9500XV CPLDs are also 1.8V I/O compatible. The X25TO18 setting is provided for generating 1.8V compatible outputs from a CPLD normally operating in a 2.5V environment. The default I/O Standard for pads without IOSTANDARD attributes is LVTTL for XC9500XV devices. The XC9536XV CPLD features both LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. 2 www.xilinx.com DS053 (v2.6) April 15, 2005 Product Specification R XC9536XV High-performance CPLD Absolute Maximum Ratings Symbol VCC VCCIO VIN VTS TSTG TJ Description Supply voltage relative to GND Supply voltage for output drivers Input voltage relative to GND(1) Voltage applied to 3-state output(1) Storage temperature (ambient) Junction temperature Value -0.5 to 2.7 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 3.6 -65 to +150 +150 Units V V V V oC oC Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. 3. For solder specifications, see Xilinx Packaging. Recommended Operation Conditions Symbol VCCINT VCCIO Parameter Supply voltage for internal logic and input buffers Commercial TA = 0oC to +70oC Industrial TA = -40oC to +85oC Min 2.37 2.37 3.0 2.37 1.71 0 1.7 0 Max 2.62 2.62 3.6 2.62 1.89 0.8 3.6 VCCIO V V V V V V Units V Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Supply voltage for output drivers for 1.8V operation VIL VIH VO Low-level input voltage High-level input voltage Output voltage Quality and Reliability Characteristics Symbol TDR NPE VESD Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Parameter Min 20 1,000 2,000 Max Units Years Cycles Volts DS053 (v2.6) April 15, 2005 Product Specification www.xilinx.com 3 XC9536XV High-performance CPLD R DC Characteristics (Over Recommended Operating Conditions) Symbol VOH Parameter Output high voltage for 3.3V outputs Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs VOL Output low voltage for 3.3V outputs Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs IIL Input leakage current Test Conditions IOH = -4.0 mA IOH = -1.0 mA IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VCC min < VIN < 3.6V CIN ICC I/O capacitance Operating Supply Current (low power mode, active) VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.0 90% VCCIO Max 0.4 0.4 0.4 10 Units V V V V V V A IIH Input high-Z leakage current - 10 A 7 150 10 A pF mA AC Characteristics XC9536XV-5 Symbol TPD TSU TH TCO fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TAO TPAO TWLH TPLH TAPRPW I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) Asynchronous preset/reset pulse width (High or Low) Parameter Min 3.5 0 1.0 2.5 2.2 5.0 5.0 Max 5.0 3.5 222.2 6.0 4.0 4.0 7.0 7.0 10.0 10.7 XC9536XV-7 Min 4.8 0 1.6 3.2 4.0 6.5 6.5 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 12.0 12.6 Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns ns 4 www.xilinx.com DS053 (v2.6) April 15, 2005 Product Specification R XC9536XV High-performance CPLD VTEST R1 Device Output R2 CL Output Type VCCIO 3.3V 2.5V 1.8V VTEST 3.3V 2.5V 1.8V R1 320 250 10K R2 360 660 14K CL 35 pF 35 pF 35 pF DS051_03_0601000 Figure 3: AC Load Circuit Internal Timing Parameters XC9536XV-5 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN TPTCK TPTSR TPTTS TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TF TPTA TPTA2 TSLEW Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay Product term clock delay Product term set/reset delay Product term 3-state delay Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay Internal low power logic delay Fast CONNECT II feedback delay Incremental product term allocator delay Adjacent macrocell p-term allocator delay Slew-rate limited delay 2.0 1.5 2.0 1.5 5.0 0.7 5.7 1.6 0.7 0.3 3.0 2.0 1.2 2.0 4.0 2.1 0 1.7 0.7 5.0 0.2 0.2 5.9 2.6 2.2 2.6 2.2 7.5 1.4 6.4 3.5 0.8 0.3 4.0 2.3 1.5 3.1 5.0 2.5 0 2.4 1.4 7.2 1.3 0.5 6.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max XC9536XV-7 Min Max Units Product Term Control Delays Internal Register and Combinatorial Delays Feedback Delays Time Adders DS053 (v2.6) April 15, 2005 Product Specification www.xilinx.com 5 XC9536XV High-performance CPLD R XC9536XV I/O Pins Function Block 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Macrocell 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 2 3 5(1) 4 6(1) 8 7(1) 9 11 12 13 14 18 19 20 22 24 VQ44 CS48 D6 C7 B7(1) C6 B6(1) A6 A7(1) C5 B5 A4 B4 A3 B2 B1 C2 C3 D2 D3 BScan Order 105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 Function Block Macrocell 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PC44 1 44 42(1) 43 40(1) 39(1) 38 37 36 35 34 33 29 28 27 26 25 - VQ44 CS48 D7 E5 E6(1) E7 F6(1) G7(1) G6 F5 G5 F4 G4 E3 F2 G1 F1 E2 E1 E4 BScan Order 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 40 41 43(1) 42 44(1) 2 1(1) 3 5 6 7 8 12 13 14 16 18 - 39 38 36(1) 37 34(1) 33(1) 32 31 30 29 28 27 23 22 21 20 19 - Notes: 1. Global control pin. XC9536XV Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS VCCINT 2.5V VCCIO 1.8vV/2.5V/3.3V GND No Connects PC44 5 6 7 42 40 39 17 15 30 16 21, 41 32 10, 23, 31 - VQ44 43 44 1 36 34 33 11 9 24 10 15, 35 26 4, 17, 25 CS48 B7 B6 A7 E6 F6 G7 A1 B3 G2 A2 C1, F7 G3 A5, D1, F3 C4, D4 6 www.xilinx.com DS053 (v2.6) April 15, 2005 Product Specification R XC9536XV High-performance CPLD Device Part Marking and Ordering Combination Information R Device Type Package Speed Operating Range XC95xxxXV TQ144 7C This line not related to device part number 1 Sample package with part marking. Notes: 1. Due to the small size of chip scale packages, part marking on these packages does not follow the above sample and the complete part number cannot be included in the marking. Part marking on chip scale packages by line: * * * * Line 1 = X (Xilinx logo), then truncated part number (no XC), i.e., 95xxxXV. Line 2 = Not related to device part number. Line 3 = Not related to device part number. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package code: C1 = CS48. Device Ordering and Part Marking Number XC9536XV-5PC44C XC9536XV-5VQ44C XC9536XV-5CS48C XC9536XV-7PC44C XC9536XV-7VQ44C XC9536XV-7CS48C XC9536XV-7PC44I XC9536XV-7VQ44I XC9536XV-7CS48I Speed (pin-to-pin delay) 5 ns 5 ns 5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns 7.5 ns Pkg. Symbol PC44 VQ44 CS48 PC44 VQ44 CS48 PC44 VQ44 CS48 No. of Pins 44-pin 44-pin 48-ball 44-pin 44-pin 48-ball 44-pin 44-pin 48-ball Package Type Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Plastic Lead Chip Carrier (PLCC) Quad Flat Pack (VQFP) Chip Scale Package (CSP) Operating Range(1) C C C C C C I I I Notes: 1. C = Commercial: TA = 0 to +70C; I = Industrial: TA = -40 to +85C. 2. Some packages available in Pb-free option. See Xilinx Packaging for more information. DS053 (v2.6) April 15, 2005 Product Specification www.xilinx.com 7 XC9536XV High-performance CPLD R Revision History Date 02/01/00 01/29/01 05/15/01 08/27/01 Revision No. 1.1 2.0 2.1 2.2 Description Initial Xilinx release. Advance information specification. Added -3 performance specification and VQ44 package. Deleted VQ64 package. Updated ICC vs. Frequency Figure 1. Updated ICC formula, Recommended Operation Conditions, -3, -4, and -5 AC Characteristics and Internal Timing Parameters Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL - added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -3 TCGK from 0.3 to 0.8; -5 TAOI from 6.5 to 5.9. Updated ICC equation on page 1. Removed -3 device. Changed to Preliminary. Added C4 and D4 as NCs in the CS48 package pinouts. Added second test condition and max measurement to IIH DC Characteristics. Added Part Marking Information to Ordering Information. Removed -4 device. Updated TSOL from 260 to 220oC. Updated Device Part Marking. Updated Package Device Marking Pin 1 orientation. Added TAPRPW specification to AC Characteristics. Added IOSTANDARD information. 05/31/02 2.3 05/27/03 08/21/03 04/15/05 2.4 2.5 2.6 8 www.xilinx.com DS053 (v2.6) April 15, 2005 Product Specification |
Price & Availability of XC9536XV-5CS48C |
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |