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ESDALC6V1C2
Quad low capacitance TRANSILTM array for ESD protection
Applications
Where transient overvoltage protection in ESD sensitive equipment is required, such as:

Computers Printers Communication systems and cellular phones Video equipment Coated lead free Flip-Chip (5 bumps)
This device is particularly adapted to the protection of symmetrical signals
Functional diagram
A1 A3 C1 C3
Features

4 unidirectional TRANSIL functions. Breakdown voltage VBR = 6.1 V min. - Low diode capacitance (12 pF @ 0 V) - Low leakage current (< 500 nA @ 3 V) - very small PCB area (1.33 mm2) Coated lead free package
ABC 1 2 3
B2
Benefits

High ESD protection level High integration Suitable for high density boards
Description
The ESDALC6V1C2 is a monolithic array designed to protect up to 4 lines againast ESD transients. The device is ideal for applications where both reduced line capacitance and board space saving are required.
Order code
Part number ESDALC6V1C2 Marking ED
Complies with the following standards:
IEC 61000-4-2 15 kV (air discharge) 8 kV (contact discharge)
TM: TRANSIL is a trademark of STMicroelectronics
MIL STD 883E - Method 3015-7: class 3 25 kV (Human body model)
August 2006
Rev 1
1/7
www.st.com
Characteristics
ESDALC6V1C2
1
Table 1.
Symbol VPP PPP Tj Tstg TL TOP
Characteristics
Absolute maximum ratings (Tamb = 25 C)
Parameter ESD discharge IEC 61000-4-2 air discharge IEC 61000-4-2 contact discharge Tj initial = Tamb Value 15 8 25 125 - 55 to +150 260 - 40 to + 125 Unit kV W C C C C
Peak pulse power dissipation (8/20 s. (1) Junction temperature Storage temperature
Maximum lead temperature for soldering during 10 s at 5 mm for case Operating temperature range
1. For a surge greater than the maximum values, the diode will fail in short-circuit
Table 2.
Synbol Rth(j-a)
Thermal resistance
Parameter Junction to ambient on printed circuit on recommended pad layout Value 150 Unit C/W
Table 3.
Symbol VRM VBR VCL IRM IPP T VF
Electrical characteristics
Parameter Stand-of voltage Breakdown voltage Clamping voltage Leakage current @ VRM Peak pulse current Voltage temperature coefficient Forward voltage drop
IRM @ VRM Type A max ESDALC6V1C2 0.5 V 3 Vmin 6.1
VBR @ IR Vmax 7.2 mA 1
RD Typ 1
T
C
10-4/C max pFtyp @0 V 5 12
2/7
ESDALC6V1C2
Characteristics
Figure 1.
Peak power dissipation versus initial junction temperature
Figure 2.
Peak pulse power versus exponential pulse duration (Tj initial = 25C)
PPP[T j initial] / PPP [T j initial=25C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 150 T j(C)
1000
PPP(W)
100
tP(s) 10 1 10 100
Figure 3.
Clamping voltage versus peak pulse current (Tj initial = 25C), rectangular waveform tp = 2.5 s).
Figure 4.
Capacitance versus reverse applied voltage (typical values)
100.0
IPP(A)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C(pF)
10.0
1.0
VCL(V) 0.1 0 5 10 15 20 25 30 35 40 45 50
VR(V) 0 1 2 3 4 5 6
Figure 5.
Relative variation of the leakage current versus junction temperature (typical values)
1.E+04
IR [T j] / IR [T j=25C]
1.E+03
1.E+02
1.E+01
T j(C) 1.E+00 25 50 75 100 125
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Ordering information scheme
ESDALC6V1C2
2
Ordering information scheme
ESDA
ESD Array Low capacitance VBR min = 6.1 V Package C = Coated Flip-Chip 2 = Leadfree Pitch = 500m, Bump = 315m
LC
-
6V1
C2
3
Package information
Figure 6. Flip-Chip dimensions
500 m 10 250 m 10 315 m 50 695 m 65
50
0
0.95 mm 50m
4/7
1.32 mm 50m
m
15
ESDALC6V1C2
Ordering information
Figure 7.
Flip-Chip footprint
Figure 8.
Marking
Copper pad Diameter : 250m recommended , 300m max
Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week)
E
Solder stencil opening : 330m
Solder mask opening recommendation : 340m min for 315m copper pad diameter
xxz y ww
Figure 9.
Flip-Chip tape and reel specifications
Dot identifying Pin A1 location 4 0.1 O 1.5 0.1
8 0.3
ST E
xxz yww
ST E
xxz yww
ST E
xxz yww
0.73 0.05
4 0.1
All dimensions in mm
User direction of unreeling
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
4
Ordering information
Part number ESDALC6V1C2 Marking ED Package Flip-Chip Weight 2.1 mg Base qty 5000 Delivery mode Tape and reel
3.5 0.1
1.75 0.1
5/7
Revision history
ESDALC6V1C2
5
Revision history
Date 07-Aug-2006 Revision 1 Initial release. Changes
6/7
ESDALC6V1C2
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