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W83176R-732 W83176G-732
Winbond 2 DIMM DDR ZERO DELAY BUFFER
Date:
March/22/2006
Revision: 1.1
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
W83176R-732/W83176G-732 Data Sheet Revision History
PAGES DATES VERSION WEB VERSION MAIN CONTENTS
1 2 3 4 5 6 7 8 9 10
n.a.
12/18/03 12/15/04 03/22/2006
0.5 1.0 1.1
n.a. 1.0 1.1
First published preliminary version Publish on Website Add lead free part
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: March, 2006 Revision 1.1
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
Table of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 1 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 2 5.1 5.2 6. 6.1 6.2 7. 7.1 7.2 7.3 7.4 8. 8.1 8.2 8.3 9. 10. 11. Clock Outputs ...........................................................................................................................2 Power Pins................................................................................................................................3 Register 5: Output Control (1 = Active, 0 = Inactive) (Default =FFh)......................................3 Register 6: Output Control (1 = active, 0 = inactive) (Default =FFh) ......................................3 Block Write protocol .................................................................................................................4 Block Read protocol .................................................................................................................4 Byte Write protocol ...................................................................................................................4 Byte Read protocol...................................................................................................................4 ABSOLUTE MAXIMUM RATINGS .........................................................................................5 AC CHARACTERISTICS.........................................................................................................5 DC CHARACTERISTICS ........................................................................................................6
REGISTER 0 ~ REGISTER 4 RESERVED ................................................................................ 3
ACCESS INTERFACE ................................................................................................................ 4
SPECIFICATIONS ...................................................................................................................... 5
ORDERING INFORMATION....................................................................................................... 7 HOW TO READ THE TOP MARKING........................................................................................ 7 PACKAGE DRAWING AND DIMENSIONS................................................................................ 8
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W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
1. GENERAL DESCRIPTION
The W83176R-732 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS chipset. W83176R732 can support 2 D.D.R. DRAM DIMMs. The W83176R-732 provides I2C serial bus interface to program the registers to enable or disable each clock outputs. The W83176R-732 accepts a reference clock as its input and runs on 2.5V supply.
2. PRODUCT FEATURES
* Zero-delay clock outputs * Feedback pins for synchronous * Supports up to 2 D.D.R. DIMMs * One pairs of additional outputs for feedback * Low Skew outputs (< 100ps) * Supports 400MHz D.D.R. SDRAM * I2C 2-Wire serial interface and supports Byte or Block Date RW * 28-pin SSOP package
3. PIN CONFIGURATION
*: Internal pull-up resistor 120K to VDD
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Publication Release Date: March, 2006 Revision 1.1
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
4. BLOCK DIAGRAM
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN OUT I/O * NC
Input Output Bi-directional Pin Internal 120k pull-up Not connect
5.1
Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
27,25,16,14,5,1 26,24,17,13,4,2 22 7 8 9,18,21 19
CLKC [5:0] CLKT [5:0] SDATA * SCLK * CLK_INT N/C FB_OUTT
OUT OUT I/O IN IN NC OUT
Complementary Clocks of differential pair outputs True Clocks of differential pair outputs Serial data of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd Serial clock of I2C 2-wire control interface Internal pull-up resistor 120K to Vdd True reference clock input, 3.3V tolerant input Not connected True Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT. True Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error.
20
FB_INT
IN
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W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
5.2 Power Pins
PIN PIN NAME DESCRIPTION
6,11,15,28 3,12,23 10
GND VDD AVDD
Ground Power Supply 2.5V Analog power supply, 2.5V
6. REGISTER 0 ~ REGISTER 4 RESERVED
6.1
BIT
Register 5: Output Control (1 = Active, 0 = Inactive) (Default =FFh)
@POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
1,2 5,4 14,13 16,17 -
CLKC0, CLKT0 (Active / Inactive) CLKC1, CLKT1 (Active / Inactive) Reserved Reserved CLKC2, CLKT2 (Active / Inactive) CLKC3, CLKT3 (Active / Inactive) Reserved Reserved
6.2
BIT
Register 6: Output Control (1 = active, 0 = inactive) (Default =FFh)
@POWERUP PIN DESCRIPTION
7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1
25,24 27,26 -
Reserved Reserved Reserved Reserved CLKC4, CLKT4 (Active / Inactive) Reserved CLKC5, CLKT5 (Active / Inactive) Reserved
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Publication Release Date: March, 2006 Revision 1.1
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
7. ACCESS INTERFACE
The W83176R-732 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83176R-732 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C write address is defined at 0xD4. The I2C read address is defined at 0xD5.
7.1
Block Write protocol
7.2
Block Read protocol
## In block mode, the command code must filled `00h'
7.3
Byte Write protocol
7.4
Byte Read protocol
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W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
8. SPECIFICATIONS
8.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
SYMBOL PARAMETER RATING
VDD, AVDD TSTG TB TA
Voltage on any pin with respect to GND Storage Temperature Ambient Temperature Operating Temperature
- 0.5 V to + 3.6 V - 65C to + 150C - 55C to + 125C 0C to + 70C
8.2
AC CHARACTERISTICS
UNIT S
VDD = AVDD = 2.5V 5 %, TA = 0C to +70C, Test load = 10 pF
PARAMETER SYMBOL MIN TYP MAX TEST CONDITIONS
Operating clock frequency Input Clock Duty Cycle Dynamic Supply Current Cycle to Cycle Jitter Output to Output Skew Output clock Rise time Output clock Fall time Output clock Duty Cycle Output differential-pair crossing voltag
FIN Dtin Idd C-Cjitter Tskew Tor Tof Dtot Voc
100 40
200 60 300 200 100
MHz % mA ps ps ps ps % V Fin=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz Fout=100 to 200Mhz
650 650 45 (Vdd/2) -0.2 Vdd/2
950 950 55 (Vdd/2) + 0.2
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Publication Release Date: March, 2006 Revision 1.1
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
8.3 DC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
Vdd = AVDD= 2.5V 5 %, TA = 0C to +70C SDATA, SCLK Input Low Voltage SDATA, SCLK Input High Voltage CLKIN, FBIN Input Voltage Low
PARAMETER
SVIL SVIH VIL 2.2
1.0
Vdc Vdc
0.4
Vdc
Fin=100 to 200Mhz
Vdd = AVDD= 2.5V 5 %, TA = 0C to +70C
SYMBOL MIN TYP MAX UNITS TEST CONDITIONS
CLKIN, FBIN Input Voltage High Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
VIH CIN COUT LIN
2.1 5 6 7
Vdc pF pF nH
Fin=100 to 200Mhz
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W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
9. ORDERING INFORMATION
Part Number W83176R-732 W83176G-732 Package Type 28 PIN SSOP 28 PIN SSOP (Lead free package) Production Flow Commercial, 0C to +70C Commercial, 0C to +70C
10. HOW TO READ THE TOP MARKING
W83176R-732 28051234 442GB
W83176G-732 28051234 442GB
1st line: Winbond logo and the type number: Normal package: W83176R-732, Lead free package:W83176G-732 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G B 442: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR B: IC revision
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: March, 2006 Revision 1.1
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY BUFFER FOR SIS CHIPSET
11. PACKAGE DRAWING AND DIMENSIONS
28pin 209mil
D
2
15 DIMENSION IN MM DIMENSION IN INCH MIN. NOM MAX. MIN. NOM MAX.
SYMBOL
DTEAIL A
HE E
1
14
A A1 A2 b c D E HE e L L1 Y
2.00 0.05 1.65 1.75 0.22 0.09 9.90 10.20 5.00 5.30 7.40 7.80 0.65 0.55 0.75 1.25 0 0.002 1.85 0.065 0.38 0.009 0.25 0.004 10.50 0.389 5.60 0.197 8.20 0.291 0.95 0.10 8
0.079 0.069 0.073 0.015 0.010 0.401 0.413 0.209 0.220 0.307 0.323
0.0256
0.021 0.030 0.037 0.050 0.004 0 8
A2 A
SEATING PLANE
Y
e
b
DETAIL A A1
SEATING PLANE
L L1
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
-8-
W83176R-732/W83176G-732
2 DIMM DDR ZERO DELAY buffer for Sis chipset
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: March, 2006 Revision 1.1

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