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| Taiwan Micropaq Corporation (c)O { (R)N SPECIFICATION FOR APPROVAL TM50S116T-7G *s|E*s|Eu*~IaAEo 4 No.4 Wenhua Rd. HsinChu Industrial Park HuKou , Taiwan, R.O.C. TELG 886-3-597-9402 FAXG 886-3-597-0775 http://www.tmc.com.tw TMC SDRAM Description TM50S116T-7G The TM50S116T is organized as 2-bank x 524288-word x 16-bit(1Mx16), fabricated with high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. Features Package 400-mil 50-pin TSOP(II) JEDEC PC133/PC100 compatible Single 3.3V Power Supply LVTTL Signal Compatible Programmable - CAS Latency (3 or 2 clocks) - Burst Length (1,2,4,8 & full page) - Burst type (Sequential & Interleave) Auto and Self Refresh 64ms refresh period (4K cycles) 11-Row x 8-Columnorganization 2-Bank operation controlled by BA0 Pin33 and 37 are "No Connected" Fully synchronous operation referenced to clock rising edge Frequency vs. AC Parameter Symbol tCK fCK tAC trcd Parameter Min. clock cycle time @CL=3 Max. operating frequency @CL=3 Max. access time from clock @CL=3 Min. row to column delay - 6G 6 166 5.0 18 - 7G 7 143 5.4 18 - 75G 7.5 133 5.4 20 Unit ns Mhz ns ns For reference only. 2 TMC Rev:1.0 TMC Pin Description Pin Name CLK CKE /CS /RAS /CAS /WE DQ0~DQ15 Function Master Clock Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Data I/O TM50S116T-7G SDRAM Pin Name DQML/DQMU A0-10 BA0 Vdd VddQ Vss/VssQ NC Function Output Disable(Write Mask) Address Input Bank Address Power Supply Power Supply for Output Ground No Connection For reference only. 3 TMC Rev:1.0 TMC Pin Function TM50S116T-7G SDRAM Pin Function CLK Active on the positive going edge to sample all inputs. /CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK,CKE and DQML/DQMU. CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0~A10 Address input Row/column addresses are multiplexed on the same pins. Row address:A0~A10, Column address:A0~A7 BA0 Bank address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables rows access & pre-charge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row pre-charge. Latches data in starting from /CAS,/WE active. DQMU/DQM Data I/O mask Makes data output Hi-Z, tSHZ after the clock and L masks the output. Blocks data input when (Byte controll) DQML/DQMU active. DQ0~15 Data input/output Data inputs/outputs are multiplexed on the same pins. Vdd/Vss Power supply/ground Power and ground for the input buffers and the core logic. VddQ/VssQ Data output power / Isolated power supply and ground for the output ground buffers to provide improved noise immunity. NC/RFU No connection / This pin is recommended to be left no connection reserved for future use on the device. Pin Name System clock For reference only. 4 TMC Rev:1.0 TMC Absolute maximum ratings Parameter Voltage on any pin relative to Vss Voltage supply relative to Vss(VssQ) Operating temperature Power dissipation Output Shorted current TM50S116T-7G SDRAM Symbol VIN, VOUT Vdd,VddQ Topr PD IOS Ratings -0.5 to 4.6 -0.5 to 4.6 0 to +70 1 50 Unit V V J W mA to 70J ) Unit V V V V V g A DC OPERATING CONDITIONS Recommended operating conditions(Referenced to Vss=0V,TA=0J Parameter Power Supply Voltage Input Logic High Voltage Input Logic Low Voltage Output Logic High Voltage Output Logic Low Voltage Input/Output Leakage Current Symbol Vdd, VddQ VIH VIL VOH VOL IIL, IOL Min. 3.0 2.0 -0.3 2.4 -5 to 70J Typ. 3.3 Max. 3.6 Vdd +0.3 0.8 0.4 5 DC Characteristics (Recommended operating condition TA = 0J Parameter Operating Current (One bank active) Pre-charge Standby Current in Power Down Mode Pre-charge Standby Current in Non-Power Down Mode Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS , unless otherwise noted.) Limits -6G -7G -75G 95 85 85 2 2 20 20 7 5 mA mA mA mA mA mA mA Unit mA mA Test Conditions Burst length=1, CL=3, tRC = tRC(min), tCK = tCK(min) CKE=VIL(max), tCK = 15ns CKE & CLK=VIL(max) CKE>=VIH(min),/CS> = VIH (min) , tCK = 15ns CKE>=VIH(min),/CS> = VIH (min), CLK<= VIL(max) , CKE<=VIL(max), tCK =10ns CKE & CLK<=VIL(max) Active Standby Current I P CC3 in Power Down Mode ICC3PS Active Standby Current ICC3N in Non-Power Down Mode ICC3NS Operating Current (Burst ICC4 mode) Auto Refresh Current ICC5 Self Refresh Current ICC6 /CS=CKE=VIH(min), 35 tCK =15ns /CS=CKE=VIH(min), 35 CLK= VIL(max ) BL=4,CL=3,All Banks Active 130 100 100 CBR Command cycling CKE<= 0.2V 150 130 2 130 For reference only. 5 TMC Rev:1.0 TMC TM50S116T-7G SDRAM AC Characteristics Recommended operating conditions(Vdd=VddQ=3.3V,Vss=0V,TA= 0 to 70J Symbol ) Unit Parameter -6G Min 6.0 Max 166 5.0 2.5 2.5 1.5 0.8 1.0 18 60 42 15 12 64 2.5 2.5 1.5 0.8 1.0 18 63 42 18 14 64 -7G Min 7.0 Max 143 5.4 -75G Min 7.5 Max 133 5.4 2.5 2.5 1.5 0.8 1.0 20 67 45 20 15 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tCK fCK tAC tCH tCL tIS tIH tT tRCD tRC tRAS tRP tRRD tREF Clock Cycle Time,CL=3 Clock Frequency,CL=3 Clock Access Time,CL=3 Clock High Pulse Width Clock Low Pulse Width Input Setup time(all inputs) Input Hold time(all inputs) Transition time of clock /RAS to /CAS delay Row Cycle time Row active time Pre-charge time Row active to active delay Refresh time 10 10 10 ns Mhz ns ns ns ns ns ns ns ns ns ns ns ms For reference only. 6 TMC Rev:1.0 TMC TM50S116T SDRAM For reference only. 7 TMC Rev:1.0 |
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