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| Z9974 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Features * * * * * * * * * * Output Frequency up to 125 MHz Supports PowerPC(R), and Pentium(R) processors 15 Clock outputs: frequency configurable Two Reference clock inputs for dynamic toggling Output Three-State control Spread spectrum compatible 3.3V power supply Pin compatible with MPC974 Industrial temperature range: -40C to +85C 52-pin TQFP package The Z9974 integrates PLL technology for zero delay propagation from input to output. The PLL feedback is externally available for propagation delay tuning and divide ratio alternatives as per Table 1. The Z9974 has three banks of outputs with independent divider stages. These dividers allow the banks to have different frequencies as per Table 2. TCLK0 and TCLK1 are selectable input reference clocks and may be toggled dynamically during operation to provide modulation and phase shifting designs. This device includes a Master Reset signal, which disables the outputs (Hi-Z) mode, and reset all internal digital circuitry (excluding the PLL). An Output Enable, OE, input pin is available for disabling the Qa(0:4), Qb(0:4), and Qc(0:3) outputs and forcing them to LOW state. All outputs are held LOW with input clock turned off. Description The Z9974 is a low-cost 3.3V zero delay clock driver for high-speed signal buffering and redistribution. The designer can select various Input/Output Frequency by setting fsela, fselb, fselc, fselFB(0:1), and VCO_Sel. Pin Configuration VCO_Sel VSSc QC0 52 51 50 49 48 47 46 45 44 43 42 41 40 VSSA MR# OE fselb fselc PLL_EN fsela TClk_Sel TClk0 TClk1 NC VDDI VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 VSSb QB1 VDDb Qb2 VSSb Qb3 VDDb Qb4 FB_IN VSSFB QFB VDDFB NC Z9974 14 15 16 17 18 19 20 21 22 23 24 25 26 VDDa Qa3 VSSa selFB1 Qa2 VDDa Qa1 VSSa Qa0 VDDa selFB0 VSSI Qa4 Cypress Semiconductor Corporation Document #: 38-07090 Rev. *C * 3901 North First Street VDDc QC1 VSSc QC2 VDDc Qc3 VSSc NC VDDb Qb0 * San Jose * CA 95134 * 408-943-2600 Revised December 21, 2002 Z9974 Block Diagram fsela 250K 0 1 A AND Gate B 5 250K Y 5 5 Qa(0:4) TCLK_sel VDD 250K 0 1 0 1 250K Feedback PLL Ref-in VCO-out 0 1 C /2 /4 Reset# Divide by 2&4 0 1 C /2 /4 B 5 A AND Gate Y 5 5 TCLK0 TCLK1 Qb(0:4) VDD 250K /6 Reset# Divide by 2, 4 & 6 0 1 A B 4 AND Gate Y 4 4 Qc(0:3) FB_In VDD 250K PLL_EN VCO_sel 250K 0 1 C /2 Reset# 250K Div. by 2 0 1 1 QFB fselb fselc 250K fselFB1 250K fselFB0 250K VDD 250K OE VDD 250K MR# Table 1. Feedback Divider Selection Inputs VCO_Sel 0 0 0 0 1 1 1 1 Table 2. Output Divider Selection VCO_Sel 0 0 1 1 fsela 0 1 0 1 Qa VCO/4 VCO/8 VCO/8 VCO/16 fselb 0 1 0 1 Qb VCO/4 VCO/8 VCO/8 VCO/16 fselC 0 1 0 1 Qc VCO/8 VCO/12 VCO/16 VCO/24 Page 2 of 7 fselFB0 0 0 1 1 0 0 1 1 fselFB1 0 1 0 1 0 1 0 1 Output QFB VCO/8 VCO/12 VCO/16 VCO/24 VCO/16 VCO/24 VCO/32 VCO/48 Document #: 38-07090 Rev. *C Z9974 Pin Description[1] Pin 2 Name MR# PWR I I/O Description Master Reset pin. Active LOW. It has a 250-K internal pull-up. When forced LOW, all outputs are three-stated (high impedance) and internal dividers are reset. Output Enable pin. Active LOW. It has a 250-K internal pull-up. When forced LOW, Qa(0:4), Qb(0:4), and Qc(0:3) outputs are stopped in a LOW state. QFB is not affected by this control signal. Input select pins for setting the output dividers of Qa(0:4), Qb(0:4), and Qc(0:3) respectively. Each pin has an internal 250-K pull-down. See Table 2 for output divide ratios. Input pin for bypassing the PLL. It has an internal 250-K pull-up. When forced LOW, the input reference clock (applied at TCLK0, or TCLK1) bypasses the PLL and drives the dividers, typically for device testing. Input pin for selecting TCLK0 or TCLK1 as input reference. When TCLK_sel = 0, TCLK0 is selected, when TCLK_sel = 1, TCLK1 is selected. This pin has a 250-k internal pull-down. Input pins for applying a reference clock to the PLL. The active input is selected by TCLK_sel, pin# 8. TCLK0 has a 250-K internal pull-down. TCLK1 has a 250-K internal pull-up. Input select pins for setting the Feedback divide ratio at QFB output, pin #29. See Table 1. Each of these pins has a 250-K internal pull-down. High-drive, low-voltage CMOS, output clock buffers, Bank Qa. Their divide ratio is programmed by fsela, pin #7. Low-voltage CMOS output feedback clock to the internal PLL. The divide ratio for this output is set by fselFB(0:1). A delay capacitor or trace may be applied to this pin in order to control the Input Reference/Output Banks phase relationship. Feedback input pin. Typically connects to the QFB output for accessing the feedback to the PLL. It has a 250-k internal pull-up. High-drive, low-voltage CMOS, output clock buffers, Bank Qb. Their divide ratio is programmed by fselb, pin #4. High-drive, low-voltage CMOS, output clock buffers, Bank Qc. Their divide ratio is programmed by fselc, pin #5. Input select pin for setting the divider of the VCO output. It has a 250-k internal pull-down. If VCO_sel = 0, then the PLL VCO output is divided by 2. If VCO_sel = 1, then the PLL VCO output is divided by 4. See Table 1 and Table 2. These pins are not connected internally. They may be attached to a ground plane. Power for input logic circuitry. Ground for input logic circuitry. Power and Ground supply pins for internal analog circuitry. 3.3V supply for Qa(0:4) output bank, and fselFB1 input. Common ground for Qa(0:4) output bank, and fselFB1 input. Power supply pin for QFB output and FB_In input pins and digital circuitry. Ground supply pin for QFB output and FB_In input pins and digital circuitry. 3.3V supply for Qb(0:4) output bank. 3 OE I 7, 5, 4 fsel(a,b, c) I 6 PLL_EN I 8 TCLK_sel I 9,10 TCLK(0:1) I 14,20 fselFB(0:1) VDDa VDDFB I O O 16,18,21,23, Qa(0:4) 25 29 QFB 31 FB_In VDDb VDDc I O O I 32,34,36,48, Qb(0:4) 40 44,46,48,50 52 Qc(0:3) VCO_Sel 11,27,42 12 15 13 17,22,26 19,24 28 30 33,37,41 n/c VDDI VSSI VDDA VDDa VSSa VDDFB VSSFB VDDb P P P P P P P P Note: 1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins, their high-frequency filtering characteristic will be cancelled by the lead inductances of the traces. Document #: 38-07090 Rev. *C Page 3 of 7 Z9974 Pin Description[1] (continued) Pin 35,39 45,49 43,47,51 1 Name VSSb VDDc VSSc VSSA PWR I/O P P P P Description Common ground for Qb(0:4) output bank. 3.3V supply for Qc(0:3) output bank and VCO_sel pin. Common ground for Qc(0:3) output bank and VCO_sel pin. Analog Ground Glitch-Free Output Frequency Transitions Customarily when zero delay buffers have their internal counters change "on the fly" their output clock periods will: 1. Contain short or "runt" clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. 2. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed "on the fly" while it is operating: Fsela, Fselb, Fselc, and VCO_Sel Document #: 38-07090 Rev. *C Page 4 of 7 Z9974 Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ -65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum Power Supply: ................................................5.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = 3.3V 5%, TA = -40C to +85C Parameter VIL VIH IIL IIH VOL VOH IDDQ Cin Description Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage Quiescent Supply Current Input Capacitance per input IOL = 20 mA IOH = -20 mA 2.4 20 8 Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD -100 100 0.5 Unit V V A A V V mA pF AC Parameters[3] VDD = 3.3V 5%, TA = -40C to +85C Parameter TLOCK FVCO Tinr,Tinf FREF FREFpw Tpw Tr,Tf Zo Ts Tpd Tj TPLZ, TPHZ TPZL Fout Description Maximum PLL Lock Time VCO Lock Range TCLK(0:1) Input Rise/Fall Time Input Reference Frequency Input Reference Duty Cycle Output Duty Cycle Rise Time/Fall Time Output Impedance Output to Output Skew Propagation Delay, TCLK(0:1) to FBIN Cycle to Cycle Jitter Output Disable Time Output Enable Time Maximum Output Frequency All outputs equally loaded Measured at 50 MHz, VDD/2 Measured at 50 MHz, VDD/2 After MR# goes LOW After MR# goes HIGH Q (/2) Q (/4) Q (/6) 2 2 -250 100 10 10 125 62 41 Measured at VDD/2 Measured between 0.8V and 2.0V Note 4 Note 4 Tcycle/2 - 800 0.15 7 Tcycle/2 500 Conditions Stable power supply & valid clocks presented on TCLK(0:1) pins FselFB(0:1)=/4 to /12 200 Min. Typ. Max. 10 500 3 Note 4 Note 4 Tcycle/2 + 800 1.5 10 250 100 Unit ms MHz ns MHz % ps ns ps ps ps ns ns MHz Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. Z9974 outputs can drive series or parallel terminator 50 (or 50 to VDD/2). 4. Input Reference Frequency is limited by the divider selection and the VCO lock range. Document #: 38-07090 Rev. *C Page 5 of 7 Z9974 Test Circuit Diagram VDD* 1K Output under Test 43 7 50 Impedance PROBE 1K Note: All buffer outputs are tied to a common 3.3-Volt VDD (VDD*) for testing purposes Ordering Information Part Number IMIZ9974CA IMIZ9974CAT Package Type 52-pin TQFP 52-pin TQFP-Tape and Reel Production Flow Industrial, -40C to +85C Industrial, -40C to +85C Package Drawing and Dimensions 52-Lead Thin Plastic Quad Flat Pack (10x10x1.4 mm) A52 51-85131-** PowerPC is a registered trademark of International Business Machines. Pentium is a registered trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07090 Rev. *C Page 6 of 7 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.. Z9974 Document Title: Z9974 3.3V, 125-MHz, Multi-Output Zero Delay Buffer Document #: 38-07090 REV. ** *A *B ECN NO. 107126 108068 116195 Issue Date 06/05/01 07/03/01 08/14/02 Orig. of Change IKA NDP ITH Description of Change Converted to IMI Cypress Spec Changed Commercial to Industrial Converted from Word to Framemaker Corrected TCLK0 & TCLK1 on schematic to match the Pull-up/down in the pin description Corrected PLL_EN in the pin description. Corrected the package drawing and dimension Add power up requirements to maximum ratings information. *C 122775 12/21/02 RBI Document #: 38-07090 Rev. *C Page 7 of 7 |
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