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Part Number 440EPx Revision 1.26 - October 15, 2007 440EPx PowerPC 440EPx Embedded Processor Features * PowerPC(R) 440 processor operating up to 667 MHz with 32 KB I-cache and D-cache with parity checking. * 16 KB of on-chip SRAM. * Selectable processor:bus clock ratios of N:1, N:2. * Floating Point Unit with single- and doubleprecision and single-cycle throughput. * Dual bridged Processor Local Buses (PLBs) with 64- and 128-bit widths. * Double Data Rate 2/1 (DDR2/1) Synchronous DRAM (SDRAM) interface operating up to 166 MHz (333 MHz data transfer rate) with optional ECC. * DMA support for external peripherals, internal UART and memory. * Programmable Interrupt Controller supports interrupts from a variety of sources. * Programmable General Purpose Timers (GPT). * PCI V2.2 interface (3.3 V only). Thirty-two bits at up to 66 MHz. * Two Ethernet 10/100/1000 Mbps half- or full- Preliminary Data Sheet duplex interfaces. Operational modes supported are with packet reject, Jumbo frames, and interrupt coalescing. * Up to four serial ports (16750 compatible UART). * One USB 2.0 Device or Host interface with internal PHY and one USB 2.0 direct Device UTMI interface. * External peripheral bus (32-bit data) for up to six devices with external mastering. * Two IIC interfaces (one with boot parameter read capability). * NAND Flash interface. * SPI interface. * General Purpose I/O (GPIO) interface. * JTAG interface for board level testing. * Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface. * Optional security feature (PPC440EPx-S). * Available in RoHS compliant, lead-free package. Description Designed specifically to address high-end embedded applications, the PowerPC 440EPx (PPC440EPx) provides a high-performance, low-power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC processor, on-chip SRAM, a floating point unit, DDR2/1 SDRAM controller, PCI bus interface, control for external ROM and peripherals, DMA with scatter/gather support, Ethernet ports, serial ports, IIC interfaces, SPI interface, USB ports, NAND Flash interface, an optional security feature (PPC440EPx-S), and general purpose I/O. Technology: CMOS Cu-11, 0.13 m. Package: 35 mm, 680-ball thermally enhanced plastic ball grid array (TE-EPBGA). RoHS compliant package available. Typical power: Less than 3 W at 533 MHz. Supply voltages required: 3.3 V, 2.5 V, 1.8 V (DDR2) or 2.5 V (DDR1), 1.5 V. AMCC Proprietary 1 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Contents Ordering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Floating Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SRAM Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Security Function (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 KASUMI Algorithm (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DDR2/1 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Ethernet Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DMA-to-PLB3 (64-bit) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DMA-to-PLB4 (128-bit) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Serial Ports (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IIC Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Serial Peripheral Controller (SPI/SCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Universal Serial Bus 2.0 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 NAND Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DDR2/1 SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 2 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. PPC440EPx Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. 35 mm, 680-Ball TE-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 4. Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 5. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 6. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 7. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 8. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 9. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 10. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 11. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Figure 12. DDR SDRAM DQS Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Tables Table 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. DCR Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3 Recommended Reflow Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4. JEDEC Moisture Sensitivity Level and Ball Composition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 7. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 8. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 10. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 11. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 12. Overshoot and Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 13. Typical DC Power Supply Requirements Using DDR2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 14. Typical DC Power Supply Requirements Using DDR1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 15. VDD Supply Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 16. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 17. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 18. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 19. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 20. I/O Specifications--All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 21. I/O Specifications--400 MHz to 667 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 22. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 23. DDR SDRAM Write Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 24. I/O Timing--DDR SDRAM TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 25. I/O Timing--DDR SDRAM TSK, TSA, and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 26. I/O Timing--DDR SDRAM TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 AMCC Proprietary 3 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 27. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Ordering and PVR Information For information on the availability of the following parts, contact your local AMCC sales office. For additional information on the part number structure see Figure 1. Product Name PPC440EPx PPC440EPx Order Part Number (see Notes) PPC440EPx-SpAfffTs PPC440EPX-NPAFFFTS Package 35 mm, 680 TE-EPBGA 35 mm, 680 TE-EPBGA Revision Level A A PVR Value 0x216218D0 0x216218D4 JTAG ID 0x0440F1E1 0x0440F1E1 Notes: Characters following the dash (-): 1. 2. 3. 4. 5. 6. S = Security feature present, N = Security feature not present p = Package type: U = lead-free (RoHS compliant), T = contains lead. A = Chip revision level A fff = Processor frequency: 400 = 400 MHz, 533 = 533 MHz, 667 = 667 MHz T = Case temperature range of -40C to +100C. s = Shipping package type: Z = tape-and-reel. Blank = tray Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only. The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. Refer to the PPC440EPx User's Manual for details on accessing these registers. Figure 1. Order Part Number Key PPC440EPx-SUA667TZ Shipping Package AMCC Part Number Security Feature Package Case Temperature Range Processor Frequency Revision Level Note: The example P/N above contains the security feature, is lead-free, is capable of running at 667MHz, and is shipped in tape-and-reel packaging. AMCC Proprietary 5 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Block Diagram Figure 2. PPC440EPx Functional Block Diagram 10 External Interrupts Clock Control, Reset Timers MMU UIC PPC440 Processor FPU JTAG 32KB D-Cache Security (optional) Trace 32KB I-Cache SRAM 16KB PLB (PLB4--128 bits) PLB-PLB Bridges PLB (PLB3--64 bits) DCR Bus External Peripheral Controller NAND Flash Controller PCI Bridge Power Mgmt DCRs 83MHz max - 30-bit addr - 32/16-bit data 66MHz max - 32 bits - 6 devices OPB OPB OPB DMA Controller Bridge Bridge Bridge DDR2/1 SDRAM Controller 333MHz max data rate - 14-bit addr - 64/32-bit data OPB Bridge DMA Controller GPT OPB 1 OPB 2 On-chip Peripheral Bus (OPB 0) Device Host MAL USB 2.0 Ethernet 10/100/1000 x2 ZMII RGMII GPIO SPI IIC x2 BSC UART x4 2.0 PHY D+/D- The PPC440EPx is a system on a chip (SOC) using IBM CoreConnect BusTM Architecture. Address Maps The PPC440EPx incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440EPx processor through the use of mtdcr and mfdcr instructions. 6 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 1. System Memory Address Map (Sheet 1 of 2) Function Total System Memory Address Space DDR SDRAM Local Memory Reserved OPB1 Arbiter Reserved USB 2.0 Device Device Controller Reserved OPB2 Arbiter Reserved USB 2.0 Host Host EHIC Host OHIC Reserved SRAM On-Chip Memory Reserved Security Function Security (PPC440EPx-S) KASUMI Algorithm Reserved PCI 1 EBC 1 Reserved I/O Reserved I/O Reserved Configuration Registers PCI 1 Reserved Interrupt Ack/Special Cycle Reserved Local Configuration Registers Reserved 1 EEC0 0008 1 EED0 0000 1 EED0 0004 1 EF40 0000 1 EF40 0040 1 EECF FFFF 1 EED0 0003 1 EF3F FFFF 1 EF40 003F 1 EF4F FFFF 64 B 4B 1 E000 0000 1 E800 0000 1 E801 0000 1 E880 0000 1 EC00 0000 1 EEC0 0000 1 E7FF FFFF 1 E800 FFFF 1E87F FFFF 1 EBFF FFFF 1 EEBF FFFF 1 EEC0 0007 8B 56 MB 64 KB Memory Controller 0 E001 4000 0 E010 0000 0 E018 0000 0 E018 0800 1 8000 0000 1 C000 0000 0 E00F FFFF 0 E017 FFFF 0 E018 07FF 1 7FFF FFFF 1 BFFF FFFF 1 DFFF FFFF 1GB 512 MB 512 KB 2 KB 0 E000 0100 0 5000 0180 0 E000 0200 0 E000 0240 0 E000 0300 0 E000 0400 0 E000 0500 0 E001 0000 0 E000 017F 0 5000 01FF 0 E000 023F 0 E000 02FF 0 E000 03FF 0 E000 04FF 0 E000 FFFF 0 E001 3FFF 16 KB 256 B 256 B 64B 128 B 0 8000 0000 0 E000 0000 0 E000 0040 0 DFFF FFFF 0 E000 003F 0 E000 00FF 64B Sub Function Start Address 0 0000 0000 0 0000 0000 End Address 1 FFFF FFFF 0 7FFF FFFF Size 8GB 2GB AMCC Proprietary 7 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 1. System Memory Address Map (Sheet 2 of 2) Function Reserved General Purpose Timer Reserved UART0 Reserved UART1 Reserved UART2 Reserved UART3 Reserved IIC0 Reserved IIC1 Reserved Internal Peripherals SPI Reserved OPB0 Arbiter Reserved GPIO0 Controller Reserved GPIO1 Controller Reserved Ethernet PHY ZMII Reserved Ethernet 0 Controller Reserved Ethernet 1 Controller Reserved Ethernet PHY RGMII Reserved EBC 1 Boot space Notes: 1. EBC and PCI are relocatable, but this map reflects the suggested configuration. EBC Bank 0 or PCI Sub Function Start Address 1 EF50 0000 1 EF60 0000 1 EF60 0200 1 EF60 0300 1 EF60 0308 1 EF60 0400 1 EF60 0408 1 EF60 0500 1 EF60 0508 1 EF60 0600 1 EF60 0608 1 EF60 0700 1 EF60 0720 1 EF60 0800 1 EF60 0820 1 EF60 0900 1 EF60 0907 1 EF60 0A00 1 EF60 0A40 1 EF60 0B00 1 EF60 0B80 1 EF60 0C00 1 EF60 0C80 1 EF60 0D00 1 EF60 0D10 1 EF60 0E00 1 EF60 0E78 1 EF60 0F00 1 EF60 0F78 1 EF60 1000 1 EF60 1080 1 F000 0000 1 FFE0 0000 End Address 1 EF5F FFFF 1 EF60 01FF 1 EF60 02FF 1 EF60 0307 1 EF60 03FF 1 EF60 0407 1 EF60 04FF 1 EF60 0507 1 EF60 05FF 1 EF60 0607 1 EF60 06FF 1 EF60 071F 1 EF60 07FF 1 EF60 081F 1 EF60 08FF 1 EF60 0906 1 EF60 09FF 1 EF60 0A3F 1 EF60 0AFF 1 EF60 0B7F 1 EF60 0BFF 1 EF60 0C7F 1 EF60 0CFF 1 EF60 0D0F 1 EF60 0DFF 1 EF60 0E77 1 EF60 0EFF 1 EF60 0F77 1 EF60 0FFF 1 EF60 1103 1 EFFF FFFF 1 FFDF FFFF 1 FFFF FFFF 254MB 2MB 264B 120B 120B 16B 128B 128B 64B 6B 32B 32B 8B 8B 8B 8B 512B Size 8 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 2. DCR Address Map (Sheet 1 of 2) Function Total DCR Address Space1 By function: Reserved Clocking Power On Reset (CPR0) System DCRs (SDR0) Memory Controller (SDRAM0) External Bus Controller (EBC0) Reserved PLB4-to-PLB3 Bridge PLB3-to-PLB4 Bridge Reserved PLB3 Arbiter PLB4 Arbiter PLB3-to-OPB0 Bridge Reserved Power Management Reserved Interrupt Controller 0 Interrupt Controller 1 Interrupt Controller 2 Power Management 1 Reserved DMA-to-PLB3 Controller Reserved Ethernet MAL PLB4-to-OPB1 Bridge Reserved DMA-to-PLB4 Controller PLB4-to-OPB2 Bridge OPB2-to-PLB4 Bridge Reserved USB 2.0 Host OPB Master DCR Reserved USB 2.0 Host OPB Slave DCR Reserved 000 00C 00E 010 012 014 020 030 040 070 080 090 0A0 0B0 0B8 0C0 0D0 0E0 0F0 0F8 100 140 180 200 210 300 340 350 358 360 368 370 374 00B 00D 00F 011 013 01F 02F 03F 06F 07F 08F 09F 0AF 0B7 0BF 0CF 0DF 0EF 0F7 0FF 13F 17F 1FF 20F 2FF 33F 34F 357 35F 367 36F 373 37F 12W 2W 2W 2W 2W 12W 16W 16W 48W 16W 16W 16W 16W 8W 8W 16W 16W 16W 8W 8W 64W 64W 128W 16W 240W 64W 16W 8W 8W 8W 8W 4W 12W Start Address 000 End Address 3FF Size 1KW (4KB)1 AMCC Proprietary 9 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 2. DCR Address Map (Sheet 2 of 2) Function On Chip Memory (SRAM Controller) Reserved Notes: 1. DCR addresses are 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit (word) register. One kiloword (1024 W) equals 4 KB (4096 B). Start Address 380 390 End Address 38F 3FF Size 16W 112W 10 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet PowerPC 440 Processor The PowerPC 440 processor is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the 128-bit version of IBM's on-chip CoreConnect Bus Architecture. Features include: * Up to 667 MHz operation * PowerPC Book E architecture * 32 KB I-cache, 32 KB D-cache - UTLB Word Wide parity on data and tag address parity with exception force * Three logical regions in D-cache: locked, transient, normal * D-cache full line flush capability * 41-bit virtual address, 36-bit (64 GB) physical address * Superscalar, out-of-order execution * 7-stage pipeline * 3 execution pipelines * Dynamic branch prediction * Memory management unit - 64-entry, full associative, unified TLB with optional parity - Separate instruction and data micro-TLBs - Storage attributes for write-through, cache-inhibited, guarded, and big or little endian * Debug facilities - Multiple instruction and data range breakpoints - Data value compare - Single step, branch, and trap events - Non-invasive real-time trace interface * 24 DSP instructions - Single cycle multiply and multiply-accumulate - 32 x 32 integer multiply - 16 x 16 -> 32-bit MAC Floating Point Unit (FPU) The chip has a built-in super scalar FPU that supports both single- and double-precision operations, and offers single cycle through put on most instructions. Features include: * Five stages with 2 MFlops/Hz * Hardware support for IEEE 754 * Single- and double-precision * Single-cycle throughput on most instructions * Thirty-two 64-bit floating point registers SRAM Controller The internal SRAM controller (ISC) supports the following features: * One bank (Bank 0) of 16 KB configurable as 4 KB, 8 KB or 16 KB (128 bits wide) * 128-bit slave attachment addressable by any PLB master * Transfers by PLB slave cycles: - Single-beat read and write (1 to 8 bytes for 64-bit masters, 1 to 16 bytes for 128-bit masters) - 4-word line read and write - 8-word line read and write - Double word read and write bursts for 64-bit masters - Quadword read and write bursts for 128-bit masters AMCC Proprietary 11 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet - Slave-terminated double word and quadword fixed length bursts - Master-terminated variable length bursts Guarded memory access on 4 KB boundaries Data parity checking Data transfers occur at PLB bus speeds. Power management * * * * Internal Buses The PowerPC 440EPx features six standard internal buses: two Processor Local Buses (PLBs), three On-Chip Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor, the DDR SDRAM memory controller, and the PCI bridge connect to the PLBs. OPB0 hosts lower data rate peripherals. OPB1 is dedicated to USB 2.0 Device support, and OPB2 is dedicated to USB 2.0 Host. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor and the other on-chip cores. Features include: * PLB4 (128-bit) - 128-bit implementation of the PLB architecture - Separate and simultaneous read and write data paths - 36-bit address - Simultaneous control, address, and data phases - Four levels of pipelining - Byte-enable capability supporting unaligned transfers - 32- and 64-byte burst transfers - 166 MHz, maximum 5.3 GB/s (simultaneous read and write) - Processor:bus clock ratios of N:1 and N:2 * PLB3 (64-bit) - 64-bit implementation of the PLB architecture - 32-bit address - 166 MHz (1:1 ratio with PLB4), maximum 1.3 GB/s (no simultaneous read and write) * OPBs (OPB0, OPB1, and OPB2) - 32-bit data path - 32-bit address - 83 MHz * DCR - 32-bit data path - 10-bit address Security Function (optional) The built-in security function (PPC440EPx-S only) is a cryptographic engine attached to the 128-bit PLB with builtin DMA and interrupt controllers. Features include: * Federal Information Processing Standard (FIPS) 140-2 design * Support for an unlimited number of Security Associations (SA) * Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP) * Internet Protocol Security (IPSec) features * Full packet transforms (ESP & AH) * Complete header and trailer processing (IPv4 and IPv6) * Multi-mode automatic padding * "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers 12 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet * Secure Socket Layer (SSL) and Transport Layer Security (TLS) features - Packet transforms - One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher * Secure Real-Time Protocol (sRTP) features - Packet transforms - ROC removal and TAG insertion - Variable bypass offset of header length per packet * IPsec/SSL security acceleration engine * DES, 3DES, AES, ARC-4 encryption * MD-5, SHA-1 hashing, HMAC encrypt-hash and hash-decrypt, and KASUMI * Public key acceleration for RSA, DSA and Diffie-Hellman * True or pseudo random number generators - Non-deterministic true random numbers - Pseudo random numbers with lengths of 8 B or 16 B - ANSI X9.17 Annex C compliant using a DES algorithm * Interrupt controller - Fifteen programmable, maskable interrupts - Initiate commands via an input interrupt - Sixteen programmable interrupts indicating completion of certain operations - All interrupts mapped to one level- or edge-sensitive programmable interrupt output * DMA controller - Autonomous, 4-channel - 1024-words (32 bits/word) per DMA transfer - Scatter/gather capability with byte aligned addressing KASUMI Algorithm (optional) * * * * * * Key scheduling hardware f8 and f9 algorithm support Automatic data padding mechanism for f9 algorithm KASUMI encryption and decryption modes 32-bit slave interface Fully synchronous to PLB clock PCI Controller The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices. Reference Specifications: * PowerPC CoreConnect Bus (PLB) Specification Version 3.1 * PCI Specification Version 2.2 * PCI Bus Power Management Interface Specification Version 1.1 Features include: * PCI 2.2 * Frequency to 66 MHz * 32-bit bus * PCI Host Bus Bridge or an Adapter Device's PCI interface * Internal PCI arbitration function, supporting up to six external devices, that can be disabled for use with an external arbiter * Support for Message Signaled Interrupts * Simple message passing capability * Asynchronous to the PLB AMCC Proprietary 13 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet * * * * * PCI Power Management 1.1 PCI register set addressable both from on-chip processor and PCI device sides Ability to boot from PCI bus memory Error tracking/status Supports initiation of transfers of the following types: - Single beat I/O reads and writes - Single beat and burst memory reads and writes - Single beat configuration reads and writes (type 0 and type 1) - Single beat special cycles DDR2/1 SDRAM Memory Controller The Double Data Rate 2/1 (DDR2/1) SDRAM memory controller supports industry standard discrete devices that are compatible with both the DDR1 or DDR2 specifications. The correct I/O supply voltage must be provided for the two types of DDR devices: DDR1 devices require +2.5 V and DDR2 devices require +1.8 V. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include: * 32-bit memory interface for DDR1 * 32- or 64-bit memory interface for DDR2 * Optional Error Checking and Correcting (ECC) * 2.6-GB/s peak data rate * Two memory banks of up to 1 GB each * Maximum capacity of 2GB * Support for 128-Mb, 256-Mb, 512-Mb, and 1-Gb DDR devices, with CAS latencies of 2, 2.5, or 3 * Clock frequencies from 133 MHz (266 Mbps) to 166 MHz (333 Mbps) supported (Faster parts may be used, but must be clocked no faster than 166 MHz) * Page mode accesses (up to 16 open pages) with configurable paging policy * Programmable address mapping and timing * Software initiated self-refresh * Power management (self-refresh, suspend, sleep) * One or two chip selects External Peripheral Bus Controller (EBC) Features include: * Up to six ROM, EPROM, SRAM, Flash memory, and slave peripheral I/O banks supported * Up to 83 MHz operation * Burst and non-burst devices * 32-bit byte-addressable data bus * Data parity * 30-bit address * Peripheral Device pacing with external "Ready" * Latch data on Ready, synchronous or asynchronous * Programmable access timing per device - 256 Wait States for non-burst - 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses - Programmable CSon, CSoff relative to address - Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS * Programmable address mapping * External DMA Slave Support 14 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet * External master interface - Write posting from external master - Read prefetching on PLB for external master reads - Bursting capable from external master - Allows external master access to all non-EBC PLB slaves - External master can control EBC slaves for access Ethernet Controller Ethernet support provided by the PPC440EPx interfaces to the physical layer but the PHY is not included on the chip: * Two 10/100/1000 interfaces running in full- and half-duplex modes providing: - One Gigabit Media Independent Interface (GMII) - One Media Independent Interface (MII) - Two Reduced Gigabit MII (RGMII) - Two Serial MII (SMII) at 100/10 Mbps. - Packet reject support - Jumbo frame support - DMA capability - Interrupt coalescence DMA-to-PLB3 (64-bit) Controller This DMA controller provides a DMA interface between OPB0 and PLB3. Features include: * Supports the following transfers: - Memory-to-memory transfers - Buffered peripheral to memory transfers - Buffered memory to peripheral transfers * Four channels * Scatter/Gather capability for programming multiple DMA operations * 32-byte buffer * 8-, 16-, 32-bit peripheral support (OPB and external) * 32-bit addressing * Address increment or decrement * Supports internal and external peripherals * Support for memory mapped peripherals * Support for peripherals running on slower frequency buses DMA-to-PLB4 (128-bit) Controller This DMA controller provides a DMA interface between the OPB1 dedicated to the USB 2.0 device ports and PLB4. Features include: * Four independent channels supporting internal USB 2.0 Device endpoints 1 and 2 * Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers * Scatter/gather capability * 128-byte buffer with programmable thresholds AMCC Proprietary 15 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Serial Ports (UART) Features include: * Up to four ports in the following combinations: - One 8-pin (UART0) - Two 4-pin (UART0 and UART1) - One 4-pin (UART0) and two 2-pin (UART1 and UART2) - Four 2-pin (UART0, UART1, UART2, and UART3) * Selectable internal or external serial clock to allow wide range of baud rates * Register compatibility with NS16750 register set * Complete status reporting capability * Fully programmable serial-interface characteristics * Supports DMA using internal DMA function on PLB3 IIC Bus Controller Features include: * Two IIC interfaces provided * Support for Philips(R) Semiconductors I2C Specification, dated 1995 * Operation at 100 kHz or 400 kHz * 8-bit data * 10- or 7-bit address * Slave transmitter and receiver * Master transmitter and receiver * Multiple bus masters * Two independent 4 x 1 byte data buffers * Twelve memory-mapped, fully programmable configuration registers * One programmable interrupt request signal * Provides full management of all IIC bus protocols * Programmable error recovery * Includes an integrated bootstrap controller (BSC) that is multiplexed with the second IIC interface Serial Peripheral Controller (SPI/SCP) The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include: * Three-wire serial port interface * Full-duplex synchronous operation * SCP bus master * OPB bus slave * Programmable clock rate divider * Clock inversion * Reverse data * Local data loop back for test Universal Serial Bus 2.0 (USB) The USB 2.0 interface provides both device and host support. One interface provides host or device support and operates through an internal PHY. The other interface provides device support only through the UTMI interface with no internal PHY. 16 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Features include: * USB 2.0 Host with internal PHY - Fully compliant to the following specifications: * Universal Serial Bus Specification, Revision 2.0. * Enhanced Host Controller Interface (EHCI) Specification for USB, Revision 1.0. * Open Host Controller Interface (OHCI) Specification for USB, Revision 1.0a. - One USB port provided through a UTMI transceiver interface connected to the internal USB 2.0 Physical Layer (Single port USB 2.0 Physical Layer UTMI+ version 1.05). - One USB EHCI high speed (480 Mbps) host controller with 1024-byte packet buffer. - One USB OHCI full/low speed (12 Mbps/1.5 Mbps) host controller. - Host controller does not support high-bandwidth isochronous transfers - Independent OPB master and slave ports which run asynchronously to the USB clocks. - USB OHCI/EHCI registers and data structures implemented in Big Endian format. * USB 2.0 Device UTMI or USB 2.0 Device with internal PHY (excluding USB 2.0 Host function) - Device support provides six end points (3 IN, 3 OUT) - 8192-byte FIFO by endpoint (supports high-bandwidth isochronous transfers, double buffering of 1024byte packets) - FIFOs are not shared between IN and OUT endpoints - Two USB 2.0 device end points have DMA dedicated channels (DMA-to-PLB4) NAND Flash Controller The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND Flash devices. It provides both direct command, address, and data access to the external device as well as a memory-mapped linear region that generates data accesses. NAND Flash data is transferred on the peripheral data bus. Features include: * One to four banks supported on EBC * Direct interface to: - Discrete NAND Flash devices (up to four devices) - SmartMedia Card socket (22-pins) * Device Sizes: - 4 MB and larger supported for read/write access - 4MB to 256MB for boot-from-NAND flash (size supported depends on addressing mode) * (512 + 16)-B or (2 K + 64)-B page sizes supported * Boot-from-NAND - Execute up to 4KB of boot code out of first block - Automatic page read accesses performed based on device configuration and addressing mode * ECC provides single-bit error correction and double-bit error detection in each 256 B of stored data General Purpose Timers (GPT) Provides a separate time base counter and additional system timers in addition to those defined in the processor. Features include: * 32-bit Time Base Counter driven by the OPB bus clock * Seven 32-bit compare timers AMCC Proprietary 17 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet General Purpose IO (GPIO) Controller * Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master accesses. * 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose. * Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). Universal Interrupt Controller (UIC) Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) do not use UIC resources. Features include: * 10 external interrupts * Edge triggered or level-sensitive * Positive or negative active * Non-critical or critical interrupt to the on-chip processor * Programmable interrupt priority ordering * Programmable critical interrupt vector for faster vector processing JTAG Features include: * IEEE 1149.1 Test Access Port * JTAG Boundary Scan Description Language (BSDL) * Refer to http://www.amcc.com/Embedded/Partners for a list of AMCC partners supplying probes for use with this port. 18 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Package Diagram Figure 3. 35 mm, 680-Ball TE-PBGA Package Top View Logo View Part Number (R) 30 24 TYP TYP PPC440EPx e1 PPC440EPx-nprffft ccccccc Heat Slug 1YWWBZZZZZ MMDDQL Side View 2.65 max Mold Compound PCB Substrate Lot Number (ZZZZZ) Gold Gate Release Corresponds to A01 Ball Location Bottom View 0.4 - 0.6 35.0 0.20 33.0 AP AM AK AH AF AD AB Y V T P M K H F D AN AL AJ AG AE AC AA W U R N L J G E 9.0 Thermal Balls 1.0 Notes: 1. All dimensions are in mm. 2. Package is available with lead or lead-free (RoHS compliant). 3. Package conforms to JEDEC MS-034. C B A 01 03 05 07 09 11 13 15 17 19 21 23 25 27 29 31 33 02 04 06 08 10 12 14 16 18 20 22 24 26 28 30 32 34 680 x 0.60 0.10 Solder Ball AMCC Proprietary 19 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Assembly Recommendations Table 3. Recommended Reflow Soldering Profile Profile Feature Average ramp-up rate Preheat * Temperature Min * Temperature Max * Time (min to max) Time Maintained Above: * Temperature * Time Peak Temperature Time within 5C of Actual Peak Temperature Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/Second Max Pb Free Reflow Assemble 3C/Second Max 100C 150C 60-120 Seconds 150C 180C 60-120 Seconds 183C 60-150 Seconds 225 +0/-5C 10-30 Seconds 6C/Second Max 6 Minutes Max 230C 30-50 Seconds 260 +5/-0C 10-20 Seconds 6C/Second Max 8 Minutes Max Table 4. JEDEC Moisture Sensitivity Level and Ball Composition Sn-Pb Eutectic Assembly MSL Level Solder Ball Metallurgy 3 63Sn/37Pb 3 Sn/4Ag/05Cu Pb Free Reflow Assembly 20 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list--once for each signal name on the ball. The page number listed gives the page in Table 8 on page 57 where the signals in the indicated interface group begin. In cases where signals in the same interface group (for example, Ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary mode name appearing first. In cases where the signals have the same function but are associated with different ports (for example, UART), the signals are separated by a slash (/). These signals are listed only once, and appear alphabetically by the primary mode or primary port name. Alphabetical Signal List Table 5. Signals Listed Alphabetically (Sheet 1 of 25) Signal Name AGND AVDD BA0 BA1 BA2 BankSel0 BankSel1 [BusReq][USB2TermSel]GPIO31 CAS ClkEn DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8 [DMAAck0][IRQ8]GPIO47 [DMAAck1][IRQ4]GPIO44 [DMAAck2][PerAddr06]GPIO01 [DMAAck3][PerAddr03]GPIO04 [DMAReq0][IRQ7]GPIO46 [DMAReq1]IRQ5[ModeCtrl] [DMAReq2][PerAddr07]GPIO00 [DMAReq3][PerAddr04]GPIO03 Ball AP25 Power AP24 AJ03 AK03 AP08 AH02 DDR SDRAM AH01 P04 AH04 AN09 AL21 AM18 AP15 AL14 AE04 AB03 Y01 U03 AN10 T34 V32 External Slave Peripheral C25 D26 U32 W34 External Slave Peripheral B25 A26 60 60 DDR SDRAM 58 External Master Peripheral DDR SDRAM DDR SDRAM 61 58 58 58 DDR SDRAM 58 65 Interface Group Page AMCC Proprietary 21 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 2 of 25) Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 [DrvrInh1]USB2LS0 [DrvrInh2]Halt EAGND EAVDD ECC0 ECC1 ECC2 ECC3 ECC4 ECC5 ECC6 ECC7 [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD EOVDD [ExtAck][USB2XcvrSel]GPIO30 22 Ball AM21 AM19 AL16 AM13 AE03 AB04 W04 U04 AP10 R02 System E32 AP27 Power AP28 AM11 AL11 AM09 AL09 DDR SDRAM AP11 AN11 AM10 AP09 T32 U33 External Slave Peripheral D25 C26 AA22 AB21 AC33 AF30 AH30 AJ30 Power AK26 AK28 AK29 AK33 AN23 AN30 M03 External Master Peripheral 61 AMCC Proprietary 65 60 58 65 64 DDR SDRAM 58 Interface Group Page Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 3 of 25) Signal Name [ExtReq][USB2RxErr]GPIO27 ExtReset GMCCD, GMC1RxClk GMCCrS, GMC1TxClk GMCGTxClk, GMC0TxClk GMCMDClk GMCMDIO GMCRefClk, SMIIRefClk GMCRxClk, GMC0RxClk, SMIISync GMCRxD0, GMC0RxD0, SMII0RxD GMCRxD1, GMC0RxD1, SMII1RxD GMCRxD2, GMC0RxD2 GMCRxD3, GMC0RxD3 GMCRxD4, GMC1RxD0 GMCRxD5, GMC1RxD1 GMCRxD6, GMC1RxD2 GMCRxD7, GMC1RxD3 GMCRxDV, GMC0RxCtl GMCRxEr, GMC1RxCtl GMCTxClk GMCTxD0, GMC0TxD0, SMII0TxD GMCTxD1, GMC0TxD1, SMII1TxD [GMCTxD2, GMC0TxD2] GPIO24 [GMCTxD3, GMC0TxD3] GPIO25 [GMCTxD4, GMC1TxD0] GPIO16 [GMCTxD5, GMC1TxD1] GPIO17 [GMCTxD6, GMC1TxD2] GPIO18 [GMCTxD7, GMC1TxD3] GPIO19 GMCTxEr, GMC1TxCtl GMCTxEn, GMC0TxCtl A04 D06 AJ32 AK32 AM27 AL34 AK34 AJ33 AN28 AL28 AP29 AM28 AN29 AM29 AP30 AP31 Ethernet AM30 AJ31 AL33 AL27 AL24 AN25 AM25 AL25 AP26 AL26 AN26 AM26 AM24 AN24 59 Ball Interface Group External Master Peripheral External Master Peripheral Page 61 61 AMCC Proprietary 23 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 4 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A01 A02 A03 A28 A32 A33 A34 B01 B02 B03 B04 B08 B16 B19 B26 B27 B31 B32 B33 B34 C02 C03 C04 C31 C32 C33 C34 D03 D04 D05 D30 D31 D32 D33 E05 E08 E10 Power 65 Ball Interface Group Page 24 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 5 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND E16 E18 E19 E25 E27 E30 E31 H01 H02 H05 H30 H33 K05 K30 N01 N04 N13 N15 N17 N18 N20 N22 P14 P15 P17 P18 P20 P21 R13 R14 R15 R16 R17 R18 R19 R20 R21 Power 65 Ball Interface Group Page AMCC Proprietary 25 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 6 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND R22 T02 T05 T15 T16 T17 T18 T19 T20 T30 T33 U05 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V30 W02 W05 W15 W16 Power 65 Ball Interface Group Page 26 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 7 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball W17 W18 W19 W20 W30 W33 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA14 AA15 AA17 AA18 AA20 AA21 AB13 AB15 AB17 AB18 AB20 AB22 AD01 AE05 AE30 AG02 AG05 AG30 AG33 AJ01 AK04 Power 65 Interface Group Page AMCC Proprietary 27 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 8 of 25) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Ball AK05 AK08 AK10 AK16 AK17 AK19 AK25 AK27 AK30 AK31 AL03 AL04 AL05 AL06 AL29 AL30 AL31 AL32 AM01 AM02 AM03 AM04 AM31 AM32 AM33 AM34 AN01 AN02 AN03 AN04 AN08 AN16 AN19 AN27 AN31 AN32 AN33 Power 65 Interface Group Page 28 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 9 of 25) Signal Name GND GND GND GND GND GND GND GPIO00[PerAddr07][DMAReq2] GPIO01[PerAddr06][DMAAck2] GPIO02[PerAddr05][EOT2/TC2] GPIO03[PerAddr04][DMAReq3] GPIO04[PerAddr03][DMAAck3] GPIO05[PerAddr02][EOT3/TC3] GPIO06[PerCS1][NFCE1] GPIO07[PerCS2][NFCE2] GPIO08[PerCS3][NFCE3] GPIO09[PerCS4] GPIO10[PerCS5] GPIO11[PerErr] GPIO12[NFREn] GPIO13[NFWEn] GPIO14[NFCLE] GPIO15[NFALE] GPIO16[GMCTxD4, GMC1TxD0] GPIO17[GMCTxD5, GMC1TxD1] GPIO18[GMCTxD6, GMC1TxD2] GPIO19[GMCTxD7, GMC1TxD3] GPIO20[RejectPkt0] GPIO21[RejectPkt1] GPIO22[NFRdyBusy] GPIO23[SCPDO] GPIO24[GMCTxD2, GMC0TxD2] GPIO25[GMCTxD3, GMC0TxD3] [GPIO26]IIC0SData GPIO27[USB2RxErr][ExtReq] GPIO28[USB2TxVal] GPIO29[USB2Susp][HoldAck] GPIO30[USB2XcvrSel][ExtAck] GPIO31[USB2TermSel][BusReq] Ball AN34 AP01 AP02 AP03 AP32 AP33 AP34 B25 C25 D25 A26 D26 C26 B09 D09 D08 A09 A08 C07 D17 A16 A18 B17 System AP26 AL26 AN26 AM26 AM23 AL23 A17 AB31 AM25 AL25 AB33 A04 C06 C05 M03 P04 64 Power 65 Interface Group Page AMCC Proprietary 29 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 10 of 25) Signal Name GPIO32[USB2OM0][PerDataPar2] GPIO33[USB2OM1][PerDataPar3] GPIO34[UART0_DCD/UART1_CTS/UART2_Tx] GPIO35[UART0_DSR/UART1_RTS/UART2_Rx] GPIO36[UART0_CTS/UART3_Rx][PerDataPar0] GPIO37[UART0_RTS/UART3_Tx][PerDataPar1] GPIO38[UART0_DTR/UART1_Tx] GPIO39[UART0_RI/UART1_Rx] GPIO40[IRQ0] GPIO41[IRQ1] GPIO42[IRQ2] GPIO43[IRQ3] GPIO44[IRQ4][DMAAck1] GPIO45[IRQ6][EOT1/TC1] GPIO46[IRQ7][DMAReq0] GPIO47[IRQ8[DMAAck0] GPIO48[IRQ9][EOT0/TC0] GPIO49[TrcBS0] GPIO50[TrcBS1] GPIO51[TrcBS2] GPIO52[TrcES0] GPIO53[TrcES1] GPIO54[TrcES2] GPIO55[TrcES3] GPIO56[TrcES4] GPIO57[TrcTS0] GPIO58[TrcTS1] GPIO59[TrcTS2] GPIO60[TrcTS3] GPIO61[TrcTS4] GPIO62[TrcTS5] GPIO63[TrcTS6] Halt[DrvrInh2] [HoldAck][USB2Susp]GPIO29 [HoldPri]USB2LS1[LeakTest] [HoldReq]USB2RxAct[RcvrInh] IIC0SClk IIC0SData[GPIO26] R03 R04 C28 C29 A29 B29 D28 B28 AD33 AC31 AD34 U34 V32 U33 U32 T34 System T32 AE34 AE32 AE33 AE31 AF34 AF33 AF32 AF31 AG34 AG31 AH33 AH34 AH32 AJ34 AH31 E32 C05 P01 D07 AB32 IIC0 Peripheral AB33 61 External Master Peripheral 61 System 64 64 Ball Interface Group Page 30 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 11 of 25) Signal Name [IIC1SClk]SCPClkOut [IIC1SData]SCPDI [IRQ0]GPIO40 [IRQ1]GPIO41 [IRQ2]GPIO42 [IRQ3]GPIO43 [IRQ4]GPIO44[DMAAck1] IRQ5[ModeCtrl][DMAReq1] [IRQ6]GPIO45[EOT1/TC1] [IRQ7]GPIO46[DMAReq0] [IRQ8]GPIO47[DMAAck0] [IRQ9]GPIO48[EOT0/TC0] [LeakTest]USB2LS1[HoldPri] [LeakTest2]USB2RxDV MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemAddr13 MemClkOut MemClkOut Ball AC34 IIC1 Peripheral AC32 AD33 AC31 AD34 U34 V32 Interrupts W34 U33 U32 T34 T32 P01 System C08 AM05 AP04 AP05 AM06 AP06 AN06 AL07 DDR SDRAM AN07 AM07 AP07 AL02 AL08 AM08 AG04 AL01 DDR SDRAM AK01 58 58 64 63 61 Interface Group Page AMCC Proprietary 31 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 12 of 25) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 MemData28 MemData29 MemData30 MemData31 Ball AN22 AP22 AM20 AL20 AL22 AM22 AN21 AP21 AP20 AL18 AN17 AP17 AN20 AP19 AN18 AP18 DDR SDRAM AM16 AP16 AL15 AP14 AL17 AM17 AN15 AM15 AP13 AN13 AP12 AL12 AM14 AN14 AL13 AM12 58 Interface Group Page 32 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 13 of 25) Signal Name MemData32 MemData33 MemData34 MemData35 MemData36 MemData37 MemData38 MemData39 MemData40 MemData41 MemData42 MemData43 MemData44 MemData45 MemData46 MemData47 MemData48 MemData49 MemData50 MemData51 MemData52 MemData53 MemData54 MemData55 MemData56 MemData57 MemData58 MemData59 MemData60 MemData61 MemData62 MemData63 MemODT0 MemODT1 [ModeCtrl]IRQ5[DMAReq1] Ball AF03 AF01 AD04 AD03 AG03 AF02 AE02 AE01 AC03 AC01 AA04 AA03 AD02 AC04 AB01 AB02 DDR SDRAM Y03 Y02 V04 V03 AA02 AA01 W03 W01 U01 U02 T04 R01 V02 V01 T01 T03 AH03 DDR SDRAM AG01 W34 System 64 58 58 Interface Group Page AMCC Proprietary 33 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 14 of 25) Signal Name [NFALE]GPIO15 [NFCE0]PerCS0 [NFCE1][PerCS1]GPIO06 [NFCE2][PerCS2]GPIO07 [NFCE3][PerCS3]GPIO08 [NFCLE]GPIO14 [NFRdyBusy]GPIO22 [NFREn]GPIO12 [NFWEn]GPIO13 No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball B17 D10 B09 D09 D08 A18 A17 D17 A16 F06-F29 G06-G29 H06-H29 J06-J29 K06-K29 L06-L29 M06-M29 N06-N12 N23-N29 P06-P12 P23-P29 R06-R12 R23-R29 T06-T12 T23-T29 U06-U12 U23-U29 V06-V12 V23-V29 W06-W12 W23-W29 Y06-Y12 Y23-Y29 AA06-AA12 AA23-AA29 AB06-AB12 AB23-AB29 A physical ball does not exist at these ball coordinates. NA NAND Flash 62 Ball Interface Group Page 34 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 15 of 25) Signal Name No ball No ball No ball No ball No ball No ball No ball OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Ball AC06-AC29 AD06-AD29 AE06-AE29 AF06-AF29 AG06-AG29 AH06-AH29 AJ06-AJ29 B05 B12 B23 B30 E02 E06 E07 E09 E17 E26 E28 E29 E33 Power F05 F30 G05 G30 J05 J30 M02 M33 N14 N21 P13 P22 U30 65 A physical ball does not exist at these ball coordinates. NA Interface Group Page AMCC Proprietary 35 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 16 of 25) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 PCIAD28 PCIAD29 PCIAD30 PCIAD31 PCIC0/BE0 PCIC1/BE1 PCIC2/BE2 PCIC3/BE3 PCIClk PCIDevSel PCIFrame D29 A30 C30 A31 D34 F31 E34 F32 F33 F34 G31 G33 G34 H31 H32 H34 PCI L31 L33 M32 M31 M34 N31 N33 N32 P31 P33 P32 P34 R31 R32 R33 R34 G32 J31 PCI L34 N34 AA32 K32 L32 PCI PCI PCI 57 57 57 57 57 Ball Interface Group Page 36 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 17 of 25) Signal Name PCIGnt0/Req PCIGnt1 PCIGnt2 PCIGnt3 PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY Y34 Y33 Y32 PCI Y31 AA33 AA34 T31 AB34 K33 J32 J33 V34 U31 V33 PCI V31 W32 W31 AA31 J34 K31 K34 PCI PCI PCI PCI 57 57 57 57 57 PCI PCI PCI PCI PCI 57 57 57 57 57 57 Ball Interface Group Page AMCC Proprietary 37 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 18 of 25) Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 PerAddr30 PerAddr31 PerBLast PerClk PerCS0[NFCE0] [PerCS1][NFCE1]GPIO06 [PerCS2][NFCE2]GPIO07 [PerCS3][NFCE3]GPIO08 [PerCS4]GPIO09 [PerCS5]GPIO10 C26 D26 A26 D25 C25 B25 A25 C24 D24 B24 D23 A24 C23 A23 D22 External Slave Peripheral C22 A22 D21 C21 B21 A21 D20 C20 B20 D19 C19 A19 D18 C18 B18 B07 A07 D10 B09 D09 External Slave Peripheral D08 A09 A08 60 External Slave Peripheral External Master Peripheral 60 61 60 Ball Interface Group Page 38 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 19 of 25) Signal Name PerData00 PerData01 PerData02 PerData03 PerData04 PerData05 PerData06 PerData07 PerData08 PerData09 PerData10 PerData11 PerData12 PerData13 PerData14 PerData15 PerData16[USB2DO0] PerData17[USB2DO1] PerData18[USB2DO2] PerData19[USB2DO3] PerData20[USB2DO4] PerData21[USB2DO5] PerData22[USB2DO6] PerData23[USB2DO7] PerData24[USB2DI0] PerData25[USB2DI1] PerData26[USB2DI2] PerData27[USB2DI3] PerData28[USB2DI4] PerData29[USB2DI5] PerData30[USB2DI6] PerData31[USB2DI7] [PerDataPar0]GPIO36[UART0_CTS/UART3_Rx] [PerDataPar1]GPIO37[UART0_RTS//UART3_Tx] [PerDataPar2]GPIO32[USB2OM0] [PerDataPar3]GPIO33[USB2OM1] [PerErr]GPIO11 PerOE PerReady C14 D14 A13 B13 C13 D13 A12 C12 A11 D12 B11 C11 D11 A10 B10 C10 E03 C01 External Slave Peripheral D02 E04 D01 E01 F04 F03 F02 F01 G03 G04 G02 G01 H04 H03 A29 B29 R03 R04 C07 B14 C17 External Master Peripheral External Slave Peripheral External Slave Peripheral 60 60 60 60 Ball Interface Group Page AMCC Proprietary 39 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 20 of 25) Signal Name PerR/W PerWBE0 PerWBE1 PerWBE2 PerWBE3 PSROOut RAS [RcvrInh]USB2RxAct[HoldReq] [RefEn]USB2TxRdy [RejectPkt0]GPIO20 [RejectPkt1]GPIO21 SCPClkOut[IIC1SClk] SCPDI[IIC1SData] [SCPDO]GPIO23 SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SOVDD SVREF1A SVREF1B SVREF2A SVREF2B SysClk SysErr SysReset TCK TDI A14 A15 B15 External Slave Peripheral C15 D15 A20 AJ04 D07 B06 AM23 Ethernet AL23 AC34 AC32 AB31 V05 AA13 AB14 AC02 AF05 AH05 AJ05 Power AK02 AK06 AK07 AK09 AK18 AN05 AN12 Y04 AL10 DDR SDRAM AF04 AL19 AP23 AD32 AD31 P02 K03 System System System JTAG JTAG 64 64 64 63 63 58 65 Serial Peripheral (SPI) 63 59 System DDR SDRAM System System 64 58 64 64 60 Ball Interface Group External Slave Peripheral Page 60 40 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 21 of 25) Signal Name TDO TestEn TherMonA TherMonB TmrClk TMS [TrcBS0]GPIO49 [TrcBS1]GPIO50 [TrcBS2]GPIO51 TrcClk [TrcES0]GPIO52 [TrcES1]GPIO53 [TrcES2]GPIO54 [TrcES3]GPIO55 [TrcES4]GPIO56 [TrcTS0]GPIO57 [TrcTS1]GPIO58 [TrcTS2]GPIO59 [TrcTS3]GPIO60 [TrcTS4]GPIO61 [TrcTS5]GPIO62 [TrcTS6]GPIO63 TRST [UART0_CTS/UART3_Rx]GPIO36[PerDataPar0] [UART0_DCD/UART1_CTS/UART2_Tx]GPIO34 [UART0_DSR/UART1_RTS/UART2_Rx]GPIO35 [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 [UART0_RTS/UART3_Tx]GPIO37[PerDataPar1] UART0_Rx UARTSerClk UART0_Tx B22 C09 C16 System D16 P03 K02 AE34 AE32 AE33 AG32 AE31 AF34 AF33 AF32 AF31 AG34 AG31 AH33 AH34 AH32 AJ34 AH31 A06 A29 C28 C29 D28 B28 B29 C27 A27 D27 UART Peripheral 61 JTAG 63 Trace 65 Trace 65 Trace 65 Trace 65 System JTAG 64 63 64 Ball JTAG System Interface Group Page 63 64 AMCC Proprietary 41 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 22 of 25) Signal Name U1AVDD U1AVDD U2AVDD U2AVDD U1AGND U1AGND U2AGND U2AGND UA2GND USB2Clk [USB2DI0]PerData24 [USB2DI1]PerData25 [USB2DI2]PerData26 [USB2DI3]PerData27 [USB2DI4]PerData28 [USB2DI5]PerData29 [USB2DI6]PerData30 [USB2DI7]PerData31 [USB2DO0]PerData16 [USB2DO1]PerData17 [USB2DO2]PerData18 [USB2DO3]PerData19 [USB2DO4]PerData20 [USB2DO5]PerData21 [USB2DO6]PerData22 [USB2DO7]PerData23 USB2LS0[DrvrInh1] USB2LS1[LeakTest][HoldPri] [USB2OM0]GPIO32[PerDataPar2] [USB2OM1]GPIO33[PerDataPar3] USB2RExt USB2RxAct[HoldReq][RcvrInh] USB2RxDV[LeakTest2] [USB2RxErr]GPIO27[ExtReq] [USB2Susp]GPIO29[HoldAck] [USB2TermSel]GPIO31[BusReq] USB2TxRdy[RefEn] [USB2TxVal]GPIO28 L01 L02 J04 L04 M01 M04 J03 K04 K01 A05 F02 F01 G03 G04 Universal Serial Bus G02 G01 H04 H03 E03 C01 D02 E04 Universal Serial Bus D01 E01 F04 F03 R02 Universal Serial Bus P01 R03 Universal Serial Bus R04 L03 D07 C08 A04 C05 P04 B06 C06 Universal Serial Bus Universal Serial Bus Universal Serial Bus Universal Serial Bus Universal Serial Bus Universal Serial Bus Universal Serial Bus Universal Serial Bus 62 62 62 62 62 62 62 62 62 62 62 62 Universal Serial Bus 62 Power 65 Ball Interface Group Page 42 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 23 of 25) Signal Name [USB2XcvrSel]GPIO30[ExtAck] USB2Xcvr USB2Xcvr USB2XtalIn USB2XtalOut M03 J02 Universal Serial Bus J01 N02 Universal Serial Bus N03 62 62 Ball Interface Group Universal Serial Bus Page 62 AMCC Proprietary 43 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 24 of 25) Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD E11 E12 E13 E14 E15 E20 E21 E22 E23 E24 L05 L30 M05 M30 N05 N16 N19 Power N30 P05 P16 P19 P30 R05 R30 T13 T14 T21 T22 W13 W14 W21 W22 Y05 Y30 65 Ball Interface Group Page 44 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 5. Signals Listed Alphabetically (Sheet 25 of 25) Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD WE Ball AA05 AA16 AA19 AA30 AB05 AB16 AB19 AB30 AC05 AC30 AD05 Power AD30 AK11 AK12 AK13 AK14 AK15 AK20 AK21 AK22 AK23 AK24 AJ02 DDR SDRAM 58 65 Interface Group Page Signals in Ball Assignment Order In the following table, only the primary (default) signal name is shown for each ball. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what other signals or functions are on those balls, look up the primary signal name in Table 5 on page 21. AMCC Proprietary 45 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 1 of 9) Ball A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 GND GND GND GPIO27* USB2Clk TRST PerClk GPIO10* GPIO09* PerData13 PerData08 PerData06 PerData02 PerR/W PerWBE0 GPIO13* GPIO22* GPIO14* PerAddr28 PSROOut PerAddr22 PerAddr18 PerAddr15 PerAddr13 PerAddr08 GPIO03* UARTSerClk GND GPIO36* PCIAD01 PCIAD03 GND GND GND Signal Name Ball B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 GND GND GND GND Signal Name Ball C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 Signal Name PerData17* GND GND GND GPIO29* GPIO28* GPIO11* USB2RxDV* TestEn PerData15 PerData11 PerData07 PerData04 PerData00 PerWBE2 TherMonA PerReady PerAddr30 PerAddr27 PerAddr24 PerAddr20 PerAddr17 PerAddr14 PerAddr09 GPIO01* GPIO05* UART0_Rx GPIO34* GPIO35* PCIAD02 GND GND GND GND Ball D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 Signal Name PerData20* PerData18* GND GND GND ExtReset USB2RxAct* GPIO08* GPIO07* PerCS0* PerData12 PerData09 PerData05 PerData01 PerWBE3 TherMonB GPIO12* PerAddr29 PerAddr26 PerAddr23 PerAddr19 PerAddr16 PerAddr12 PerAddr10 GPIO02* GPIO04* UART0_Tx GPIO38* PCIAD00 GND GND GND GND PCIAD04 OVDD USB2TxRdy* PerBLast GND GPIO06* PerData14 PerData10 OVDD PerData03 PerOE PerWBE1 GND GPIO15* PerAddr31 GND PerAddr25 PerAddr21 TDO OVDD PerAddr11 GPIO00* GND GND GPIO39* GPIO37* OVDD GND GND GND GND 46 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 2 of 9) Ball E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 Signal Name PerData21* OVDD PerData16* PerData19* GND OVDD OVDD GND OVDD GND VDD VDD VDD VDD VDD GND OVDD GND GND VDD VDD VDD VDD VDD GND OVDD GND OVDD OVDD GND GND Halt* OVDD PCIAD06 Ball F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 Signal Name PerData25* USB2DI0* PerData23* PerData22* OVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball OVDD PCIAD05 PCIAD07 PCIAD08 PCIAD09 Ball G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 Signal Name PerData29* PerData28* PerData26* PerData27* OVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball OVDD PCIAD10 PCIC0/BE0 PCIAD11 PCIAD12 Ball H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 GND GND Signal Name PerData31* PerData30* GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND PCIAD13 PCIAD14 GND PCIAD15 AMCC Proprietary 47 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 3 of 9) Ball J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 J31 J32 J33 J34 Signal Name USB2Xcvr USB2Xcvr U2AGND U2AVDD OVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball OVDD PCIC1/BE1 PCIPar PCIPErr PCISErr Ball K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 K32 K33 K34 Signal Name U2AGND TMS TDI U2AGND GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND PCIStop PCIDevSel PCIIRDY PCITRDY Ball L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 Signal Name U1AVDD U1AVDD USB2RExt U2AVDD VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIAD16 PCIFrame PCIAD17 PCIC2/BE2 Ball M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 Signal Name U1AGND OVDD GPIO30* U1AGND VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIAD19 PCIAD18 OVDD PCIAD20 48 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 4 of 9) Ball N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 N29 N30 N31 N32 N33 N34 GND USB2XtalIn USB2XtalOut GND VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND OVDD GND VDD GND GND VDD GND OVDD GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIAD21 PCIAD23 PCIAD22 PCIC3/BE3 Signal Name Ball P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33 P34 Signal Name USB2LS1* TCK TmrClk GPIO31* VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball OVDD GND GND VDD GND GND VDD GND GND OVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIAD24 PCIAD26 PCIAD25 PCIAD27 Ball R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 Signal Name MemData59 USB2LS0* GPIO32* GPIO33* VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND GND GND GND GND GND GND GND GND GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIAD28 PCIAD29 PCIAD30 PCIAD31 Ball T01 T02 T03 T04 T05 T06 T07 T08 T09 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 Signal Name MemData62 GND MemData63 MemData58 GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD VDD GND GND GND GND GND GND VDD VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND PCIIDSel GPIO48* GND GPIO47* AMCC Proprietary 49 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 5 of 9) Ball U01 U02 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 U31 U32 U33 U34 Signal Name MemData56 MemData57 DM7 DQS7 GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND GND GND GND GND GND GND GND GND GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball OVDD PCIReq1 GPIO46* GPIO45* GPIO43* Ball V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 Signal Name MemData61 MemData60 MemData51 MemData50 SOVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND GND GND GND GND GND GND GND GND GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND PCIReq3 GPIO44* PCIReq2 PCIReq0/Gnt Ball W01 W02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 W29 W30 W31 W32 W33 W34 Signal Name MemData55 GND MemData54 DQS6 GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD VDD GND GND GND GND GND GND VDD VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND PCIReq5 PCIReq4 GND IRQ5* Ball Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 DM6 Signal Name MemData49 MemData48 SVREF1A VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND GND GND GND GND GND GND GND GND GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIGnt3 PCIGnt2 PCIGnt1 PCIGnt0/Req 50 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 6 of 9) Ball AA01 AA02 AA03 AA04 AA05 AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AA32 AA33 AA34 Signal Name MemData53 MemData52 MemData43 MemData42 VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball SOVDD GND GND VDD GND GND VDD GND GND EOVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD PCIReset PCIClk PCIGnt4 PCIGnt5 Ball AB01 AB02 AB03 AB04 AB05 AB06 AB07 AB08 AB09 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AB32 AB33 AB34 Signal Name MemData46 MemData47 DM5 DQS5 VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND SOVDD GND VDD GND GND VDD GND EOVDD GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD GPIO23* IIC0SClk GPIO26* PCIINT Ball AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AC32 AC33 AC34 Signal Name MemData41 SOVDD MemData40 MemData45 VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD GPIO41* SCPDI* EOVDD SCPClkOut* Ball AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD32 AD33 AD34 GND Signal Name MemData44 MemData35 MemData34 VDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball VDD SysReset SysErr GPIO40* GPIO42* AMCC Proprietary 51 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 7 of 9) Ball AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE31 AE32 AE33 AE34 Signal Name MemData39 MemData38 DQS4 DM4 GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND GPIO52* GPIO50* GPIO51* GPIO49* Ball AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AF31 AF32 AF33 AF34 Signal Name MemData33 MemData37 MemData32 SVREF2A SOVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball EOVDD GPIO56* GPIO55* GPIO54* GPIO53* Ball AG01 AG02 AG03 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AG31 AG32 AG33 AG34 Signal Name MemODT1 GND MemData36 MemAddr13 GND No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball GND GPIO58* TrcClk GND GPIO57* Ball AH01 AH02 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AH31 AH32 AH33 AH34 Signal Name BankSel1 BankSel0 MemODT0 CAS SOVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball EOVDD GPIO63* GPIO61* GPIO59* GPIO60* 52 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 8 of 9) Ball AJ01 AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AJ31 AJ32 AJ33 AJ34 GND WE BA0 RAS SOVDD No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball No Ball EOVDD GMCRxDV* GMCCD* GMCRefClk* GPIO62* Signal Name Ball AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK08 AK09 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 Signal Name MemClkOut SOVDD BA1 GND GND SOVDD SOVDD GND SOVDD GND VDD VDD VDD VDD VDD GND GND SOVDD GND VDD VDD VDD VDD VDD GND EOVDD GND EOVDD EOVDD GND GND GMCCrS* EOVDD GMCMDIO Ball AL01 AL02 AL03 AL04 AL05 AL06 AL07 AL08 AL09 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 Signal Name MemClkOut MemAddr10 GND GND GND GND MemAddr06 MemAddr11 ECC3 SVREF1B ECC1 MemData27 MemData30 DM3 MemData18 DQS2 MemData20 MemData09 SVREF2B MemData03 DM0 MemData04 GPIO21* GMCTxD0* GPIO25* GPIO17* GMCTxClk* GMCRxD0* GND GND GND GND GMCRxEr* GMCMDClk Ball AM01 AM02 AM03 AM04 AM05 AM06 AM07 AM08 AM09 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 GND GND GND GND Signal Name MemAddr00 MemAddr03 MemAddr08 MemAddr12 ECC2 ECC6 ECC0 MemData31 DQS3 MemData28 MemData23 MemData16 MemData21 DM1 DQS1 MemData02 DQS0 MemData05 GPIO20* GMCTxEr* GPIO24* GPIO19* GMCGTxClk* GMCRxD2* GMCRxD4* GMCRxD7* GND GND GND GND AMCC Proprietary 53 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 6. Signals Listed by Ball Assignment (Sheet 9 of 9) Ball AN01 AN02 AN03 AN04 AN05 AN06 AN07 AN08 AN09 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 GND GND GND GND SOVDD MemAddr05 MemAddr07 GND ClkEn DM8 ECC5 SOVDD MemData25 MemData29 MemData22 GND MemData10 MemData14 GND MemData12 MemData06 MemData00 EOVDD GMCTxEn* GMCTxD1* GPIO18* GND GMCRxClk* GMCRxD3* EOVDD GND GND GND GND Signal Name Ball AP01 AP02 AP03 AP04 AP05 AP06 AP07 AP08 AP09 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 GND GND GND Signal Name Ball Signal Name Ball Signal Name MemAddr01 MemAddr02 MemAddr04 MemAddr09 BA2 ECC7 DQS8 ECC4 MemData26 MemData24 MemData19 DM2 MemData17 MemData11 MemData15 MemData13 MemData08 MemData07 MemData01 SysClk AVDD AGND GPIO16* EAGND EAVDD GMCRxD1* GMCRxD5* GMCRxD6* GND GND GND 54 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Signal Descriptions The PPC440EPx embedded controller is packaged in a 680-ball thermally enhanced plastic ball grid array (TE-PBGA). The following tables describe the package level pin-out. Table 7. Pin Summary Group Total Signal Pins AVDD AGND EAVDD EAGND UAVDD UAGND OVDD SOVDD EOVDD VDD GND Total Power Pins Reserved Total Pins No. of Pins 367 1 1 1 1 4 5 26 14 12 56 192 313 0 680 In the table Table 8 on page 57, each I/O signal is listed along with a short description of its function. Active-low signals (for example, RAS) are marked with an overline. Please see Table 5 on page 21 for the pin (ball) number to which each signal is assigned. Multiplexed Signals Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in Table 5 on page 21. It is expected that in any single application a particular pin will always be programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. Note: Signals multiplexed with GPIO default to GPIO receivers and float after reset. Initialization software must configure the GPIO registers for the desired function as described in the GPIO chapter of the user's manual. Any of these signals requiring a particular state prior to running initialization code must be terminated with pull ups or pull downs. Multipurpose Signals In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address pins (PerAddr) are used as outputs by the PPC440EPx to broadcast an address to external slave devices when the PPC440EPx has control of the external bus. When, during normal operation, an external master gains ownership AMCC Proprietary 55 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440EPx. In this example, the pins are also bidirectional, serving both as inputs and outputs. Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see "Strapping" on page 91). Note that these are not multiplexed pins since the function of the pins is not programmable. Unused I/Os Termination of unused receivers is generally required; however, there are some exceptions that reduce or eliminate the need for termination. Signals Multiplexed with GPIO: By default after reset, signals shared with GPIO pins are configured as GPIO receivers. Termination however, is not needed if the GPIO during initialization are configured as outputs. To configure as drivers, set and clear the appropriate bits in the GPIOx_ODR, GPIOx_TCR and GPIOx_OR registers as described in the GPIO chapter of the user's manual. PCI: When the PCI bridge is unused, configure the PCI controller to park on the bus by pulling the PCIReg0[Gnt} signal low. Parking forces the PLB3 to PCI bridge to actively drive PCIAD31:0 and PCIC3:0[BE3:0]. The remaining PCI control signals must be terminated as follows: - Disable the internal PCI arbiter and enable PCI synchronous mode. (See IIC Boot Strap Chapter in the user's manual). Note: Synchronous mode is not supported when operating the PCI bus. This mode should only be used for terminating an unused PCI interface). - Individually connect PCISErr, PCITRDY, and PCIStop through 3k resistors to +3.3V. - Individually connect PCIReq1:5 through 3k resistors to +3.3V. - Connect PCIReq0[Gnt] through 1k resistor to GND. DDR: - In 32 bit mode, termination is not needed on the upper data, strobe and mask signals when the DDR I/O and DDR controller are configured for 32 bit mode, SDR0_DDRCFG[64B32B]=0 and DDR0_14[REDUC]=1. - Termination of unused ECC signals (ECC0:7, DM8, DQS8) is not needed. 56 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 1 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name PCI Interface PCIAD00:31 PCIC0:3/BE0:3 PCIClk PCIDevSel Address/Data bus (bidirectional). PCI Command/Byte Enables. Provides timing to the PCI interface for PCI transactions. Indicates the driving device has decoded its address as the target of the current access. (PCI 2.2 specification requires 8.2K pull up on host system) Driven by the current master to indicate beginning and duration of an access. (PCI 2.2 specification requires 8.2K pull up on host system) Indicates that the specified agent is granted access to the bus. When the internal arbiter is enabled, output is PCIGnt0. When the internal arbiter is disabled, output is Req. (PCI 2.2 specification requires 8.2K pull up on host system) Indicates that the specified agent is granted access to the bus. Used only when internal PCI arbiter enabled. Used as a chip select during configuration read and write transactions. Level sensitive PCI interrupt. Indicates initiating agent's ability to complete the current data phase of the transaction. (PCI 2.2 specification requires 8.2K pull up on host system) Even parity. Reports data parity errors during all PCI transactions except a Special Cycle. (PCI 2.2 specification requires 8.2K pull up on host system) Indicates to the PCI arbiter that the specified agent wishes to use the bus. When the internal arbiter is enabled, input is PCIReq0. When internal arbiter is disabled, input is Gnt. An indication to the PCI arbiter that the specified agent wishes to use the bus. Used only when internal PCI arbiter enabled. Brings PCI device registers and logic to a consistent state. Reports address parity errors, data parity errors on the Special Cycle command, or other catastrophic system errors. (PCI 2.2 specification requires 8.2K pull up on host system) Indicates the current target is requesting the master to stop the current transaction. (PCI 2.2 specification requires 8.2K pull up on host system) I/O I/O I I/O 3.3 V PCI 3.3 V PCI 3.3 V PCI 3.3 V PCI 1, 5 Description I/O Type Notes PCIFrame I/O 3.3 V PCI PCIGnt0/Req O 3.3 V PCI PCIGnt1:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr O I O I/O I/O I/O 3.3 V PCI 3.3 V PCI 3.3 V PCI 3.3 V PCI 3.3 V PCI 3.3 V PCI PCIReq0/Gnt I 3.3 V PCI 1, 4 PCIReq1:5 PCIReset PCISErr I O I/O 3.3 V PCI 3.3 V PCI 3.3 V PCI 1, 4 PCIStop I/O 3.3 V PCI PCITRDY Indicates the target agent's ability to complete the current data phase of the transaction. (PCI 2.2 specification requires 8.2K pull up on host system) I/O 3.3 V PCI AMCC Proprietary 57 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 2 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name DDR2/1 SDRAM Interface BA0:2 BankSel0:1 CAS ClkEn DM0:7 DM8 DQS0:7 DQS8 ECC0:7 MemAddr00:13 MemData00:63 MemClkOut MemClkOut MemODT0:1 RAS WE SVREF1A:B SVREF2A:B Bank Address supporting up to eight internal banks. Selects up to two external DDR SDRAM banks. Column Address Strobe. Clock Enable. Memory write data byte lane masks. DM8 is the byte lane mask for the ECC byte lane. Byte lane data strobe. Byte lane data strobe for ECC. ECC check bits 0:7. Memory address bus. Memory data bus (MemData32:63 available for DDR2 only). O O O O O I/O I/O O I/O 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR Diff driver 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR 2.5 V (1.8 V) SDRAM-DDR Volt ref receiver (1.25 V or 0.9 V ) Volt ref driver (1.25 V or 0.9 V ) Description I/O Type Notes Subsystem clock. O DDR2 On-die termination enable (not used with DDR1). Row Address Strobe. Write Enable. DDR SDRAM reference voltage 1 input. DDR SDRAM reference voltage 2 input. O O O I I 58 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 3 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name Ethernet Interface GMCRxD0:1, GMC0RxD0:1, SMII0:1RxD GMCRxD2:3 GMC0RxD2:3 GMCRxD4:7, GMC1RxD0:3 GMCTxD0:1, GMC0TxD0:1, SMII0:1TxD GMCTxD2:3, GMC0TxD2:3 GMCTxD4:7, GMC1TxD0:3 GMCRxEr, GMC1RxCtl GMCRxClk, GMC0RxClk, SMIISync GMCRxDV, GMC0RxCtl GMCCrS, GMC1TxClk GMCTxEr, GMC1TxCtl GMCTxEn, GMC0TxCtl GMCTxClk GMCCD, GMC1RxClk GMCMDClk GMCMDIO GMCGTxClk, GMC0TxClk GMCRefClk, SMIIRefClk RejectPkt0:1 GMII/MII: Receive data. RGMII 0: Receive data. SMII 0:1: Receive data. GMII/MII: Receive data. RGMII 0: Receive data. GMII/MII: Receive data. RGMII 1: Receive data. GMII/MII: Transmit data. RGMII 0: Transmit data. SMII 0:1: Transmit data. GMII/MII: Transmit data. RGMII 0: Transmit data. GMII/MII: Transmit data. RGMII 1: Transmit data. GMII/MII: Receive error. RGMII 1: Receive control. GMII/MII: Receive clock. RGMII 0: Receive clock. SMII: Synchronizing signal. GMII/MII: Receive data valid. RGMII 0: Receive control. GMII/MII: Carrier sense. RGMII 1: Transmit clock. GMII/MII: Transmit error. RGMII 1: Transmit control. GMII/MII: Transmit enable. RGMII 0: Transmit control. MII: Transmit clock for MII. GMII/MII: Collision detect. RGMII 1: Receive clock. Management data clock Management data I/O GMII: Transmit clock for GMII. RGMII 0: Transmit clock. GMII, RGMII: Reference clock. SMII: Reference clock. External request to reject a packet. I 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5 V CMOS 3.3 V tolerant 2.5V CMOS Rcvr 3.3 V tolerant 2.5V CMOS 1, 5 1, 5 1, 5 1 1 1 1 Description I/O Type Notes I I 1 1 O O O I I 1, 5 I I/O O O O I O I/O O 1 1 I I 1, 5 AMCC Proprietary 59 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 4 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Slave Peripheral Interface DMAAck0:3 DMAReq0 DMAReq1 DMAReq2:3 EOT0:3/TC0:3 PerAddr02:07 PerAddr08:31 Used by the PPC440EPx to indicate that data transfers have occurred. Used by slave peripherals to indicate they are prepared to transfer data. Used by slave peripherals to indicate they are prepared to transfer data. Used by slave peripherals to indicate they are prepared to transfer data. End Of Transfer/Terminal Count. Peripheral address bus used by the PPC440EPx when not in external master mode; otherwise, used by external master. Peripheral address bus used by the PPC440EPx when not in external master mode; otherwise, used by external master. Peripheral data bus used by the PPC440EPx when not in external master mode; otherwise, used by external master. Note: PerData00 is the most significant bit (msb) on this bus. Peripheral data bus parity used by the PPC440EPx when not in external master mode; otherwise, used by external master. Used by either the peripheral controller, DMA controller, or external master to indicates the last transfer of a memory access. External peripheral device select. External peripheral device select. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PPC440EPx is the bus master, it enables the selected device to drive the bus. Used by a peripheral slave to indicate it is ready to transfer data. Used by the PPC440EPx when not in external master mode, as output by either the peripheral controller or DMA controller depending upon the type of transfer involved. High indicates a read from memory, low indicates a write to memory. Otherwise, it is used by the external master as an input to indicate the direction of transfer. External peripheral data bus byte enables. External Error. Used as an input to record external slave peripheral errors. O I I I I/O I/O I/O 3.3V LVTTL 3.3 V LVTTL 3.3 V LVTTL 3.3 V LVTTL 3.3 V LVTTL 3.3V LVTTL 3.3V LVTTL 1 1 1, 5 1 1 1, 2 Description I/O Type Notes PerData00:31 I/O 3.3V LVTTL PerDataPar0:3 PerBLast PerCS0 PerCS1:5 PerOE PerReady I/O I/O O I/O O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 4 2 1, 2 1, 2 1 PerR/W I/O 3.3V LVTTL 1, 2 PerWBE0:3 PerErr I/O I 3.3V LVTTL 3.3V LVTTL 1, 2 1 60 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 5 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface BusReq ExtAck ExtReq Bus Request. Used when the PPC440EPx needs to regain control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440EPx to indicate that a data transfer occurred. External Request. Used by an external master to indicate it is prepared to transfer data. Peripheral Reset. Used by an external master and by synchronous peripheral slaves. Note: The state of signals or clocks cannot be guaranteed until the ExtReset signal has been de-asserted. Hold Acknowledge. Used by the PPC440EPx to transfer ownership of peripheral bus to an external master. Hold Request. Used by an external master to request ownership of the peripheral bus. Hold Primary. Used by an external master to indicate the priority of a given external master tenure. Peripheral Clock. Used by an external master and by synchronous peripheral slaves. O O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1 Description I/O Type Notes ExtReset O 3.3V LVTTL HoldAck HoldReq HoldPri PerClk O I I O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 1 UART Peripheral Interface The UART interface can be configured as follows: 1. One 8-pin, where n = 0 2. Two 4-pin, where n = 0 & 1 3. One 4-pin, where n = 0 and two 2-pin, where n = 1 & 2 4. Four 2-pin, where n = 0 & 1 & 2 & 3 UARTSerClk The SerClk input provides an alternative to the internally generated serial clock. It is used in cases where the allowable internally generated clock rates are not satisfactory. Receive data. Transmit data. Data Carrier Detect. Data Set Ready. Clear To Send. Data Terminal Ready. Request To Send. Ring Indicator. I 3.3V LVTTL 3.3V LVTTL Rcvr 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 6 1, 6 1, 6 1 1 1 1, 4 UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RTS UARTn_RI IIC Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData I O I I I O O I 1, 4 IIC0 Serial Clock. IIC0 Serial Data. IIC1 Serial Clock. IIC1 Serial Data. I/O I/O I/O I/O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1, 2 1, 2 1 AMCC Proprietary 61 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 6 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name USB UTMI Peripheral Interface USB2DI7:0 USB2DO7:0 USB2TxRdy USB2RxAct USB2RxDV USB2RxErr USB2LS0:1 USB2TxVal USB2Susp USB2XcvrSel USB2TermSel USB2OM0:1 USB2Clk USB PHY Peripheral Interface USB2Xcvr USB2Xcvr USB 2.0 differential transceiver. USB 2.0 external crystal (48 MHz) or external oscillator (48 MHz). External crystal: In/Out differential must not be less than 500 mV. External oscillator: Connect oscillator with signal swing of 3.3 V between USB2XtalOut and ground. See Table 19 on page 76. External resistor connection for bias current. Use 3.4 k, 1% resistor connected to GND. I/O 5 V tolerant Analog 5 Unidirectional data inputs. Unidirectional data outputs. Transmit data ready. Receive active. Receive valid. Receive error. Line state 0 and Line state 1. Transmit valid. Suspend. Transceiver select. Termination select. Operational mode. USB 2.0 Clock (60 MHz). I/O I/O I I I/O I/O I I/O I/O I/O I/O I/O I 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL w/pull-down 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1 1 1 1 1 1, 5 1 1 Description I/O Type Notes USB2XtalIn USB2XtalOut I/O Analog USB2RExt NAND Flash Interface NFALE NFCE0:3 NFCLE I/O Analog Address Latch Enable. Chip Enable (multiplexed with the PerCS0:3 signals). Command Latch Enable. Latches operational commands into the NAND Flash. Ready/Busy. Indicates status of device during program erase or page read. This signal is wire-OR connected from all NAND Flash devices. Read Enable. Data is latched on the rising edge. Write Enable. Data is latched on the rising edge. O O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL 1 1 1 NFRdyBusy I 3.3V LVTTL 1 NFREn NFWEn O O 3.3V LVTTL 3.3V LVTTL 1 1 62 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 7 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name Serial Peripheral Interface SCPClkOut SCPDI SCPDO Interrupts Interface IRQ0:4 IRQ5 IRQ6:9 JTAG Interface TCK TDI TDO TMS TRST Test Clock. Test Data In. Test Data Out. Test Mode Select. Test Reset. I I O I I 3.3 V LVTTL w/pull-up 3.3 V LVTTL w/pull-up 3.3V LVTTL 3.3 V LVTTL w/pull-up 3.3 V LVTTL w/pull-up 1 1, 5 1 1, 4 External interrupt requests 0 through 4. External interrupt request 5. External interrupt requests 6 through 9. I/O I I/O 3.3 V LVTTL 3.3 V LVTTL Rcvr 3.3 V LVTTL 1 1, 5 1 Clock output. Data input. Data output. I/O I/O O 3.3V LVTTL 3.3V LVTTL 3.3V LVTTL Description I/O Type Notes AMCC Proprietary 63 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 8 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name System Interface SysClk SysErr Main system clock input. Set to 1 when a machine check is generated. Main system reset. External logic can drive this bidirectional pin low (minimum of 16 cycles) to initiate a system reset. A system reset can also be initiated by software. Implemented as an opendrain output (two states; 0 or open circuit). Halt from external debugger. Processor timer external input clock. General purpose I/O. To access these functions, software must set DCR register bits. General purpose I/O. To access these functions, software must set DCR register bits. General purpose I/O. To access these functions, software must set DCR register bits. Test Enable. Note: Do not connect for normal operation. Receiver Inhibit. Active only when TestEn is active. Used for manufacturing test only. Mode Control. Active only when TestEn is active. Used for manufacturing test only. Leakage Test. Active only when TestEn is active. Used for manufacturing test only. Reference Enable. Active only when TestEn is active. Used for manufacturing test only. Driver Inhibit. Active only when TestEn is active. Used for manufacturing test only. Tie up as specified in Note 2 for normal operation. On-chip PNP thermal monitor transistor. A is the emitter and B is the base. The collector is grounded. Module characterization and screening. Use for test purposes only. Tie down as specified in Note 3 for normal operation. I O 3.3 V tolerant 2.5V CMOS 3.3 V tolerant 2.5V CMOS 3.3 V tolerant 2.5V CMOS 3.3V LVTTL Rcvr w/pull-up 3.3V LVTTL 3.3V LVTTL 3.3 V tolerant 2.5V CMOS 3.3 V tolerant 2.5V CMOS 3.3V LVTTL Rcvr w/pulldown 3.3V LVTTL 3.3 V tolerant 2.5V CMOS Rcvr 3.3V LVTTL w/pull-up 3.3V LVTTL 3.3 V LVTTL w/pull-up Thermal monitor Perf screen ring oscillator 1 1 1 Description I/O Type Notes SysReset I/O 1, 2 Halt TmrClk GPIO00:15 GPIO22:23 GPIO26:48 GPIO16:21 GPIO24:25 GPIO49:63 I I I/O I/O I/O 1 TestEn I RcvrInh I ModeCtrl LeakTest LeakTest2 RefEn I 1 I I 1 1 DrvrInh1:2 I 1 TherMonA:B PSROOut I O 5 1, 3 64 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 8. Signal Functional Description (Sheet 9 of 9) Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 3. Must pull down (recommended value is 1 k) 4. If not used, must pull up (recommended value is 3 k to OVDD (EOVDD for Ethernet) 5. If not used, must pull down (recommended value is 1 k) 6. Strapping input during reset; pull-up or pull-down required Signal Name Trace Interface TrcBS0:2 TrcClk TrcES0:4 TrcTS0:6 Power VDD OVDD EOVDD SOVDD GND AVDD AGND EAVDD EAGND U1AVDD U2AVDD U1AGND U2AGND +1.5 V--Logic voltage. +3.3 V-- I/O (except DDR2 SDRAM and Ethernet). +2.5 V-- I/O Ethernet. +1.8 V (DDR2) or +2.5 V (DDR1)-- I/O DDR SDRAM. Ground for logic and I/O voltage. +1.5 V--Filtered voltage for system PLLs (analog). Ground for system PLL voltage (analog). +1.5 V--Filtered voltage for Ethernet PLLs (analog). Ground for Ethernet PLL voltage (analog). +3.3 V--Filtered voltage for USB PLL (analog). Connect to OVDD. +3.3 V--Filtered voltage for USB PHY (analog). Connect to OVDD. Ground for USB PLL (analog) voltage. Connect to GND. Ground for USB PHY (analog) voltage. Connect to GND. n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a Trace branch execution status. Trace data capture clock, runs at 1/4 the frequency of the processor. Trace Execution Status is presented every fourth processor clock cycle. Additional information on trace execution and branch status. I/O O I/O I/O 3.3V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS 3.3 V tolerant 2.5V CMOS 3.3V tolerant 2.5V CMOS Description I/O Type Notes n/a n/a n/a n/a n/a n/a AMCC Proprietary 65 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Device Characteristics Table 9. Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings. Characteristic Internal logic supply voltage I/O supply voltage Ethernet I/O supply voltage DDR2 (DDR1) SDRAM I/O supply voltage System analog supply voltage Ethernet analog supply voltage USB PLL analog supply voltage USB PHY analog supply voltage Storage Temperature Range Case temperature under bias Notes: 1. If OVDD 0.4 V, it is required that VDD 0.4 V. Supply excursions not meeting this criteria must be limited to less than 25 ms duration during each power up or power down event. 2. This value is not a specification of the operational temperature range, it is a stress rating only. Symbol VDD OVDD EOVDD SOVDD AVDD EAVDD U1AVDD U2AVDD TSTG TC Value 0 to +1.65 0 to +3.6 0 to +2.7 0 to +1.94 (+2.7 V) 0 to +1.65 0 to +1.65 0 to +3.6 0 to +3.6 -55 to +150 -40 to +120 Unit V V V V V V V V C C 2 Notes 1 1 1 1 Table 10. Recommended DC Operating Conditions (Sheet 1 of 2) Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Logic Supply Voltage I/O Supply Voltage Ethernet I/O Supply Voltage DDR2 (DDR1) SDRAM I/O Supply Voltage System Analog Supply Voltages Ethernet Analog Voltage USB Analog Voltages DDR2 (DDR1) SDRAM Reference Voltage Symbol VDD OVDD EOVDD SOVDD AVDD EAVDD UnAVDD SVREF Minimum +1.425 +3.15 +2.4 +1.7 (+2.4) +1.425 +1.425 +3.15 +0.85 (+1.19) Typical +1.5 +3.3 +2.5 +1.8 (+2.5) +1.5 +1.5 +3.3 +0.9 (+1.25) Maximum +1.6 +3.45 +2.6 +1.9 (+2.6) +1.6 +1.6 +3.45 +0.95 (+1.31) Unit V V V V V V V V Notes 4 4 4 4 3, 4 3, 4 3, 4 2 66 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 10. Recommended DC Operating Conditions (Sheet 2 of 2) Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended conditions can affect device reliability. Parameter Input Logic High 3.3V PCI Input Logic High 3.3V LVTTL Input Logic High 2.5V CMOS, 3.3 V tolerant Input Logic High 1.8V DDR2 (2.5V DDR1) Input Logic Low 3.3V PCI Input Logic Low 3.3V LVTTL Input Logic Low 2.5V CMOS Input Logic Low 1.8V DDR2 (2.5V DDR1) Output Logic High 3.3V PCI Output Logic High 3.3V LVTTL VOH Output Logic High 2.5V CMOS Output Logic High 1.8V DDR2 (2.5V DDR1) Output Logic Low 3.3V PCI Output Logic Low 3.3V LVTTL VOL Output Logic Low 2.5V CMOS Output Logic Low 1.8V DDR2 (2.5V DDR1) Input Leakage Current (no pull-up or pull-down) Input Leakage Current for pull-down Input Leakage Current for pull-up Input Max Allowable Overshoot 3.3V LVTTL Input Max Allowable Undershoot 3.3V LVTTL Output Max Allowable Overshoot 3.3V LVTTL Output Max Allowable Undershoot 3.3V LVTTL Case Temperature Notes: 1. PCI drivers meet PCI specifications. 2. SVREF = SOVDD/2. SOVDD = +1.8 V for DDR2 memory or +2.5 V for DDR1 memory. 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440EPx. See "Absolute Maximum Ratings" on page 66. 4. Startup sequencing of the power supply voltages is not required. A power-down cycle must complete (OVDD and VDD are below +0.4 V) before a new power-up cycle is started 5. At IOH = IOL= 10 ma. 6. Case temperature, TC, is measured at top center of case surface with device soldered to a circuit board. IIL1 IIL2 IIL3 VIMAO VIMAU VOMAO VOMAU3 TC -0.6 -40 +100 -0.6 +3.9 0 0 0 0 (LPDL) -150 (LPDL) +0.4 +0.43 (+0.54) 0 200 (MPUL) 0 (MPUL) +3.9 V V 5 +2.0 +0.95 (+1.7) 0 +2.7 +1.95 (+2.7) 0.1OVDD +0.4 V V V V 5 1 VIL VIH Symbol Minimum 0.5OVDD +2.0 +1.7 SVREF + 0.125 (0.15) -0.5 0 0 -0.3 (-0.3) 0.9OVDD +2.4 Typical Maximum OVDD+0.5 +3.6 +3.6 2.2 (3.0) 0.35OVDD +0.8 +0.7 SVREF - 0.125 (0.15) +3.6 Unit V V V V V V V V V V 1 1 Notes 1 A A A V V V V C 6 AMCC Proprietary 67 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 11. Input Capacitance Parameter 2.5 V/1.8 V DDR 3.3 V LVTTL PCI 3.3 V tolerant CMOS USB Symbol CIN1 CIN2 CIN3 CIN5 CIN6 Maximum 2.9 2.1 2.5 2.4 3.0 Unit pF pF pF pF pF Notes Figure 4. Overshoot Waveform AC Overshoot (V) DC Overshoot (V) TCYC DC Undershoot (V) AC Undershoot (V) TOS TOS 68 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 12. Overshoot and Undershoot Receiver 3.3V LVTTL 2.5V (3.3V tolerant) DDR PCI AC Overshoot (V) 3.9 3.9 1.2*SOVDD 1.2*OVDD DC Overshoot (V) 3.6 3.6 SOVDD + 0.3 OVDD + 0.5 DC Undershoot (V) -0.16 -0.16 -0.3 -0.5 AC Undershoot (V) -0.6 -0.6 -0.6 -0.2*OVDD TOS 0.1*TCYC1 0.1*TCYC1 0.1/MemClkOut 0.1/PCIClk Notes: 1. TCYC is the period of the bus clock. 1/PerClk - EBC and NAND flash interfaces. 1/GMCRXClk - GMII and MII modes 1/SMIIRefClk - SMII mode 1/GMCGRXClk - RGMII mode 1/USB2Clk - UTMI 1/TrcClk - instruction trace interface 1/IIC0Clk and 1/IIC1Clk - IIC interfaces 1/SPIClkOut - SPI Power Sequencing Startup sequencing of the power supply voltages is not required. However, a power-down cycle must complete (OVDD and VDD are below +0.4 V) before a new power-up cycle is started. Analog Voltage Filter The analog voltages (AVdd, EAVdd, and UnAVdd) used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before the PPC440EPx. A Separate filter, as shown below, is recommended for each voltage. * The filter should keep the analog voltage to analog ground compression/expansion due to noise less than +50 mV. * Keep all wire lengths as short as possible. * Analog grounds must be brought out and connected to the digital ground plane at the filter capacitor. * The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies where noise is expected. VDD L AVDD, SAVDD, UnAVdd C AGND, SAGND, UnAGND GND L - SMT ferrite bead chip, Murata BLM21PG600SN1 AMCC Proprietary 69 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 13. Typical DC Power Supply Requirements Using DDR2 Memory Frequency (MHz) 400 533 667 +1.5 V Supply (VDD+AVDD+EAVDD) 1.61 1.82 2.16 +1.8 V Supply (SOVDD) 0.35 0.36 0.37 +2.5 V Supply (EOVDD) 0.28 0.28 0.28 +3.3 V Supply (OVDD+UAVDD) 0.2 0.2 0.2 Total 2.44 2.66 3.01 Unit W W W Notes 1 1 1 Notes: 1. Typical power is measured and is based on a nominal voltage of VDD = +1.5 V, TC = 100C, while running Linux and a test application that exercises each function with representative traffic. Table 14. Typical DC Power Supply Requirements Using DDR1 Memory Frequency (MHz) 400 533 667 +1.5 V Supply (VDD+AVDD+EAVDD) 1.69 1.88 2.20 +1.8 V Supply (SOVDD) na na na +2.5 V Supply (SOVDD + EOVDD) 1.33 1.35 1.37 +3.3 V Supply (OVDD+UAVDD) 0.2 0.2 0.2 Total 3.22 3.43 3.77 Unit W W W Notes 1 1 1 Notes: 1. Typical power is measured and is based on a nominal voltage of VDD = +1.5 V, TC = 100C, while running Linux and a test application that exercises each function with representative traffic. Table 15. VDD Supply Power Dissipation Frequency (MHz) 400 533 667 +1.425 V 1.49 1.64 1.94 +1.5 V 1.69 1.88 2.20 +1.6 V 2.00 2.21 2.78 Unit W W W Notes 1 1 1 Notes: 1. Power is measured and is based on VDD specified in the table and TC = 100C, while running Linux and a test application that exercises each function with representative traffic. 70 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 16. DC Power Supply Loads Parameter VDD (+1.5V) active operating current OVDD (+3.3 V) active operating current EOVDD (+2.5 V) active operating current SOVDD (+1.8 V) DDR2 active operating current 2 SOVDD (+2.5 V) DDR1 active operating current 2 AVDD (+1.5 V) input current 1 EAVDD (+1.5 V) active operating current UnAVDD (+3.3 V) active operating current Notes: 1. See "Absolute Maximum Ratings" on page 66 for filter recommendations. 2. SOVDD will be either +2.5 V or +1.8 V but not both. 3. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors including the type of applications running, clock rates, use of internal functional capabilities, external interface usage, case temperature, and the power supply voltages. Your specific application can produce significantly different results. VDD (logic) current and power are primarily dependent on the applications running and the use of internal chip functions (DMA, PCI, Ethernet, and so on). OVDD (I/O) current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. 4. Typical current is estimated at 667 MHz with VDD = +1.5 V, OVDD = +3.3 V, EOVDD = +2.5 V, SOVDD = +2.5 V (DDR1) or +1.8 V (DDR2), and TC = +100C with a typical process. 5. Maximum current is measured at 667 MHz with VDD = +1.6 V, OVDD = +3.45 V, EOVDD = +2.6 V, SOVDD = +2.6 V (DDR1) or +1.9 V (DDR2), and TC = +100C, and best-case process (which drives worst-case power). Symbol IDD IODD IEODD ISODD2 ISODD1 IADD IEADD IUADD Typical 4 1575 60 115 210 440 20 20 90 Maximum 5 3350 70 120 300 450 30 30 110 Unit mA mA mA mA mA mA mA mA 1 1 Notes AMCC Proprietary 71 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 17. Package Thermal Specifications Thermal resistance values for the TE-PBGA package in a convection environment at 6.3 W are as follows: Airflow ft/min (m/sec) 0 (0) Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink 100 (0.51) 11.7 8.2 200 (1.02) 10.9 7.2 300 (1.53 10.5 6.8 400 (2.04) 10.3 6.6 500 (2.55) 10 6.3 C/W C/W 5 5, 6 Parameter Symbol Unit Notes JA JA 13.1 11.1 Resistance Value Junction-to-case thermal resistance Junction-to-board thermal resistance Notes: 1. Case temperature, TC, is measured at top center of case surface with device soldered to circuit board. 2. TA = TC - Px CA, where TA is ambient temperature and P is power consumption. JC JB 3.5 7.3 C/W C/W 5 5 3. TC Max = TJ Max - PxJC, where TJ Max is maximum junction temperature (+125C) and P is power consumption. 4. The preceding equations assume that the chip is mounted on a board with at least one signal and two power planes. 5. Values in the table were achieved using a JEDEC standard board with the following characteristics: 114.5 mm x 101.6 mm x 1.6 mm, 4 layers. The board has 100 thermal vias (same as the number of thermal balls on the TE-PBGA package). 6. Values for an attached heat sink were achieved with a 35 mm x 35 mm x 15 mm unit (see Thermal Management below), attached with a 0.1 mm thickness of adhesive having a thermal conductivity of 1.3 W/mK. Thermal Management The following heat sink was used in the above thermal analysis: ALPHA LPD35-15B (35 mm x 35 mm x15 mm) The heat sink is manufactured by: Alpha Novatech, Inc. (www.alphanovatech.com) 473 Sapena Court, #12 Santa Clara, CA 95054 Phone: 408-567-8082 72 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Thermal Monitor Thermal monitoring of the chip is accomplished using the PNP transistor ( 2) provided on the chip. The collector of the transistor is connected to ground (GND). The emitter (TherMonA) and base (TherMonB) are connected to chip pins. A voltage measurement (VBE1 and VBE2) across the TherMonA and TherMonB pins at the two current values I1 and I2 provides the chip temperature in K according to the equation: T = (q/nk)(VBE2-VBE1)/ln(I2/I1) K where q = 1.602 176 53x10-19, n = 1.0 0.015, and k = 1.380 6505x10-23. Note: VBE2 and VBE1 should be specified in Volts. I1 and I2 can be any units of measure provided they are the same. The small values require precision measurement and current sources. The calculated on chip (ball to ball) series resistance for the PPC440EPx thermal monitor circuit is 2.0 ohms. The thermal sensor reflects the PPC440EPx junction temperature. PPC440EPx C B TherMonB Note: The bias voltage VEB should be between +0.5V and +0.7V. E TherMonA I1, I2 (Max = 300A) VBE1, VBE2 Test Conditions Clock timing and switching characteristics are specified in accordance with operating conditions shown in Table 10 on page 66. AC specifications are characterized with VDD = +1.5 V, TC = +85 C and a 50 pF test load as shown in the figure to the right. Output Pin 50pF Table 18. Clocking Specifications Symbol SysClk Input FC TC TCS TCH TCL Frequency Period Edge stability (cycle-tocycle jitter) High time Low time 33.33 15 - 40% of nominal period 40% of nominal period 66.66 30 0.15 60% of nominal period 60% of nominal period MHz ns ns ns ns Parameter Min Max Units Notes Note: Input slew rate 1 V/ns PLL VCO FC TC Frequency Period 600 0.750 1333.33 1.66 MHz ns Processor (CPU) Clock FC AMCC Proprietary Frequency 333.33 666.66 MHz 1 73 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 18. Clocking Specifications (continued) Symbol TC Period Parameter Min 1.5 Max 3 Units ns Notes MemClkOut and PLB Clock FC TC TCH MAL Clock FC TC Frequency Period 45 12 83.33 22.2 MHz ns Frequency Period High time 133.33 6 45% of nominal period 166.66 7.5 55% of nominal period MHz ns ns Figure 5. Timing Waveform 1.7V (2.0V) 0.7V (0.8V) TCH TC Note: TCL SysClk and GMCRefClk are 2.5V (3.3V tolerant). Slew rate should be measured between 0.7V and 1.7V. 74 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440EPx. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC440EPx the following conditions must be met: * The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC440EPx with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency. * The maximum frequency deviation cannot exceed -3%, and the modulation frequency cannot exceed 40 kHz. In some cases, on-board PPC440EPx peripherals impose more stringent requirements. * Use the Peripheral Bus Clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. * Use the DDR SDRAM MemClkOut since it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Important: It is up to the system designer to ensure that any SSCG used with the PPC440EPx meets the above requirements and does not adversely affect other aspects of the system. AMCC Proprietary 75 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet I/O Specifications Table 19. Peripheral Interface Clock Timings (Sheet 1 of 3) Parameter PCIClk frequency (asynchronous mode) PCIClk period (asynchronous mode) PCIClk high time PCIClk low time GMCMDClk frequency GMCMDClk period GMCMDClk high time GMCMDClk low time GMCTxClk frequency MII GMCTxClk period MII GMCTxClk high time GMCTxClk low time GMCRxClk frequency MII GMCRxClk period MII GMCRxClk high time GMCRxClk low time GMCRefClk frequency GMCRefClk period GMCRefClk high time GMCRefClk low time GMCRefClk Edge Stability (cycle-to-cycle jitter) GMCRefClk Slew Rate Min - 15 40% of nominal period 40% of nominal period - 400 160 160 2.5 40 35% of nominal period 35% of nominal period 2.5 40 35% of nominal period 35% of nominal period - 8 40% of nominal period 40% of nominal period - 2 Max 66.66 - 60% of nominal period 60% of nominal period 2.5 - - - 25 400 - - 25 400 - - 125 - 60% of nominal period 60% of nominal period +0.15 - Units MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz ns ns ns MHz MHz ns ns ns V/ns 2 2 2 2 Notes 76 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 19. Peripheral Interface Clock Timings (Sheet 2 of 3) Parameter PerClk (and OPB Clock) frequency (for ext. master or sync. slaves) PerClk period PerClk high time PerClk low time UARTSerClk frequency UARTSerClk period UARTSerClk high time UARTSerClk low time USB2Clk frequency USB2Clk period USB2XtalIn/USB2XtalOut frequency USB2XtalIn/USB2XtalOut period USB2XtalIn/USB2XtalOut high time USB2XtalIn/USB2XtalOut low time Min 33.33MHz 12 50% of nominal period 33% of nominal period - 2TOPB1+2 TOPB1+1 TOPB1+1 60 16.66 12 20.8 40% of nominal period 40% of nominal period Max 83.33 30 66% of nominal period 50% of nominal period 1000 / (2TOPB1+2ns) - - - 60 16.66 48 83.33 60% of nominal period 60% of nominal period Units MHz ns ns ns MHz ns ns ns MHz ns MHz ns ns ns 1 1 1 1 3 3 3 3 Notes AMCC Proprietary 77 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 19. Peripheral Interface Clock Timings (Sheet 3 of 3) Parameter TmrClk frequency TmrClk period TmrClk high time TmrClk low time Notes: 1. TOPB is the period in ns of the OPB clock. The internal OPB clock runs at 1/2 the frequency of the PLB clock. The maximum OPB clock frequency is 83 MHz. 2. An internal PLL improves this duty cycle to a worst case of 48% minimum, 52% maximum. 3. Crystals, external clocks, or external oscillators must have a maximum tolerance of 100 ppm and maximum jitter of 100 ps.Only a frequencies of 48 MHz is allowed for oscillators; only a frequencies of 48 MHz is allowed for crystals. Crystals and oscillators should be connected as shown below: Min - 10 40% of nominal period 40% of nominal period Max 100 - 60% of nominal period 60% of nominal period Units MHz ns ns ns Notes PPC440EPx USB2XtalIn Crystal C USB2XtalOUT PPC440EPx USB2XtalIn Osc USB2XtalOut C Crystal - Frequency: 48MHz Resonance mode: parallel CO: 15-30pF ESR: 20-60 Drive level: 50-500W C = 2(CL - CStray) where CL is the load capacitance required by the crystal for oscillation CStray is the board parasitic capacitance 78 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Figure 6. Input Setup and Hold Waveform Clock 1.25V(1.5V) TIS min Inputs Valid TIH min Figure 7. Output Delay and Float Timing Waveform Clock 1.25V(1.5V) TOV max Outputs TOH min TOV max TOH min TOV max TOH min High (Drive) Float (High-Z) Low (Drive) Valid Valid AMCC Proprietary 79 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Figure 8. Input Setup and Hold Waveform for RGMII Signals GMCnRxClk 1.25V TIS min Inputs Valid Valid TIH min TIS min TIH min RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnRxClk. RGMII 10/100Mb timing is with reference only to the raising edge of GMCnRxClk. Figure 9. Output Delay and Hold Timing Waveform for RGMII Signals GMCnTxClk 1.25V TOH min Outputs High (Drive) Float (High-Z) Low (Drive) Valid Valid Valid TOV max TOV max TOH min Valid RGMII 1000Mb timing is with reference to the raising and falling edge of GMCnTxClk. RGMII 10/100Mb timing is with reference only to the raising edge of GMCnTxClk. 80 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 20. I/O Specifications--All Speeds (Sheet 1 of 3) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal PCI Interface PCIAD31:00 PCIC3:0/BE3:0 PCIClk PCIDevSel PCIFrame PCIGnt0:5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0:5 PCIReset PCISErr PCIStop PCITRDY Ethernet MII Interface GMCCD GMCCrS GMCMDClk GMCMDIO GMCRxClk GMCRxD0:3 GMCTxD0:3 GMCRxDV GMCRxEr GMCTxClk GMCTxEr GMCTxEn Ethernet GMII Interface GMCCD GMCCrS GMCGTxClk GMCMDClk GMCMDIO GMCRefClk GMCRxClk GMCRxD0:3 GMCTxD0:3 GMCRxDV GMCRxEr GMCTxEr GMCTxEn 2 n/a 2 2 n/a n/a 0 n/a 0 0 n/a n/a n/a 2.5 n/a n/a 2.5 2.5 n/a 1 n/a n/a 1 1 10 10 10 1.5 n/a n/a n/a n/a n/a n/a n/a n/a 5.1 5.1 5.1 5.1 5.1 n/a 5.1 5.1 5.1 5.1 5.1 5.1 5.1 6.8 6.8 6.8 6.8 6.8 n/a 6.8 6.8 6.8 6.8 6.8 6.8 6.8 GMCRxClk GMCGTxClk GMCRxClk GMCRxClk GMCGTxClk GMCGTxClk GMCMDClk async async n/a n/a n/a n/a 10 10 1 1 10 n/a 10 10 10 n/a 10 10 n/a 10 n/a n/a n/a 1 n/a n/a 10 10 10 1.5 n/a n/a n/a n/a n/a n/a n/a n/a 5.1 5.1 5.1 5.1 n/a 5.1 5.1 5.1 5.1 n/a 5.1 5.1 6.8 6.8 6.8 6.8 n/a 6.8 6.8 6.8 6.8 n/a 6.8 6.8 GMCTxClk GMCTxClk GMCRxClk GMCTxClk GMCRxClk GMCRxClk GMCMDClk async async 5 5 n/a 5 n/a 5 5 5 5 n/a 5 5 5 0 0 n/a 0 n/a 0 0 0 0 n/a 0 0 0 6 6 6 n/a n/a 6 6 6 n/a n/a 6 6 6 2 2 2 n/a n/a 2 2 2 n/a n/a 2 2 2 3 3 0 0 6 6 2 2 0.5 0.5 n/a 0.5 0.5 0.5 n/a 0.5 0.5 0.5 0.5 n/a n/a 0.5 0.5 0.5 1.5 1.5 n/a 1.5 1.5 1.5 n/a 1.5 1.5 1.5 1.5 n/a n/a 1.5 1.5 1.5 PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk PCIClk async PCIClk PCIClk PCIClk PCIClk async PCIClk PCIClk async Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (minimum) I/O L (minimum) Clock Notes AMCC Proprietary 81 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 20. I/O Specifications--All Speeds (Sheet 2 of 3) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal Setup Time (TIS min) Hold Time (TIH min) Output (ns) Valid Delay (TOV max) Hold Time (TOH min) Output Current (mA) I/O H (minimum) n/a 5.1 1 1 n/a n/a 1 1 n/a n/a n/a n/a 0.5 0.5 n/a n/a 3.5 3.5 5.1 5.1 5.1 5.1 n/a 5.1 1 1 n/a n/a 1 1 n/a n/a n/a n/a 0.5 0.5 n/a n/a 3.5 3.5 5.1 5.1 5.1 5.1 n/a n/a n/a 1.5 1.5 n/a n/a n/a 1 1 n/a n/a 3 n/a n/a 3 3 1 n/a n/a 1 1 5.1 5.1 5.1 5.1 5.1 27.7 n/a n/a 5 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 4 n/a 4 n/a 4 n/a n/a n/a n/a 1.5 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0 n/a 0 n/a 0 n/a n/a 5 5 n/a 6 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 4 n/a 4 n/a 4 4 0 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 1 n/a 1 n/a 1 1 0 0 27.7 27.7 27.7 27.7 27.7 15.3 n/a n/a 19.1 n/a n/a n/a 19.1 n/a 19.1 19.1 USB 2.0 USB 2.0 14.6 14.6 n/a 19.1 n/a n/a 19.1 I/O L (minimum) n/a 6.8 6.8 6.8 6.8 6.8 n/a 6.8 6.8 6.8 6.8 6.8 n/a n/a 6.8 6.8 6.8 6.8 6.8 12.8 12.8 12.8 12.8 12.8 12.8 10.2 n/a n/a 8.7 n/a n/a n/a 8.7 n/a 8.7 8.7 USB 2.0 USB 2.0 6.6 6.6 n/a 8.7 n/a n/a 8.7 SMIIRefClk SMIIRefClk SMIIRefClk SMIIRefClk SMIIRefClk GMC1RxClk GMC1RxClk GMC1TxClk GMC1TxClk GMC0RxClk GMC0RxClk GMC0TxClk GMC0TxClk Clock Notes Ethernet RGMII Interface GMC0RxClk GMC0TxClk GMC0RxD0:3 GMC0RxCtl GMC0TxD0:3 GMC0TxCtl GMC1RxClk GMC1TxClk GMC1RxD0:3 GMC1RxCtl GMC1TxD0:3 GMC1TxCtl GMCRefClk Ethernet SMII Interface SMIIRefClk SMIISync SMII0RxD SMII1RxD SMII0TxD SMII1TxD Internal Peripheral Interface IIC0SClk IIC0SData IIC1SClk IIC1SData SCPClkOut SCPDI SCPDO UARTSerClk UARTn_Rx UARTn_Tx UARTn_DCD UARTn_DSR UARTn_CTS UARTn_DTR UARTn_RI UARTn_RTS USB2Clk USB2Xcvr USB2Xcvr USB2DI0:7 USB2DO0:7 USB2LS0:1 USB2OM0:1 USB2RxAct USB2RxDV USB2RxErr 82 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 20. I/O Specifications--All Speeds (Sheet 3 of 3) Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. Input (ns) Signal USB2Susp USB2TermSel USB2TxRdy USB2TxVal USB2XcvrSel Interrupts Interface IRQ0:9 JTAG Interface TCK TDI TDO TMS TRST System Interface SysClk TmrClk SysReset Halt SysErr TestEn DrvrInh1:2 RcvrInh GPIO00:11 GPIO12:25 GPIO26:48 GPIO49:63 Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 5.1 5.1 5.1 5.1 6.8 6.8 6.8 6.8 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 5.1 n/a n/a n/a 19.1 5.1 14.6 5.1 n/a n/a n/a n/a 6.8 n/a n/a n/a 8.7 6.8 6.6 6.8 async async async async async n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a async async async async async n/a n/a n/a n/a n/a n/a Setup Time (TIS min) n/a n/a 4 n/a n/a Hold Time (TIH min) n/a n/a 0 n/a n/a Output (ns) Valid Delay (TOV max) 4 4 n/a 4 4 Hold Time (TOH min) 1 1 n/a 1 1 Output Current (mA) I/O H (minimum) 19.1 19.1 n/a 19.1 19.1 I/O L (minimum) 8.7 8.7 n/a 8.7 8.7 Clock Notes AMCC Proprietary 83 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Table 21. I/O Specifications--400 MHz to 667 MHz Notes: 1. PerClk rising edge at package pin with a 10 pF load trails the internal PLB clock by approximately 1.3 ns. Input (ns) Signal Setup Time (TIS min) n/a 4 4 4 4 n/a 4 4 n/a 4 4 4 n/a n/a 4 n/a n/a 4 4 4 n/a n/a n/a 4 n/a n/a Hold Time (TIH min) n/a 1 1 1 1 n/a 1 1 n/a 1 1 1 n/a n/a 1 n/a n/a 1 1 1 n/a n/a n/a 1 n/a n/a Output (ns) Valid Delay (TOV max) 6 n/a 6 6 6 6 6 6 6 n/a 6 6 6 6 n/a 6 6 n/a n/a n/a 6 6 6 n/a 6 6 Hold Time (TOH min) 1 n/a 1 1 1 1 1 1 1 n/a 1 1 1 1 n/a 1 1 n/a n/a n/a 1 1 1 n/a 1 1 Output Current (mA) I/O H (minimum) 19.1 n/a 19.1 19.1 19.1 19.1 19.1 14.6 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 19.1 n/a n/a 19.1 n/a 19.1 19.1 19.1 n/a 19.1 19.1 I/O L (minimum) 8.7 n/a 8.7 8.7 8.7 8.7 8.7 6.6 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 8.7 n/a n/a 8.7 n/a 8.7 8.7 8.7 n/a 8.7 8.7 PLB Clk PerClk PerClk PerClk PerClk PerClk PerClk PerClk 1 Clock Notes External Slave Peripheral Interface DMAAck0:3 DMAReq0:3 EOT0:3/TC0:3 PerAddr02:31 PerBLast PerCS0:5 PerData00:15 PerData16:31 PerOE PerReady PerR/W PerWBE0:1 BusReq ExtAck ExtReq ExtReset HoldAck HoldReq HoldPri PerClk PerErr NAND Flash Interface NFALE NFCE0:3 NFCLE NFRdyBusy NFREn NFWEn PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk PerClk External Master Peripheral Interface 84 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet DDR2/1 SDRAM I/O Specifications The DDR2/1 SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However, MemClkOut is the same frequency as the PLB clock signal and is in phase with the PLB clock signal. The phase skew between MemClkOut and the PLB clock is affected by the loading on MemClkOut. Read capture logic in the DDR controller captures read data using a delayed version of DQS and internally resynchronizes the data to the PLB clock.The PPC440EPx contains three independently programmable digital delay lines (DLLs) that control the timing of the indicated signals in read and write operations: 1. DQS (with respect to MemClkOut) for write operations. 2. MemData, ECC, and DM (with respect to MemClkOut) for write operations. 3. DQS (with respect to inbound MemData) for read operations. There is also a master delay line for calibration. Programming details can be found in the PPC440EPx Embedded Processor Users Manual. The signals are terminated as indicated in Figure 10 for the DDR timing data in the following sections. The PPC440EPx uses a clock forwarding scheme in which it drives the clock to the memory devices. Data signals are divided into eight subgroups--one for each byte lane (see Table 26 on page 89)-- plus a ninth subgroup for the ECC byte lane. These signals include MemData00:63, DQS0:8, DM0:8, and ECC0:7 signals. Signals within a data subgroup (byte lane) should be routed together. Command Bus Operation The command bus (MemAddr, RAS, CAS, WE, BA, ClkEn, BankSel, MemODT) is driven 180 out-of-phase with MemClkOut, and has no corresponding delay line. Therefore, board designers must consider two different types of systems: 1) registered DIMMs and 2) unbuffered DIMMs. The system clocking design must also be considered. To avoid crosstalk, the command bus signals and the data signals should not be routed together. Board Layout Restrictions The paths (traces) for the data and the associated data strobe signal should be routed with the same length between the PPC440EPx and the SDRAM devices, allowing the rising and falling edges of the strobe to arrive at the capture logic at the same time the data is in transition. All of the following timing assumes a trace velocity of 167 ps/in. Board designs must meet the following criteria: * Skew on the signals in any byte lane should not exceed 50 ps (0.3 in). * Data subgroup trace lengths must be no more than 5 in. (800 ps) and have a difference of no more than 2.5 in. (400 ps). * Byte lane subgroup trace length must be no less than 1.25 in. (209 ps). For example, traces that average 3.00 in. in length and 167 ps/in., and meet the maximum 50 ps skew requirement, would have a maximum length difference of 0.3 in. So, they would be between 2.85 in. and 3.15 in. in length. If the above timing recommendations are followed, the package wire bond lengths can be ignored. Clocking Clocking skew to all DRAMs must be minimized. The maximum allowed is considered to be 10 ps. Because of the stringent requirements on DDR device clock inputs, it is expected that board designers will use some type of external PLL suitable to redrive the clock to the DDR SDRAMs. In such a system, the PLL acts like a zero-delay AMCC Proprietary 85 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet insertion buffer. When using unbuffered DIMMS, the loading on the address bus will be considerably greater than the clock (up to 18 loads for double-sided DIMMs). In this case, it is strongly suggested that a delay of 500 ps in the clock path so that the Address/Command setup time at the DIMMs can be met. This delay is sufficient to meet the setup time, without having to change the programmable delay (internal to the PPC440EPx) between the DQS/DQ/DM and the clock (assuming nominal settings as specified in the PPC440EPx Users Manual). While the clock is now 500 ps later than the nominal DQS arrival time, this still falls well within the window allowed by the JEDEC spec for TDQSS ( 0.25 cycle, or 1.5 ns at 166 MHz). In the case where it is not possible to anticipate which kind of DIMMs may be employed in a system, it is always safe to use this 500 ps clock delay, since registered DIMMs (the least heavily loaded) will have more than enough margin (almost 1/2 cycle) to accommodate the slight decrease in address hold time. Termination Model Figure 10. DDR SDRAM Simulation Signal Termination Model MemClkOut 10pF 120 10pF MemClkOut VTT = SOVDD/2 PPC440EPx 50 Addr/Ctrl (DDR2) Addr/Ctrl/Data/DQS/DM (DDR1) 30pF Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data. It is not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout. DDR2 SDRAM On-Die Termination Impedance Setting For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations. 86 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 22. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:63 ECC0:7 DM0:8 MemClkOut MemAddr00:13 BA0:2 RAS CAS WE BankSel0:1 ClkEn DQS0:8 MemODT0:1 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Output Current (mA) I/O H (maximum) I/O L (maximum) DDR SDRAM Write Operation The rising edge of MemClkOut aligns with the first rising edge of the DQS signal on writes. The following data is generated by means of simulation and includes logic, driver, package RLC, and lengths. Values are calculated over best case and worst case processes with speed, junction temperature, and voltage as follows: Table 23. DDR SDRAM Write Operation Conditions Case Best Worst Process Speed Fast Slow Junction Temperature (C) -40 +125 Voltage (V) +1.6 +1.425 Note: In the following tables and timing diagrams, minimum values are measured under best case conditions and maximum values are measured under worst case conditions. The timing numbers in the following sections are obtained using a simulation that assumes a model as shown in Figure 10. The following diagram illustrates the relationship among the signals involved with a DDR write operation. AMCC Proprietary 87 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Figure 11. DDR SDRAM Write Cycle Timing PLB Clk MemClkOut TSA Addr/Cmd TSK THA TDS TDS DQS TSD MemData THD TSD THD TSK = Delay from falling edge of MemClkOut to rising/falling edge of signal (skew) TSA = Setup time for address and command THA = Hold time for address and command signals from MemClkOut TSD = Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ) THD = Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ) TDS = Delay from rising/falling edge of clock to the rising/falling edge of DQS Note: The timing data in the following tables is based on simulation runs using Einstimer. Table 24. I/O Timing--DDR SDRAM TDS Notes: 1. All of the DQS signals are referenced to MemClkOut with the DQS delay line programmed to 1 cycle. 2. Clock speed is 166 MHz. Signal Name DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 TDS (ns) Minimum -0.030 -0.030 -0.050 -0.110 -0.140 -0.120 -0.060 -0.010 -0.140 Maximum +0.650 +0.620 +0.580 +0.480 +0.410 +0.480 +0.580 +0.690 +0.420 88 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Table 25. I/O Timing--DDR SDRAM TSK, TSA, and THA Notes: 1. Clock speed is 166 MHz. TSK is referenced to MemClkOut falling edge. TSA and THA are referenced to MemClkOut rising edge. 2. The timing in this table assumes a single registered DIMM load on the outputs. To adjust the timing for unbuffered DIMMs, use the following values by subtracting them from TSA and adding them to TSK and THA: 5 loads adjust by 0.41 ns 9 loads adjust by 1.12 ns 18 loads adjust by 2.12 ns 3. To obtain adjusted TSA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and subtract TSK maximum (0.5TCYC - TSKmax). 4. To obtain adjusted THA values for lower clock frequencies, use 1/2 of the cycle time for the lower clock frequency and add TSK minimum (0.5TCYC + TSKmin). Signal Name MemAddr00:13 BA0:2 BankSel0:1 ClkEn CAS RAS WE -0.960 -0.270 3.27 2.04 TSK (ns) Minimum Maximum TSA (ns) Minimum THA (ns) Minimum Table 26. I/O Timing--DDR SDRAM TSD and THD Notes: 1. TSD and THD are measured under worst case conditions. 2. Clock speed for the values in the table is 166 MHz. 3. The time values in the table include 1/4 of a cycle at 166 MHz (6 ns x 0.25 = 1.5 ns). 4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.5 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (for example, TSD - 1.5 + 0.25TCYC). Signal Names MemData00:07, DM0 MemData08:15, DM1 MemData16:23, DM2 MemData24:31, DM3 MemData32:39, DM4 MemData40:47, DM5 MemData48:55, DM6 MemData56:63, DM7 ECC0:7, DM8 Reference Signal DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8 TSD (ns) 1.37 1.41 1.40 1.41 1.45 1.40 1.46 1.45 1.46 THD (ns) 1.23 1.18 1.17 1.20 1.18 1.18 1.17 1.10 1.18 DDR SDRAM Read Operation The read data capture logic is responsible for capturing the data outputs from the SDRAM devices and passing the data back to the system clock domain. The data strobe signal (DQS) signals used to capture data are delayed to ensure that the rising and falling edges of these strobes are in the middle of the valid window of data. DDR devices send a DQS coincident with the read data so that the data can be reliably captured by the PPC440EPx. The edges of these strobe signals are aligned with the data output by the SDRAM devices. In order to reliably latch the data into a synchronizing FIFO, the PPC440EPx produces an internal, delayed version of DQS. The amount of delay is user programmable. In the example shown in Figure 12, the delay is set to approximately 25% of the system clock. A delay compensation circuit in the PPC440EPx keeps this delay AMCC Proprietary 89 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet constant. Figure 12. DDR SDRAM DQS Read Timing MemClkOut DQS MemData Delayed DQS (data strobe) DQS delay 90 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Initialization The PPC440EPx provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see "Serial EEPROM" below). Some of the default values can be altered by strapping on external pins (see "Strapping" below). Strapping While the SysReset input pin is low (system reset), the state of certain I/O pins is read to enable certain default initial conditions prior to PPC440EPx start-up. The actual capture instant is the nearest reference clock edge before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. These pins are used for strap functions only during reset. Following reset they are used for normal functions. The signal names assigned to the pins for normal operation are shown in parentheses following the pin number. Note: When UART0_DCD, UART0_DSR and UART0_CTS are used functionally, the pin straps should be isolated from the UART transceiver during reset as the transceiver may overdrive the pin straps and cause the PPC440EPx to read incorrect straps. The following table lists the strapping pins along with their functions and strapping options: Table 27. Strapping Pin Assignments Pin Strapping Function Option C28 (UART0_DCD) 0 0 0 0 1 1 1 1 C29 (UART0_DSR) 0 0 1 1 0 1 0 1 A29 (UART0_CTS) 0 1 0 1 0 0 1 1 Serial device is disabled. Each of the six options (A- F) is a combination of boot source, boot-source width, and clock frequency specifications. Refer to the IIC Bootstrap Controller chapter in the PPC440EPx Embedded Processor User's Manual for details. A B C D E F Serial device is enabled. The option being selected is the IIC0 slave address that will respond with strapping data. G (0xA8) H (0xA4) Serial EEPROM During reset, initial conditions other than those obtained from the strapping pins can be read from a ROM device connected to the IIC0 port. At the de-assertion of reset, if the bootstrap controller is enabled, the PPC440EPx sequentially reads 16 B from the ROM device on the IIC0 port and sets the SDR0_SDSTP0, SDR0_SDSTP1, SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly. The initialization settings and their default values are covered in detail in the PowerPC 440EPx User's Manual. AMCC Proprietary 91 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Revision Log Date 06/01/2005 06/03/2005 07/06/2005 08/29/2005 09/12/2005 10/03/2005 10/05/2005 Version Initial creation of document. Add "Preliminary--Subject to Change" watermark. Change maximum NAND Flash to 256 MB. Update with signal-to-pin assignment and I/O circuit type specifications. Replace existing DDR SDRAM information with new DDR2 SDRAM information. Implement updates from the 09/12 review. Misc. updates. Correct MemClkOut duty cycle. Correct description and move PerErr signal from master to slave. Change maximum VCO frequency to 1334 MHz. Update corporate address and copyright date Update available Ethernet interface configurations (no RMII). Add four peripheral data parity signals. Change multiplexing of six GPIO signals. Update DDR2 SDRAM data. Adjust all other I/O timing. Misc. updates. Remove Confidential status. Correct OPB bridge information. Misc. updates. Correct security function designation. Add new power and current values. Misc. updates. Remove data for 333 MHz CPU speed. Change all GPIOxx signals from alternate to primary. Change UART designations to eliminate letter designations B, C, D. Misc. updates. Correct list containing balls by ball number. Update power and temperature data. Add clocking information. Update EEPROM. Memory address corrections. Change and delete incorrect MemClkEn references. Correct enable/disable specifications for PCI Gnt/Req signals. Change USB2Rext pull-down from 2.4k to 3.4k Change analog voltage filter circuit inductor part number. Switch multiplex defaults for PerData16:31 from the USB signals to the PerData signals. Correct I/O designation for some Ethernet signals. Add thermal monitor information. Provide corrected and additional information on USB crystal/oscillator inputs. Remove leaded PNs. Contents of Modification 11/14/2005 1.07 03/01/2006 1.08 03/15/2006 1.09 04/05/2006 1.10 04/24/2006 1.11 05/12/2006 1.12 05/15/2006 1.13 05/30/2006 1.14 07/12/2006 07/19/2006 1.15 1.16 11/02/2006 1.17 92 AMCC Proprietary Revision 1.26 - October 15, 2007 440EPx - PPC440EPx Embedded Processor Preliminary Data Sheet Date Version Contents of Modification Indicate that two USB analog voltages are needed with separate filters. Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals. Add information concerning address bus loading on DDR SDRAMs. Additions to information on USB crystal/oscillator inputs. Restore leaded PNs. Update DDR2/1 SDRAM timing and board design data. Update power data. Change VIL. Change Typical Power on first page. Change VIL back to what it was. Update package drawing with another view. 04/23/2007 07/18/2007 08/06/2007 1.22 1.23 1.24 Remove all valid USB oscillator and crystal frequencies except 48 MHz. Added more information to the Thermal Monitor section. Changes to Figure 3. Added Assembly Recommendations, added Tables 3 and 4. Added recommendations for Unused I/O. Updated signal description in table 7 for signals SPCClkOUT, SCPDI, SCPDO, LeakTest and LeakTest2. Updated Table 19 to include reference clocks. Removed all references to TBI and RTBI as these modes are not supported due to errata: Chip_4 and Chip_5. Added voltage reference to Figures 4, 5, and 6 Corrected I/O comments for UART and Ethernet signals in Table 6. Removed Note 2 from Table 7 and added section on Analog Voltage Filter Added Figure and Table for Overshoot and Undershoot. Added section on Power Sequencing. Added slew rate and jitter requirements for GMCRefClk in Table 20. Added note in Strapping section Changed GPIO26[IIC0SData] to [GPIO26]IIC0SData. Added figures showing setup, hold, output valid and output hold timing for RGMII signals. Corrected telephone numbers on the last page. Corrected RGMII timing relative to GMCnTXClk in table 21. Added pull up recommendations to Table 9 for PCI signals. 12/28/2006 1.18 01/10/2007 02/01/2007 1.19 1.20 03/12/2007 1.21 08/24/2007 1.25 10/15/2007 1.26 AMCC Proprietary 93 440EPx - PPC440EPx Embedded Processor Revision 1.26 - October 15, 2007 Preliminary Data Sheet Applied Micro Circuits Corporation 215 Moffett Park Drive, Sunnyvale, CA 94089 Phone: (408) 542-8600 -- (800) 840-6055 -- Fax: (408) 542-8601 http://www.amcc.com AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and warrants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC's Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright (c) 2007 Applied Micro Circuits Corporation. All Rights Reserved. 94 AMCC Proprietary |
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