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NTMD4820N Power MOSFET
Features
30 V, 8 A, Dual N-Channel, SOIC-8
* * * *
Low RDS(on) to Minimize Conduction Losses Low Capacitance to Minimize Driver Losses Optimized Gate Charge to Minimize Switching Losses Dual SOIC-8 Surface Mount Package Saves Board Space
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V(BR)DSS 30 V 27 mW @ 4.5 V RDS(on) Max 20 mW @ 10 V 8A
ID Max
Applications
* Disk Drives * DC-DC Converters * Printers
MAXIMUM RATINGS (TJ = 25C unless otherwise stated)
Rating Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current RqJA (Note 1) Power Dissipation RqJA (Note 1) Continuous Drain Current RqJA (Note 2) Power Dissipation RqJA (Note 2) Continuous Drain Current RqJA t < 10 s (Note 1) Power Dissipation RqJA t < 10 s (Note 1) Pulsed Drain Current TA = 25C TA = 70C TA = 25C TA = 25C Steady State TA = 70C TA = 25C TA = 25C TA = 70C TA = 25C TA = 25C, tp = 10 ms PD IDM TJ, TSTG IS EAS PD ID PD ID Symbol VDSS VGS ID Value 30 20 6.4 5.1 1.28 4.9 3.9 0.75 8.0 6.4 2.0 32 -55 to +150 1.7 60.5 W A C A mJ W A 8 W Unit V V A
N-Channel D
G
S A
MARKING DIAGRAM & PIN ASSIGNMENT
D1 D1 D2 D2
8 SOIC-8 CASE 751 STYLE 11 1
S1 G1 S2 G2
1
4820N AYWW G
Operating Junction and Storage Temperature Source Current (Body Diode) Single Pulse Drain-to-Source Avalanche Energy TJ = 25C, VDD = 30 V, VGS = 10 V, IL = 11 Apk, L = 1.0 mH, RG = 25 W Lead Temperature for Soldering Purposes (1/8 from case for 10 s)
4820N A Y WW G
= Device Code = Assembly Location = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
TL 260 C Device NTMD4820NR2G Symbol RqJA RqJA RqJF RqJA Max 97.5 62 40 167.5 C/W Unit Package SOIC-8 (Pb-Free) Shipping 2500/Tape & Reel
THERMAL RESISTANCE RATINGS
Rating Junction-to-Ambient - Steady State (Note 1) Junction-to-Ambient - t 10 s (Note 1) Junction-to-FOOT (Drain) Junction-to-Ambient - Steady State (Note 2)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
1. Surface-mounted on FR4 board using 1 inch sq pad size, 1 oz Cu. 2. Surface-mounted on FR4 board using the minimum recommended pad size.
(c) Semiconductor Components Industries, LLC, 2007
1
December, 2007 - Rev. 0
Publication Order Number: NTMD4820N/D
NTMD4820N
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)jk
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage Drain-to-Source Breakdown Voltage Tem perature Coefficient Zero Gate Voltage Drain Current Gate-to-Source Leakage Current ON CHARACTERISTICS (Note 3) Gate Threshold Voltage Negative Threshold Temperature Coeffi cient Drain-to-Source On Resistance Forward Transconductance VGS(TH) VGS(TH)/TJ RDS(on) gFS VGS = 10 V VGS = 4.5 V CHARGES, CAPACITANCES AND GATE RESISTANCE Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Threshold Gate Charge Gate-to-Source Charge Gate-to-Drain Charge Total Gate Charge SWITCHING CHARACTERISTICS (Note 4) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time DRAIN-TO-SOURCE CHARACTERISTICS Forward Diode Voltage Reverse Recovery Time Charge Time Discharge Time Reverse Recovery Time PACKAGE PARASITIC VALUES Source Inductance Drain Inductance Gate Inductance Gate Resistance LS LD LG RG TA = 25C 0.66 0.20 1.50 1.5 3.0 nH nH nH W VSD tRR Ta Tb QRR VGS = 0 V, dIS/dt = 100 A/ms, IS = 1.7 A VGS = 0 V ID = 1.7 A TJ = 25C TJ = 125C 0.75 0.59 17.8 8.3 9.5 8.0 nC ns 1.0 V td(ON) tr td(OFF) tf VGS = 10 V, VDD = 15 V, ID = 1.0 A, RG = 6.0 W 9.4 4.0 21 6.5 ns CISS COSS CRSS QG(TOT) QG(TH) QGS QGD QG(TOT) VGS = 10 V, VDS = 15 V, ID = 7.5 A VGS = 4.5 V, VDS = 15 V, ID = 7.5 A VGS = 0 V, f = 1.0 MHz, VDS = 15 V 940 225 125 7.7 1.1 3.3 3.2 15.2 nC nC pF ID = 7.5 A ID = 6.5 A VGS = VDS, ID = 250 mA 1.5 26 15 20 21 20 27 3.0 V mV/C mW S V(BR)DSS V(BR)DSS/TJ IDSS IGSS VGS = 0 V, VDS = 24 V TJ = 25C TJ = 100C VGS = 0 V, ID = 250 mA 30 5.0 1.0 10 100 V mV/C mA nA Symbol Test Condition Min Typ Max Unit
VDS = 0 V, VGS = 20 V
VDS = 1.5 V, ID = 7.5 A
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%. 4. Switching characteristics are independent of operating junction temperatures.
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NTMD4820N
TYPICAL PERFORMANCE CURVES
15 10V ID, DRAIN CURRENT (AMPS) 12.5 10 7.5 5 2.5 0 6V 5V 4.5 V 4.2 V 4V 3.8 V TJ = 25C ID, DRAIN CURRENT (AMPS) 3.6 V 15 VDS 10 V
3.4 V
10
3.2 V 2.8 V 3.0 V
5
TJ = 125C TJ = 25C
TJ = -55C 3 3.5 4 4.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0
1
1.5
2
2.5
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
Figure 1. On-Region Characteristics
RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 0.095 0.085 0.075 0.065 0.055 0.045 0.035 0.025 0.015 0.005 2 4 6 8 10 TJ = 25C ID = 9 A 0.030
Figure 2. Transfer Characteristics
TJ = 25C 0.025 0.020 0.015 0.010 0.005 0 2 VGS = 10 V VGS = 4.5 V
4
6
8
10
12
14
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On-Resistance vs. Gate-to-Source Voltage
1.6 RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -50 100 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (C) IDSS, LEAKAGE (nA) 10000 ID = 7.5 A VGS = 10 V 100000
Figure 4. On-Resistance vs. Drain Current and Gate Voltage
VGS = 0 V
TJ = 150C
1000 TJ = 100C
3
6
9
12
15
18
21
24
27
30
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current vs. Voltage
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3
NTMD4820N
TYPICAL PERFORMANCE CURVES
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 0 10 TJ = 25C Ciss VGS = 0 V 9 8 7 6 5 4 3 2 1 0 0 2 ID = 7.5 A TJ = 25C 6 10 4 8 12 QG, TOTAL GATE CHARGE (nC) 14 4 QGS QGD 8 VDS VGS 12 QT 16 20 VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Coss
Crss 5 10 15 20 25 DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30
0 16
Figure 7. Capacitance Variation
Figure 8. Gate-To-Source and Drain-To-Source Voltage vs. Total Charge
1000 IS, SOURCE CURRENT (AMPS) VDD = 10 V ID = 1 A VGS = 15 V 100 t, TIME (ns) td(off) tf tr td(on)
3 VGS = 0 V TJ = 25C 2
10
1
1
1
10 RG, GATE RESISTANCE (OHMS)
100
0 0.4
0.5
0.6
0.7
0.8
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation vs. Gate Resistance
EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) 100 ID, DRAIN CURRENT (AMPS) 10 ms 10 100 ms 1 ms 1 VGS = 20 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 dc 10 ms 75
Figure 10. Diode Forward Voltage vs. Current
ID = 11 A
50
25
0.1
0.01 0.1
100
0 25
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C)
150
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature
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4
NTMD4820N
PACKAGE DIMENSIONS
-XA
8 5
SOIC-8 NB CASE 751-07 ISSUE AJ
B
1 4
S
0.25 (0.010)
M
Y
M
-YG C -ZH D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004) M ZY
S
J
X
S
SOLDERING FOOTPRINT*
DIM A B C D G H J K M N S
1.52 0.060
STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NTMD4820N/D

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