View ICS844002AG_4145124.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ICS844002
GENERAL DESCRIPTION
The ICS844002 is a 2 output LVDS Synthesizer IC S optimized to generate Fibre Channel reference HiPerClockSTM clock frequencies and is a member of the HiPerClocks TM family of high performance clock solutions from IDT. Using a 26.5625MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz. The ICS844002 uses IDT's 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Fibre Channel jitter requirements. The ICS844002 is packaged in a small 20-pin TSSOP package.
FEATURES
* Two LVDS outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal (637kHz - 10MHz): 0.65ps (typical) * Full 3.3V or 2.5V supply modes * 0C to 70C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
FREQUENCY SELECT FUNCTION TABLE
Inputs Input Frequency (MHz) 26.5625 26.5625 26.5625 26.5625 23.4375 F_SEL1 F_SEL0 0 0 1 1 0 0 1 0 1 0 M Divider Value 24 24 24 24 24 N Divider Value 3 4 6 12 3 M/N Divider Value 8 6 4 2 8 Output Frequency (MHz) 212.5 159.375 106.25 53.125 187.5
PIN ASSIGNMENT
nc VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 nQ1 GND nc nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1
ICS844002
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL Pulldown REF_CLK Pulldown
26.5625MHz
2
Q0
1
1
XTAL_IN
OSC
XTAL_OUT nXTAL_SEL
Pulldown
0
Phase Detector
VCO 637.5MHz
(w/26.5625MHz Reference)
F_SEL[1:0] 0 0 /3 0 1 /4 1 0 /6 11 /12
nQ0
Q1 nQ1
0
M = 24 (fixed)
MR
Pulldown
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
1
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number 1, 7 2, 20 3, 4 5 Name nc VDDO Q0, nQ0 MR Type Unused Power Ouput Input Description No connect. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pins. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL reference clock input. Selects between cr ystal or REF_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. No connect. Power supply ground. Differential output pair. LVDS interface levels.
6 8 9, 11 10 12, 13 14 15 16 17 18, 19
nPLL_SEL VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN REF_CLK nXTAL_SEL nc GND nQ1, Q1
Input Power Input Power Input Input Input Unused Power Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
2
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, JA 73.2C/W (0 lfpm)
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 VDD - 0.12 3.135 Typical 3.3 3.3 3.3 Maximum 3.465 3.465 3.465 105 12 120 Units V V V mA mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 VDD - 0.10 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 95 10 90 Units V V V mA mA mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current REF_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, REF_CLK, MR, F_SEL0, F_SEL1, nPLL_SEL, nXTAL_SEL, Test Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V VDD = 2.5V VDD = VIN = 3.465 or 2.5V VDD = 3.465V or 2.5V, VIN = 0V -150 Minimum Typical 2 1.7 -0.3 -0.3 Maximum VDD + 0.3 VDD + 0.3 0.8 0.7 150 Units V V V V A
IIL
A
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
3
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.4 1.525 Test Conditions Minimum 300 Typical 450 Maximum 600 50 1.65 50 Units mV mV V mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.0 Test Conditions Minimum 250 Typical 400 Maximum 550 50 1.4 50 Units mV mV V mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. 23.33 Test Conditions Minimum Typical 26.5625 Maximum 28.33 50 7 1 Units MHz pF mW Fundamental
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
4
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions F_SEL[1:0] = 00 fOUT Output Frequency F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 tsk(o) Output Skew; NOTE 1, 2 212.5MHz, (637kHz - 10MHz) 159.375MHz, (637kHz - 10MHz) tjit(O) RMS Phase Jitter (Random); NOTE 3 106.25MHz, (637kHz -10MHz) 53.125MHz, (637kHz - 10MHz) 187.5MHz, (637kHz - 10MHz) tR / tF Output Rise/Fall Time 20% to 80% 250 0.65 0.61 0.74 0.64 0.80 500 52 55 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.66 170 113.33 56.66 15 Units MHz MHz MHz MHz ps ps ps ps ps ps ps % %
F_SEL[1:0] /3 48 odc Output Duty Cycle F_SEL[1:0] = /3 45 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter Test Conditions F_SEL[1:0] = 00 fOUT Output Frequency F_SEL[1:0] = 01 F_SEL[1:0] = 10 F_SEL[1:0] = 11 t sk(o) Output Skew; NOTE 2, 4 212.5MHz, (637kHz - 10MHz) 159.375MHz, (637kHz - 10MHz) t jit(O) RMS Phase Jitter (Random); NOTE 3 106.25MHz, (637kHz -10MHz) 53.125MHz, (637kHz - 10MHz) 187.5MHz, (637kHz - 10MHz) tR / tF odc Output Rise/Fall Time Output Duty Cycle 20% to 80% 250 0.65 0.61 0.74 0.64 0.80 500 52 55 Minimum 186.67 140 93.33 46.67 Typical Maximum 226.66 170 113.33 56.66 15 Units MHz MHz MHz MHz ps ps ps ps ps ps ps % %
F_SEL[1:0] /3 48 F_SEL[1:0] = /3 45 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
5
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
Fibre Channel Jitter Filter 212.5MHz
RMS Phase Jitter (Random) 637khz to 10MHz = 0.65ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
-110 -120 -130 -140 -160 -170 -180 -190 100 1k -150
Phase Noise Result by adding Fibre Channel Filter to raw data
100k 1M 10M 100M
10k
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M
Fibre Channel Jitter Filter 106.25MHz
RMS Phase Jitter (Random) 637khz to 10MHz = 0.74ps (typical)
NOISE POWER dBc Hz
Raw Phase Noise Data
Phase Noise Result by adding Fibre Channel Filter to raw data
OFFSET FREQUENCY (HZ)
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
6
0
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
SCOPE
3.3V5% POWER SUPPLY + Float GND -
SCOPE
2.5V5% POWER SUPPLY + Float GND -
VDD, VDDO V DDA
Qx
VDD, VDDO V DDA
Qx
LVDS
nQx
LVDS
nQx
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ0, nQ1 Q0, Q1
t PW
t
PERIOD
tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
Phase Noise Plot
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Noise Power
80%
Phase Noise Mask
80% VSW I N G
Clock Outputs
Offset Frequency
20% tR tF
20%
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
VDD out
OUTPUT RISE/FALL TIME
VDD out
DC Input
100
VOD/ VOD out
out
VOS/ VOS
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
7
ICS844002AG REV. A SEPTEMBER 28, 2007
LVDS
DC Input
LVDS
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844002 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844002 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 26.5625MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
Figure 2. CRYSTAL INPUt INTERFACE
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
8
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
VDD
VDD
R1 Ro Rs Zo = 50 .1uf XTAL_IN
Zo = Ro + Rs
R2
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTPUTS:
LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
9
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
2.5V or 3.3V VDD LVDS_Driv er + R1 100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
10
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844002. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844002 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (105mA + 12mA) = 405.4mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 120mA = 415.8mW
Total Power_MAX = 405.4mW + 415.8mW = 821.2mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.821W * 66.6C/W = 124.6C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 20-LEAD TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
11
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844002 is: 2914
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
12
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
13
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS844002AG ICS844002AGT ICS844002AGLF ICS844002AGLFT Marking ICS844002AG ICS844002AG ICS844002AGL ICS844002AGL Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
14
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET Rev A A A T1 Table Page 6 11 1 2 Added Phase Noise Plots. Power Consideraitons - corrected sentence after the Tj calculation. Pin Assignment - corrected Pin 16 from VDD to nc. Pin Description Table - deleted number 16 from VDD row and added row Pin 16 as a "nc". Description of Change Date 7/24/06 1/19/07 9/28/07
IDT TM / ICSTM LVDS FREQUENCY SYNTHESIZER
15
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002 FEMTOCLOCKSTM CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
netcom@idt.com 480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851
(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS, FemtoClocks and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of ICS844002AG

	To Download ICS844002AG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .