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CY28331
Clock Generator for AMDTM Hammer
Features
* Supports AMDTM Hammer CPU * Two differential pairs of CPU clocks * Eight low-skew/low-jitter PCI clocks * One free-running PCI clock * Four low-skew/low-jitter PCI/HyperTransportTM clocks * One 48M output for USB * One programmable 24M or 48M for FDC * Three REF 14.318 MHz clocks * Dial-a-Frequency programmability * Lexmark Spread Spectrum for optimal electromagnetic interference (EMI) reduction * SMBus register-programmable options * 5V-tolerance SCLK and SDATA lines * 3.3V operation * Power management control pins * 48-pin SSOP package 0001 0010 0011 0100 0101 0110 0111 (default) 1000 1001 1010 1011 1100 1101 1110 1111 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 Table 1. Frequency Table (MHz)[1] FS (3:0) 0000 PCI_HT SEL X CPU HT66 PCI
High-Z (All outputs except XOUT are three-stated) 133.9 166.9 200.9 100.0 133.3 166.7 200.0 105.0 110.0 210.0 240.0 270.0 233.3 266.7 300.0 67.0/33.5 66.8/33.4 67.0/33.5 66.7/33.3 66.7/33.3 66.7/33.3 66.7/33.3 70.0/35.0 73.3/36.7 70.0/35.0 60.0/30.0 67.5/33.8 58.3/29.2 66.7/33.3 75.0/37.5 33.5 33.4 33.5 33.3 33.3 33.3 33.3 35.0 36.7 35.0 30.0 33.8 29.2 33.3 37.5
Block Diagram
XIN XOUT 14.31818MHz XTAL REF(0:2)
Pin Configuration
/4 PLL1
USB
24_48MHz /2 SEL#
SRESET#
FS(0:3) PCISTOP# SPREAD PD# SCLK SDATA
PLL2
CPUT(0:1) CPUC(0:1)
Control Logic
/N
PCI33_F
*FS0/REF0 VDD XIN XOUT VSS PCI33HT66_0/*PCI33HT66SEL0# PCI33HT66_1/*PCI33HT66SEL1# PCI33_HT66_2 VDD VSS PCI33_HT66_3 PCI33_7 PCI33_0 PCI33_1 VSS VDD PCI33_2 PCI33_3 VDD VSS PCI33_4 PCI33_5 PCISel/PCI33_F *PCI33_6/PCISTOP#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
*FS1/REF1 VSS VDD *FS2/REF2 SRESET#/PD# VDDA VSSA CPUT0 CPUC0 VSS VDD CPUT1 CPUC1 VDD VSS VSSF VDDF **USB/FS3 VSS VDD 24_48MHz/**SEL# VSS SDATA SCLK
CY28331
STOP
PCI33_(0:7)
*100K Internal Pull-up **100K Internal Pull-down
CNTL
PCI33_HT66_(0:3)
Note: 1. HCLK, 66 MHz, and 33 MHz are in phase and synchronous at power-up.
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 16
www.SpectraLinear.com
CY28331
Pin Description
Pin 3 4 41, 37 40, 36 XIN XOUT CPUT(0:1) CPUC(0:1) Name PWR VDD VDD VDDC VDDC I/O I O O O O I/O Description Oscillator Buffer Input. Connect to a crystal or to an external clock. Oscillator Buffer Output. Connect to a crystal. Do not connect when an external clock is applied at XIN. CPU clock outputs 0 and 1: push-pull "true" output of differential pair. CPU clock outputs 0 and 1: push-pull "complement" output of differential pair. 3.3V PCI clock outputs controlled by PCISTOP#. PCISel is a strap option during power-up to select Pin 24 functionality: 0: Configure Pin 24 as PCI33_6 1: Configure Pin 24 as PCISTOP# (default 100k internal pull-up) After power-up, this pin reverts to standard PCI33_F output. 3.3V PCI 33 MHz or HyperTransport 66 clock outputs. This group is selectable between 33 MHz and 66 MHz, based on the state of PCI33HT66SEL[0:1]#. PCI33 or HT66 select. This input strap selects the output frequency of PCI33_HT66 outputs to either 33 MHz or 66 MHz. There is an internal 100Kohm pull-up resistor. After power-up, this pin becomes PCI33_HT66_[0:1] output. SEL1 SEL0 PIN6 PIN7 PIN8 PIN11 0 0 HT66_0 HT66_1 HT66_2 HT66_3 0 1 HT66_0 HT66_1 HT66_2 PCI33_3 1 0 HT66_0 HT66_1 PCI33_2 PCI33_3 1 1 HT66_0 PCI33_1 PCI33_2 PCI33_3 3.3V USB clock output at 48 MHz. At power-up this pin is sensed to determine the CPU output frequency. There is an internal 100K-ohm pull-down resistor. 3.3V super I/O clock output. At power-up this pin is sensed to determine whether the output is 24 MHz or 48 MHz. There is an internal 100K-ohm pull-down resistor. This pin will be externally strapped high using a 10K-ohm resistor to VSS. 0 = 48 MHz, 1 = 24 MHz. 3.3V reference clock output. At power-up this pin is sensed to determine the CPU output frequency. There is an internal 100K-ohm pull-up resistor for FS0, while FS(1:2) includes 100K ohm pull-up resistors. Watchdog Time-out Reset Output. Power-down input (100K internal pull-up). When configured through pin 23 as PCI_STOP#, this pin controls the PCI33(0:5,7) and PCI33_HT66(1:3) outputs. Active LOW control input to halt all 33-MHz PCI clocks except PCI33_F. Only the PCI33_HT66 outputs that are running at 33 MHz will be stopped. The outputs will be glitch-free when turning off and turning on (100K internal pull-up). When configured through pin 23 as PCI33_6, PCI_STOP# is unavailable. 3.3V PCI clock outputs controlled by PCISTOP#. Data pin for SMBus (rev2.0). There is an internal 100K-ohm pull-up resistor. Clock pin for SMBus (rev2.0). There is an internal 100K-ohm pull-up resistor.
13, 14, 17, PCI33(0:5) 18, 21, 22 23 PCISel / PCI33_F
8, 11
PCI33_HT66(2:3)
VDDD
O
6, 7
PCI33_HT66_[0:1]/ PCI33_HT66SEL[0:1]#
VDDD
I/O
31
USB/FS3
I/O
28
24_48MHz/SEL#
I/O
1, 48, 45
REF(0:2)/FS(0:2)
I/O
44 24
SRESET#/PD# PCI33_6/ PCISTOP#
I/O I/O
12 26 25
PCI33_7 SDATA SCLK
O I/O I
VDD 2, 9, 16, 19, 29, 35, 38, 46 5, 10, 15, VSS 20, 27, 30, 34, 39, 47
PWR Power connection to 3.3V for the core.
GND Power connection to GROUND for the CORE section of the chip.
Rev 1.0, November 24, 2006
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CY28331
Pin Description (continued)
Pin 43 42 32 33 VDDA VSSA VDDF VSSF Name PWR I/O Description PWR Power connection to 3.3V for the ANALOG section of the chip. GND Power connection to GROUND for the analog section of the chip. PWR Power connection to 3.3V for the 48 MHz PLL section of the chip. GND Power connection to GROUND for the 48 MHz PLL section of the chip.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface (SDI), various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the SDI initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation. Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000.'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) - 8 bits Acknowledge from slave Data Byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data byte from slave - 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Not Acknowledge Stop Block Read Protocol Description
Rev 1.0, November 24, 2006
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CY28331
Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '1xxxxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Not Acknowledge Stop Byte Read Protocol Description
19 20:27 28 29
19 20 21:27 28 29 30:37 38 39
Serial Control Registers
Byte 0: Frequency and Spread Spectrum Control Register Bit 7 @Pup Inactive = 0 Pin# Name Description Write Disable (write once). A 1 written to this bit after a 1 has been written to Byte0 bit0 will permanently disable modification of all configuration registers until the part has been powered off. Once the clock generator has been Write Disabled, the SMBus controller should still accept and acknowledge subsequent write cycles but it should not modify any of the registers. For Test, always program to `0' 12 31 45 48 1 PCI33_7 FS3 FS2 FS1 FS0 Enable (1 = Enabled, 0 = Disabled) corresponds to Frequency Selection. See Table 1. corresponds to Frequency Selection. See Table 1. corresponds to Frequency Selection. See Table 1. corresponds to Frequency Selection. See Table 1. Write Enable. A 1 written to this bit after power-up will enable modification of all configuration registers and subsequent 0's written to this bit will disable modification of all configuration except this single bit. Note that block write transactions to the interface will complete, however unless the interface has been previously unlocked, the writes will have no effect. The effect of writing this bit doe not take effect until the subsequent block write command.
6 5 4 3 2 1 0
0 1 FS3 pin FS2 pin FS1 pin FS0 pin Inactive = 0
Byte 1: PCI Clock Control Register Bit 7 6 5 4 3 2 1 @Pup 1 1 1 1 1 1 1 Pin# 23 24 22 21 18 17 14 Name PCI33_F PCI33_6 PCI33_5 PCI33_4 PCI33_3 PCI33_2 PCI33_1 Description Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled)
Rev 1.0, November 24, 2006
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CY28331
Byte 1: PCI Clock Control Register (continued) Bit 0 @Pup 1 Pin# 13 Name PCI33_0 Description Enable (1 = Enabled, 0 = Disabled)
Byte 2: USB, 24-48MHz, REF(0:2) Control Register Bit 7 6 5 4 3 2 1 0 @Pup active = 1 active = 1 active = 1 active = 1 active = 1 active = 1 active = 1 0 Pin # 37, 36 41, 40 45 48 1 28 31 Name Description CPUT/C(1) CPUT/C(1) shutdown. This bit can be optionally used to disable the CPUT/C(1) clock pair. During shutdown, CPUT = low and CPUC = high CPUT/C(0) CPUT/C(0) shutdown. This bit can be optionally used to disable the CPUT/C(0) clock pair. During shutdown, CPUT = low and CPUC = high REF2 REF1 REF0 USB Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) Enable (1 = Enabled, 0 = Disabled) For Test, always program to `0'
24_48MHz Enable (1 = Enabled, 0 = Disabled)
Byte 3: PCI Clock Free Running Select Control Register Bit 7 @Pup Inactive = 0 Pin # Name PCI_DRV 0 = Low Strength 1 = High Strength PCI33_HT66 Drive Strength 0 = Low Strength 1 = High Strength 22 21 18 11 8 7 PCI5 PCI4 PCI3 Free running enable (10 = Free running, 0 = Disabled) Free running enable (1 = Free running, 0 = Disabled) Free running enable (1 = Free running, 0 = Disabled) Description
6
Inactive = 0
5 4 3 2 1 0
Inactive = 0 Inactive = 0 Inactive = 0 1 1 1
PCI33_HT66_3 Enable (1 = Enabled, 0 = Disabled) PCI33_HT66_2 Enable (1 = Enabled, 0 = Disabled) PCI33_HT66_1 Enable (1 = Enabled, 0 = Disabled)
Byte 4: Pin Latched/Real-time State Bit 7 6 5 4 3 2 1 0 @Pup 1 HW 0 1 FS3 pin FS2 pin FS1 pin FS0 pin 31 45 48 1 Pin# 6 Name PCI33_HT66_0 Reserved SSEN FS3 FS2 FS1 FS0 24_48MHz/SEL# Pin power-up latched state For Test, always program to `0' Spread Spectrum enable (0 = disable, 1 = enable). This bit provides a SW programmable control for spread spectrum clocking. Power-up latched state Power-up latched state Power-up latched state Power-up latched state Description Enable (1 = Enabled, 0 = Disabled)
Rev 1.0, November 24, 2006
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CY28331
Byte 5: SSCG, Dial-a-SkewTM, and Dial-a-RatioTM Register Bit 7 6 @Pup 0 1 Spread Spectrum Selection: bit7 bit6 bit5 % Spread 0 0 0 -1.5 0 0 1 -1.0 0 1 0 -0.7 0 1 1 -0.5 (default) 1 0 0 0.75 1 0 1 0.50 1 1 0 0.35 1 1 1 0.25 HT66 Frequency Fractional Aligner: These bits determine the HT66 fixed frequency when the HT66 Output Frequency Selection bit is set. It does not incorporate spread spectrum. Fract_Align PCI_HT PCI bit[4:0] (MHz) (MHz) 00000 Off Off (default) 00001 66.5 33.2 00010 67.5 33.7 00011 68.5 34.3 00100 69.5 34.8 00101 70.6 35.3 00110 71.6 35.8 00111 72.6 36.3 01000 73.6 36.8 01001 74.7 37.3 01010 75.7 37.8 01011 76.7 38.4 01100 77.7 38.9 01101 78.7 39.4 01110 79.8 39.9 01111 80.8 40.4 10000 81.8 40.9 10001 82.8 41.4 10010 83.9 41.9 10011 84.9 42.4 10100 85.9 43.0 10101 86.9 43.5 10110 88.0 44.0 10111 89.0 44.5 11000 90.0 45.0 11001 91.0 45.5 11010 92.0 46.0 11011 93.1 46.5 11100 94.1 47.0 11101 95.1 47.6 11110 96.1 48.1 11111 97.2 48.6 Description
5
1
4 3 2 1 0
0 0 0 0 0
Byte 6: Watchdog Control Register Bit 7 @Pup 0 Name Description HT66 Output Frequency HT66 Output Frequency Selection: Selection 0: Set according to Frequency Selection Table 1: Set according to Fractional Aligner Table Pin 44 Mode Select Pin 44 Mode Select: 0 = Pin 12 is the output pin as SRESET# signal. 1 = Pin 12 is the input pin which functions as a PD# signal.
6
0
Rev 1.0, November 24, 2006
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CY28331
Byte 6: Watchdog Control Register (continued) Bit 5 @Pup 0 Name Frequency Reversion Description Frequency Reversion: This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time out only. 0 = Selects frequency of existing H/W setting 1 = Selects frequency of the second to last S/W setting. (the software setting prior to the one that caused a system reboot). WD Time-out: This bit is set to "1" when the Watchdog times out. It is reset to "0" when the system clears the WD time stamps (WD3:0). This bit allows the selection of the time stamp for the Watchdog timer. After a Watchdog time-out, the frequency will revert to the original frequency. WD3 .. .. WD0 0 00 0 Off (default) 0 00 1 1 second 0 01 0 2 seconds 0 01 1 3 seconds 0 10 0 4 seconds 0 10 1 5 seconds 0 11 0 6 seconds 0 11 1 7 seconds 1 00 0 8 seconds 1 00 1 9 seconds 1 01 0 10 seconds 1 01 1 11 seconds 1 10 0 12 seconds 1 10 1 13 seconds 1 11 0 14 seconds 1 11 1 15 seconds
4
0
WD Time-out
3 2 1
0 0 0
WD3 WD2 WD1
0
0
WD0
Byte 7: Clock Vendor ID Bit 7 6 5 4 3 2 1 0 Byte 8: Device ID Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 1 0 1 1 Device ID Device ID Device ID Device ID Device ID Device ID Device ID Device ID Description @Pup 0 1 0 1 1 0 0 0 Revision ID[1] Revision ID[0] Device ID[9] Device ID[8] Vendor ID[3] Vendor ID[2] Vendor ID[1] Vendor ID[0] Description
Rev 1.0, November 24, 2006
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CY28331
Byte 9: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @PUp 0 N6 N5 N4 N3 N2 N1 N0 ATPG Pulse These bits are for programming the PLL's internal N register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. Description
Byte 10: Dial-a-Frequency Control Register M Bit 7 6 5 4 3 2 1 0 Byte 11: Bit 7 6 5 4 3 2 1 0 @Pup 0 HW HW 0 0 0 0 0 7 6 PCI33HT66SEL1# PCI33HT66SEL0# Pin # Name For Test, ALWAYS program to `0' PCI33/HT66 Mode Select 1 Power-up Latched State of PCI33HT66SEL1# Mode Select 1 (read only). PCI33/HT66 Mode Select 0 Power-up Latched State of PCI33HT66SEL0# Mode Select 0 (read only). Reserved Set = 0 Reserved Set = 0 Reserved Set = 0 Reserved Set = 0 Reserved Set = 0 Description @Pup 0 M5 M4 M3 M2 M1 M0 DAFEN When this bit = 1, it enables the Dial-a-Frequency N and M bits to be multiplexed into the internal N and M registers. When this bit = 0, the ROM based N and M values are loading into the internal N and M registers. ATPG Mode (default = 0) These bits are for programming the PLL's internal M register. This access allows the user to modify the CPU frequency with great accuracy. All other synchronous clocks (clocks that are generated from the same PLL, such as PCI, remain at their existing ratios relative to the CPU clock. Description
System Self-Recovery Clock Management
This feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. When the system sends an SMBus command requesting a frequency change through the Dial-a-Frequency Control Registers, it must have previously sent a command to the Watchdog Timer to select which time out stamp the Watchdog must perform, otherwise the System Self-Recovery feature will not be applicable. Consequently, this device will change frequency and then the Watchdog timer starts timing. Meanwhile, the system BIOS is running its operation with the new frequency. If this device receives a new SMBus command to clear the bits originally programmed in Watchdog Timer bits (reprogram to 0000) before the Watchdog times out, then this device will keep operating in its normal condition with the new selected frequency. The Watchdog timer will also be triggered if you program the software frequency select bits (FSEL) to a new frequency selection. If the Watchdog times out before the new SMBus reprograms the Watchdog Timer bits to (0000), then this device will send a low system reset pulse, on SRESET#, and changes WD Time-out bit to "1."
Rev 1.0, November 24, 2006
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CY28331
RESET W ATCHDOG TIMER Set WD(0:3) Bits = 0
INITIALIZE W ATCHDOG TIMER Set Frequency Revert Bit Set WD(0:3) = (# of Sec ) x 2
SET SOFTW ARE FSEL Set SW Freq_Sel = 1 Set FS(0:4)
SET DIAL-A-FREQUENCY Load M and N Registers Set Pro_Freq_EN = 1
Wait for 6msec For Clock Output to Ramp to Target Frequency
Hang?
N
CLEAR W D Set WD(0:3) Bits = 0
Exit
Y
W ATCHDOG TIMEOUT
Frequency Revert Bit = 0 Set Frequency to FS_HW_Latched
Frequency Revert Bit = 1 Set Frequency to FS_SW
Set SRESET# = 0 for 6 msec
Reset
Figure 1. Watchdog Flow Chart
Rev 1.0, November 24, 2006
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CY28331
Dial-a-Frequency
ROM M Register
SMBus Control Register N
Latch
Control Register N White
N Register
SMBus Control Register M
Control Register M White
DAFEN
Figure 2. Dial-a-Frequency Feature The SMBus controlled Dial-a-Frequency feature is available in this device via Dial-a-Frequency Control Register N and Dial-a-Frequency Control Register M. P is a PLL constant that depends on the frequency selection prior to accessing the Dial-a-Frequency feature. Table 5. FS(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 127994667 191992000 191992000 95996000 127994667 191992000 191992000 95966000 95966000 191992000 191992000 191992000 191992000 191992000 191992000 P
Operation
Pin strapping on any configuration pin is based on a 10K ohm resistor connected to either 3.3V (VDD) or ground (VSS). When the VDD supply goes above 2.0V, the Power-on-Reset circuitry latches all of the configuration bits into their respective registers and then allows the outputs to be enabled. The output may not occur immediately after this time as the PLL needs to be locked and will not output an invalid frequency. The CPU frequencies are defined from the hardware-sampled inputs. Additional frequencies and operating states can be selected through the SMBus-programmable interface. Spread spectrum modulation is required for all outputs derived from the internal CPU PLL2. This include the CPU(0:1), PCI33(0:6), PCI33_F, and PCI33_HT66(0:3). The REF (0:2), USB, and 24_48 clocks are not affected by the spread spectrum modulation. The spread spectrum modulation is set for both center and down modes using a Lexmark profiles for amounts of 0.5% and 1.0% at a 33-KHz rate. The CPU clock driver is of a push-pull type for the differential outputs, instead of the Athlon open-drain style. The CPU clock termination has been derived such that a 15-40 ohm, 3.3V output driver can be used for the CPU clock. The PCISTOP# signal provides for synchronous control over the any output, except the PCI33_F, that is running at 33 MHz. If the PCI33_HT66 outputs are configured to run at 66 MHz will not be stopped by this signal. The PCISTOP# signal is sampled by an internal PCI clock such that once it is sensed low or active, the 33-MHz signals are stopped on the next high to low transition and remains low.
The algorithm is the same for all P values, which is Fcpu = (P*N)/M with the following conditions. M = (20..58), N = (21..125) and N > M > N/2.
Rev 1.0, November 24, 2006
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CY28331
Absolute Maximum Ratings
Parameter VDD, VDDA, VDDF VIN TS TJ OJC OJA ESDh Ul-94 MSL Input Voltage Storage Temperature Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Description Supply Voltage Conditions Non-functional Functional Non-functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 V-0 @1/8 in. 1 32.78 73.61 > 2,000 10 Min. -0.5 -0.5 -65 Max. 4.6 VDD + 0.5 +150 +150 Unit V V C C C/W C/W V ppm
Recommended Operating Conditions
Parameter VDD, VDDA, VDDF TA FXIN Supply Voltage Operating Temperature, Ambient Input Frequency (Crystal or Reference) Description Min. 3.135 0 10 14.318 Typ. 3.3 Max. 3.465 70 16 Unit V C MHz
SCLK and SDATA Input Electrical Characteristics (5V-tolerant)
Parameter VIL VIH IIL, IIH VOL IOL Description Input Low Voltage Input High Voltage Input High/Low Current Output High Voltage Output Low Current 0 < VIN < VDD IOL = 1.75 mA VO = 0.8V VSS - 0.3 2 Conditions Min. VSS - 0.5 2.0 Typ. Max. 0.8 VDD + 0.3 5 0.4 6 Unit V V A V mA
DC Electrical Specifications (All outputs loaded)
Parameter VIL VIH IIL IIH LTSL IDD3.3V IPD3.3V CIN COUT LPIN CXTAL VBIAS Description Input Low Voltage Input High Voltage Input Low Current Input High Current Three-state Leakage Current Dynamic Supply Current Power-down Supply Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Crystal DC Bias Voltage Measured from Pin to Ground. 27 0.3VDD 36 VDD/2 Except XIN and XOUT CPU(0:1) @ 200 MHz 250 2 5 6 7 45 0.7VDD @VIL = VSS, except PU and PD @VIH = VDD, except PU and PD Conditions Min. VSS - 0.5 2.0 Typ. Max. 0.8 VDD + 0.5 -5 5 10 Unit V V A A A mA mA pF pF nH pF V
Rev 1.0, November 24, 2006
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CY28331
AC Electrical Specifications
PCI133_HT66 = 66MHz Parameter Hammer CPU TR TF VDIFF
DIFF
Description Output Rise Edge Rate Output Fall Edge Rate Differential Voltage Change in VDIFF_DC Magnitude Common Mode Voltage Change in VCM Duty Cycle Jitter, Cycle to Cycle Jitter, Accumulated Frequency Stabilization from Power-up Output Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Frequency Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Cycle-to-Cycle Jitter Long Term Jitter Output Low Voltage Output High Voltage Output Low Current Output High Current Frequency, Actual Output Rise Edge Rate Output Fall Edge Rate Duty Cycle Cycle-to-Cycle Jitter Long-term Jitter Frequency Stabilization from Power-up
Test Condition Measured @ the Hammer test load using VOCM 400 mV, 0.850V to 1.650V Measured @ the Hammer test load using VOCM 400 mV, 1.650V to 0.850V Measured @ the Hammer test load (single-ended) Measured @ the Hammer test load (single-ended) Measured @ the Hammer test load (single-ended) Measured @ the Hammer test load (single-ended) Measured at VOX Measured at VOX Measured at VOX Measure from full supply voltage Average value during switching transition IOL = 9.0 mA IOH = -12.0 mA VO = 0.8V VO = 2.0V
Min. 2 2 0.4 -150 1.05 -200 45 0 -1000 0 15
Typ.
Max. 7 7
Unit V/ns V/ns V mV V mV % ps ps ms W V V mA
1.25
2.3 150
VCM VCM TDC TCYC TACCUM TFS RON VOL VOH IOL IOH F33 F66 TR TF TDC TCCJ TLTJ VOL VOH IOL IOH F TR TF TDC TCCJ TLTJ TFS
1.25
1.45 200
50 100
53 200 1000 3
35
55 0.4
PCI/HyperTransport Clock Outputs 2.4 10 -15 33.33 66.67 Measured from 20% to 60% Measured from 60% to 20% Measured at 1.5V Measured at 1.5V Measured at 1.5V IOL = 9.0 mA IOH = -12.0 mA VO = 0.8V VO = 2.0V 14.318 Measured from 20% to 60% Measured from 60% to 20% Measured at 1.5V Measured at 1.5V Measured at 1.5V Measure from full supply voltage 0.5 0.5 45 0 -1000 0 500 2 2 55 1000 1000 3 2.4 16 -22 0.5 0.5 45 0 -1000 4 4 55 400 1000 0.4
mA MHz MHz V/ns V/ns % ps ps V V mA mA MHz V/ns V/ns % ps ps mS
REF(0:2) Clock Outputs
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CY28331
AC Electrical Specifications (continued)
PCI133_HT66 = 66MHz Parameter RON VOL VOH IOL IOH F33 F66 tR tF tD TCCJ TCCJ TLTJ TSTABLE RON Output Rise Edge Rate Output Fall Edge Rate Duty Cycle 24_48MHz Cycle-to-Cycle Jitter USB Cycle-to-Cycle Jitter Long-term Jitter Frequency Stabilization from Power-up Output Impedance Measured from 20% to 80% Measured from 80% to 20% Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V Measure from full supply voltage Average value during switching transition 0.5 0.5 45 0 0 -1000 0 20 24 250 Description Output Impedance Output Low Voltage Output High Voltage Output Low Current Output High Current Frequency Actual Test Condition Average value during switching transition IOL = 9.0 mA IOH = -12.0 mA VO = 0.8V VO = 2.0V 24.004 48.008 2 2 55 500 200 1000 3 60 2.4 16 -22 Min. 20 Typ. 24 Max. 60 0.4 Unit W V V mA mA MHz MHz V/ns V/ns % ps ps ps ms W
USB, 24_48 Clock Outputs
Table 6. Skew [2] Parameter TSK_CPU_CPU TSK_CPU_PCI33 TSK_PCI33_PCI33 TSK_PCI33_HT66 TSK_CPU_HT66 TSK_HT66_HT66 TSK_CPU_CPU TSK_CPU_PCI33 TSK_PCI33_PCI33 TSK_PCI33_HT66 TSK_CPU_HT66 TSK_HT66_HT66 Description Conditions Skew Window Unit 250 500 500 500 500 500 200 200 200 200 200 200 ps ps ps ps ps ps ps ps ps ps ps ps CPU to CPU skew, time independent Measured @ crossing points for CPUT rising edges1 CPU to PCI33 skew, time independent PCI33 to PCI33 skew, time independent PCI33 to HT66 skew, time independent CPU to HT66 skew, time independent HT66 to HT66 skew, time independent CPU to CPU skew, time variant CPU to PCI33 skew, time variant PCI33 to PCI33 skew, time variant PCI33 to HT66 skew, time variant CPU to HT66 skew, time variant HT66 to HT66 skew, time variant Measured @ crossing points for CPUT rising edge and 1.5V PCI clocks Measured between rising @ 1.5V Measured between rising @ 1.5V Measured @ crossing points for CPUT rising edge and 1.5V for HyperTransport clocks Measured between rising @ 1.5V Measured @ crossing points for CPUT rising edges Measured @ crossing points for CPUT rising edge and 1.5V PCI clocks Measured between rising @ 1.5V Measured between rising @ 1.5V Measured @ crossing points for CPUT rising edge and 1.5V for HyperTransport clocks Measured between rising @ 1.5V
Note: 2. All skews in this skew budget are measured from the first referenced signal to the next. Therefore, this skew specifies the maximum SKEW WINDOW between these two signals to be 500 ps whether the CPU crossing leads or lags the PCI clock. This should NOT be interpreted to mean that the PCI33 edge could either be 500 ps before the CPU clock to 500 ps after the clock, thus defining a 1000ps window in which the PCI33 clock edge could fall.
Rev 1.0, November 24, 2006
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CY28331
Table 7. Clock Name CPU, USB, 24_48MHz, REF PCI33, PCI33_F, PCI33_HT66 Max Load (in pF)[3] 20 30
Tsu
PCI_STP# PCI_F
PCI
Figure 3. PCISTOP# Assertion Waveform
Tsu
PCI_STP# PCI_F
PCI
Figure 4. PCISTOP# Deassertion Waveform
Vbias=1.25V 125 ohms 15 ohms 3900pF 169 ohms 15 ohms 3900pF 5pF 5pF 125 ohms
Figure 5. Test Load Configuration
Note: 3. The above loads are positioned near each output pin when tested.
Rev 1.0, November 24, 2006
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CY28331
SRESET#/PD# CPUT CPUC PCI/PCI_HT USB,24_48MHz REF
Figure 6. PD# Assertion Waveform
PD# CPUT CPUC PCI 33MHz
3V66 USB 48MHz REF 14.318MHz
Figure 7. PD# Deassertion Waveform
Ordering Information
Part Number Package Type Product Flow
CY28331OC CY28331OCT
Lead-free
48-pin SSOP 48-pin SSOP - Tape and Reel 48-pin SSOP 48-pin SSOP - Tape and Reel
Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C Commercial, 0 to 70 C
CY28331OXC CY28331OXCT
Rev 1.0, November 24, 2006
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CY28331
Package Drawing and Dimensions
48-pin Shrunk Small Outline Package O48
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 24, 2006
Page 16 of 16

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