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XC61G Series
Low Voltage Detectors (VDF= 0.8V1.5V) Standard Voltage Detectors (VDF 1.6V6.0V)
ETR0203_001
GENERAL DESCRIPTION
The XC61G series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-channel open drain output configurations are available.
APPLICATIONS
Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors
FEATURES
Highly Accurate : 2% Low Power Consumption : 0.7 A [ VIN=1.5V ] (TYP.) Detect Voltage Range : 0.8V ~ 1.5V in 100mV increments (Low Voltage) : 1.6V6.0V in 100mV increments (Standard Voltage) Operating Voltage Range : 0.7V ~ 6.0V (Low Voltage) : 0.7V10.0V (Standard Voltage) Detect Voltage Temperature characteristics : 100ppm/ (TYP.) Output Configuration : N-channel open drain or CMOS CMOS Ultra Small Package : USP-3 (120mW)
TYPICAL APPLICATION CIRCUITS
TYPICAL PERFORMANCE CHARACTERISTICS
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XC61G Series
PIN CONFIGURATION
PIN ASSIGNMENT
PIN NUMBER USP-3 3 1 2 PIN NAME VIN VSS VOUT FUNCTION Supply Voltage Ground Output
PRODUCT CLASSIFICATION
Ordering Information
XC61G DESIGNATOR DESCRIPTION Output Configuration SYMBOL C N 08 ~ 60 0 2 H R L DESCRIPTION : CMOS output : N-ch open drain output : e.g. 0.8V 0, 8 : e.g. 1.5V 1, 5 : No delay : Within 2% : USP-3 : Embossed tape, standard feed : Embossed tape, reverse feed

Detect Voltage Output Delay Detect Accuracy Package Device Orientation
BLOCK DIAGRAMS
(1) CMOS Output (2) N-ch Open Drain Output
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XC61G
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ABSOLUTE MAXIMUM RATINGS
Ta = 25 PARAMETER Input Voltage Output Current *1 *2 *1 *2 SYMBOL VIN IOUT RATINGS 9.0 12.0 50 50 VSS -0.3 ~ VIN +0.3 VSS -0.3 ~ 9.0 VSS -0.3 ~ 12.0 120 -40+85 -40+125 UNITS V mA
CMOS N-ch Open Drain Output *1 N-ch Open Drain Output *2 Power Dissipation USP-3 Operating Temperature Range Storage Temperature Range Output Voltage
VOUT Pd Topr Tstg
V mW
ELECTRICAL CHARACTERISTICS
VDF (T) = 0.9 to 1.5V 2% PARAMETER Detect Voltage Hysteresis Range SYMBOL VDF VHYS VIN = 1.5V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VDF(T) = 0.9V to 1.5V VDF(T) = 1.6V to 6.0V N-ch, VDS = 0.5V CMOS, P-ch, VDS=2.1V IOUT Output Current (Standard Voltage) N-ch, VDS = 0.5V VIN =0.7V VIN =1.0V VIN =6.0V VIN =1.0V VIN =2.0V VIN =3.0V VIN =4.0V VIN =5.0V CMOS, P-ch, VDS=2.1V Temperature VDF Characteristics ToprVDF Delay Time tDLY (VDR VOUT inversion)
NOTE: VDF (T): Setting detect voltage Release Voltage: VDR = VDF + VHYS
Ta=25 CONDITIONS MIN. VDF x 0.98 VDF x 0.02 0.7 0.7 0.10 0.85 1.0 3.0 5. 0 6.0 7.0 TYP. VDF VDF x 0.05 0.7 0.8 0.9 1.0 1.1 0.80 2.70 -7.5 2.2 7.7 10.1 11.5 13.0 -10.0 100 MAX. VDF x 1.02 VDF x 0.08 2.3 2.7 3.0 3.2 3.6 6.0 10.0 -1.5 -2.0 0.2 ppm/ ms 4 5 mA 3 UNITS V V CIRCUITS 1 1
Supply Current
ISS
A
2
Operating Voltage Output Current (Low Voltage)
VIN
V
1 3 4
VIN =8.0V
-40 Topr 85
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XC61G Series
OPERATIONAL EXPLANATION
CMOS output
When input voltage (VIN) rises above detect voltage (VDF), output voltage (VOUT) will be equal to VIN. (A condition of high impedance exists with N-ch open drain output configurations.) When input voltage (VIN) falls below detect voltage (VDF), output voltage (VOUT) will be equal to the ground voltage (VSS) level. When input voltage (VIN) falls to a level below that of the minimum operating voltage (VMIN), output will become unstable. In this condition, VIN will equal the pulled-up output (should output be pulled-up.) When input voltage (VIN) rises above the ground voltage (VSS) level, output will be unstable at levels below the minimum operating voltage (VMIN). Between the VMIN and detect release voltage (VDR) levels, the ground voltage (VSS) level will be maintained. When input voltage (VIN) rises above detect release voltage (VDR), output voltage (VOUT) will be equal to VIN. (A condition of high impedance exists with N-ch open drain output configurations.) The difference between VDR and VDF represents the hysteresis range.
Timing Chart
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XC61G
Series
NOTES ON USE
1. Please use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage to the device. 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. (refer to the Oscillation Description (1) below) 3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT) does not exist. (refer to the Oscillation Description (2) below ) 4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. 5. In order to stabilize the IC's operations, please ensure that VIN pin's input frequency's rise and fall times are more than several sec / V. 6. Please use N-ch open drains configuration, when a resistor RIN is connected between the VIN pin and power source. In such cases, please ensure that RIN is less than 10k and that C is more than 0.1F.
Oscillation Description
(1) Output current oscillation with the CMOS output configuration When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow at RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current Since the XC61G series are CMOS IC S, through current will flow when the IC's internal circuit switching operates (during release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through current's resistor (RIN) during release voltage operations. (refer to Figure 3 ) Since hysteresis exists during detect operations, oscillation is unlikely to occur.
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XC61G Series
TEST CIRCUITS
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XC61G
Series
TYPICAL PERFORMANCE CHARACTERISTICS
Low Voltage
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XC61G Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Low Voltage (Continued)
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XC61G
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage
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XC61G Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage (Continued)
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XC61G
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage (Continued)
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XC61G Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Standard Voltage (Continued)
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XC61G
Series
PACKAGING INFORMATION
USP-3
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XC61G Series
REFERENCE PATTERN LAYOUT DIMENSIONS
USP-3
Note: Recommended metal mask design
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XC61G
Series
MARKING RULE
USP-3
Represents integer of output voltage and detect voltage CMOS Output (XC61GC series) MARK CONFIGURATION A CMOS B CMOS C CMOS D CMOS E CMOS F CMOS G CMOS N-channel Open Drain Output (XC61GN series) MARK CONFIGURATION K N-ch L N-ch M N-ch N N-ch P N-ch R N-ch S N-ch Represents decimal number of detect voltage MARK 0 1 2 3 4 VOLTAGE (V) x.0 x.1 x.2 x.3 x.4 MARK 5 6 7 8 9 VOLTAGE (V) x.5 x.6 x.7 x.8 x.9 VOLTAGE (V) 0.x 1.x 2.x 3.x 4.x 5.x 6.x VOLTAGE (V) 0.x 1.x 2.x 3.x 5.x 6.x 7.x
USP-3 TOP VIEW
Based on internal standards MARK 3 Represents production lot number 0 to 9, A to Z repeated (G, I, J, O, Q, W excepted)
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XC61G Series
1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this catalog is up to date. 2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this catalog. 3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this catalog. 4. The products in this catalog are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.) 5. Please use the products listed in this catalog within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives. 6. We assume no responsibility for damage or loss due to abnormal use. 7. All rights reserved. No part of this catalog may be copied or reproduced without the prior permission of Torex Semiconductor Ltd.
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