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HTG2190
8-Bit 1024 Pixel Dot Matrix LCD MCU Series
Features
* Operating voltage: 2.4V~3.6V * 64K16 bits program ROM * 2.3K8 bits data RAM * 15~39 bidirectional I/O lines * 16 common40~64 segment LCD driver * Two 16-bit programmable timer/event counters with * R to F function for temperature measurement * Synchronous serial interface * On-chip RC oscillator for system clock * 32768Hz crystal oscillator for time base and LCD
driver
* Watchdog Timer * HALT function and wake-up feature reduce power
overflow interrupts
* One 8-bit programmable timer with 8-stage prescaler
consumption
* Eight-level subroutine nesting * Bit manipulation instructions * 63 powerful instructions * Built-in supply voltage detection circuit * One interrupt input * 128-pin QFP package
for PFD
* One 8-bit programmable timer with 8-stage prescaler
for time base
* One 8-bit PWM audio output to directly drive speaker
or buzzer
* One 12-bit current type D/A output with 4-bit volume
control
General Description
The HTG2190 is an 8-bit high performance RISC-like microcontroller capable of driving 1024 pixel (max.) LCD display. Its single cycle instruction and two-stage pipeline architecture make it suitable for high speed applications. The device is suited for use in multiple LCD low power applications among which are calculators, clock timer, game, scales, leisure products, other hand held LCD products and battery operated systems in particular.
Rev. 1.20
1
July 5, 2002
HTG2190
Block Diagram
S Y S C L K /4 STACK0 STACK1 STACK2 P ro g ra m C o u n te r P ro g ra m ROM STACK3 STACK4 STACK5 STACK6 STACK7 In te rru p t C ir c u it IN T /S IN M U X
TM R0 TM R0C
P B 7 /T M R 0
1 6 b it
S Y S C L K /4 RT. TM R1 TM R1C 1 6 b it M U X
IN T C
P B 6 /T M R 1
In s tr u c tio n R e g is te r
MP0 MP1 M
U X
DATA M e m o ry
W DTS W D T P r e s c a le r 256
W DTRC OSC
In s tr u c tio n D ecoder ALU X IN /P C 7 /S E G 6 3 X O U T /P C 6 /S E G 6 2 T im in g G e n e r a tio n
MUX
PEC PE STATUS PDC PD PCC
PORT E
P E 0 ~ P E 7 /S E G 4 0 ~ S E G 4 7
S h ifte r
PORT D
P D 0 ~ P D 7 /S E G 4 8 ~ S E G 5 5
PORT C
OSCO
OS RE VD VS S
S D
CI LCD M e m o ry
ACC
PC PBC PB PAC PA PORT A PORT B
P C 0 ~ P C 7 /S E G 5 6 ~ S E G 6 3
PB0,PB2~PB7
LCD
D r iv e r
S u p p ly V o lta g e D e te c tio n
PA0~PA7
CO M 0~CO M 15
SEG0 PE0~ PD 0~ PC 0~ XOUT X IN /P
~3 PE PD PC /P C7
7 /S E 7 /S E 5 /S E C 6 /S /S E G
9
G4 G4 G5 EG 63
0~SEG 47 8~SEG 55 6~SEG 61 62
TM R2
8 -s ta g e P r e s c a le r PW MDAC1 M U X U X M
SYS C LK
P B 0 /P W M 1 P W M 2 /A U D
TM R2C
P.D PW MDAC2
S C L K /P B 5 IN T /S IN S O U T /P B 4
S e r ia l In te rfa c e
SYS CLK
8 -s ta g e P r e s c a le r
SYS C LK
8 -s ta g e P r e s c a le r
3 2 7 6 8 H z C ry s ta l 4 b its V o lu m e c o n tro l 1 2 b its D /A 8 -s ta g e P r e s c a le r M U X
TM R3
SYS CLK PW MDAC1 PW MDAC2
PW M D /A
TM R3C
Rev. 1.20
2
July 5, 2002
HTG2190
Pin Assignment
X IN /P C X O U T /P C PC PC PC PC PC PC PD PD PD PD PD PD PD PD PE
PE
PE
PE
PE
PE
PE
PE
P 7SEG 6SEG 5 /S E G 4 /S E G 3 /S E G 2 /S E G 1 /S E G 0 /S E G 7 /S E G 6 /S E G 5 /S E G 4 /S E G 3 /S E G 2 /S E G 1 /S E G 0 /S E G 7 /S E G 6 /S E G 5 /S E G 4 /S E G 3 /S E G 2 /S E G 1 /S E G 0 /S E G SEG SEG SEG SEG
128 127126 125124123 122121120119 118 117116 115114113112111110 109 108107106 105104103102 101100 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
NC A0 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 NC
98 97
NC
SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE S S S S S S
G3 G3 G3 G3 G3 G3 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G1 G1 G1 G1 G1 G1 G1 G1 G1 G1 EG EG EG EG EG EG 0 9 8 7 6 5 4
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
HTG 2190 1 2 8 Q . P -A
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
NC PA PA PA PA PA PA PA PB PB PB PB PB PB PB AU RE IN T VD OS NC NC NC NC OS NC VS NC CA NC NC NC S
1 2 3 4 5 6 7 2 3 4 /S O 5 /S C 6 /T M 7 /T M 0 /P W D /P W S /S IN D C1 UT LK R 1 /R T . R0 M1 M2
C0
P1
NC CA CA NC NC NC NC CA VO VO VO VO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO SE SE SE SE P4 UT UT UT UT M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M1 M1 M1 M1 M1 M1 G0 G1 G2 G3 11 22 44 33 2 5 4 3 1 0 P3 P2
Rev. 1.20
3
July 5, 2002
HTG2190
Pad Assignment
X IN /P C X O U T /P C PC PC PC PC PC PC PD PD PD PD PD PD PD PD PE PE PE PE PE PE PE 7 /S 6 /S 5 /S 4 /S 3 /S 2 /S 1 /S 0 /S 7 /S 6 /S 5 /S 4 /S 3 /S 2 /S 1 /S 0 /S 7 /S 6 /S 5 /S 4 /S 3 /S 2 /S 1 /S EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG EG 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P E 0 /S E G 4 0
SE SE SE SE G3 G3 G3 G3 6 7
1
114 113 112
8
111
9
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE S S S S
G3 G3 G3 G3 G3 G3 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G1 G1 G1 G1 G1 G1 G1 G1 G1 G1 EG EG EG EG 6
4 2 1 0 3
5
2 3 4 5 6 7
87 86 85 8 84 83 82 81 80 79 78 (0 , 0 ) 77 76 75 74 73 72 71 70 69 68
8 7 6 4 3 1 0 9 7 5 3 1 9 8 7 0 2 4 6 8 2 5
9
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB2 PB3 PB4 PB5 PB6 PB7
/S O /S C /T M /T M
UT LK R 1 /R T . R0
P B 0 /P W M 1 P W M 2 /A U D RES IN T /S IN VDD OSCI OSCO VSS
62
T R IM 4 6 7 T R IM 3 6 6 T R IM 1 5 9 6 3 T R IM 2
55 56 57 58 60 61
65 64
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 X -1561.08 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 Y 1781.81 1535.18 1428.50 1322.07 1215.39 1108.96 1002.28 895.86 Pad No. 58 59 60 61 62 63 64 65 X 1214.37 1156.72 1331.47 1442.47 1559.56 1264.67 1492.25 1492.25 Y
CA CA CA VO VO VO VO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO CO SE SE SE SE SE SE P2 P3 P4 UT UT UT UT M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M1 M1 M1 M1 M1 M1 G0 G1 G2 G3 G4 G5 44 33 22 11 5 4 3 2 1 0
CAP1
Chip size: 3420 3855 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork. Unit: mm
-1797.56 -1465.33 -1797.56 -1797.56 -1797.56 -1465.33 -1516.38 -1404.62
Rev. 1.20
4
July 5, 2002
HTG2190
Pad No. 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 X -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1577.85 -1471.17 -1364.74 -1258.06 -1151.64 -1044.96 -938.53 -831.85 -725.42 -618.74 -512.32 -405.64 -299.21 -192.53 -86.11 20.57 127.00 233.45 340.11 446.53 553.21 659.64 766.83 873.25 979.68 1100.07 Y 789.18 682.75 576.33 469.65 363.22 256.54 150.11 43.43 -62.99 -169.67 -276.10 -382.78 -489.20 -595.88 -702.31 -809.99 -915.42 -1022.10 -1128.52 -1235.20 -1341.63 -1448.31 -1554.73 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 -1797.56 Pad No. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 X 1264.67 1240.28 1492.25 1515.36 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1517.14 1544.83 1427.99 1313.94 1196.85 1083.06 965.96 851.92 735.08 621.03 503.94 389.89 273.05 159.00 41.91 -72.14 -188.98 -303.02 -420.12 -534.16 -651.00 -765.05 -882.14 -995.93 -1113.03 -1241.55 -1347.98 -1454.66 Y -1351.53 -1235.20 -1119.38 -991.36 -867.16 -745.49 -596.65 -422.91 -271.27 -154.18 -40.13 76.45 190.50 307.34 421.39 538.23 652.27 768.86 882.90 999.74 1113.79 1230.63 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1734.82 1781.81 1781.81 1781.81
Rev. 1.20
5
July 5, 2002
HTG2190
Pad Descriptions
Pad No. Pad Name I/O O O O 3/4 3/4 3/4 I O 3/4 Mask Option 3/4 3/4 3/4 3/4 3/4 3/4 Description LCD segment signal output LCD common signal output LCD driving power generated LCD system voltage booster condenser connecting terminal. Test pin only Negative power supply, ground OSCI and OSCO are connected to an RC network or a crystal (by mask option) for the internal system clock. In the case of RC operation,OSCI is connected to the RC network of the internal system clock. Positive power supply Selectable as external interrupt Schmitt trigger input or serial data input by mask option. External interrupt Schmitt trigger input with pull-high resistor. Edge triggered activated on INT or Serial data input a high to low transition. Serial data input with pull-high resistor. INT shares pad with SIN. Schmitt trigger reset input. Active low without pull-high resistor. Selectable as negative PWM CMOS output or audio output by mask option. PWM2 share pad with AUD. Selectable as bidirectional input/output or positive PWM CMOS output by mask option. On bidirectional input/output mode, software instructions determine whether each pad is a CMOS output or Schmitt trigger input with pull-high resistor. PB0 shares pad with PWM1. Selectable as bidirectional input/output or TMR0 input by mask option. On bidirectional input/output mode, software instructions determine whether it is a CMOS output or Schmitt trigger input with pull-high resistor. On TMR0 input mode, it uses Timer/Event Counter 0. Software can be optioned with or without pull-high resistor. PB7 shares pad with TMR0. Selectable as bidirectional input/output or TMR1 input or RTF input by mask option. On bidirectional input/output mode, software instructions determine whether it is a CMOS output or Schmitt trigger input with pull-high resistor. On TMR1 and RTF input mode, it uses Timer/Event Counter 1. Software can be optioned with or without pull-high resister and be option the RTF function disable or enable. PB6 and TMR1 share pad with RTF. 37~1 SEG0~SEG39 114~112 53~38 54~57 62, 61, 60, 58 59, 63 66, 67 64 68 65 69 COM0~COM15 VOUT11, VOUT22 VOUT33, VOUT44 CAP1, CAP2, CAP3, CAP4 TRIM1~TRIM4 VSS OSCI OSCO VDD
Crystal or RC
3/4
70
INT/SIN
I
INT or Serial Data Input
71
RES
I
3/4 PWM2 CMOS Output or AUD Output I/O or PWM1 CMOS Output
72
PWM2/AUD
O
73
PB0/PWM1
I/O or O
74
PB7/TMR0
I/O or I
I/O or TMR0 Input
75
PB6/TMR1/RTF
I/O or I
I/O or TMR1 Input or RTF Input
Rev. 1.20
6
July 5, 2002
HTG2190
Pad No. Pad Name I/O Mask Option Description Selectable as bidirectional input/output or serial interface clock signal by mask option. On bidirectional input/output mode, software instructions determine whether it is a CMOS output or Schmitt trigger input . 76 PB5/SCLK I/O I/O or SCLK Signal Serial I/O interface clock signal. At Master mode: SCLK should be set as serial clock output pin and after 8 clock output from SCLK terminal, clock output is automatically suspended and SCLK terminal is fixed at a high level. At Slave mode: SCLK should be set as serial clock input pin and after 8 clock input from SCLK terminal, subsequent clock input are masked. PB5 shares pad with SLCK Selectable as bidirectional input/output or serial data output master by mask option. On bidirectional input/output mode, software instructions determine whether it is a CMOS output or Schmitt trigger input . On serial output mode, SOUT pin is a CMOS output. PB4 shares pad with SOUT. Software instructions determine whether it is a CMOS output or Schmitt trigger input with pull-high resistor. When the PB6/TMR1/RTF pad is selected to be in RTF mode, the PB3, PB2 pull-high resistor is not present.
77
PB4/SOUT
I/O or O
I/O or SOUT Output
78 79
PB3 PB2
I/O
3/4
87~80
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by mask option. Software instructions determine whether it is a CMOS output or Schmitt None Wake-up trigger input with pull-high resistor. Wake-up or Crystal or I/O or Segment Output Selectable as 32768Hz crystal or bidirectional input/output or segment signal output by mask option. 32768Hz crystal for timer3 and LCD clock source. XOUT and PC6 share with SEG62 Pad,XIN and PC7 share with SEG63 pad.
88 89
XIN/PC7/SEG63 XOUT/PC6/SEG62
I or I/O or O
PC0~5/SEG56~61 95~90 103~96 PD0~7/SEG48~55 111~104 PE0~7/SEG40~47
I/O or O
Three bidirectional 8-bit input/output ports. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor. PC, PD, PE can be individually I/O or optioned for segment output by mask option. PC0~PC7 Segment Output share pads with SEG56~SEG63, PD0~PD7 share pads with SEG48~SEG55, and PE0~PE7 share pads with SEG40~SEG47.
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 3.6V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...............................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.20
7
July 5, 2002
HTG2190
D.C. Characteristics
Symbol VDD IDD ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 IOL1 IOH1 VLCD IOL2 IOH2 IOL3 IOH3 IOL4 IOH4 IOL5 IOH5 RPH Parameter Operating Voltage Operating Current (RC OSC) Standby Current (RTC ON, LCD ON) Standby Current (RTC ON, LCD OFF) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (TMR0, TMR1, INT) Input High Voltage (TMR0, TMR1, INT) Input Low Voltage (RES) Input High Voltage (RES) I/O Ports Sink Current I/O Ports Source Current LCD Voltage PWM1/PWM2 Sink Current PWM1/PWM2 Source Current Audio Sink Current Audio Source Current Segment 0~39 Output Sink Current Segment 0~39 Output Source Current Segment 40~63 Output Sink Current Segment 40~63 Output Source Current Pull-high Resistance of I/O Ports, TMR0, TMR1 & INT Test Conditions VDD 3/4 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Conditions 3/4 No load, fSYS=4MHz No load, HALT No load, HALT 3/4 3/4 3/4 3/4 3/4 3/4 VOL=0.3V VOH=2.7V 3/4 VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V 3/4 Min. 2.4 3/4 3/4 3/4 0 2.1 0 2.3 3/4 3/4 1.5 -1 3.96 12 -8 1.5 -1.5 80 -50 40 -30 30 Typ. 3/4 1 9 3.5 3/4 3/4 3/4 3/4 1.5 2.4 4 -2 4.4 16 -10 2 -2 130 -90 80 -60 60 Max. 3.6 1.5 30 15 0.9 3 0.7 3 3/4 3/4 3/4 3/4 4.84 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 100 Ta=25C Unit V mA mA mA V V V V V V mA mA V mA mA mA mA mA mA mA mA kW
A.C. Characteristics
Symbol fSYS fTIMER Parameter System Clock (RC OSC) Timer Input Frequency (TMR0,TMR1) Test Conditions VDD 3V 3V 3V 3V 3/4 3/4 3/4 Conditions 3/4 3/4 3/4 Without WDT prescaler 3/4 Power-up or wake-up from HALT 3/4 Min. 400 0 45 12 1 3/4 1 Typ. 3/4 3/4 90 23 3/4 1024 3/4 Max. 4000 4000 180 45 3/4 3/4 3/4
Ta=25C Unit kHz kHz ms ms ms tSYS ms
tWDTOSC Watchdog Oscillator tWDT tRES tSST tINT Watchdog Time-out Period (RC) External Reset Low Pulse width System Start-up Timer Period Interrupt Pulse Width
Note: tSYS=1/fSYS Rev. 1.20 8 July 5, 2002
HTG2190
Functional Description
Execution flow The system clock for the HTG2190 is derived from either a crystal or an RC oscillator. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruction to effectively execute within one cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. Program counter - PC The 13-bit program counter (PC) controls the sequence in which the instructions stored in program ROM are executed.
T1 S y s te m O S C 2 (R C C lo c k o n ly ) PC PC
. e tc h IN S T (P C ) E x e c u te IN S T (P C -1 )
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the program counter (PCL) is a read/write register (06H). Moving data into the PCL perT4 1 3 b its P ro g ra m C o u n te r B ank0
T2
T3
T4
T1
T2
T3
T4
T1
T2
T3
B ank1 B ank2 819216 B its 4000H 5...H E000H ....H B ank7
PC+1
PC+2 S ta c k
. e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 )
0000H 1...H
2000H 3...H
. e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C )
B a n k P o in te r R e g is te r B it7 ,B it6 ,B it5
A 1 5 ,A 1 4 ,A 1 3 B u ffe r
L a tc h d a ta o n E x e c u tio n o f J u m p o r C a ll In s tr u c tio n 6 4 K P r o g r a m R O M A d d r e s s in g A r c h ite c tu r e
Execution flow Program ROM Address *15 0 0 0 0 0 0 *15 *14 *13 *12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *11 0 0 0 0 0 0 *11 *10 0 0 0 0 0 0 *10 *9 0 0 0 0 0 0 *9 #9 S9 *8 0 0 0 0 0 0 *8 #8 S8 *7 0 0 0 0 0 0 @7 #7 S7 *6 0 0 0 0 0 0 @6 #6 S6 *5 0 0 0 0 0 0 @5 #5 S5 *4 0 0 0 0 1 1 @4 #4 S4 *3 0 0 1 1 0 0 @3 #3 S3 *2 0 1 0 1 0 1 @2 #2 S2 *1 0 0 0 0 0 0 *0 0 0 0 0 0 0
Mode Initial reset External or serial input interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Timer 2 overflow Timer 3 overflow Skip Loading PCL Jump, call branch Return from subroutine
PC+2 *14 *13 *12 @1 @0 #1 S1 #0 S0 BP.7 BP.6 BP.5 #12 #11 #10 S15 S14 S13 S12 S11 S10
Program ROM address Note: *15~*0: Program ROM address @7~@0: PCL bits #12~#0: Instruction code bits S15~S0: Stack register bits BP.5~BP.7: Bit 5~7 of bank pointer (04H)
Rev. 1.20
9
July 5, 2002
HTG2190
forms a short jump. The destination must be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program memory - ROM The program memory, which contains executable program instructions, data and table information, is composed of a 65536 x 16 bit format. However as the PC (program counter) is comprised of only 13 bits, the remaining 3 ROM address bits are managed by dividing the program memory into 8 banks, each bank having a range between 0000H and 1FFFH. To move from the present ROM bank to a different ROM bank, the higher 3 bits of the ROM address are set by the BP (Bank Pointer), while the remaining 13 bits of the PC are set in the usual way by executing the appropriate jump or call instruction. As the full 16 address bits are latched during the execution of a call or jump instruction, the correct value of the BP must first be setup before a jump or call is executed. When either a software or hardware interrupt is received, note that no matter which ROM bank the program is in the program will always jump to the appropriate interrupt service address in Bank 0. The original full 16 bit address will be stored on the stack and restored when the relevant RET/RETI instruction is executed, automatically returning the program to the original ROM bank. This eliminates the need for programmers to manage the BP when interrupts occur. Certain locations in Bank 0 of program memory are reserved for special usage:
* ROM Bank 0 (BP5~BP7=000B)
0000H 0004H 0008H 000CH 010H 014H 018H D e v ic e in itia liz a tio n p r o g r a m E x te r n a l o r s e r ia l in p u t in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e T im e r 2 in te r r u p t s u b r o u tin e T im e r 3 in te r r u p t s u b r o u tin e D /A b u ffe r e m p ty in te r r u p t P ro g ra m ROM
....H 1 6 b its
Program memory Timer/Event Counter 0/1 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 008H/00CH and begins execution. Location 010H/014H This area is reserved for the timer 2/3 interrupt service program. If a timer interrupt resulting from a timer 2/3 overflow, and if the interrupt is enabled and the stack is not full, the program will jump to location 010H/014H and begins execution. Location 018H This area is reserved for the PWM D/A buffer empty interrupt service program. After the system latch a D/A code at RAM address 28H, the interrupt is enable, and the stack is not full, the program begins execution at location 018H. Location 020H For best condition, this location is reserved as the beginning when writing a program. ROM Bank 1~7 (BP5~BP7=001B~111) The range of the ROM starts from n000H to (n+1)FFFH. (n=2,4,6,8,10,12,14) Table location Any location in the ROM space can be used as look up table. The instructions TABRDC [m] (use for any bank) and TABRDL [m] (only used for last page of program ROM) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the table is well-defined, the
*
*
The ROM bank 0 ranges from 0000H to 1FFFH.
* Location 000H
*
This area is reserved for the initialization program. After a chip reset, the program always begins execution at location 000H. * Location 004H This area is reserved for the external interrupt or serial input interrupt service routine. If the INT input pin is activated, and the interrupt is enabled and the stack is not full, the program will jump to location 004H and begins execution.
* Location 008H/00CH
*
*
This area is reserved for the Timer/Event Counter 0/1 interrupt service program. If a timer interrupt results from a
Instruction TABRDC [m] TABRDL [m]
Table Location *15 #7 1 *14 #6 1 *13 #5 1 *12 #4 1 *11 #3 1 *10 #2 1 *9 #1 1 *8 #0 1 *7 @7 @7 *6 @6 @6 *5 @5 @5 *4 @4 @4 *3 *2 *1 *0 @3 @2 @1 @0 @3 @2 @1 @0
Table location Note: @7~@0: TBLP register bit7~bit0 #7~#0: TBHP register bit7~bit0 *15~*0: Program ROM table address bit15~bit0
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higher-order byte of the table word are transferred to the TBLH. The Table Higher-order byte register (TBLH) is read only. The Table Pointer (TBHP, TBLP) is a read/write register (1FH, 07H), used to indicate the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. If this happens errors can occur. In other words, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both the main routine and the ISR, the interrupt(s) should be disabled prior to the table read instruction. It should not be enabled until the TBLH has been backed up. All table related instructions need two cycles to complete the operation. These areas may function as normal program memory depending upon requirements. Stack register - STACK This is a special part of memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a similar case, if the stack is full and a CALL is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). Data memory - RAM
* Bank 0 (BP4~BP0=00000)
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0D H 0EH 0.H 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1C H 1DH 1EH 1.H 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2.H 30H 31H 32H 33H 3.H 40H ..H 40H ..H 40H ..H 80H ..H 80H ..H B a n k 1 4 D a ta M e m o ry (1 2 8 B y te ) B a n k 1 5 D a ta M e m o ry (1 2 8 B y te ) IN T C 1 TBHP TM R2 TM R2C TM R3 TM R3C X 'T A L C PW MC PW M SERC SERDATA CO L0 CO L1 CO L2 CO L3 COMR DAL DAH VO LC In te r r u p t C o n tr o l R e g is te r 1 T a b le P o in te r H ig h e r - o r d e r B y te R e g is te r T im e r 2 R e g is te r T im e r 2 C o n tr o l R e g is te r T im e r 3 R e g is te r T im e r 3 C o n tr o l R e g is te r X 't a l . a s t O s c illa t o r u p C o n t r o l PW M PW M C o n tro l D a ta IA R 0 MP0 IA R 1 MP1 BP ACC PCL TBLP TBLH W DTS STATUS IN T C 0 TM R0H TM R0L TM R0C TM R1H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PE PEC P ro g ra m In d ir e c t A d d r e s s in g R e g is te r 0 M e m o r y P o in te r 0 In d ir e c t A d d r e s s in g R e g is te r 1 M e m o r y P o in te r 1 B a n k P o in te r A c c u m u la to r C o u n te r L o w e r - b y te R e g is te r T a b le P o in te r L o w e r - o r d e r B y te R e g is te r T a b le H ig h e r - o r d e r B y te R e g is te r W a tc h d o g T im e r O p tio n S e ttin g R e g is te r S ta tu s R e g is te r In te r r u p t C o n tr o l R e g is te r 0 T im e r C o u n te r 0 H ig h e r - o r d e r B y te R e g is te r T im e r C o u n te r 0 L o w e r - o r d e r B y te R e g is te r T im e r C o u n te r 0 C o n tr o l R e g is te r T im e r /E v e n t C o u n te r 1 H ig h e r - o r d e r B y te R e g is te r T im e r /E v e n t C o u n te r 1 L o w - o r d e r B y te R e g is te r T im e r /E v e n t C o u n te r 1 C o n tr o l R e g is te r P A I/O D a ta R e g is te r P A I/O P B I/O P B I/O PC PC PD I/O I/O PD P E I/O P E I/O I/O C o n tr o l R e g is te r D a ta R e g is te r C o n tr o l R e g is te r D a ta R e g is te r C o n tr o l R e g is te r D a ta R e g is te r I/O C o n tro l D a ta R e g is te r C o n tr o l R e g is te r S p e c ia l P u r p o s e D a ta M e m o ry
S e r ia l C o n tr o l S e r ia l D a ta C o lo r 0 P a le tte s C o lo r 1 P a le tte s C o lo r 2 P a le tte s C o lo r 3 P a le tte s C o m m o n P a d A d d re s s R o ta to r D /A D a ta L o w e r - o r d e r B y te R e g is te r D /A D a ta H ig h e r - o r d e r B y te R e g is te r V o lu m e C o n tr o l R e g is te r
:U nused G e n e ra l P u rp o s e B a n k 0 D a ta M e m o ry (1 9 2 B y te ) G e n e ra l P u rp o s e B a n k 1 D a ta M e m o ry (1 9 2 B y te ) G e n e ra l P u rp o s e B a n k 1 1 D a ta M e m o ry (1 9 2 B y te )
RAM mapping
The Bank 0 data memory includes special purpose and general purpose memory. The special purpose memory is addressed from 00H to 3FH. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respectively. They are also indirectly accessible through the memory pointer registers (MP0;01H, MP1;03H).
* Bank 1~11 (BP4~BP0=0001B~1011B)
The range of RAM starting from 40H to FFH are for general purpose. Only MP1 can deal with the memory of this range.
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* Bank 14/15 (BP4~BP0=01110B~01111B)
The range of RAM starts from 80H to FFH. Every bit stands for one dot on the LCD. If the bit is 1, the light of the dot on the LCD will be turned on. If the bit is 0, then it will be turned off. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COMMON, and SEGMENT is as follows. LCD driver output The maximum output number of the HTG2190 LCD driver is 1664. The Common output signal can be selected as 16 com or 8 com by mask option. The LCD driver bias type is C type, external capacitor is required and the bias voltage is 1/4 bias. Some of the SegAddress 80H 81H 82H 83H 84H 85H D7 D6 D5 D4 SEG0~COM3 SEG0~COM7 SEG1~COM3 SEG1~COM7 SEG2~COM3 SEG2~COM7 SEG0~COM2 SEG0~COM6 SEG1~COM2 SEG1~COM6 SEG2~COM2 SEG2~COM6
ment outputs share pins with I/O pins, PE0~PE7 (SEG40~47), PD0~PD7(SEG48~55) and PC0~PC7 (SEG56~63). Whether segment output or I/O pin can be decided by mask option. LCD driver output can be enabled or disabled by setting COL3 (bit 6 of COL3; 2EH) without the influence of the related memory condition. On the Color LCD Mode: Every two bits stands for one dot on the ECB. If the both bits is not 0, the light of the dot on the ECB will be turned on. If the both bits is 0, then it will be selected to color 0. Only MP1 can be deal with the memory of this range. The contrast form of RAM location, COMMON, and SEGMENT is as follows. D3 D2 D1 D0
SEG0~COM1 SEG0~COM5 SEG1~COM1 SEG1~COM5 SEG2~COM1 SEG2~COM5
SEG0~COM0 SEG0~COM4 SEG1~COM0 SEG1~COM4 SEG2~COM0 SEG2~COM4
FAH FBH FCH FDH FEH FFH
SEG61~COM3 SEG61~COM7 SEG62~COM3 SEG62~COM7 SEG63~COM3 SEG63~COM7
SEG61~COM2 SEG61~COM6 SEG62~COM2 SEG62~COM6 SEG63~COM2 SEG63~COM6
SEG61~COM1 SEG61~COM5 SEG62~COM1 SEG62~COM5 SEG63~COM1 SEG63~COM5
SEG61~COM0 SEG61~COM4 SEG62~COM0 SEG62~COM4 SEG63~COM0 SEG63~COM4
LCD RAM mapping Bank14
Address 80H 81H 82H 83H 84H 85H
D7
D6
D5
D4
D3 SEG0~COM9
D2
D1 SEG0~COM8
D0
SEG0~COM11 SEG0~COM15 SEG1~COM11 SEG1~COM15 SEG2~COM11 SEG2~COM15
SEG0~COM10 SEG0~COM14 SEG1~COM10 SEG1~COM14 SEG2~COM10 SEG2~COM14
SEG0~COM13 SEG1~COM9 SEG1~COM13 SEG2~COM9 SEG2~COM13
SEG0~COM12 SEG1~COM8 SEG1~COM12 SEG2~COM8 SEG2~COM12
FAH FBH FCH FDH FEH FFH
SEG61~COM11 SEG61~COM15 SEG62~COM11 SEG62~COM15 SEG63~COM11 SEG63~COM15
SEG61~COM10 SEG61~COM14 SEG62~COM10 SEG62~COM14 SEG63~COM10 SEG63~COM14
SEG61~COM9 SEG61~COM13 SEG62~COM9 SEG62~COM13 SEG63~COM9 SEG63~COM13
SEG61~COM8 SEG61~COM12 SEG62~COM8 SEG62~COM12 SEG63~COM8 SEG63~COM12
LCD RAM mapping Bank15
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Register COL0 COL1 COL2 How to select the color: Dn+1 Color 0 Color 1 Color 2 Color 3 0 0 1 1 Segment3/4Common LCDC register Register Bit No. 0~4 5 COL3 6 7 Label P0~P4 3/4 LCD RC Color3 palette Unused bit, read as 0 Controls the LCD output (0=disable, 1=enable) (Default=1) LCD clock source select (Default=0) 1=32768Hz crystal 0=system clock (note*) COL3 register Note: * When the mask option is selected to 32K xtal disable, user should be set 0 to COL3.7. But the 32K xtal cant be disabled in the HT-IDE2000 tools, so user should take care of this difference. Function Dn 0 1 0 1 Address 2BH 2CH 2DH Bit No. 0~4 5~7 0~4 5~7 0~4 5~7 Label P0~P4 3/4 P0~P4 3/4 P0~P4 3/4 Description Color0 palette Unused bit read only Color1 palette Unused bit read only Color2 palette Unused bit read only
An example of an ECB driving waveform is shown below: 8 COM, 1/4 bias LCD clock source=16384Hz
8 3 /4 V D D 2 /4 V D D 1 /4 V D D GND w' 3 /4 V D D 2 /4 V D D 1 /4 V D D GND V
LCD
1 W
2
8 1
2
V
DD
COM0
V
DD
SEG
w'
C O M 0 -S E G
1 /4 V -1 /4 V -V
LCD LCD
LCD
ON
O.. 64Hz
N o t e : W ' R e a l a c t iv e s e g m e n t s ig n a l w id t h W '= 13 W2 ~ 3 1 W 32 2 B H ,2 C H ,2 D H b it0 ~ b it4 ) W : M a x . a c tiv e s e g m e n t s ig n a l w id th
( a d ju s ta b le w id th b y R A M
A d d re s s
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16COM, 1/4bias LCD clock source=32768Hz
16 3 /4 V D D 2 /4 V D D 1 /4 V D D GND w' 3 /4 V D D 2 /4 V D D 1 /4 V D D GND V
LCD
V
W
1
2
16
1
2
DD
COM0
V
DD
SEG
w'
C O M 0 -S E G
1 /4 V -1 /4 V -V
LCD LCD
LCD
ON
O.. 64Hz
N o t e : W ' R e a l a c t iv e s e g m e n t s ig n a l w id t h W '= 13 W2 ~ 3 1 W 32 2 B H ,2 C H ,2 D H b it0 ~ b it4 ) W : M a x . a c tiv e s e g m e n t s ig n a l w id th
( a d ju s ta b le w id th b y R A M
A d d re s s
On the BW LCD Mode: Bank14 has a general purpose data RAM and for Bank15, every 1 bit stands for one dot on the LCD. If the bits is not 0, the light of the dot on the LCD will be turned on. If the bits is 0, then it will be turned off. Only MP1 can deal with the memory of this range. The contrast form of RAM location, COMMON and SEGMENT is as follows: Address COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 Address COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 80H Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 C0H Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 -------------SEG17 SEG18 LCD display memory: (Bank15) ---------SEG63 C1H C2H C3H C4H C5H ---------------------------------FEH FFH 81H 82H 83H 84H 85H --------------------91H 92H ---------BFH
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An example of an LCD driving waveform is shown below. 8 COM, 1/4 bias
32Hz 1 512Hz 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5
COM0
VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
COM1
SEG0
VDD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
16 COM, 1/4 bias
32Hz 1 1024H z 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
COM0
V DD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND V DD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
COM1
SEG0
V DD 3 /4 V D D 2 /4 V D D 1 /4 V D D GND
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SSL3 x x x x x x x x SSL2 0 0 0 0 1 1 1 1 SSL1 0 0 1 1 0 0 1 1 SSL0 0 1 0 1 0 1 0 1 Description The Pad of common 0 is connected to common 0 signal and the Pad of common 1 is connected to common 1 signal and so on. The Pad of common 0 is connected to common 1 signal and the Pad of common 1 is connected to common 2 signal and so on. The Pad of common 0 is connected to common 2 signal and the Pad of common 1 is connected to common 3 signal and so on. The Pad of common 0 is connected to common 3 signal and the Pad of common 1 is connected to common 4 signal and so on. The Pad of common 0 is connected to common 4 signal and the Pad of common 1 is connected to common 5 signal and so on. The Pad of common 0 is connected to common 5 signal and the Pad of common 1 is connected to common 6 signal and so on. The Pad of common 0 is connected to common 6 signal and the Pad of common 1 is connected to common 7 signal and so on. The Pad of common 0 is connected to common 7 signal and the Pad of common 1 is connected to common 0 signal and so on. COMR register
Indirect addressing register Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and MP1 (03H) respectively. Reading location 00H or 02H indirectly returns the result 00H, while writing to it indirectly results in no operation. The data movement function between two indirect addressing registers is not supported. The memory pointer registers MP0 and MP1, are 8-bit registers used to access the data memory by combining corresponding indirect addressing registers, Bank1~Bank11, Bank14 and Bank15 can use MP1 only. Accumulator The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is the one which can operate with immediate data. The data movement between two data memory must pass through the accumulator. Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions:
* Arithmetic operations (ADD, ADC, SUB,
Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and Watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PD flags, bits in the status register can be altered by instructions like any other register. Any data written into the status register will not change the TO or PD flags. In addition, operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by a system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watchdog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status register are important and the subroutine can corrupt the status register, the programmer must take precautions to save it properly. Interrupt The HTG2190 provides external and a PWM D/A interrupt and internal timer/event counter interrupts. The interrupt control register (INTC;0BH, INTCH;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags.
SBC, DAA)
* Logic operations (AND, OR, XOR, CPL) * Rotation (RL, RR, RLC, RRC) * Increment and Decrement (INC, DEC) * Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but can also change the status register.
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Labels C Bits 0 Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. Also it is affected by a rotate through carry instruction. AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction. TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. Unused bit, read as 0 STATUS register
AC Z OV PD TO 3/4
1 2 3 4 5 6,7
Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the interrupt request flag is recorded. If a certain interrupt needs servicing within the service routine, the EMI bit and the corresponding INTC bit may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. All these kinds of interrupt have the wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter and A15~A13 bits onto the stack and then branching to subroutines at specified location(s) in the program memory. Only the program counter are pushed and A15~A13 bits onto the stack. If the contents of the register and Status register (STATUS) are altered by the interrupt service program which corrupt the desired control sequence, the contents must be saved first. External interrupt is triggered by a high to low transition of INT which sets the related interrupt request flag (EIF; bit 4 of INTC0). When the interrupt is enabled, and the stack is not full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter 0 interrupt is initialized by setting the Timer/Event Counter 0 interrupt request flag (T0F; bit 5 of INTC0), caused by a Timer/Event Counter 0 overflow. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the bit cleared to disable further interrupts.
The Timer/Event Counter 1 and timer 2/3 interrupt is operated in the same manner as Timer/Event Counter 0. The related interrupt control bits ET1I and T1F of Timer/Event Counter 1 are bit 3 and bit 6 of INTC0 respectively. While ET2I/ET3I and T2F/T3F are the related control bits and the related request flags of TMR2/TMR3, which locate at bit0/bit1 and bit4/bit5 of the INTC1 respectively. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the RETI instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source External interrupt Timer/Event Counter 0 overflow Timer/Event Counter 1 overflow Timer 2 overflow Timer 3 overflow PWM D/A interrupt Priority 1 2 3 4 5 6 Vector 04H 08H 0CH 10H 14H 18H
The Timer/Event Counter 0/1 and timer 2/3 interrupt request flag (T0F/T1F/T2F/T3F), external interrupt request flag (EIF), PWM D/A interrupt request flag (PWMF) enable timer/ event counter 0/1/2/3 bit (ET0I/ET1I/ET2I/ ET3I), enable PWM D/A interrupt bit (PWMI), enable external interrupt bit (EEI) and enable master interrupt bit (EMI) form
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Register Bit No. 0 1 2 3 INTC0 4 5 6 7 Label EMI EEI ET0I ET1I EIF T0F T1F 3/4 Function Master (Global) interrupt (1=enable; 0=disable) External interrupt (1=enable; 0=disable) Timer/Event Counter 0 interrupt (1=enable; 0=disable) Timer/Event Counter 1 interrupt (1=enable; 0=disable) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter 0 request flag. (1=active; 0=inactive) Internal Timer/Event Counter 1 request flag. (1=active; 0=inactive) Unused bit, read as 0 INTC0 register
Register
Bit No. 0 1 2 3
Label ET2I ET3I PWMI 3/4 T2F T3F PWMF 3/4
Function Controls the Timer 2 interrupt. (1=enable; 0=disable) Controls the Timer 3 interrupt. (1=enable; 0=disable) PWM D/A interrupt (1=enable; 0=disable) Should be set 0 always. Internal Timer 2 request flag. (1=active; 0=inactive) Internal Timer 3 request flag. (1=active; 0=inactive) PWM D/A flag (1=enable; 0=disable) Should be set 0 always. INTC1 register
INTC1 4 5 6 7
the interrupt control register (INTC0/INTC1) located at 0BH/1EH in the data memory. EMI, EEI, ET0I, ET1I, ET2I, ET3I, PWMI, are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt being serviced. Once the interrupt request flags (T0F, T1F, T2F, T3F, EIF, PWMF) are set, they will remain in the INTC0/INTC1 register until the interrupts are serviced or cleared by a software instruction. It is recommended that application programs do not use CALL subroutines within an interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt enable is not well controlled, once a CALL subroutine if used in the interrupt subroutine will corrupt the original control sequence. Oscillator configuration There are two oscillator circuit in the HTG2190.
OSCI X IN
The RC oscillator signal provides the internal system clock. The HALT mode stops the system oscillator and ignores any external signal to conserve power. Only the RC oscillator is designed to drive the internal system clock. The RTC oscillator provides the timer3 and LCD driver clock source. The RC oscillator needs an external resistor connected between OSCI and VSS. The resistance value must range from 50kW~400kW However, the frequency of the oscillator may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. The RTC oscillator is used to provide clock source for LCD driver and Timer3. It can be enabled or disabled by mask option. There is another oscillator circuit designed for the real time clock. In this case, only the 32768Hz crystal oscillator can be applied. The crystal should be connected between and XOUT, and two external capacitors along with one external resistor are required for the oscillator circuit in order to get a stable frequency.
32768H z RC O s c illa to r
XOUT R T C O s c illa to r
System and RTC oscillator
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The WDT oscillator is a free running on-chip RC oscillator, requiring no external components. Even if the system enters the power down mode, and the system clock is stopped, the WDT oscillator still runs with a period of approximately 78ms. The WDT oscillator can be disabled by mask option to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator). This timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by a mask option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. Once the internal WDT oscillator (RC oscillator with a nominal period of 78ms) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approximately 20 ms. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, WS0 all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds. WS2 0 0 0 0 1 1 1 1 WS1 0 0 1 1 0 0 1 1 WS0 0 1 0 1 0 1 0 1 WDTS register If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. The WDT overflow under normal operation will initialize a chip reset and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a warm re set only the PC and SP are reset to zero. To clear the contents of the WDT (including the WDT prescaler ), three methods are adopted; external reset (a low level to Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 RES), software instructions, or a HALT instruction. The software instruction is CLR WDT and execution of the CLR WDT instruction will clear the WDT. Power down operation - HALT The HALT mode is initialized by a HALT instruction and results in the following.
* The system oscillator will turn off but the WDT oscilla-
tor keeps running (if the WDT oscillator is selected).
* The contents of the on chip RAM and registers remain
unchanged.
* WDT and WDT prescaler will be cleared and recount
again.
* All I/O ports maintain their original status. * The PD flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a warm reset. By examining the TO and PD flags, the reason for the chip reset can be determined. The PD flag is cleared when the system powers-up or executing the CLR WDT instruction and is set when the HALT instruction is executed. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the PC and SP. The others maintain their original status. The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake up the device by a mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If awakening from an interrupt, two sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is enabled and the stack is not full, the regular interrupt response takes place. Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy cycle period will be inserted after a wake-up. If the wake-up results from an interrupt acknowledge, the actual interrupt subroutine will be delayed by one more cycle. If the wake-up results in next instruction execution, this will be executed immediately after a dummy period is finished. If an interrupt request
W DT OSC
W D T P r e s c a le r 8 - b it C o u n te r 7 - b it C o u n te r
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
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HTG2190
flag is set to 1 before entering the HALT mode, the wake-up function of the related interrupt will be disabled. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are 3 ways in which a reset can occur:
* RES reset during normal operation * RES reset during HALT * WDT time-out reset during normal operation
HALT W DT W DT T im e - o u t R eset W a rm R eset
VDD
RES
S S T T im e - o u t C h ip R eset
tS
ST
Reset timing chart
The WDT time-out during HALT is different from other chip reset conditions, since it can perform a warm re set that resets only the PC and SP, leaving the other circuits in their original state. Some registers remain unchanged during any other reset conditions. Most registers are reset to their initial condition when the reset conditions are met. By examining the PD flag and TO flag, the program can distinguish between different chip resets. TO 0 u 0 1 1 PD 0 u 1 u 1 RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT
RES SST 1 0 -s ta g e R ip p le C o u n te r P o w e r - o n D e te c tin g C o ld R eset
OSCI
Reset configuration When a system power up occurs, the SST delay is added during the reset period. But when the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status is shown in the table. Program Counter Interrupt Prescaler WDT Timer/Event Counter (0/1/2/3) 000H Disable Clear Clear. After master reset, WDT begins counting Off Enable
Note: u stands for unchange To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses after a system power up or when awakening from a HALT state.
V
DD
RES
LCD Display
Pull-high of TMR0/TMR1 With pull-high resistor Input/output Ports SP Input mode Points to the top of the stack
Reset circuit
The state of the registers is summarized in the following table: Register TMR1H TMR1L TMR1C TMR0H Reset (power on) xxxx xxxx xxxx xxxx 00-0 1--xxxx xxxx WDT time-out (normal operation) uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu RES reset (normal operation) uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu RES reset (HALT) uuuu uuuu uuuu uuuu 00-0 1--uuuu uuuu WDT time-out (HALT)* uuuu uuuu uuuu uuuu uu-u u--uuuu uuuu
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HTG2190
Register TMR0L TMR0C TMR2 TMR2C TMR3 TMR3C INTCH TBHP Program Counter MP0 MP1 ACC TBLP TBLH STATUS BP INTCL WDTS PA PAC PB PBC PC PWMC PWM SERC SERDATA COL0 COL1 COL2 COL3 DAL DAH VOLC PCC PD PDC PE PEC XTAL Note: Reset (power on) xxxx xxxx 00-0 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 xxxx xxxx 0000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx 0000 0000 -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 xxxx xxxx -111 1111 xxxx xxxx ---0 0000 ---0 0000 ---0 0000 0000 0000 0000 ---0000 0000 0000 ---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1100 * stands for warm reset u stands for unchange x stands for unknown - stands for unknown WDT time-out (normal operation) uuuu uuuu 00-0 1--uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1000 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu 0000 0000 -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu -111 1111 xxxx xxxx ---0 0000 ---0 0000 ---0 0000 0000 0000 0000 ---0000 0000 0000 ---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1100 RES reset (normal operation) uuuu uuuu 00-0 1--uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1000 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu 0000 0000 -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu -111 1111 xxxx xxxx ---0 0000 ---0 0000 ---0 0000 0000 0000 0000 ---0000 0000 0000 ---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1100 RES reset (HALT) uuuu uuuu 00-0 1--uuuu uuuu 00-0 1000 uuuu uuuu 00-0 1000 0000 0000 uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --01 uuuu 0000 0000 -000 0000 0000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu -111 1111 xxxx xxxx ---0 0000 ---0 0000 ---0 0000 0000 0000 0000 ---0000 0000 0000 ---1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 1100 WDT time-out (HALT)* uuuu uuuu uu-u u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu 0000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -111 1111 uuuu uuuu ---0 0000 ---0 0000 ---0 0000 0000 0000 0000 ---0000 0000 0000 ---uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 1100
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Timer/Event Counter 0/1 Two timer/event counters are implemented in the HTG2190. The Timer/Event Counter 0 and 1 contain 16-bit programmable count-up counters whose clock may come from an external source or the system clock divided by 4. It should be noted that, if the Timer/Event Counter 0 is selected, the TMR0 pin should be enabled by mask option. The pull-high resistor can be disabled or enabled by software instruction. Using the internal instruction clock, there is only one reference time-base. The external clock input allows the user to count external events, measure time intervals or pulse width, or to generate an accurate time base. There are three registers related to Timer/Event CounS y s te m TM R0 TM R1 C lo c k /4
ter 0; TMR0H (0CH), TMR0L (0DH), TMR0C (0EH). Writing to TMR0L only writes the data into a low byte buffer. Writing to TMR0H will write the data and the contents of the low byte buffer into the Timer/Event Counter 0 preload register (16-bit) simultaneously. The Timer/Event Counter 0 preload register is changed only by a write to TMR0H operation. Writing to TMR0L will keep the Timer/Event Counter 0 preload register unchanged. Reading TMR0H will also latch the TMR0L into the low byte buffer to avoid false timing problems. Reading the TMR0L only returns the value from the low byte buffer which may be a previously loaded value. In other words, the low byte of Timer/Event Counter 0 cannot be read diD a ta B u s
TM 1 TM 0
T im e r /E v e n t C o u n te r 0 /1 P r e lo a d R e g is te r
R e lo a d
TE TM 1 TM 0 TON P u ls e W id th M e a s u re m e n t M o d e C o n tro l T im e r /E v e n t C o u n te r 0 /1 O v e r flo w to In te rru p t
L o w B y te B u ffe r
Timer/Event Counter 0/1 Label 3/4 TE TON 3/4 Bits 0~2 3 4 5 Unused bit, read as 0 Defines the TMR0/TMR1 active edge of timer/event counter (0=active on low to high; 1=active on high to low) Enable/disable timer counting (0=disabled; 1=enabled) Unused bit, read as 0 Define the operating mode (TM1, TM0) 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Unused 00=Unused TMR0C/TMR1C register Label FAST RTF RTMR0 RTMR1 VDET 3/4 Bits 0 1 2 3 4 5~7 0=speed-up 32K x'tal (default) 1=Non-speed-up 32K x'tal Select the R-to-F function 0=disable R-to-F (default), 1=enable R-to-F Select the TMR0 pull-high resistor (1=with pull-high; 0=without pull-high) Select the TMR1 pull-high resistor (1=with pull-high; 0=without pull-high) Supply voltage detection circuit (1=enable VDET, 0=disable VDET) Unused bit, read as 0 X'TALC register Function Function
TM1, TM0
7, 6
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rectly. It must read the TMR0H first to ensure that the low byte contents of Timer/Event Counter 0 are latched into the buffer. There are three registers related to the Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). The Timer/Event Counter 1 operates in the same manner as Timer/Event Counter 0. The TMR0C is the Timer/Event Counter 0 control register, which defines the Timer/Event Counter 0 options. The Timer/Event Counter 1 has the same options as the Timer/Event Counter 0 and is defined by TMR1C. The timer/event counter control registers define the operating mode, counting enable or disable and active edge. The TM0, TM1 bits define the operating mode. The event count mode is used to count external events, which implies that the clock source comes from an external (TMR0/TMR1) pin. The timer mode functions as a normal timer with the clock source coming from the instruction clock. The pulse width measurement mode can be used to count the high or low level duration of an external signal (TMR0/TMR1). The counting method is based on the instruction clock. In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow occurs, the counter is reloaded from the timer/event counter preload register and generates a corresponding interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the same time. To enable the counting operation, the Timer ON bit (TON; bit 4 of TMR0C/TMR1C) should be set to 1. In the pulse width measurement mode, TON will be cleared automatically after the measurement cycle is complete. But in the other two modes TON can only be reset by instruction. The overflow of the timer/event counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to ET0I/ET1I can disable the corresponding interrupt service. In the case of a timer/event counter OFF condition, writing data to the timer/event counter preload register will also reload that data to the timer/event counter. But if the timer/event counter is turned on, data written to the timer/event counter will only be kept in the timer/event counter preload register. The timer/event counter will continue to operate until an overflow occurs. When the timer/event counter (reading TMR0H/ TMR1H) is read, the clock will be blocked to avoid errors. As this may result in a counting error, this must be taken into consideration by the programmer. Low voltage detect function (LVD) The HTG2190 provides low voltage detect to monitor the supply voltage of devices. The user can use the xtalc.4 to enable/disable (1/0) the LVD function and read the LVD detect status (0/1) from xtalc.4 otherwise, the LVD function is disabled. If the xtalc.4 is 1, means low battery otherwise if still work (VD=(V22+150mV) 100mV, VD means voltage detect value). R to F function The HTG2190 provides an R to F (Resistor to Frequency) function for temperature measurement and so on. The application circuit is shown below.
PB2 PB3 R2 R1
H TG 2190
TM R1
C
R to F application circuit
V
DD
R T M R 1 ( X 'T A L C . 3 ) 1 T o T im e r 1 M ax 0 TM R1 S1
R - . ( X 'T A L C . 1 )
R to F structure R1 is a fixed resistor about 10kW for reference, while R2 is a thermistor whose resistance is variable according to the temperature. C is a capacitance about 2200pF for charge and discharge purposes. It should be noted that, if the R to F function is selected, the pull-high resistors of TMR1. The TMR1 pull-high resistor can be disabled by software instruction. The related frequency of R1 is measured by setting PB3 to be an output pin and PB2 to be an input pin. Then set the PB3 to be a source current to charge the capacitance C. If the charged voltage ar-
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HTG2190
rives as VIH (input high voltage) of S1 gate, the NMOS will be turned on for discharge. The same manner can be used for measuring the related frequency of R2, but the roles of PB2 and PB3 should be exchanged.
V
IH
to TMR2 location; writing to TMR2 makes the starting value be placed in the Timer 2 preload register and reading the TMR2 obtains the contents of the timer 2 counter. The TMR2C is a control register, which defines the division ratio of the prescaler and counting enable or disable. Writing data to B2, B1 and B0 (bit 2, 1, 0 of TMR2C) can generate various clock source.
V
IL
Charge/discharge waveform During execution of R to F function, the TMR1 should be set as event counter to count the charge/discharge waveform. Since the falling edge of the charge/discharge waveform is sharper than the rising edge, it is recommended that the active edge of the event counter on high to low be defined by setting TE (bit 3 of TMR1C). For other detailed operation about Timer/Event Counter 1, refer to a related section of the Timer/Event Counter 0/1. An example of a software program written for the purpose of measuring related frequency of R2 is shown below. SET CLR SET CLR Mov Mov CLR CLR SET SET PBC.3 PBC.2 PB.2 XTALC.3 A, 48H TMR1C, A TMR1L TMR1H TMR1C.4 XTALC.1 ; set PB.3 to be input pin ; set PB.2 to be output pin ; output source current at PB.2 ; disable TMR1 pull-high resistor ; set TMR1 to be event counter ; and active edge on high to low ; set TMR1L and TMR1H to be 00 ; ; turn on TMR1 ; turn on R to F function
Once the timer 2 starts counting, it will count from the current contents in the counter to FFH. Once an overflow occurs, the counter is reloaded from the preload register, and generates an interrupt request flag (T2F; bit 4 of the INTCH). To enable the counting operation, the timer on bit (TON ; bit 4 of TMR2C) should be set to 1. For proper operation, bit 6 of TMR2C should be set to 1, and bit3, bit7 should be set to 0. Timer 2 can also be used as a buzzer output by setting PB.0 and AUD to be PWM1 and PWM2 output respectively by mask option. When the PWM1/PWM2 is selected, setting 2FH.6/2FH.7 to 1 will select PFD/PFDB output and setting 2FH.6/2FH.7 to 0 will select PWM1/PWM2 output. When the PFD/PFDB function is selected, setting 2FH.4/2FH.5 to 1 will enable PFD/PFDB output and setting 2FH.4/2FH.5 to 0 will disable PFD/PFDB output. PFD Frequency= T2f/ [(256-TMR2)2]. TMR2C B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 T2f SYS CLK/2 SYS CLK/4 SYS CLK/8 SYS CLK/16 SYS CLK/32 SYS CLK/64 SYS CLK/128 SYS CLK/256
TMR2C Bit4 to enable/disable timer counting (0=disable;1=enable) TMR2C Bit3, always write 0 TMR2C Bit5, always write 0 TMR2C Bit6, always write 1 TMR2C Bit7, always write 0
Timer 2/3 Timer 2 is an 8-bit counter, and its clock source come from the system clock divided by an 8-stage prescaler. There are two registers related to timer 2 ; TMR2 (21H) and TMR2C (22H). Two physical registers are mapped
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HTG2190
D a ta B u s S y s te m C lo c k 8 -s ta g e P r e s c a le r T2f TON T im e r 2 O v e r flo w T im e r 2 P r e lo a d R e g is te r R e lo a d
T o in te r r u p t 2 2 . H .5 2 . H .4 PW MDAC1 2 . H .6 PW MDAC2 2 . H .7 PW M1 PW M2
Timer 2
S y s te m C lo c k
8 S ta g e P r e s c a le r m a s k o p tio n
.0
near32768H z T3f 8 S ta g e P r e s c a le r TON 2 E H .7 * If If If If th th th th e8 e1 e8 e1 CO 6C CO 6C M B /W m o d O M B /W m o M ECB m od OM ECB mo 32 e is s d e is e is s d e is
P r e lo a d
.1 3 2 K X 'A T L
T im e r 3 L C D D r iv e r (1 0 2 4 H z ) va ev va ev lu e a lu lu e a lu of eo of eo th e f th th e f th d iv id e e d iv id d iv id e e d iv id r is 6 e r is r is 2 e r is 4. 32. . 1.
IN T
*
e le c s e le e le c s e le te d c te te d c te , th e d , th , th e d , th
Timer 3 Label SSL3~0 PFD PFDB PWM1 PWM2 Bits 3~0 4 5 6 7 Function LCD common used Enable/disable PFD output (0=disable, 1=enable) Enable/disable PFDB output (0=disable, 1=enable) Select PFDB/PWM1 output (0=PWM1, 1=PFDB) S el e c t P FD / P W M 2 o u t p u t (0=PWM2, 1=PFD) COMR register TMR3C B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 F1/2 F1/4 F1/8 F1/16 F1/32 F1/64 F1/128 F1/256 T3f F1 can select 4 frequencies by mask option Auto Mask Option System Clock near 512kHz System Clock near 1024kHz System Clock near 2048kHz System Clock near 4096kHz F0 fSYS/16 fSYS/32 fSYS/64 fSYS/128
Time base frequency = T3f / (256 - TMR3) TMR3C Bit 4 to enable/disable timer counting (0=disable; 1=enable) TMR3C Bit6, always write 1 TMR3C Bit7, always write 0 TMR3C Bit 3, always write 0 Timer 3 has the same structure and operating manner with timer 2, except for clock source and PFD function. The timer 3 can be used as a time base to generate a regular internal interrupt. The clock source of timer 3 can come from RTC OSC (X'tal 32kHz) or system clock divided by an 8-stage prescaler. If the RTC mask option is enabled, a 32kHz crystal is needed to connect across XIN and XOUT pins. The 32kHz signal is processed by an 8-stage prescaler to generate various counting clock for timer 3. There are two registers related to timer 3; TMR3 (24H) and TMR3C (25H). Writing data to B2, B1, B0 (bit 2, 1, 0 of TMR3C) can generate various counting clock. 25 July 5, 2002
Rev. 1.20
HTG2190
Input/output ports There are 39 bidirectional input/output lines in the HTG2190, labeled from PA to PE, which are mapped to the data memory of [12H], [14H], [16H], [18H], [1AH], respectively. All these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction MOV A,[m] (m=12H, 14H, 16H, 18H, 1AH). For output operation, all data is latched and remain unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PCC, PDC, PEC) which controls the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically (i.e., on-the-fly) under software control. To function as an input, the corresponding latch of the control register must write 1. The pull-high resistance will be exhibited automatically if the pull-high option is selected. The input source also depends on the control register. If the control register bit is 1 input will read the pad state. If the control register bit is 0 the contents of the latches will move to the internal bus. The latter is possible in read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H, 1BH. After a chip reset, these input/output lines stay at Schmitt trigger input with pull-high resistor. Each bit of these input/output latches can be set or cleared by the SET [m].i or CLR [m].i (m=12H, 14H, 16H, 18H, 1AH) instruction. Some instructions first input data and then follow the output operations. For example, the SET [m].i, CLR [m].i, CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator.
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r D W r ite I/O CK S Q D CK S Q
Each line of port A has a wake-up capability. PC, PD and PE can be selected as segment output by mask option. If the segment output is selected, the related I/O register (PC, PD and PE) cannot be used as a general purpose register. Reading the register will result to an unknown state. PWM interface The HTG2190 provides an 8 bit (bit7 is a sign bit) PWM D/A interface, which is good for speech synthesis. The user can record or synthesize the sound and digitize it into the program ROM. These sound could be played back in sequence of the function as designed by the internal program ROM. There are several algorithms that can be used in the HTG2190, they are PCM, mLAW, DPCM, ADPCM..... The PWM circuit provides two pad outputs: PWM2, PWM1 which can directly drive a piezo or a 32W speaker without adding any external element. Refer to the Application Circuits. The PWM clock source comes from the system clock divided by a 3-bit prescaler. Setting data to P0, P1 and P2 (bit 3, 4, 5 of 27H) can generate various clock sources. The clock source are used for PWM modulating clock and sampling clock. After setting the start bit (bit 0 of 27H) and the next falling edge coming from the prescaler, the DIV will generate a serial clock to PWM counter for modulation and PWMI for interrupt. The PWM counter latch data at the first F1 clock falling edge and the start counter at F1 rising edge. The PWM base frequency is 32kHz. For every 32kHz latch data once. The F2 clock is synchronous with the first F1 clock and it is also connected to the PWM output latch. In setting the start bit initial status, the PWM1 DAC outputs a low level and change the output status to high while the 7-bit counter overflows.
V V
DD
Q
DD
W eak P u ll- u p M a s k O p tio n PA0 PB0 PC0 PD0 PE0 ~P ,P ~P ~P ~P A7 B2~PB7 C7 D7 E7
Q
M U X
R e a d I/O S y s te m W a k e - U p ( P A o n ly ) M a s k O p tio n
Input/output ports
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BZ/SP 0 0 1 1 Note: 6/7 Bit 0 1 0 1 F1 F0 F0 F0 F0 F2 (Sampling Rate) F0/64 F0/128 F0/64 F0/128 Bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Device 32W speaker 32W speaker Buzzer/8W speaker Buzzer/8W speaker Note: 7-bit 6-bit D7 D7 D6 D6 D5 D5 D4 D4 D3 D3 D2 D2 D1 D1 D0 X
PWM data buffer X stands for dont care bit7: Sign bit
F1 for PWM modulation clock and F2 for sampling clock F0 fSYS/(n+1) n=0~7 (n:3 bits preload counter)
Serial I/O interface function The serial interface of the HTG2190 has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock. In the slave mode, the synchronous output from the external (master side) serial device is input. The master mode and slave mode are selected through registers SERC.2 and SERC.3; when the master mode is selected, a synchronous clock may be selected from among 2 types as shown in table. SERC.3 1 1 0 0 SERC.2 1 0 1 0 Mode Slave mode Master mode Master mode No used Synchronous Clock External clock SCLKS SCLKX
On the above table, we can easily see that the sampling rate is dependent on the system clock. If start bit is set to 1, the PWM2 and PWM1 will output a GND level voltage. Label PWM dis/EN BZ/SP 6/7 Bits Bits 0 1 2 Function Enable/disable PWM output 0: enable, 1: disable Output driver select 1:buzzer ; 0:speaker PWM counter bit select 1:7 bits ; 0:6 bits
P0~P2 D0, D1
3 bits preload counter 3~5 Bit543: 000B~111B (0~7) Bit3: LSB 6, 7 PWMI PWMC register D1 0 0 1 1 D0 0 1 0 1 The ratio of latch to interrupt PWM Interrupt 1 2 4 8
.0
PW M
d is /E N L a tc h .1 .2
32kH z 1 2 8 c lo c k
O n e s a m p lin g tim e
7 bits PWM counter bit
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D a ta B u s
S y s te m
c lo c k
P r e s c a le r .0 .1
P W M D a ta B u ffe r (2 8 H ) V
DD
S ta r t b it 2 7 H .0 PW MI .2
D iv .
CK PE
7 B its C o u n te r O v e r flo w
D CK Q
Q
R
P W M D A C 1 fo r 3 2 W
SPK
P W M D A C 2 fo r 3 2 W
SPK
27H.1=0 speaker
D a ta B u s
S y s te m
C lo c k
P r e s c a le r .0 .1
P W M D a ta B u ffe r (2 8 H ) V
DD
S ta r t b it 2 7 H .0 PW MI .2
D iv .
CK PE
7 - b it C o u n te r O v e r flo w
D CK Q
Q
R
S ig n b it P W M D A C 1 fo r B Z P W M D A C 2 fo r B Z
27H.1=1 buzzer SOUT is latch data at H to L by fixed mode SERC b6 0 0 0 0 1 1 1 1 b5 0 0 1 1 0 0 1 1 b4 0 1 0 1 0 1 0 1 SCLKX 16K 8K 4K 2K 1K 512 256 128 SCLKS fSYS/4 fSYS/8 fSYS/16 fSYS/32 fSYS/64 fSYS/128 fSYS/256 fSYS/512
CLK SOUT S IN PB2
At initial reset, the slave mode (external clock mode) is selected. Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as follows:
* At master mode, after output of 8 clock from the SCLK
terminal, clock output is automatically suspended and SCLK terminal is fixed at high level. * At slave mode, after input of 8 clocks to the terminal, subsequent clock inputs are masked. Serial data output By setting the parallel data to serial data registers SERDATA individually and writing 0 to SERC.0, it synchronizes with the synchronous clock and serial data is output at the SOUT terminal.
SC LK SOUT S IN PB2 CLK SOUT S IN In p u t T e r m in a l
SC LK SOUT S IN In p u t T e r m in a l
H TG 2190
E x te rn a l S e r ia l D e v ic e
H TG 2190
E x te rn a l S e r ia l D e v ic e
(a ) M a s te r m o d e
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( b ) S la v e m o d e
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HTG2190
When the output of the 8 bits data from D0~D7 is completed, the interrupt factor flag is set to 1 and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register INTC. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to 1 after output of the 8 bits data. Serial data input By writing 0 to SERC.0, the serial data is input from the SIN terminal, synchronizes with the synchronous clock, and is sequentially read in the 8 bits shift register. ;* use master mode ;* serial clock=F1/2 ;* The input data will be fetched at the rising edge (.1=0) of SCLK. When the input of the 8 bits data from D0~D7 is completed, the interrupt factor flag EIF is set to 1 and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register SERDATA. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to 1 after input of the 8 bits data.
serial serc data
equ equ equ org jmp
2Ah 29h 51h 004h serial_op
;serialdatabuffer ;serial control register ;
;serial
; ; serialap: mov mov mov set serail_I: clr mov mov wait: sz jmp set clr ret serial_op: mov mov clr ret a,data serial,a serc.0 ;enable serial ;reload data to register pb.2 wait EEI serc.0 ;trigger the serial interface start ; pbc.5 a,00000111b serc,a ;serial clock output ;SCLKX=F1/2 ;latch data (h->1) a,55h data,a serial,a pbc ;write data to serial register ;set port B I/P ;serial function testing (PA=16h)
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HTG2190
;* use slave mode ;* serial clock=external clock ;*
org jmp
004h serial_ip ;serial interrupt
; serialap: clr mov mov serial_i: set set set set clr clr set set wait: sz jmp mov mov ret serial_ip: mov mov clr reti a,serial data,a pb.2 pb.2 wait a,data pa,a ;trigger the serial interface start ;show register data to port A ; pbc.5 serc.2 serc.3 serc.1 serc.0 pbc.2 EEI pb.2 ;select salve mode ;latch data (h->1) ;enable trigger ;set pb.2 output pin ;serial clock input pac a,serial pa,a ;serial function testing (PA=16h) ;set port A O/P ;show initial data from serial buffer
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HTG2190
D B7~D B0 SD 0~SD 7 S IN D0 S e r io u s B u ffe r MSB D7 D C S0 S1 S3 Q SOUT
SEN
.CLK
C lo c k S e le c to r C lo c k C o n tro l
3 - b it C o u n te r
In te rru p t C o n tro l
IN T 0
SC LK
S ta r tin g C o n tr o l S IT R G
Serial I/O
IN P U T , S E N = 0 S IT R G SC LK S IN SD0 IN T 0 PB2 IN P U T , S E N = 1 S IT R G SC LK S IN SD0 IN T 0 PB2 OUTPUT S IT R G SC LK SD7 SOUT IN T 0 B7 B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 B7 B7 B6 B6 B5 B5 B4 B4 B3 B3 B2 B2 B1 B1 B0 B0 B7 B6 B5 B4 B3 B2 B1 B0
N o te : * B 0 ~ B 7 m e a n s 8 b its * * T h e s e r ia l d a ta tr a n s fe r fr o m
H i b it to L o w b it.
Serial data
Rev. 1.20
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July 5, 2002
HTG2190
The audio output
D a ta B u s DAH (D 0 ~ D 7 ) DAL (D 4 ~ D 7 ) VO LC (D 4 ~ D 7 ) V3~V0 C11~C0
DAC
Only 12 bits which include the high nibble of DAL and the whole byte of DAH are used. The correct procedure for DAC output as shown below, high nibble data of DAL must be written next at first, and then the DAH data is written.
AUD P IN
The HTG2190 series provide a 12-bits current type DAC devices for driving an external 8W speaker through an external NPN transistor. The programmer must write the voice data to the register DAL (30H) and DAH (31H).
There are 16 scales of volume controllable level that are provided for the current type DAC output. The programmer only writes the volume control data to the VOLC register (32H). Only the high nibble of VOLC are used. Note that writing 0H to the high nibble of VOLC does not denote mute output, this means there is still leakage from AUD pin through external NPN transistor, and also external 8W speaker leak current. Only load 00h to DAH-DAL will turn off DAC and prevent leakage.
Mask option The following shows many kinds of mask options in the HTG2190. All these option should be defined on order to ensure proper system functioning. No. 1 2 3 Mask Option WDT enable or disable selection. WDT can be enable or disable by mask option. Wake-up selection. This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the chip from a HALT mode by a following edge. External interrupt input pin share with other function selection. INT/SEG37: INT can be set as an external interrupt input pin or LCD segment output pin. I/O pins share with other functions selection. PB0/PWM1: PB0 can be set as I/O pin or positive audio PWM output pin. PWM2/AUD: PWM2 can be set as negative PWM output pin or current type D/A output pin. PB4/SOUT: PB4 can be set as I/O pin or serial data output pin. PB5/SCLK: PB5 can be set as I/O pin or serial driving clock pin. PB6/TMR1/RTF: PB6 can be set as I/O pin, Timer/Event Counter 1 input pin or resistor to frequency input pin. PB7/TMR0: PB7 can be set as I/O pin or Timer/Event Counter 0 input pin. I/O pins share with other function selection. PC0/SEG56, PC1/SEG57, PC2/SEG58, PC3/SEG59, PC4/SEG60, PC5/SEG61: PC0~PC5 can be set as I/O pins or LCD segment output pins. PC6/SEG63/XIN, PC7/SEG62/XOUT: PC6, PC7 can be set as I/O pins, LCD segment output pins or XIN, XOUT pins are connect to 32768Hz crystal. Segment output pins share with other function selection. SEG55~SEG48/PD7~PD0: SEG55~SEG48 can be set as LCD segment output pins or I/O pins. SEG47~SEG40/PE7~PE0: SEG47~SEG40 can be set as LCD segment output pins or I/O pins LCD common selection. There are two types of selection: 8-common or 16-common LCD type selection. There are two types of selection: black/white LCD or color ECB
4
5
6 7 8
Rev. 1.20
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HTG2190
Application Circuits
32 s p e a k e r /b u z z e r a p p lic a tio n 8 s p e a k e r a p p lic a tio n
(fS
YS
** 62kW =4M H z)
OSCI CO M 0~15 SEG 0~63 (M a x .)
LCD PANEL
(fS
YS
** 62kW =4M H z)
OSCI CO M 0~15 SEG 0~63 (M a x .)
DD
LCD PANEL
V
DD
P W M 1 /P B 0 32W SPK orB uzzer P W M 2 /A U D RES 30kW PB2 PB3 30kW 2200p. 0 .1 m .
V
30kW PB2 PB3 P B 6 /T M R 1 RES 30kW 2200p.
0 .1 m .
PA0~PA7 V
DD
*
P B 6 /T M R 1 X IN /S E G 6 3 /P C 7
*
X IN /S E G 6 3 /P C 7 8W SPK 8050
X O U T /S E G 6 2 /P C 6
X O U T /S E G 6 2 /P C 6 PW M 2 /A U D
2kW 0 .1 m .
IN T /S IN P B 7 /T M R 0
PA0~PA7 P B 5 /S C L K P B 4 /S O U T CAP1 CAP2
IN T /S IN P B 7 /T M R 0 P B 5 /S C L K P B 4 /S O U T
0 .1 m .
CAP1 CAP2 CAP3 CAP4 VO UT11 VO UT22 VO UT33 VO UT44
0 .1 m .
0 .1 m .
CAP3 CAP4
VO UT11 VO UT22 VO UT33 VO UT44
0 .1 m . 0 .1 m . 0 .1 m . 0 .1 m .
0 .1 m .
0 .1 m . 0 .1 m . 0 .1 m . 0 .1 m .
HTG 2190
HTG 2190
Note: * Optional capacitors can be added to get a more accurate frequency. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate value of external capacitors. ** R=100kW, fSYS=2MHz R=200kW, fSYS=1MHz
Rev. 1.20
33
July 5, 2002
HTG2190
Instruction Set Summary
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add data memory to ACC Add ACC to data memory Add immediate data to ACC Add data memory to ACC with carry Add ACC to data memory with carry Subtract immediate data from ACC Subtract data memory from ACC Subtract data memory from ACC with result in data memory Subtract data memory from ACC with carry Subtract data memory from ACC with carry and result in data memory Decimal adjust ACC for addition with result in data memory 1 1(1) 1 1 1(1) 1 1 1(1) 1 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV C Description Instruction Cycle Flag Affected
Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC Complement data memory Complement data memory with result in ACC 1 1 1 1(1) 1(1) 1(1) 1 1 1 1(1) 1 Z Z Z Z Z Z Z Z Z Z Z
Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Clear bit of data memory Set bit of data memory 1(1) 1(1) None None Move data memory to ACC Move ACC to data memory Move immediate data to ACC 1 1(1) 1 None None None Rotate data memory right with result in ACC Rotate data memory right Rotate data memory right through carry with result in ACC Rotate data memory right through carry Rotate data memory left with result in ACC Rotate data memory left Rotate data memory left through carry with result in ACC Rotate data memory left through carry 1 1(1) 1 1(1) 1 1(1) 1 1(1) None None C C None None C C Increment data memory with result in ACC Increment data memory Decrement data memory with result in ACC Decrement data memory 1 1(1) 1 1(1) Z Z Z Z
Rev. 1.20
34
July 5, 2002
HTG2190
Mnemonic Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear data memory Set data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of data memory Swap nibbles of data memory with result in ACC Enter power down mode 1 1(1) 1(1) 1 1 1 1(1) 1 1 None None None TO,PD TO(4),PD(4) TO(4),PD(4) None None TO,PD Read ROM code (current page) to data memory and TBLH Read ROM code (last page) to data memory and TBLH 2(1) 2(1) None None Jump unconditionally Skip if data memory is zero Skip if data memory is zero with data movement to ACC Skip if bit i of data memory is zero Skip if bit i of data memory is not zero Skip if increment data memory is zero Skip if decrement data memory is zero Skip if increment data memory is zero with result in ACC Skip if decrement data memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) 2 2 2 2 None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
x: Immediate data m: Data memory address A: Accumulator i: 0~7 number of bits addr: Program memory address O: Flag is affected -: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). : If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more cycle (four system clocks). Otherwise the original instruction cycle is unchanged. : and (2)
(2)
(3) (1) (4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PD are cleared. Otherwise the TO and PD flags remain unchanged.
Rev. 1.20
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July 5, 2002
HTG2190
Instruction Definition
ADC A,[m] Description Operation Affected flag(s) TC2 3/4 ADCM A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,[m] Description Operation Affected flag(s) TC2 3/4 ADD A,x Description Operation Affected flag(s) TC2 3/4 ADDM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Add data memory and carry to the accumulator The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. ACC ACC+[m]+C
Add the accumulator and carry to data memory The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. [m] ACC+[m]+C
Add data memory to the accumulator The contents of the specified data memory and the accumulator are added. The result is stored in the accumulator. ACC ACC+[m]
Add immediate data to the accumulator The contents of the accumulator and the specified data are added, leaving the result in the accumulator. ACC ACC+x
Add the accumulator to the data memory The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. [m] ACC+[m]
Rev. 1.20
36
July 5, 2002
HTG2190
AND A,[m] Description Operation Affected flag(s) TC2 3/4 AND A,x Description Operation Affected flag(s) TC2 3/4 ANDM A,[m] Description Operation Affected flag(s) TC2 3/4 CALL addr Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical AND accumulator with data memory Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND [m]
Logical AND immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_AND operation. The result is stored in the accumulator. ACC ACC AND x
Logical AND data memory with the accumulator Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory. [m] ACC AND [m]
Subroutine call The instruction unconditionally calls a subroutine located at the indicated address. The program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. The indicated address is then loaded. Program execution continues with the instruction at this address. Stack PC+1 PC addr
Operation Affected flag(s)
TC2 3/4 CLR [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Clear data memory The contents of the specified data memory are cleared to 0. [m] 00H
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
37
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HTG2190
CLR [m].i Description Operation Affected flag(s) TC2 3/4 CLR WDT Description Operation Affected flag(s) TC2 3/4 CLR WDT1 Description TC1 3/4 TO 0 PD 0 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Clear bit of data memory The bit i of the specified data memory is cleared to 0. [m].i 0
Clear Watchdog Timer The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are cleared. WDT 00H PD and TO 0
Preclear Watchdog Timer Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CLR WDT2 Description
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Preclear Watchdog Timer Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PD flags remain unchanged. WDT 00H* PD and TO 0*
Operation Affected flag(s)
TC2 3/4 CPL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 0*
PD 0*
OV 3/4
Z 3/4
AC 3/4
C 3/4
Complement data memory Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. [m] [m]
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Rev. 1.20
38
July 5, 2002
HTG2190
CPLA [m] Description Complement data memory and place result in the accumulator Each bit of the specified data memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged. ACC [m]
Operation Affected flag(s)
TC2 3/4 DAA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z O
AC 3/4
C 3/4
Decimal-Adjust accumulator for addition The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored in the data memory and only the carry flag (C) may be affected. If ACC.3~ACC.0 >9 or AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 and If ACC.7~ACC.4+AC1 >9 or C=1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s) TC2 3/4 DEC [m] Description Operation Affected flag(s) TC2 3/4 DECA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Decrement data memory Data in the specified data memory is decremented by 1. [m] [m]-1
Decrement data memory and place result in the accumulator Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]-1
Rev. 1.20
39
July 5, 2002
HTG2190
HALT Description Enter power down mode This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is cleared. PC PC+1 PD 1 TO 0
Operation
Affected flag(s) TC2 3/4 INC [m] Description Operation Affected flag(s) TC2 3/4 INCA [m] Description Operation Affected flag(s) TC2 3/4 JMP addr Description Operation Affected flag(s) TC2 3/4 MOV A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 0 PD 1 OV 3/4 Z 3/4 AC 3/4 C 3/4
Increment data memory Data in the specified data memory is incremented by 1 [m] [m]+1
Increment data memory and place result in the accumulator Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. ACC [m]+1
Directly jump The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. PC addr
Move data memory to the accumulator The contents of the specified data memory are copied to the accumulator. ACC [m]
Rev. 1.20
40
July 5, 2002
HTG2190
MOV A,x Description Operation Affected flag(s) TC2 3/4 MOV [m],A Description Operation Affected flag(s) TC2 3/4 NOP Description Operation Affected flag(s) TC2 3/4 OR A,[m] Description Operation Affected flag(s) TC2 3/4 OR A,x Description Operation Affected flag(s) TC2 3/4 ORM A,[m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Move immediate data to the accumulator The 8-bit data specified by the code is loaded into the accumulator. ACC x
Move the accumulator to data memory The contents of the accumulator are copied to the specified data memory (one of the data memories). [m] ACC
No operation No operation is performed. Execution continues with the next instruction. PC PC+1
Logical OR accumulator with data memory Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR [m]
Logical OR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical_OR operation. The result is stored in the accumulator. ACC ACC OR x
Logical OR data memory with the accumulator Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. [m] ACC OR [m]
Rev. 1.20
41
July 5, 2002
HTG2190
RET Description Operation Affected flag(s) TC2 3/4 RET A,x Description Operation Affected flag(s) TC2 3/4 RETI Description Operation Affected flag(s) TC2 3/4 RL [m] Description Operation Affected flag(s) TC2 3/4 RLA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Return from subroutine The program counter is restored from the stack. This is a 2-cycle instruction. PC Stack
Return and place immediate data in the accumulator The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. PC Stack ACC x
Return from interrupt The program counter is restored from the stack, and interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit. PC Stack EMI 1
Rotate data memory left The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 [m].7
Rotate data memory left and place result in the accumulator Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7
Rev. 1.20
42
July 5, 2002
HTG2190
RLC [m] Description Operation Rotate data memory left through carry The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position. [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) [m].0 C C [m].7
Affected flag(s) TC2 3/4 RLCA [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate left through carry and place result in the accumulator Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 C C [m].7
Operation
Affected flag(s) TC2 3/4 RR [m] Description Operation Affected flag(s) TC2 3/4 RRA [m] Description Operation Affected flag(s) TC2 3/4 RRC [m] Description Operation TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Rotate data memory right The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 [m].0
Rotate right and place result in the accumulator Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 [m].0
Rotate data memory right through carry The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m].7 C C [m].0
Affected flag(s) TC2 3/4 Rev. 1.20 TC1 3/4 TO 3/4 PD 3/4 43 OV 3/4 Z 3/4 AC 3/4 C O July 5, 2002
HTG2190
RRCA [m] Description Rotate right through carry and place result in the accumulator Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator. The contents of the data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit i of the data memory (i=0~6) ACC.7 C C [m].0
Operation
Affected flag(s) TC2 3/4 SBC A,[m] Description Operation Affected flag(s) TC2 3/4 SBCM A,[m] Description Operation Affected flag(s) TC2 3/4 SDZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C O
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator. ACC ACC+[m]+C
Subtract data memory and carry from the accumulator The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory. [m] ACC+[m]+C
Skip if decrement data memory is 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, [m] ([m]-1)
Operation Affected flag(s)
TC2 3/4 SDZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Decrement data memory and place result in ACC, skip if 0 The contents of the specified data memory are decremented by 1. If the result is 0, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]-1)=0, ACC ([m]-1)
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
44
July 5, 2002
HTG2190
SET [m] Description Operation Affected flag(s) TC2 3/4 SET [m]. i Description Operation Affected flag(s) TC2 3/4 SIZ [m] Description TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 Set data memory Each bit of the specified data memory is set to 1. [m] FFH
Set bit of data memory Bit i of the specified data memory is set to 1. [m].i 1
Skip if increment data memory is 0 The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, [m] ([m]+1)
Operation Affected flag(s)
TC2 3/4 SIZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Increment data memory and place result in ACC, skip if 0 The contents of the specified data memory are incremented by 1. If the result is 0, the next instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if ([m]+1)=0, ACC ([m]+1)
Operation Affected flag(s)
TC2 3/4 SNZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is not 0 If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i0
Operation Affected flag(s)
TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
45
July 5, 2002
HTG2190
SUB A,[m] Description Operation Affected flag(s) TC2 3/4 SUBM A,[m] Description Operation Affected flag(s) TC2 3/4 SUB A,x Description Operation Affected flag(s) TC2 3/4 SWAP [m] Description Operation Affected flag(s) TC2 3/4 SWAPA [m] Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z 3/4 AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O TC1 3/4 TO 3/4 PD 3/4 OV O Z O AC O C O Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+[m]+1
Subtract data memory from the accumulator The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory. [m] ACC+[m]+1
Subtract immediate data from the accumulator The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ACC+x+1
Swap nibbles within the data memory The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory and place result in the accumulator The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Rev. 1.20
46
July 5, 2002
HTG2190
SZ [m] Description Skip if data memory is 0 If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZA [m] Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move data memory to ACC, skip if 0 The contents of the specified data memory are copied to the accumulator. If the contents is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m]=0
Operation Affected flag(s)
TC2 3/4 SZ [m].i Description
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Skip if bit i of the data memory is 0 If bit i of the specified data memory is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle). Skip if [m].i=0
Operation Affected flag(s)
TC2 3/4 TABRDC [m] Description Operation Affected flag(s) TC2 3/4 TABRDL [m] Description Operation Affected flag(s) TC2 3/4
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (current page) to TBLH and data memory The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved to the specified data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Move the ROM code (last page) to TBLH and data memory The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. [m] ROM code (low byte) TBLH ROM code (high byte)
TC1 3/4
TO 3/4
PD 3/4
OV 3/4
Z 3/4
AC 3/4
C 3/4
Rev. 1.20
47
July 5, 2002
HTG2190
XOR A,[m] Description Operation Affected flag(s) TC2 3/4 XORM A,[m] Description Operation Affected flag(s) TC2 3/4 XOR A,x Description Operation Affected flag(s) TC2 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 TC1 3/4 TO 3/4 PD 3/4 OV 3/4 Z O AC 3/4 C 3/4 Logical XOR accumulator with data memory Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator. ACC ACC XOR [m]
Logical XOR data memory with the accumulator Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected. [m] ACC XOR [m]
Logical XOR immediate data to the accumulator Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected. ACC ACC XOR x
Rev. 1.20
48
July 5, 2002
HTG2190
Package Information
128-pin QFP (1420) outline dimensions
C D 102 65 G I 103 64 H
.
A B
E
128
39
K 1 38 = J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 17.00 13.90 23.00 19.90 3/4 3/4 2.50 3/4 3/4 0.65 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.50 0.20 3/4 3/4 0.10 3/4 3/4 3/4 Max. 17.50 14.10 23.50 20.10 3/4 3/4 3.10 3.40 3/4 0.95 0.20 7
Rev. 1.20
49
July 5, 2002
HTG2190
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com
Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
50
July 5, 2002

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