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| 2M x 8 SRAM MODULE SYS82000RKXD - 85/10/12 Issue 1.4 : April 2001 Description The SYS82000RKXD is a plastic 16Mbit Static RAM Module housed in a standard 36 pin Single-InLine package organised as 2M x 8. This offers an extremely high PCB packing density. The module is constructed using four 512Kx8 SRAMs in TSOPII packages mounted on a FR4 epoxy substrate. Access times are 85, 100 and 120ns. The SYS82000RKXD is offered in standard and low power versions, with the -L module having a low voltage data retention mode for battery backed applications. Features * Access Times of 85/100/120ns. * 36 Pin Industry Standard Single-In-Line package. * 5 Volt Supply 10% . * Power Dissipation : Operating (min cycle) Standby -L Version (CMOS) * Completely Static Operation. * Equal Access and Cycle Times. * Low Voltage VCC Data Retention. * Directly TTL Compatible. * On-board Decoding & Capacitors. * Compatible with the SYS8512RKX, SYS81000RKXB and SYS82000RKX modules. 610 mW (max). 2.2 mW (max). Block Diagram A0~A18 D0~7 /WE /OE Pin Definition A20 Vcc WE D2 D3 D0 A1 A2 A3 A4 GND D5 A10 A11 A5 A13 A14 A19 CS A15 A16 A12 A18 A6 D1 GND A0 A7 A8 A9 D7 D4 D6 A17 Vcc OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM 512K x 8 SRAM /CS /CS /CS /CS /CS A19 A20 Decoder Pin Functions Address Inputs Data Input/Output Chip Select Write Enable Output Enable No Connect Power (+5V) Ground A0 - A20 D0 - D7 CS WE OE NC VCC GND Package Details Plastic 36 Pin Single-In-Line (SIP) SYS82000RKXD - 70/85/10/12 Issue 1.3 February 2000 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Voltage on any pin relative to VSS Power Dissipation Storage Temperature Symbol VT PT TSTG (2) Min -0.3 -55 Typ 4.0 - Max 7.0 125 Unit V W o C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature Symbol VCC VIH VIL TA TAI Min 4.5 2.2 -0.3 0 -40 Typ 5.0 - Max 5.5 VCC+0.3 0.8 70 85 Unit V V V o C o C (Commercial) (Industrial) DC Electrical Characteristics (VCC=5V10%) TA 0 to 70 oC Parameter I/P Leakage Current Symbol Test Condition Address,OE,WE Min Typ -4 -4 2.4 - max Unit 4 4 110 12 8 400 0.4 A A mA mA mA A V V ILI ILO ICC1 0V < VIN < VCC CS = VIH, VI/O = GND to VCC Min. Cycle, CS = VIL,VIL TTL levels CMOS levels -L Version (CMOS) ISB1 ISB2 ISB3 VOL VOH Output Voltage Typical values are at VCC=5.0V,TA=25oC and specified loading. Capacitance (VCC=5V10%,TA=25oC) Note: Capacitance calculated, not measured. Parameter Input Capacitance (Address,OE,WE) I/P Capacitance (other) I/O Capacitance Symbol Test Condition CIN1 CIN2 CI/O VIN = 0V VIN = 0V VI/O = 0V max 32 8 40 Unit pF pF pF 2 SYS82000RKXD - 70/85/10/12 Issue 1.3 February 2000 AC Test Conditions Output Load * Input pulse levels: 0V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC=5V10% I/O Pin 645 1.76V 100pF Operation Truth Table CS H L L L L OE X L H L H WE X H L L H DATA PINS High Impedance Data Out Data In Data In High-Impedance SUPPLY CURRENT ISB1 , ISB2 , ISB3 ICC1 ICC1 ICC1 ISB1 , ISB2 , ISB3 MODE Standby Read Write Write High-Z Notes : H = VIH : L =VIL : X = VIH or VIL Low Vcc Data Retention Characteristics - L Version Only Parameter VCC for Data Retention Data Retention Current Symbol V DR Test Condition CS > VCC-0.2V VCC = 3.0V, CS > VCC-0.2V TOP = 0C to 40C See Retention Waveform See Retention Waveform min 2.0 0 5 typ(1) - max 220 - Unit V A ns ms ICCDR1 (2) Chip Deselect to Data Retention Time t CDR Operation Recovery Time tR Notes (1) Typical figures are measured at 25C. (2) This parameter is guaranteed not tested. 3 SYS82000RKXD - 70/85/10/12 Issue 1.3 February 2000 AC OPERATING CONDITIONS Read Cycle Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to O/P in High Z Output Disable to Output in High Z Symbol t RC tAA tACS tOE t OH tCLZ tOLZ t CHZ t OHZ -85 min max 85 10 10 5 0 0 85 85 45 30 30 -10 min max 100 10 10 5 0 0 100 100 50 35 35 -12 min max 120 10 10 5 0 0 120 120 60 45 45 Unit ns ns ns ns ns ns ns ns ns Write Cycle Parameter Write Cycle Time Chip Selection to End of Write Address Valid to End of Write Address Setup Time Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output active from end of write Symbol t WC t CW t AW tAS t WP t WR t WHZ t DW t DH t OW -85 min max 85 75 75 0 55 3 0 35 0 5 30 - - 10 min max 100 80 80 0 60 3 0 40 0 5 35 - -12 min max 120 100 100 0 70 3 0 45 0 5 40 - Unit ns ns ns ns ns ns ns ns ns ns 4 SYS82000RKXD - 70/85/10/12 Issue 1.3 February 2000 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OLZ t OH CS t ACS t CLZ (4,5) t OHZ (3) Don't care. Dout Data Valid t CHZ (3,4,5) AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform(1,4) tWC Address t WR(7) OE t AS(6) t AW t CW CS Don't Care WE t OHZ(3,9) t WP(2) High-Z t DW t DH t OW (8) Dout High-Z Din Data Valid 5 SYS82000RKXD - 70/85/10/12 Issue 1.3 February 2000 Write Cycle No.2 Timing Waveform (1,5) tWC Address t AS(6) t CW t WR(7) CS t AW t WP(2) WE t WHZ(3,9) t OW High-Z t DW tOH (8) (4) Don't Care Dout High-Z t DH Din Data Valid AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS and WE low. (3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes. (7) CS or WE must be high during address transitions. (8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. Data Retention Waveform Vcc 4.5V DATA RETENTION MODE 4.5V t CDR 2.2V tR 2.2V V DR CS > Vcc -0.2V 0V CS 6 SYS82000RKXD - 70/85/10/12 Issue 1.3 February 2000 Package Information Dimensions in mm Plastic 36 Pin Single-In-Line (SIP) 97.20 MAX 3.40 MAX 15.70 MAX 1 1.00 3.50 +/- 0.50 0.50 Typ. 2.54 Typ. Ordering Information SYS82000RKXDLI-85 Speed 85 = 85 ns 10 = 100 ns 12 = 120 ns Temperature Range Blank = Commercial Temperature I = Industrial Temperature Blank = Standard Part L = Low Power Part RKXD = Plastic 36 Pin Single-In-Line (SIP) 82000 = 2M x 8 SYS = Static RAM Power Consumption Package Organization Memory Type Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 7 |
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