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Programmable Penta ULDO with RESET and I2C Interface
POWER MANAGEMENT Description
The SC900 is a highly integrated power management device for low power portable applications. The device contains five adjustable low-dropout linear regulators (LDOs) with CMOS pass-devices as well as a band-gap reference, I2C interface, and DACs to control the output voltages. Many features of the SC900 are programmable through the I2C interface. These include the ability to independently turn on any combination of the five regulators. All five of the LDO output voltages are programmable in 50mV steps from 1.45V to 3.00V. Each LDO can have an active shutdown or nonactive shutdown program option through the interface. There is also a reset monitor flag that is associated with LDOA. In addition, the device has a separate programmable power-good monitor flag that activates when one or more LDOs go out of regulation. The SC900 offers significant quiescent current and space savings to the system designer by sharing reference and biasing among five LDOs. The small and thermally efficient 20-lead MLPQ package make it ideal for use in portable products where minimizing layout area is critical.
SC900
Features
! ! ! ! ! ! ! ! ! ! ! ! !
Five LDO regulators in one package I2C interface with multiple device capability Independent I2C enable/disable of LDOs Independent I2C control of output voltages Low thermal impedance of 40C per watt 150mV dropout at 150mA Input range from 2.7V to 5.5V Programmable power-good flag Minimal number of external components Over temperature protection Small 4mm x 4mm 20-lead MLPQ package Small input/output filter capacitors Programmable VOUT range - 1.45V to 3.00V for each LDO
Applications
! ! ! ! !
Palmtop/Laptop computers Personal Digital Assistants Cellular telephones Battery-powered equipment High efficiency linear power supplies
Typical Application Circuit
SC900
LDOE LDOD VIN INA 4.7F VBAT INB INCD INE EN LDOPGD ARST SDA SCL A0 GND VASEL DGND Keypad Digital Interface 2.2F Audio Processing 0.1F VREF LDOA LDOB LDOC 2.2F 2.2F 2.2F 2.2F
Baseband Processor
Receiver Section
LNA
TXCO & Synthesizer Transmitter Section PA
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SC900
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Input Supply Voltage Digital Input Voltage Operating Ambient Temperature Range Operating Junction Temperature Range Peak IR Reflow Temperature Storage Temperature Thermal Resistance Junction to Ambient
*1 Square inch, 2 ounce copper.
Symbol VIN VDIG TA TJ TLEAD TSTG J A
Maximum -0.3 to +7 -0.3 to VIN+0.3 -40 to +85 -40 to +125 260 -60 to +150 * 40
Units V V C C C C C/W
Electrical Characteristics
Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85C. Typical values are at TA = +25C.
Parameter General Supply Voltage Quiescent Current Shutdown Supply Bypass Capacitor Digital Inputs Digital Input Voltage
Symbol
Condition
Min
Typ
Max
Units
VIN IQ-SHUTDOWN C VC C
All outputs < VIN - dropout
2.7
5.5 10
V A F
Per input pin
1
VIL VIH 1.6 -0.2
0.4
V V
Digital Input Current Digital Outputs Digital Output Voltage(1)
IDIG
0.2
A
VOL VOH
ISINK = 1.2mA, VLDOB 1.8V ISOURCE = 0.5mA, VLDOB 1.8V 90
2 98
10
% LDOB % LDOB
Reference and Biasing Circuitry Quiescent Current Reference Reference Voltage VREF Start-up Time IQ-REF VREF tVREF CVREF= 100nF 25 1.227 15 A V ms
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SC900
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85C. Typical values are at TA = +25C.
Parameters
Symbol
Conditions
Min
Typ
Max
Units
Reference and Biasing Circuitry (cont.) VREF Bypass Capacitor LDO Regulators Quiescent Supply Current Quiescent Supply Current at Start-up Dropout Voltage LDO B,C,D,E VD LD O A Current Limit Power Supply Rejection Ratio ILIM PSRR f = 10Hz -1kHz, CBYP = 0.1F, IOUT = 50mA 2.5V < VOUT < 3.0V f =10Hz to 100kHz, IOUT= 50mA CVREF = 0.1F, COUT = 2.2F 2.5V VOUT 3.0V Ceramic, low ESR 2.2 IQ IQSUP All LDOs active in default states LDO A, B, C active in default states VOUT + 0.5V < VIN < 5.5V VOUT = 3.0V, IOUT = 1mA VOUT = 3.0V, IOUT= 50mA VOUT = 3.0V, IOUT= 150mA VOUT = 3.0V, IOUT = 200mA 250 190 125 1.1 50 150 200 410 60 360 A A CVREF 0.1 F
64 190 250 650
mV
mA dB
Output Voltage Noise(2) Bypass Capacitor LDO Regulator A (CORE SUPPLY) Output Voltage Accuracy
en CBYP
45
Vrms F
VOAA
1.45V VOUT 3.00V VOUT+0.2V VIN 5.5V IOUT = 1mA, TA = 25OC IOUT = 1mA
-3
+3
%
Output Voltage Accuracy at 2.80V (DAC=11011) Output Voltage Accuracy at 1.80V (DAC=00111) Output Voltage Accuracy at 2.80V (DAC=11011) Maximum Output Current Default Setting: ON IOMAXA VOA-HI VOA-LO Line Regulation at 1.8V, 2.8V Load Regulation at 1.8V, 2.8V LINEREGA LOADREGA VOASA
-2 -3 -3.5 200
+2 +3 +3.5
% % % mA
IOUT = 1mA, TA = 25OC IOUT= 200mA, VOUT+0.5V VIN 5.5V
VASEL - High VASEL - Low IOUT = 1mA, VOUT+0.2V < VIN< 5.5V 1mA < IOUT < 200mA
2.80 1.80 2.5 -3 12 -20
V V mV mV
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SC900
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85C. Typical values are at TA = +25C.
Parameter
Symbol
Condition
Min
Typ
Max
Units
LDO Regulator B (DIGITAL I/O SUPPLY) Output Voltage Accuracy VOAB 1.45V VOUT 3.00V VOUT+0.15V VIN 5.5V IOUT = 1mA, TA = 25OC IOUT = 1mA IOUT = 150mA, VOUT +0.5V VIN 5.5V -3 -2 -3.5 150 2.80 IOUT = 1mA, VOUT +0.15V VIN 5.5V 1mA < IOUT <150mA 2.5 -3 12 -20 +3 +2 +3.5 % % % mA V mV mV
Output Voltage Accuracy at 2.80V (DAC=11011) Maximum Output Current Default Setting: ON Line Regulation 2.80V Load Regulation at 2.80V LDO Regulator C Output Voltage Accuracy
VOASB IOMAXB VOB LINEREGB LOADREGB
VOAC
1.45V VOUT 3.00V VOUT+0.15V VIN 5.5V IOUT = 1mA, TA = 25OC IOUT = 1mA IOUT = 150mA, VOUT+0.5V VIN 5.5V
-3 -2 -3.5 150 2.60
+3 +2 +3.5
% % % mA V
Output Voltage Accuracy at 2.60V (DAC=10111) Maximum Output Current Default Setting: ON Line Regulation at 2.60V Load Regulation at 2.60V LDO Regulator D Output Voltage Accuracy
VOASC IOMAXC VOC LINEREGC LOADREGC
IOUT = 1mA, VOUT+0.15V < VIN < 5.5V 1mA < IOUT <150mA
2.5 -3
12 -20
mV mV
VOAD VOASD
1.45V VOUT 3.00V VOUT+0.15V VIN 5.5V IOUT = 1mA, TA = 25OC IOUT = 1mA IOUT = 150mA, VOUT+0.5V VIN 5.5V
-3 -2 -3.5 150 2.80
+3 +2 +3.5
% % % mA V
Output Voltage Accuracy at 2.80V (DAC=11011) Maximum Output Current Default Setting: OFF Line Regulation at 2.80V Load Regulation at 2.80V
IOMAXD VOD LINEREGD LOADREGD IOUT = 1mA, VOUT+0.15V < VIN < 5.5V 1mA < IOUT <150mA
2.5 -3
12 -20
mV mV
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SC900
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85C. Typical values are at TA = +25C.
Parameter LDO Regulator E Output Voltage Accuracy Output Voltage Accuracy at 2.80V (DAC=11011) Maximum Output Current Default Setting: OFF Line Regulation at 2.80V Load Regulation at 2.80V
Symbol
Condition
Min
Typ
Max
Units
VOAE
1.45V < VOUT < 3.00V VOUT +0.15V < VIN < 5.5V IOUT = 1mA, TA = 25OC IOUT = 1mA IOUT = 150mA, VOUT + 0.5V < VIN < 5.5V
-3 -2 -3.5 150 2.80
+3 +2 +3.5
% % % mA V
VOASE
IOMAXE VOE LINEREGE LOADREGE IOUT = 1mA, VOUT +0.15V < VIN < 5.5V 1mA < IOUT < 150mA
2.5 -3
12 -20
mV mV
I2C Interface Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January 2000. Digital Input Voltage VIL 0.4 1.6 IDIN(SDA) = 3mA IDIN(SDA) = 6mA IDG CIN -0.2 10 0.4 0.6 0.2 V V V V A pF
VIH
SDA Output Low Level Digital Input Current I/O Pin Capacitance I2C Timing Clock Frequency SCL Low Period SCL High Period Data Hold Time Data Setup Time Setup Time for Repeated Start Condition Hold Time for Repeated Start Condition SetupTime for Stop Condition Bus-Free Time Between STOP and START SC L tLOW tHIGH tHD_DAT
400 1.3 0.6 0 100 0.6 0.6 0.6 1.3
kHz s s s ns s s s s
tSU_DAT
tSU_STA tHD_STA tSU_STO tBUF
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SC900
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise noted: VIN = 3.7V, EN = VIN, TA = -40 to 85C. Typical values are at TA = +25C.
Parameter A R ESET Reset Threshold Reset Active Timeout Delay LDO POWER GOOD PGOOD Threshold PGOOD Active Timeout Delay
Symbol
Condition
Min
Typ
Max
Units
RESETTHLD tRD Delay in default state 75
77 100 125
% ms
PGOODTHLD tPG Delay in default state 75
77 100 125
% ms
Notes: (1) Digital outputs are powered from LDOB, so LDOB must be active for operation of LDOPGD and ARST. (2) Below 2.5V: becomes digital regulator.
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SC900
POWER MANAGEMENT Pin Configuration
LDOC INCD LDOD LDOA INA
Ordering Information
DEVICE SC900IMLTRT(2) S C 900E V B PACKAGE(1) MLPQ20L Evaluation Board
20
19
18
17
16 15
LDOB INB SDA SCL EN
1 2 3 4 5 6 7 T 8 9 10
LDOE INE VIN GND VREF
TOP VIEW
Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in Lead-free package only. This product is fully WEEE and RoHS compliant.
14 13 12 11
LDOPGD
VASEL
DGND
MLPQ20: 4X4 20 LEAD
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ARST
A0
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SC900
POWER MANAGEMENT Pin Description
Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T Pin Name LDOB INB SD A SC L EN A0 DGND VASEL LDOPGD ARST VREF GND VIN INE LDOE LDOD INCD LDOC INA LDOA Thermal Pin Function LDO B output. Input supply for the digital system logic and the LDO B pass transistor. Bidirectional open drain digital I/O pin. I2C serial data. Digital input. I2C serial clock. Digital input. High to enable part. Low to disable part (sleep mode). Note I2C control is active only when part is enabled. One bit address for connecting two SC900 devices onto the system through the I2C interface. Digital ground. LDO A selection default voltage. Tie this pin to ground for 1.8V or INB for 2.8V. Digital output. State change indicates that one of four LDO output voltages (A,C,D or E) is out of spec. Note, desired state of pin is programmable through the I2C interface. Digital output. State change indicates LDOA output voltage is out of spec. Note; desired state of pin is programmable through the I2C interface. Bandgap reference output voltage. Connect at least 0.1F to ground (CVREF 0.1F). Analog ground. Analog supply voltage. Input supply for the LDO E pass transistor. LDO E output. LDO D output. Input supply for the LDO C and LDO D pass transistors. LDO C output. Input supply for the LDO A pass transistor. LDO A output. Pad for heat sinking purposes. Connect to ground plane using multiple vias. Not connected internally.
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SC900
POWER MANAGEMENT Block Diagram
INA INB VIN
INB
Reference
VREF
EN I2C Interface
en
DACs
DAC A en DAC B DAC C DAC CTRL LDO CTRL reset CTRL INB CTRL Input DAC D DAC E ref dac
LDO
ref input en out
LDOA
VASEL SCL SDA A0
vasel scl sda a0
LDO
en out VOB input dac
LDOB
VOB
Reset/ Shutdown CTRL
arst ldopgd reset
LDO
ref input dac en out
LDOC
ARST LDOPGD
LDO
ref input dac en out
LDOD
INCD INE
LDO
ref input dac en out
LDOE
DGND
GND
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SC900
POWER MANAGEMENT Applications Information General Description
Each of the five low-dropout linear regulators (LDOs) can be independently enabled or disabled and their output voltages can each be set by an independent DAC. These controls can be accessed through the I2C serial port. There are five 8-bit volatile registers in the SC900; one for each LDO (registers A,B,C,D,E). In addition there is one common reset and power good control register and one on/off control register. The active shutdown circuitry can be accessed through each LDO register (refer to the section "Active Shutdown" on page 11 for more information). At power-up, the register contents are reset to their default values and the ARST for LDO A has a default startup delay of 100ms. At any time the part can be put into it's lowest power state (shutdown) by pulling the EN pin low. Whenever the EN pin is forced low, the previous settings are lost and the part requires reprogramming to return to the desired state. When EN is pulled high, the device starts up in the default state. A detailed description of the protocol used to load the registers with data is described in the section entitled "Using the I2C Interface" on page 13. VIN and Enable Pin The VIN supply must be 2.7V before the EN pin can be asserted. This means that the EN pin should not be tied to VIN so that it does not reach a logic high level before the input supply reaches 2.7V. LDOA (Core Supply) LDOA is intended to be used as the MSM core supply. It has an output current capability of 200mA and a dedicated reset signal ARST. INA is the dedicated input supply for this regulator. LDOB (Digital I/O Supply) INB supplies power for the internal I2C interface and other digital I/O functions, while LDOB supplies power for ARST and LDOPGD output ports (see block diagram). Therefore it is imperative that LDOB be operational to make use of ARST and LDOPGD. If LDOB is turned off by the on/off control register, these output ports will not function.
LDO RESET Control Register: ARST Pin There are two functions that can be programmed, defining the ARST pin action: * Set the polarity of the reset signal * Set the reset clear delay time in milliseconds As soon as the LDOA output voltage falls below its programmed value, the ARST pin is asserted. The polarity of the ARST pin can be set to active high or active low during a reset condition, by bit 6 of the LDO Reset Control Register. Once the error condition is resolved (output rises to the programmed value), a delay is initiated before the ARST pin is cleared. The delay is programmable by bits 0-1 of the LDO Reset Control Register. The Default delay time is 100ms, and the delay can be programmed for 0, 50, 100, or 150ms. LDOPGD Pin There are three functions that can be programmed to define the LDOPGD pin action: * Set which LDOs are to be monitored for power-good * Set the polarity of the power-good signal * Set the power-good delay time in milliseconds Bits 4 and 5 of the LDO Reset Control Register select which LDO or LDOs are monitored. LDO C, D and E can be monitored independently or LDOs A, C, D, & E can be monitored collectively. The polarity of the LDOPGD pin can be set to active high or active low by bit 7 of the LDO Reset Control Register. As soon as any of the selected LDO output voltages which are monitored falls within spec, the LDO power-good (LDOPGD) pin is asserted. Once the LDO output power is stable (output rises to the programmed value), a delay is initiated before the LDOPGD pin is set. The delay is programmable by bits 2 and 3 of the LDO Reset Control Register. The default delay is 100ms, and this delay can be programmed to 0, 50, 100, or 150ms.
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SC900
POWER MANAGEMENT Applications Information (Cont.)
Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Each LDO register uses bit 5 of the LDO output voltage data byte to control the shutdown behavior. When the active shutdown bit is enabled (set to 1), the capacitance on the LDO output will be discharged by an on-chip FET after the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default active shutdown state for all LDOs is on. ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bit to 1. Likewise, they can be turned off by setting the on/off bit to 0. This allows for on/off control with a single write command. If the enable (EN) pin is high and data is written to the LDO voltage registers, the LDO outputs will go to the voltage prescribed by the Output Voltage Code bits (0-4). Data will not be lost when toggling the on/off bit from 0 to 1. However, if the EN pin is forced low, all circuitry in the device is disabled. All programmed information is lost when the enable bit is subsequently pulled high. VASEL Pin The VASEL pin sets the default voltage of LDO A, the core supply. When this pin is set to VIN, the default voltage is 2.80V. When this pin is set to GND, the default voltage is 1.80V. The voltage can be changed from its default state after start up by writing to the LDO voltage code register. Device Addressing Following a start condition, the master must output the address of the slave it is accessing. The most significant six bits of the slave are the device type identifier (ID). For the SC900 this is fixed at 000100[B]. The next significant bit addresses a particular device. A system can have up to two SC900 devices on the bus. The two addresses are defined by the state of the A0 input (see Figure 1).
D EVIC E TYPE ID EN TIFIER 0 0 0 1 0 0 D EVIC E AD D R ESS Pi n A0 to GND = 0 Pi n A0 to VIN = 1 R /W X
When the A0 pin is tied to GND, device 1 has an address of 0 and the combination of device type ID and address is 0x08H. When the A0 pin is tied to VIN, device 2 has and address of 1 and the combination of device type ID and address is 0x09H. The last bit of the slave address defines the operation to be performed. When set to a one a read operation is selected; when set to a zero a write operation is selected. Following a start condition, the SC900 monitors the SDA line comparing the slave address being transmitted with its slave address (device type ID and state of A0 input). Upon a correct compare the SC900 outputs an acknowledge on the SDA line. Depending on the state of the R/ W bit, the SC900 will execute a read or write operation. Protection Circuitry The SC900 provides protection circuitry that prevents the device from operating in an unspecified state. These include Under-voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under Voltage Lockout The SC900 provides an Under Voltage Lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. When the battery voltage drops below the UVLO threshold, the LDOs are disabled. As the battery voltage increases above the hysteresis level, the LDOs are re-enabled into their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900 will shut down. Over-temperature Protection The SC900 provides an internal Over-temperature (OT) protection circuit that monitors the internal junction temperature. When the temperature exceeds the OT threshold, the OT protection disables all the LDO outputs. As the junction temperature drops below the hysteresis level the OT protection re-enables all the LDOs in their previous states, provided ENABLE has remained high. If ENABLE goes low, the SC900 will shut down. Short-circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed.
Figure 1 - Slave Address Structure
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SC900
POWER MANAGEMENT Applications Information (Cont.)
Layout Considerations Layout is straightforward if you use the Gerber files on page 21 as a reference. Notice that the input voltage feed to the SC900 is on the bottom of the board and vias connect this voltage track to the top of the board and then to the SC900 itself. The input bypass can be one 4.7F capacitor, two 3.3F capacitors, three 2.2F capacitors or five 1F capacitors. The determining factor is how much copper is available on the input voltage feed track and how much room is available. If the input LDO Reset Control Logic Table (Defaults are in Bold)
Register Name LD O A LD O B LD O C LD O D LD O E LDO Reset Control On/Off Control Register Register Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 LDOPGD Pin Reset Polarity Bit X ARST Pin Reset Polarity Bit X LDOPGD Monitor Logic Bits X ON/OFF Control LD O E 1 ON 0 OFF LDOPGD Delay Bits ON/OFF Control LD O D 1 ON 0 OFF ON/OFF Control LD O C 1 ON 0 OFF LDO (A) Reset Delay Bits ON/OFF Control LD O B 1 ON 0 OFF ON/OFF Control LD O A 1 ON 0 OFF Bit 7 X Bit 6 X Bit 5 Active Shutdown 1 = ON 0 = OFF Bit 4 Bit 3 Bit 2 LDO Output Voltage Codes Table A Bit 1 Bit 0
voltage track is very thin, then use five 1F capacitors placed very close to the input pins of the SC900. If the input track is fairly thick, then you can use a single 4.7F capacitor at the beginning of the voltage feed track since a wider track has less inductance per inch. The SC900EVB has five 1F capacitors, but these can be replaced with one 4.7F in place of C1 and opens in place of C9, C14, C15, and C16 (see page 20 for details).
LDO Reset Control Logic Table (Defaults are in Bold)
Bit 7 Result Bit 6 Result Bit 5 Bit 4 Result Bit 3 Bit 2 Result Bit 1 Bit 0 Result
LDOPGD Pin Polarity 0 High: Power Fail Low: Power Good High: Pow er Good Low : Pow er Fail
ARST Pin Polarity 0 High: Reset Low: Power Good High: Pow er Good L o w : R eset
LDOPGD Monitor Logic 0 0 LDOs A,C,D&E Good LDO E Good LDO C Good LDO D Good
LDOPGD Delay 0 0 150ms
ARST Delay 0 0 150ms
1
1
0 1 1
1 0 1
0 1 1
1 0 1
100ms 50ms 0ms
0 1 1
1 0 1
50ms 100ms 0ms
Notes: Digital outputs are powered from INB, additionally LDOB must be on for operation of LDOPGD and ARST.
SC900 Slave Address:
D EVIC E TYPE ID EN TIFIER 0 0 0 1 0 0 D EVIC E AD D R ESS A0 R /W X
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SC900
POWER MANAGEMENT Applications Information (Cont.)
Output Voltage Code Bits: A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages. Table A - LDO Output Voltage Control Settings
Bit 4 0 0 0 0 0 1 1 Bit 3 0 0 0 0 0 1 1 Bit 2 0 0 0 0 1 1 1 Bit 1 0 0 1 1 0 1 1 Bit 0 0 1 0 1 0 0 1 LDO Output Voltage 1.45V 1.50V 1.55V 1.60V 1.65V 2.95V 3.00V
Using the I2C Interface
The SC900 is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated January 2000. The SC900 has six user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, in that once the slave address has been sent to the SC900 enabling it to be a slave transmitter/ receiver, any register can be written or read from independent of each other. While there is no auto increment/ decrement capability in the SC900 I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. SC900 Limitations to the I2C Specifications Seven-bit addressing is required for communicating with the SC900; ten-bit addressing is not allowed. Any general call address will be ignored by the SC900. Note that the SC900 is not CBUS compatible. Finally, the SC900 can operate in standard mode (100kbit/s) or fast mode (400kbit/s).
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SC900
POWER MANAGEMENT Applications Information (Cont.) Supported Formats
Direct Format - Write The simplest format for an I2C write is the direct format. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900 I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8-bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P].
I2C Direct Format - Write
S Slave Address W A Register Address A Data A P
S : Start Condition W: Write = '0' A : Acknowledge (sent by slave) Sr: Repeated Start Condition P : Stop Condition
Slave Address : 7 bit Register Address : 8 bit Data : 8 Bit
Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC900 I2C then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8-bit data byte. The master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P].
I2C Combined Format - Read
S Slave Address W A Register Address A Sr Slave Address R A Data B P
S : Start Condition W: Write = '0' R : Read = '1' A : Acknowledge (Sent by Slave) B : Acknowledge (Sent by Master) Sr: Repeated Start Condition P : Stop Condition
Slave Address : 7 bit Register Address : 8 bit Data : 8 Bit
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SC900
POWER MANAGEMENT Applications Information (Cont.)
Stop Separated Reads Another read format is available which is, in effect, an extension of the combined format read. This format allows a master to set up the register address pointer for a read and return to that slave some time later to read the data. After the start condition [S], the slave address is sent, followed by a write. The SC900 I2C then acknowledges that it is being addressed, and the master responds with the 8-bit register address. The master then sends a stop or restart condition, and may address another slave. Some time later the master sends a start or restart condition, and a valid slave address is sent, followed by a read. The SC900 I2C then acknowledges and returns the data at the register address location that had previously been set up.
I2CStop Separated Format - Read I2C Stop Register Address Setup Access
S Slave Address AW A Register Address A P
Master Addresses other Slaves
S Slave Address B
Register Read Access
S/ Sr Slave Address AR A Data BP
S : Start Condition Slave Address : 7 bit W: Write = '0' Register Address : 8 bit R : Read = '1' Data : 8 Bit A : Acknowledge (sent by slave) B : Acknowledge (sent by master) Sr: Repeated Start Condition P : Stop Condition
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SC900
POWER MANAGEMENT Timing Diagrams
ARST & LDOPGD Timing
LDO A: VOUTA VTH(A) VTH(A) TRD VARST 90% VARST 10% VARST
LDO A, C, D, & E: VOUT VTH VTH TPGD VLDOPGD 90% VLDOPGD 10% VLDOPGD
LDO On/Off Control via the I2C Interface
STOP
START
STOP
SCL SDA VLDOn
40us 300us
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SC900
POWER MANAGEMENT Timing Diagram
Default Start-Up, Shut-Down Timing Diagram
Enable VREF LDO A LDO B LDO C LDO D LDO E ARST LDOPGD
200us 15ms 100ms 100ms
15ms
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SC900
POWER MANAGEMENT Typical Characteristics
Dropout Voltage (LDOA)
180 160 140 Dropout Voltage (V) 120 100 80 60 40 20 0 0 25 50 75 100 125 150 175 200 Load Current (mA)
TA = 25C TA = 85C TA = -40C
Dropout Voltage (LDOB-E)
180 160 140 Dropout Voltage (V) 120 100 80 60 40 20 0 0 25 50 75 Load Current (mA) 100 125 150
TA = -40C TA = 25C TA = 85C
Load Regulation (LDOA-E)
TA = 25C, VIN = 3.7V
Line Regulation (LDOA-E)
VIN(MIN) < VIN < 5.5V
0 Output Voltage Variation (mV) Output Voltage Variation (mV) 0 25 50 75 100 Load Current (mA) 125 150 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5
7 6 5 4 3 2 1 0 1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
Output Voltage (V)
Output Noise vs. Load Current (LDOA-E)
60
VOUT = 2.5V
50 Output Noise (V) 40
VOUT = 3.0V
30 20 10 0 0 25 50 75 100 125 150 175 200 Load Current (mA)
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SC900
POWER MANAGEMENT Typical Characteristics
Line Transient
VIN = 3.7V, Io = 100mA
VIN 500mV/div
Load Transient (LDOA-E)
VIN = 3.7V, Io = 10mA to 150mA step
Vo 20mV/div
Vo 10mV/div
Io 100mA/div
100s/div
1ms/div
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SC900
POWER MANAGEMENT Evaluation Board
SC900 PWR
PROBE A TP1 1 AM1
PROBE B
PROBE C
PROBE D
PROBE E
R1 150
R2 150
R3 0 TP2
D1 LDOPGD
D2 ARST
TP8 TP7 ARST LDOPGD 1 1
1 AM2
J1 LDOA
J2 LDOB
J3 LDOC
J4 LDOD
J5 LDOE
1
1
1
1
R4 7.5K Q1 FMMT3904 Q2 FMMT3904 R5 7.5K
U1 VIN INA INB INCD INE 13 19 2 17 14 5 9 10 3 4 6 12 VIN INA INB INCD INE EN LDOPGD ARST SDA SCL A0 GND SC900 LDOA LDOB LDOC LDOD LDOE VREF 20 1 18 16 15 11
TP3 SCLK 1
TP4 SDAT 1
VASEL DGND
8 7 R6 1 100K
C2 0.1uF
C3 2.2uF
C4 2.2uF TP9 ENABLE
C5 2.2uF
C6 2.2uF
1 C7 2.2uF J7 GND
J6 2 VASEL SC900 PWR
1
R18 SC900 PWR
J8 GND
+5V EXTRNAL J9 1 2 EXTERNAL SUPPLY
R7 SC900 PWR 4.75k R8 TP5 A0
1
1
TP6 VASEL R9 SC900 PWR SC900 PWR 100K 150 R11 100K D3 ENABLE 1 2 J10 C2DAT 1 C2CLK 2 3 PROGRAM & DEBUG 3 NC7S04 4 C10 0.1uF U3 R10
100K (No-Pop)
1
C8 10uF
4.75k
R17 0 SC900 PWR 5
U2 SC900 PWR SW1 6 2 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0/C2D C2CK/RST VREGIN VBUS DD+ GND 18 17 16 15 14 13 12 11 10 9 7 8 5 4 3 C12 4.7uF C13 1uF
C11 SC900 Power Select 0.1uF
R12 150
R13 150
R14 100K
R15 100K
+5V USB
+5V USB J11 1 2 3 4 USB F1 1A
D4 EXTERNAL
D5 USB
BOARD APPLICATION I.D.
C8051F320
R16 150
D6 USB BUS
VIN
INA
INB
INCD
INE
C1 1uF
C9 1uF
C14 1uF
C15 1uF
C16 1uF
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SC900
POWER MANAGEMENT Evaluation Board Gerbers
Top Gerber
Top Silk Screen Gerber
Bottom Gerber
Bottom Silk Screen Gerber
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SC900
POWER MANAGEMENT Outline Drawing - MLPQ-20L 4 x 4
A D B
DIM
A A1 A2 b D D1 E E1 e L N aaa bbb
SEATING PLANE A1 D1 LxN E/2 E1 2 1 C
PIN 1 INDICATOR (LASER MARK)
E
A2 A aaa C
.031 .035 .040 .000 .001 .002 - (.008) .007 .010 .012 .153 .157 .161 .100 .106 .110 .153 .157 .161 .100 .106 .110 .020 BSC .011 .016 .020 20 .004 .004
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
0.80 0.90 1.00 0.00 0.02 0.05 - (0.20) 0.18 0.25 0.30 3.90 4.00 4.10 2.55 2.70 2.80 3.90 4.00 4.10 2.55 2.70 2.80 0.50 BSC 0.30 0.40 0.50 20 0.10 0.10
N bxN bbb e D/2 CAB
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
Marking Information
SC900 yyww xxxxx xxxxx
yy = two digit year of manufacture ww = two digit week of manufacture xxxxx = lot number
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SC900
POWER MANAGEMENT Land Pattern - MLPQ-20L 4 x 4
K
DIMENSIONS DIM C G H K P X Y Z INCHES (.155) .122 .106 .106 .021 .010 .033 .189 MILLIMETERS (3.95) 3.10 2.70 2.70 0.50 0.25 0.85 4.80
(C)
H
G
Z
Y X P
NOTES:
1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805)498-3804 Visit us at: www.semtech.com
2005 Semtech Corp. 23 www.semtech.com

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