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PD - 94999
IRFP23N50LPBF
SMPS MOSFET Applications HEXFET(R) Power MOSFET * Zero Voltage Switching SMPS VDSS RDS(on) typ. Trr typ. ID * Telecom and Server Power Supplies * Uninterruptible Power Supplies 0.190 500V 170ns 23A * Motor Control applications * Lead-Free Features and Benefits * SuperFast body diode eliminates the need for external diodes in ZVS applications. * Lower Gate charge results in simpler drive requirements. * Enhanced dv/dt capabilities offer improved ruggedness. * Higher Gate voltage threshold offers improved noise TO-247AC immunity.
Absolute Maximum Ratings
Parameter ID @ TC = 25C Continuous Drain Current, VGS @ 10V ID @ TC = 100C Continuous Drain Current, VGS @ 10V IDM Pulsed Drain Current PD @TC = 25C Power Dissipation VGS dv/dt TJ TSTG Max. 23 15 92 370 2.9 30 14 -55 to + 150 300 (1.6mm from case ) 10lbxin (1.1Nxm) W W/C V V/ns C A Units
Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and
e
Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- --- --- 170 220 560 7.6 23 A 92 1.5 250 330 840 11 nC A V ns
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 14A, VGS = 0V TJ = 25C, IF = 23A TJ = 125C, di/dt = 100A/s TJ = 125C, di/dt = 100A/s TJ = 25C
f f
f f
TJ = 25C, IS = 23A, VGS = 0V
980 1500
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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1
02/11/04
IRFP23N50LPBF
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Static @ TJ = 25C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
500 --- --- 3.0 --- --- --- --- --- --- 0.27 --- --- --- --- --- 1.2 --- --- 5.0 50 2.0 100 -100 --- V V A mA nA
Conditions
VGS = 0V, ID = 250A VGS = 10V, ID = 14A
V/C Reference to 25C, ID = 1mA VDS = VGS, ID = 250A VDS = 500V, VGS = 0V VDS = 400V, VGS = 0V, TJ = 125C VGS = 30V VGS = -30V f = 1MHz, open drain
0.190 0.235
f
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Coss eff. (ER)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Effective Output Capacitance (Energy Related)
Min. Typ. Max. Units
12 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 26 94 53 45 3600 380 37 4800 100 220 160 --- 150 44 72 --- --- --- --- --- --- --- --- --- --- --- pF ns nC S ID = 23A
Conditions
VDS = 50V, ID = 14A VDS = 400V VGS = 10V, See Fig. 7 & 15 VDD = 250V ID = 23A RG = 6.0 VGS = 10V, See Fig. 11a & 11b VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 400V, = 1.0MHz VGS = 0V,VDS = 0V to 400V
f f
g
Avalanche Characteristics
Symbol
EAS IAR EAR Parameter Single Pulse Avalanche Energyd Avalanche CurrentA Repetitive Avalanche Energy Typ. --- --- --- Max. 410 23 37 Units mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
--- 0.24 ---
Max.
0.34 --- 40
Units
C/W
Repetitive rating; pulse width limited by
Notes:
max. junction temperature. (See Fig. 11). Starting TJ = 25C, L = 1.5mH, RG = 25, IAS = 23A, dv/dt = 14V/ns. (See Figure 12). ISD 23A, di/dt 430A/s, VDD V(BR)DSS, TJ 150C.
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS . Coss eff.(ER) is a fixed capacitance that stores the same energy as Coss while VDS is rising from 0 to 80% VDSS .
2
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IRFP23N50LPBF
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
100
10
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
10
1
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
0.1
1
4.5V 20s PULSE WIDTH Tj = 150C
0.01
4.5V 20s PULSE WIDTH Tj = 25C
0.001 0.1 1 10 100
0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 23A
ID, Drain-to-Source Current ()
2.5
100.00
R DS(on) , Drain-to-Source On Resistance
T J = 25C
2.0
T J = 150C
10.00
(Normalized)
1.5
1.0
1.00 1.0 6.0
VDS = 15V 20s PULSE WIDTH
11.0 16.0
0.5
0.0 -60 -40 -20 0 20 40 60 80 100
V GS = 10V
120 140 160
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature
( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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IRFP23N50LPBF
100000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C gs ds SHORTED Crss = C gd Coss = C + Cgd ds
25
10000
20
C, Capacitance(pF)
1000
Energy (J)
Ciss
15
10
Coss
100
5
Crss
10 1 10 100 1000
0 0 100 200 300 400 500 600
VDS , Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typ. Output Capacitance Stored Energy vs. VDS
12
ID = 23 VDS = 400V VDS = 250V VDS = 100V
100.00
10
ISD, Reverse Drain Current (A)
T J = 150C 10.00
VGS , Gate-to-Source Voltage (V)
7
5
T J = 25C 1.00
2
VGS = 0V
0 0 24 48 72 96 120
0.10 0.0 0.5 1.0 1.5 2.0
QG, Total Gate Charge (nC)
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 8. Typical Source-Drain Diode Forward Voltage
4
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IRFP23N50LPBF
1000
25
OPERATION IN THIS AREA LIMITED BY RDS(on)
20
ID , Drain Current (A)
100
ID , Drain Current (A)
10us
15
100us 10 1ms
10
1
TC = 25 C TJ = 150 C Single Pulse
10 100
5
10ms 1000 10000
0 25 50 75 100 125 150
VDS , Drain-to-Source Voltage (V)
TC , Case Temperature
( C)
Fig 9. Maximum Safe Operating Area
Fig 10. Maximum Drain Current vs. Case Temperature
VDS V GS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
VDS 90%
D.U.T.
+
- VDD
10% VGS
td(on) tr t d(off) tf
Fig 11a. Switching Time Test Circuit
Fig 11b. Switching Time Waveforms
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IRFP23N50LPBF
10
(Z thJC )
1
D = 0.50
Thermal Response
0.1
0.20 0.10 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T t1/ t 2 +TC 1
J = P DM x Z thJC
P DM t1 t2
0.01
0.001 0.00001
0.0001
0.001
0.01
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5.0
VGS(th) Gate threshold Voltage (V)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150
ID = 250A
T J , Temperature ( C )
Fig 13. Threshold Voltage vs. Temperature
6
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IRFP23N50LPBF
750
ID TOP 10A 15A 23A
600
BOTTOM
EAS , Single Pulse Avalanche Energy (mJ)
450
300
150
0 25 50 75 100 125 150
Starting T , Junction Temperature J
( C)
Fig 14. Maximum Avalanche Energy Vs. Drain Current
15V
V(BR)DSS
VDS L
DRIVER
tp
RG
20V
D.U.T
IAS tp
+ - VDD
A
0.01
I AS
Fig 15a. Unclamped Inductive Test Circuit
Current Regulator Same Type as D.U.T.
Fig 15b. Unclamped Inductive Waveforms
QG
50K 12V .2F .3F
VGS V
D.U.T. + V - DS
QGS
QGD
VGS
3mA
VG
IG ID
Current Sampling Resistors
Charge
Fig 16a. Gate Charge Test Circuit
Fig 16b. Basic Gate Charge Waveform
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IRFP23N50LPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. For N-Channel HEXFET(R) Power MOSFETs
8
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IRFP23N50LPBF
TO-247AC Package Outline
15.90 (.626) 15.30 (.602) -B3.65 (.143) 3.55 (.140) -A0.25 (.010) M D B M 5.50 (.217) 20.30 (.800) 19.70 (.775) 1 2 3 -C14.80 (.583) 14.20 (.559) 4.30 (.170) 3.70 (.145) 0.80 (.031) 3X 0.40 (.016) C AS 2.60 (.102) 2.20 (.087)
Dimensions are shown in millimeters (inches)
-D5.30 (.209) 4.70 (.185)
2.50 (.089) 1.50 (.059) 4
2X
5.50 (.217) 4.50 (.177)
NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH. 3 CONFORMS TO JEDEC OUTLINE TO-247-AC.
2.40 (.094) 2.00 (.079) 2X 5.45 (.215) 2X
1.40 (.056) 3X 1.00 (.039) 0.25 (.010) M 3.40 (.133) 3.00 (.118)
LEAD ASSIGNMENTS Hexfet IGBT 1 -LEAD ASSIGNMENTS Gate 1 - Gate 12 - Drain GATE2 - Collector 2 - DRAIN 3 - Source 3 - Emitter 3 - SOURCE 4 - Drain DRAIN - Collector 4 4-
TO-247AC Part Marking Information
EXAMPLE: T HIS IS AN IRFPE30 WIT H ASSEMBLY LOT CODE 5657 ASSEMBLED ON WW 35, 2000 IN THE AS SEMBLY LINE "H"
Note: "P" in assembly line position indicates "Lead-Free"
INT ERNATIONAL RECT IFIER LOGO ASSEMBLY LOT CODE
PART NUMBER
IRFPE30
56 035H 57
DAT E CODE YEAR 0 = 2000 WEEK 35 LINE H
TO-247AC package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.02/04
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