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Winbond Clock Generator W83195BR/G-101 For Intel 915/925 Chipsets
Date:
March/10/2006
Revision: 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
W83195BR/G-101 Data Sheet Revision History
Pages 1 2 3 4 5 6 7 8 9 1-5, 7-15 3/10/2006 0.7 n.a. n.a. 6-11, 13 Dates 09/30/2004 11/24/2004 Version 0.5 0.6 Web Version n.a. n.a. Main Contents All of the versions before 0.5 are for internal use Correction IC version, add register default value and correction some description and default value Please see blue color text
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
Tables of Content1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 3 PIN DESCRIPTION..................................................................................................................... 4 5.1 5.2 5.3 5.4 5.5 5.6 6. 7. Crystal I/O...................................................................................................................................4 CPU, SRC, PCIF, and PCI Clock Outputs................................................................................4 Frequency select, and Fixed Frequency Outputs.....................................................................5 I2C Control Interface..................................................................................................................5 Power Management Pins ..........................................................................................................6 Power Pins .................................................................................................................................6
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 7 I2C CONTROL AND STATUS REGISTERS............................................................................... 8 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Register 0: Frequency Select Register (Default = 10h)............................................................8 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E7h)...............................8 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ................................9 Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh) ................................9 Register 4: 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh)..................9 Register 5: Watchdog Control (Default: 02h) ..........................................................................10 Register 6: SRC Control (1 = Enable, 0 = Stopped) (Default: FEh).......................................10 Register 7: Winbond Chip ID (Default: 22h) (Read Only).......................................................10 Register 8: M/N Program (Default: D0h).................................................................................11
7.10 Register 9: M/N Program Register (Default: 7Ah) ..................................................................11 7.11 Register 10: Reserved (Default: 3Bh) .....................................................................................12 7.12 Register 11: Spread Spectrum Programming (Default: 0Bh).................................................12 7.13 Register 12: Divisor Control (Default: 72h) .............................................................................12 7.14 Register 13: Step-less Enable Control (Default: 0Fh) ............................................................13 7.15 Register 14: Control (Default: 10h)..........................................................................................14 7.16 Register 15: Reserved (Default: ECh).....................................................................................14 7.17 Register 16: Skew Control (Default: E4h) ...............................................................................14 7.18 Register 17: Reserved (Default: 00h)......................................................................................14 7.19 Register 18: Reserved (Default: 00h)......................................................................................14 7.20 Register 19: Reserved (Default: DAh).....................................................................................15 - II -
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
7.21 Register 20: Watch dog timer (Default: 88h)...........................................................................15 7.22 Register21: Control (Default: 4Bh) ..........................................................................................15 8. ACCESS INTERFACE .............................................................................................................. 16 8.1 8.2 8.3 8.4 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 10. 11. 12. Block Write protocol .................................................................................................................16 Block Read protocol.................................................................................................................16 Byte Write protocol...................................................................................................................16 Byte Read protocol ..................................................................................................................16 ABSOLUTE MAXIMUM RATINGS .........................................................................................17 General Operating Characteristics..........................................................................................17 Skew Group timing clock .........................................................................................................18 CPU 0.7V Electrical Characteristics ........................................................................................18 SRC 0.7V Electrical Characteristics ........................................................................................18 PCIF, PCI Electrical Characteristics........................................................................................19 48M Electrical Characteristics .................................................................................................19 REF Electrical Characteristics .................................................................................................20 DOT 0.7V Electrical Characteristics ........................................................................................20
SPECIFICATIONS .................................................................................................................... 17
ORDERING INFORMATION..................................................................................................... 21 HOW TO READ THE TOP MARKING...................................................................................... 21 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 22
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
1. GENERAL DESCRIPTION
The W83195BR/G-101 is a Clock Synthesizer for Intel P4 processors and Intel Grandsdale chipsets. W83195BR/G-101 provides all clocks required for high-speed microprocessor and provides step-less frequency programming, 32 different frequencies of CPU, PCI, SRC clocks setting. Simultaneously W83194BR-101 supports SRC_SATA 100MHz clock output for SATA and DOT 96MHz clock outputs for integrated graphic chipsets. All clocks are externally selectable with smooth transitions. The W83195BR/G-101 programs the registers to enable or disable each clock outputs through I2C serial bus interface and provides -0.5% down type spread spectrum or programmable spread spectrum scale to reduce EMI. The W83195BR/G-101 is driven with a 14.318 MHz reference crystal and runs on a 3.3V supply.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * 2 pair 0.7 V current mode Differential clock outputs for CPU 6 pair 0.7V current mode Differential clock outputs for SRC and SRC_SATA. 1 pair 0.7V current mode Differential 96MHz clock outputs for DOT. 6 PCI clock outputs for PCI 3 PCI clock free running outputs for PCI 1 48 MHz clock output for USB. 1 14.318MHz REF clock outputs. Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% down type spread spectrum in H/W and software select mode. Programmable S.S.T. scale to reduce EMI in M/N mode. Programmable registers to enable/stop each output. Programmable clock outputs to control skew. Watch Dog Timer output
* 56 pin SSOP package
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
3. PIN CONFIGURATION
VDDPCI GND P C I3 P C I4 P C I5 GND VDDPCI P C IC L K _ F 0 P C IC L K _ F 1 P C IC L K _ F 2 VDD48 48M H Z GND D O TT_96M H Z D O TC _96M H Z *F S _ 1 V tt_ P W R G d # /P D *F S _ 0 SRCT1 SRCC1 VDDSRC SRCT2 SRCC2 SRCT3 SRCC3 SR C T4_SATA SR C C 4_SATA VDDSRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P C I2 P C I1 P C I0 /&F S _ 4 *F S _ 2 R E F 0 /&F S _ 3 GND X IN XOUT VDDREF *S D A T A *S C L K GND C PU C LKT0 C PU C LKC 0 VDDCPU C PU C LKT1 C PU C LKC 1 IR E F GNDA VDDA SRCT7 SRCC7 VDDSRC SRCT6 SRCC6 SRCT5 SRCC5 GND
#: Active low *: Internal pull up resistor 120K to VDD & : Internal Pull-down resistor 120K to GND
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
4. BLOCK DIAGRAM
48M H z PLL2 D iv id e r D O TT_96M H z D O TC _96M H z X IN XOUT XTAL OSC
2
REF0 C P U C L K T 0 :1 C P U C L K C 0 :1 SR C T4_SATA SR C C 4_SATA
6
PLL1 S p re a d S p e c tr u m
2 VCO CLK
M /N /R a tio ROM
D iv id e r
6 3
S R C T 1 :3 ,5 :7 S R C C 1 :3 ,5 :7
P C I_ F 0 :2
F S ( 0 :4 ) VTT_PW R G D #
L a tc h &POR
6
P C I 0 :5
PD
C o n tr o l L o g ic & C o n fig R e g is te r IREF 475
*S D A T A *S C L K
I2 C In te r fa c e
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtp120k INtd120k OUT I/OD # *
&
Input Latched input at power up, internal 120k pull up. Latched input at power up, internal 120k pull down. Output Bi-directional Pin, Open Drain. Active Low Internal 120k pull-up Internal 120k pull-down
5.1
Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
50 49
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF).
5.2
CPU, SRC, PCIF, and PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
44,43,41,40
CPUT [0:1] CPUC [0:1]
OUT
Low skew (< 125ps) 0.7V current mode differential clock outputs for host frequencies of CPU Low skew (<125ps)0.7V current mode differential clock outputs for PCI-E 3.3V free running PCI clock output. 3.3V PCI clock output. Latched input for FS4 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. Low skew (< 500ps) 3.3V PCI clock outputs
19,20,22,23,2 SRCT[1:3,5:7] 4,25,31,30,33 SRCC[1:3,5:7] ,32,36,35 8,9,10 PCI_F[0:2] PCI0 54
&
OUT OUT OUT INtd120k OUT
FS4
55,56,3,4,5 PCI [1:5]
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
5.3 Frequency select, and Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
18
*FS0
INtp120k
Latched input for FS0 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. Latched input for FS1 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. Latched input for FS2 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull up. 3.3V REF0 14.318MHz clock output. Latched input for FS3 at initial power up for H/W selecting the output frequency. Latched voltage level refers to Vil_FS and Vih_FS voltage level. This is internal 120K pull down. 48MHz clock output for USB. 0.7V current mode 96MHz differential clock outputs for DOT 0.7V current mode 100MHz differential clock outputs for SATA
16
*FS1
INtp120k
53
*FS2
INtp120k
52
REF0
OUT
&
FS3
INtd120k
12 14,15 26,27
48MHz DOTT/C_96MHz SRCT/C4_SATA
OUT OUT OUT
5.4
I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
47 46
*SDATA *SCLK
I/OD IN
Serial data of I2C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor.
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
5.5 Power Management Pins
PIN PIN NAME TYPE DESCRIPTION
39
IREF
OUT
Deciding the reference current for the differential pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current; 475 ohm is the standard value. Power good is a low active input signal used to determine when FS [4:0] are valid to be sample. Power Down Function. This is power down pin, high active (PD). Internal 120K pull down
VTT_PWRGD# 17 PD
IN
INtd120k
5.6
37 1,7
Power Pins
PIN PIN NAME TYPE DESCRIPTION
VDDA VDDP VDDS VDD48 VDDC VDDR GNDA GND
PWR PWR PWR PWR PWR PWR PWR PWR
3.3V power supply for PLL core. 3.3V power supply for PCI. 3.3V power supply for SRC pair. 3.3V power supply for 48MHz. 3.3V power supply for CPU. 3.3V power supply for REF. Ground pin for PLL core. Ground pin
21,28,34 11 42 48 38 2,6,13,29,45,51
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 3).
FS4 FS3 FS2 FS1 FS0 CPU (MHZ) DOT (MHZ) SRC (MHZ) PCI (MHZ)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 134.66 202.00 168.33 274.66 137.33 206.00 171.66 279.99 140.00 210.00 174.99 287.99 144.00 216.00 179.99
96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00
100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00
33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34 33.34
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
7. I2C CONTROL AND STATUS REGISTERS
7.1
BIT
Register 0: Frequency Select Register (Default = 10h)
NAME PWD DESCRIPTION
TYPE
7 6 5 4 3 2
SSEL [4] SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL
0 0 0 1 0 0 Enable software frequency table selection SSEL [4:0]. 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 7~ 3. Enable Spread Spectrum 0 = Normal 1 = Spread Spectrum enabled Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [2:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0. R/W Frequency selection by software via I2C R/W
1
SPSPEN
0
R/W
0
EN_SAFE_FREQ
0
R/W
7.2
BIT
Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default: E7h)
PIN NO PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
36,35 41,40 44,43 -
1 1 1 X X X X X
SRC7 output control CPUT1 / C1 output control CPUT0 / C0 output control Power on latched value of FS4 pin, Default: 0 (Read only). Power on latched value of FS3 pin, Default: 0 (Read only). Power on latched value of FS2 pin, Default: 1 (Read only). Power on latched value of FS1 pin, Default: 1 (Read only). Power on latched value of FS0 pin, Default: 1 (Read only).
R/W R/W R/W R R R R R
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
7.3
BIT
Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved 9,10 8 Reserved Reserved 5 Reserved 3,4
1 1 1 1 1 1 1 1
Reserved PCI_F1/PCI_F2 output control PCI_F0 output control Reserved Reserved PCI5 output control Reserved PCI3, PCI4 output control
R/W R/W R/W R/W R/W R/W R/W R/W
7.4
BIT
Register 3: PCI Clock Control (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
56 55 54 Reserved Reserved Reserved Reserved Reserved
1 1 1 1 1 1 1 1
PCI2 output control PCI1 output control PCI0 output control Reserved Reserved Reserved Reserved Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
7.5
BIT
Register 4: 48MHz, DOT, REF Control (1 = Enable, 0 = Stopped) (Default: FFh)
PIN NO PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved 14,15 12 Reserved Reserved 52 Reserved Reserved
1 1 1 1 1 1 1 1
Reserved DOT_T/C 96MHZ output control 48MHz output control Reserved Reserved REF0 output control Reserved Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
7.6
BIT
Register 5: Watchdog Control (Default: 02h)
NAME PWD DESCRIPTION TYPE
7
Reserved
X
Reserved Program this bit => 1: Enable Watchdog Timer feature. 0: Disable Watchdog Timer feature. Read-back this bit => During timer count down the bit read back to 1. If count to zero, this bit read back to 0. Read Back only. Timeout Flag. This bit is Read Only. 1: Watchdog has ever started and counts to zero. 0: Watchdog is restarted and counting.
R/W
6
EN_WD
0
R/W
5 4 3 2 1 0
WD_TIMEOUT SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 0 1 0
R R/W
These bits will be reloaded in Reg-0 to select frequency table. As the watchdog is timeout and EN_SAFE_FREQ=1.
7.7
BIT
Register 6: SRC Control (1 = Enable, 0 = Stopped) (Default: FEh)
NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved 33,32 31,30 26,27 24,25 22,23 19,20 Reserved
1 1 1 1 1 1 1 0
Reserved SRCT/C 6 outputs control SRCT/C 5 outputs control SRCT/C 4_SATA outputs control SRCT/C 3 outputs control SRCT/C 2 outputs control SRCT/C 1 outputs control Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
7.8
BIT
Register 7: Winbond Chip ID (Default: 22h) (Read Only)
NAME PWD DESCRIPTION TYPE
7 6 5
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5]
0 0 1
Winbond Chip ID. W83195BR/G-101 Winbond Chip ID. Winbond Chip ID.
R R R
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
Register 7: Winbond Chip ID (Default: 22h) (Read Only), continued
BIT
NAME
PWD
DESCRIPTION
TYPE
4 3 2 1 0
CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0 0 0 1 0
Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
R R R R R
7.9
BIT
Register 8: M/N Program (Default: D0h)
NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
N_DIV [8] N_DIV [9] M_DIV [5] M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 1 0 1 0 0 0 0
Programmable N divisor value. Bit7~0 are defined in the Register 9 Programmable N divisor value. Bit7~0 are defined in the Register 9
R/W R/W R/W R/W R/W R/W R/W R/W
Programmable M divisor value.
7.10 Register 9: M/N Program Register (Default: 7Ah)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
0 1 1 1 1 0 1 0 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 8.
R/W R/W R/W R/W R/W R/W R/W R/W
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
7.11 Register 10: Reserved (Default: 3Bh)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
SRC_SPSPEN N3VAL<6> N3VAL<5> N3VAL<4> N3VAL<3> N3VAL<2> N3VAL<1> N3VAL<0>
0 0 1 1 1 0 1 1
Enable SRC spread spectrum feature,1: Enable, 0: Disable
R/W R/W R/W R/W R/W R/W R/W R/W
Programmable N3 divisor 6~0 for programmable SATA clock.
7.12 Register 11: Spread Spectrum Programming (Default: 0Bh)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 0 0 1 0 1 1 Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0.
R/W R/W R/W R/W R/W R/W R/W R/W
7.13 Register 12: Divisor Control (Default: 72h)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved KVAL6 KVAL5 KVAL4 KVAL3 KVAL2 KVAL1 KVAL0
0 X X X X X X X
Reserved Reserved Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
Define the CPU divider ratio Refer to Table-2
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W83195BR/G-101
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Table-2 CPU, SRC, PCI divider ratio selection Table LSB MSB Bit2/ Bit4/ Bit6 0 1
00 01
CPU Bit1, 0
10 11
Div2 Div0
Div3 Div0
Div4 Div0
Div6 Div0
7.14 Register 13: Step-less Enable Control (Default: 0Fh)
BIT NAME PWD DESCRIPTION TYPE
7
EN_MN_PROG
0
0: Output frequency depend on frequency table 1: Program all clock frequency by changing M/N value The equation is VCO =14.318MHz*(N+4)/ M. Once the watchdog timer timeout, the bit will be clear. Then the frequency will be decided by hardware default FS<2:0> or desired frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ (Reg0 - bit 0). Programmable N divisor bit 10. Reserved Reserved
R/W
6 5 4 3 2 1 0
N<10> Reserved Reserved IVAL<3> IVAL<2> IVAL<1> IVAL<0>
0 0 0 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W
Charge pump current selection
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
7.15 Register 14: Control (Default: 10h)
BIT NAME PWD DESCRIPTION TYPE
CPUT / SRCT / DOT_T output state in during POWER DOWN assertion. 1: Driven (2*Iref), 0: Tristate (Floating) 7 DRI_CONT 0 CPUT / SRCT / DOT_T output state in during STOP Mode assertion. 1: Driven (6*Iref), 0: Tristate (Floating) Complementary parts always tri-state (floating) in power down or stop mode. 6 5 4 3 2 1 0 Reserved SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0] 0 0 1 0 0 0 0 Spread Spectrum Programmable time, the resolution is 280ns. Default period is 11.8us Reserved R/W R/W R/W R/W R/W R/W R/W R/W
7.16 Register 15: Reserved (Default: ECh) 7.17 Register 16: Skew Control (Default: E4h)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved Reserved Reserved Reserved Reserved PSKEW [2] PSKEW [1] PSKEW [0]
1 1 1 0 0 1 0 0
Reserved Reserved Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
CPU1 to PCI skew control, Skew resolution is 300ps The decision of skew direction is same as PSKEW [2:0] setting
7.18 Register 17: Reserved (Default: 00h) 7.19 Register 18: Reserved (Default: 00h)
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W83195BR/G-101
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7.20 Register 19: Reserved (Default: DAh) 7.21 Register 20: Watch dog timer (Default: 88h)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Reserved WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0]
1 0 0 0 1 0 0 0
Reserved
R/W R/W R/W
Setting the down count depth (Failure decision). One bit resolution represents 250ms. Default time depth is 8*250ms = 2.0 second. If the watchdog timer is counting, this register will return present down count value.
R/W R/W R/W R/W R/W
7.22 Register21: Control (Default: 4Bh)
BIT NAME PWD DESCRIPTION TYPE
7 6 5 4 3 2 1 0
Tri-state Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0 1 0 0 1 0 1 1
Tri-state all output if set 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
R/W R/W R/W R/W R/W R/W R/W R/W
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
8. ACCESS INTERFACE
The W83195BR/G-101 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83195BR/G-101 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2 C address is defined at 0xD2. Block Read and Block Write Protocol
8.1
Block Write protocol
8.2
Block Read protocol
## In block mode, the command code must filled 8'h00
8.3
Byte Write protocol
8.4
Byte Read protocol
PS: In byte Mode program register Byte number is datasheet register Byte number+1
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W83195BR/G-101
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9. SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD). Parameter Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD protection (Human body model) Rating -0.5V to +4.6V - 0.5V to + 4.6V 3.135V to 3.465V 3.135V to 3.465V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
9.2
General Operating Characteristics
Parameter Symbol VIL VIH VOL VOH Idd Cin Cout Lin 2.4 350 5 6 7 2.0 0.4 Min Max 0.8 Units Vdc Vdc Vdc Vdc mA pF pF nH CPU = 100 to 400 MHz PCI = 33.3 Mhz with load 10pF Test Conditions
VDD= 3.3V 5 %, TA = 0C to +70C, Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
9.3 Skew Group timing clock
Parameter CPU pair to CPU pair Skew SRC pair to SRC pair Skew PCI to PCI Skew Min Max 125 125 500 Units ps ps ps Test Conditions Measure Crossing point Measure Crossing point Measured at 1.5V VDD = 3.3V 5 %, TA = 0C to +70C, Cl=10pF
9.4
CPU 0.7V Electrical Characteristics
VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute Voltages crossing point Min 175 175 250 660 -150 100 45 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform
Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle
9.5
SRC 0.7V Electrical Characteristics
VDDS= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute Voltages crossing point Min 175 175 250 660 -150 125 45 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform
Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
9.6 PCIF, PCI Electrical Characteristics
Parameter Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 30 38 45 -33 -33 Min 500 500 Max 2000 2000 250 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
9.7
48M Electrical Characteristics
Parameter Min 500 500 45 -33 -33 30 38 Max 2000 2000 500 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
VDD48= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF, Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
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Publication Release Date: March 2006 Revision 0.7
W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
9.8 REF Electrical Characteristics
Parameter Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max 29 27 45 -29 -23 Min 500 500 Max 2000 2000 1000 55 Units ps ps ps % mA mA mA mA Test Conditions Vol=0.4V, Voh=2.4V Voh=2.4V, Vol=0.4V Measured at 1.5V Measured at 1.5V Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V VDD= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
9.9
DOT 0.7V Electrical Characteristics
VDD= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=2pF, Vol=0.175V, Voh=0.525V, Vr=475, IREF=2.32mA, Ioh=6*IREF Parameter Rise Time Fall Time Absolute Voltages crossing point Min 175 175 250 660 -150 250 45 55 Max 700 700 550 850 Units ps ps mV mV mV ps % Test Conditions Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Single Ended waveform Measure Differential waveform Measure Differential waveform
Voltage High Voltage Low Cycle to Cycle jitter Duty Cycle
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
10. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83195BR-101 W83195BG-101
56 PIN SSOP 56 PIN SSOP(Lead free)
Commercial, 0C to +70C Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83195BR-101 28051234 420GAASA W83195BG-101 28051234 420GAASA
1st line: Winbond logo and the type number: Normal part: W83195BR-101, Lead free part: W83195BG-101 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 420 G A A SA 420: packages made in '2004, week 20 G: assembly house ID; O means OSE, G means GR A: Internal use code A: IC revision SA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners. Publication Release Date: March 2006 Revision 0.7
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
12. PACKAGE DRAWING AND DIMENSIONS
56 PIN SSOP-300mil
.035 .045
.045 .055 0.40/0.50 DIA
SYMBOL
DIMENSION IN MM
DIMENSION IN INCH
E
END VIEW
HE
A A1 A2 b c D HE E e L L1 Y
MIN. NOM MAX. MIN. NOM 0.095 0.101 2.41 2.57 2.79 0.41 0.008 0.012 0.20 0.30 0.088 0.090 2.34 2.24 2.29 0.25 0.20 0.34 0.008 0.010 0.13 0.25 0.005 0.720 0.400 0.292 0.020 0.024 18.2 18.42 18.54 9 10.16 10.31 10.41 7.42 0.51 0.61 7.52 0.64 0.81 1.40 7.59 0.76 1.02 0.08 8
MAX. 0.110 0.016 0.092 0.0135 0.010
TOP VIEW
SEE DETAIL "A"
c
D
A2
A
Y SEATING PLANE e
SIDE VIEW A1
0.725 0.730 0.406 0.410 0.296 0.299 0.025 0.030 0.032 0.040 0.055 0.003 8
b
PARTING LINE
c
0
0
L L1
DETAIL"A"
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W83195BR/G-101
STEPLESS FOR INTEL 915/925 CHIPSETS
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: March 2006 Revision 0.7

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